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Someone resurrected a rk3128 board and provided actual SMP support

Browse Source 
for it. Of course firmware for that SoC does not come with TF-A so
 it's the old-style SMP the older arm32 Rockchip SoCs use.
 
 And additionally the rv1126 got pwm support.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmUtpzwQHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgcIVCACbU20IW+ugqCTyFjLJ4AZDKK1FL0hn7Ic1
 oonSn60ViVfp3HUzwioPFlpXI96wXdS4pUnZjYKcEkUi7LOsJRwxjgJe1Dh21Ffq
 3MtxbJfhdfL9Y3DeZgl47K1rXj57/TM2BAclUWwBK6STE0PgSNRCI1uqFMS7nzMd
 w8VXN+8oTOFD9GWZkyLddy0EZoj8Cr2HJm/FG5kK1k+ZW9JqDBWFybKB//kzgovq
 D4LlCq4h5c3eHsWY9KhuDt0lxOZjsokl0bUM/pQURbmgvC+CKc+upNn8nLWqupvu
 2zVe88dNRUUyh6JpKBu/3jaelOM4WNgFdy+b67BmOTFzpdessRYF
 =d1o3
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmUv8iQACgkQYKtH/8kJ
 UidQOg/+POx3XxSaDW5DywzC62CTy6/apzWt/eR5HqUqb0QKQwmFaIHgIfPW1qzu
 HDK5eu/+XcHYbxQycv63D3wmy3eGfD6fbARa89hCHypJwgbp/DBDsj3+UHBG606M
 cErFfN2LXOIA7nLTi0P9AsDUGS4TWs5e9BdzqpzaYksXdLioEWSVc8jpVxN/rJ2/
 GDDjUYnuxXTDJGWaE9eVLxws+5zEwBlpcTvd1caHxVhI/yLysDK8qrYpGMbQx6n3
 YEAEXsxAC1geInyoygMD60QG8a/3OI+Gl2ctufrOG61Yi1HLW+t5Tg/qmmYFNxgv
 EMj/fn8Te8cHqe7lnNvLC2OgQf2kMCIk2SPJPKRRA6HwB7Qh84sVrIIWdRjfLTX/
 f4hheXep2gpBEZRuOtVEZUwc7lki5nxamQGWQZ3+rBR3XcD5jdAbgfVUG5mTFAB6
 DIcACgjVIshr3uYFe1kGAFmM6kAcKZ33Gz6yNf46WcCBphYBaqYbiVIwMH+T4t0K
 VlJJ0SKYJjhG7fQQVyjqWPbiUFU0XxArqQWmxcb3sqMyBUjjOFM8LtkPh8P+pfkW
 o860Dg8FbxxQJA+LI9/2jUAKtX/XcKkIe9tp8Eunr/XE0E2QKLdtomT1r9hFAS2m
 pLmSBx9SEbSUD2FMqzRvfTMjvH7VKR9Lgt382Fxf2MNNkkIPp8Q=
 =bafk
 -----END PGP SIGNATURE-----

Merge tag 'v6.7-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt

Someone resurrected a rk3128 board and provided actual SMP support
for it. Of course firmware for that SoC does not come with TF-A so
it's the old-style SMP the older arm32 Rockchip SoCs use.

And additionally the rv1126 got pwm support.

* tag 'v6.7-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: Switch to operating-points-v2 for RK3128's CPU
  ARM: dts: rockchip: Enable SMP bring-up for RK3128
  ARM: dts: rockchip: Add CPU resets for RK3128
  ARM: dts: rockchip: Add SRAM node for RK3128
  ARM: dts: rockchip: Enable pwm fan for edgeble-neu2
  ARM: dts: rockchip: Add pwm11 node to rv1126
  ARM: dts: rockchip: Add pwm11m0 pins to rv1126
  ARM: dts: rockchip: Add pwm2 node to rv1126
  ARM: dts: rockchip: Add pwm2m0 pins to rv1126
  dt-bindings: pwm: rockchip: Document rv1126-pwm

Link: https://lore.kernel.org/r/2167992.Mh6RI2rZIc@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-10-18 16:56:35 +02:00
commit a8eddbe354
5 changed files with 100 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml
View File

@ -32,6 +32,7 @@ properties:
- rockchip,rk3308-pwm
- rockchip,rk3568-pwm
- rockchip,rk3588-pwm
- rockchip,rv1126-pwm
- const: rockchip,rk3328-pwm
reg:

61
arch/arm/boot/dts/rockchip/rk3128.dtsi
View File

@ -27,6 +27,7 @@ arm-pmu {
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "rockchip,rk3036-smp";
cpu0: cpu@f00 {
device_type = "cpu";
@ -34,10 +35,8 @@ cpu0: cpu@f00 {
reg = <0xf00>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
operating-points = <
/* KHz uV */
816000 1000000
>;
resets = <&cru SRST_CORE0>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
};
@ -45,18 +44,59 @@ cpu1: cpu@f01 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf01>;
resets = <&cru SRST_CORE1>;
operating-points-v2 = <&cpu_opp_table>;
};
cpu2: cpu@f02 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf02>;
resets = <&cru SRST_CORE2>;
operating-points-v2 = <&cpu_opp_table>;
};
cpu3: cpu@f03 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf03>;
resets = <&cru SRST_CORE3>;
operating-points-v2 = <&cpu_opp_table>;
};
};
cpu_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-216000000 {
opp-hz = /bits/ 64 <216000000>;
opp-microvolt = <950000 950000 1325000>;
};
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000 950000 1325000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000 950000 1325000>;
};
opp-696000000 {
opp-hz = /bits/ 64 <696000000>;
opp-microvolt = <975000 975000 1325000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1075000 1075000 1325000>;
opp-suspend;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1200000 1200000 1325000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1325000 1325000 1325000>;
};
};
@ -76,6 +116,19 @@ xin24m: oscillator {
#clock-cells = <0>;
};
imem: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10080000 0x2000>;
smp-sram@0 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x00 0x10>;
};
};
pmu: syscon@100a0000 {
compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
reg = <0x100a0000 0x1000>;

4
arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts
View File

@ -88,6 +88,10 @@ eth_phy_rst: eth-phy-rst {
};
};
&pwm11 {
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;

16
arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi
View File

@ -87,6 +87,22 @@ i2c0_xfer: i2c0-xfer {
<0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
};
};
pwm2 {
/omit-if-no-ref/
pwm2m0_pins: pwm2m0-pins {
rockchip,pins =
/* pwm2_pin_m0 */
<0 RK_PC0 3 &pcfg_pull_none>;
};
};
pwm11 {
/omit-if-no-ref/
pwm11m0_pins: pwm11m0-pins {
rockchip,pins =
/* pwm11_pin_m0 */
<3 RK_PA7 6 &pcfg_pull_none>;
};
};
rgmii {
/omit-if-no-ref/
rgmiim1_pins: rgmiim1-pins {

22
arch/arm/boot/dts/rockchip/rv1126.dtsi
View File

@ -247,6 +247,17 @@ uart1: serial@ff410000 {
status = "disabled";
};
pwm2: pwm@ff430020 {
compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
reg = <0xff430020 0x10>;
clock-names = "pwm", "pclk";
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2m0_pins>;
#pwm-cells = <3>;
status = "disabled";
};
pmucru: clock-controller@ff480000 {
compatible = "rockchip,rv1126-pmucru";
reg = <0xff480000 0x1000>;
@ -276,6 +287,17 @@ dmac: dma-controller@ff4e0000 {
clock-names = "apb_pclk";
};
pwm11: pwm@ff550030 {
compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
reg = <0xff550030 0x10>;
clock-names = "pwm", "pclk";
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
pinctrl-0 = <&pwm11m0_pins>;
pinctrl-names = "default";
#pwm-cells = <3>;
status = "disabled";
};
uart0: serial@ff560000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff560000 0x100>;