From b0d587be2407ae7319098339034296370a851939 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Jul 2023 16:05:06 +0530 Subject: [PATCH 01/10] dt-bindings: pwm: rockchip: Document rv1126-pwm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document pwm compatible for rv1126 which is fallback compatible of rk3328-pwm group. Signed-off-by: Jagan Teki Acked-by: Conor Dooley Acked-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20230731103518.2906147-2-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml index f2d1dc7e7b3f..65bfb492b3a4 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml @@ -32,6 +32,7 @@ properties: - rockchip,rk3308-pwm - rockchip,rk3568-pwm - rockchip,rk3588-pwm + - rockchip,rv1126-pwm - const: rockchip,rk3328-pwm reg: From 5162bba5b38ce18906fe2be14f0c41e016a88d61 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Jul 2023 16:05:07 +0530 Subject: [PATCH 02/10] ARM: dts: rockchip: Add pwm2m0 pins to rv1126 Add pwm2m0 pins for Rockchip RV1126 PWM2. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230731103518.2906147-3-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi index 554353e0a758..4a9c6d93cdc0 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi @@ -87,6 +87,14 @@ i2c0_xfer: i2c0-xfer { <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; }; }; + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_pin_m0 */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + }; rgmii { /omit-if-no-ref/ rgmiim1_pins: rgmiim1-pins { From 28b2ae4ab0d139b5e1d64e4cbb245f2661a83036 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Jul 2023 16:05:08 +0530 Subject: [PATCH 03/10] ARM: dts: rockchip: Add pwm2 node to rv1126 Add PWM2 node for Rockchip RV1126. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230731103518.2906147-4-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rv1126.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi index 9c918420ecd5..0b2d3e2ee553 100644 --- a/arch/arm/boot/dts/rockchip/rv1126.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -247,6 +247,17 @@ uart1: serial@ff410000 { status = "disabled"; }; + pwm2: pwm@ff430020 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff430020 0x10>; + clock-names = "pwm", "pclk"; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + pmucru: clock-controller@ff480000 { compatible = "rockchip,rv1126-pmucru"; reg = <0xff480000 0x1000>; From 61e510db47ac3c6b371006705c7f563435ae0a30 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Jul 2023 16:05:09 +0530 Subject: [PATCH 04/10] ARM: dts: rockchip: Add pwm11m0 pins to rv1126 Add pwm11m0 pins for Rockchip RV1126 PWM11. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230731103518.2906147-5-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi index 4a9c6d93cdc0..bb34b0c9cb4a 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi @@ -95,6 +95,14 @@ pwm2m0_pins: pwm2m0-pins { <0 RK_PC0 3 &pcfg_pull_none>; }; }; + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_pin_m0 */ + <3 RK_PA7 6 &pcfg_pull_none>; + }; + }; rgmii { /omit-if-no-ref/ rgmiim1_pins: rgmiim1-pins { From c5cb195053aebf9eafece6f54ac25fdf3e694df7 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Jul 2023 16:05:10 +0530 Subject: [PATCH 05/10] ARM: dts: rockchip: Add pwm11 node to rv1126 Add pwm11 node for Rockchip RV1126. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230731103518.2906147-6-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rv1126.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi index 0b2d3e2ee553..9ccd1bad6229 100644 --- a/arch/arm/boot/dts/rockchip/rv1126.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -287,6 +287,17 @@ dmac: dma-controller@ff4e0000 { clock-names = "apb_pclk"; }; + pwm11: pwm@ff550030 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff550030 0x10>; + clock-names = "pwm", "pclk"; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + pinctrl-0 = <&pwm11m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + uart0: serial@ff560000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff560000 0x100>; From ef4907deff89dd547c8fdfe4fdd4bbfe6b4446d8 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Jul 2023 16:05:14 +0530 Subject: [PATCH 06/10] ARM: dts: rockchip: Enable pwm fan for edgeble-neu2 Edgeble Neu2 IO board Fan connected to PWM11. Enable the pwm fan for it. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230731103518.2906147-10-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts index 3d587602e13a..f09be8405964 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts @@ -88,6 +88,10 @@ eth_phy_rst: eth-phy-rst { }; }; +&pwm11 { + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; From 9107283badc7d058e34ef3b60a52afe6a5e0acfb Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 29 Aug 2023 23:40:03 +0200 Subject: [PATCH 07/10] ARM: dts: rockchip: Add SRAM node for RK3128 RK3128 SoCs have 8KB of SRAM. Add the respective device tree node for it. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20230829214004.314932-4-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index b63bd4ad3143..3a0856973795 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -76,6 +76,14 @@ xin24m: oscillator { #clock-cells = <0>; }; + imem: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x2000>; + }; + pmu: syscon@100a0000 { compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; reg = <0x100a0000 0x1000>; From 02941bc2a1bc8ea82617ba1fd4d2c0643399a9ea Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 29 Aug 2023 23:40:05 +0200 Subject: [PATCH 08/10] ARM: dts: rockchip: Add CPU resets for RK3128 In order to support bring-up of the non-boot cores, this patch adds the reset controls for the cpu cores. They are required/will be used by the Rockchip platsmp driver. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20230829214004.314932-6-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index 3a0856973795..2778049003a1 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -34,6 +34,7 @@ cpu0: cpu@f00 { reg = <0xf00>; clock-latency = <40000>; clocks = <&cru ARMCLK>; + resets = <&cru SRST_CORE0>; operating-points = < /* KHz uV */ 816000 1000000 @@ -45,18 +46,21 @@ cpu1: cpu@f01 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf01>; + resets = <&cru SRST_CORE1>; }; cpu2: cpu@f02 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf02>; + resets = <&cru SRST_CORE2>; }; cpu3: cpu@f03 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf03>; + resets = <&cru SRST_CORE3>; }; }; From da8b973957ca03f05f78384f2bf6d79a3fce9fb0 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 29 Aug 2023 23:40:07 +0200 Subject: [PATCH 09/10] ARM: dts: rockchip: Enable SMP bring-up for RK3128 For bring-up of the non-boot cpu cores the enable-method for RK3036 can be re-used. This adds a (small) chunk of SRAM for execution of the SMP trampoline code and the respective enable-method property to the cpus. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20230829214004.314932-8-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index 2778049003a1..877854dd765d 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -27,6 +27,7 @@ arm-pmu { cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "rockchip,rk3036-smp"; cpu0: cpu@f00 { device_type = "cpu"; @@ -86,6 +87,11 @@ imem: sram@10080000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x10080000 0x2000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x00 0x10>; + }; }; pmu: syscon@100a0000 { From c96b13d7c0e494e1072648301e61e13a2a85a362 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 29 Aug 2023 23:40:09 +0200 Subject: [PATCH 10/10] ARM: dts: rockchip: Switch to operating-points-v2 for RK3128's CPU This will allow frequency-scaling for the cpu-cores. Operating frequencies and voltages have been taken from Rockchip's downstream kernel. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20230829214004.314932-10-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 43 +++++++++++++++++++++++--- 1 file changed, 39 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index 877854dd765d..71964262cd5f 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -36,10 +36,7 @@ cpu0: cpu@f00 { clock-latency = <40000>; clocks = <&cru ARMCLK>; resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; + operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ }; @@ -48,6 +45,7 @@ cpu1: cpu@f01 { compatible = "arm,cortex-a7"; reg = <0xf01>; resets = <&cru SRST_CORE1>; + operating-points-v2 = <&cpu_opp_table>; }; cpu2: cpu@f02 { @@ -55,6 +53,7 @@ cpu2: cpu@f02 { compatible = "arm,cortex-a7"; reg = <0xf02>; resets = <&cru SRST_CORE2>; + operating-points-v2 = <&cpu_opp_table>; }; cpu3: cpu@f03 { @@ -62,6 +61,42 @@ cpu3: cpu@f03 { compatible = "arm,cortex-a7"; reg = <0xf03>; resets = <&cru SRST_CORE3>; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + cpu_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <950000 950000 1325000>; + }; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000 950000 1325000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000 950000 1325000>; + }; + opp-696000000 { + opp-hz = /bits/ 64 <696000000>; + opp-microvolt = <975000 975000 1325000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1075000 1075000 1325000>; + opp-suspend; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1200000 1200000 1325000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1325000 1325000 1325000>; }; };