github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-11-06 21:58:01 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

Pin control bulk changes for the v7.4 kernel cycle:

Browse Source 
Core changes:
 
 - Support input-debounce-ns pin config property.
 
 New drivers:
 
 - Qualcomm:
 
   - Hawi SoC TLMM and LPASS LPI TLMM.
 
   - Kuno (ARM32!) SoC TLMM.
 
   - MSM8952 SoC TLMM.
 
   - PMAU0102 SPMIO GPIO.
 
 - Starfive JHB100 SoC sys0, sys0h, sys1, sys2, per0, per1,
   per2 per2pok and per3 (apparently strongly modularized silicon).
 
 - Ambarella CV75.
 
 - Apple T8140 SoC used in iPhone 16 [Pro] and MacBook Neo.
 
 - Econet EN7528.
 
 - Allwinner Sunxi A733.
 
 - Mediatek MT6735.
 
 Improvements:
 
 - Renesas RZ/3GL: SD channel PoC, I2C power source etc.
 
 - The SCMI pin controller uses generic helpers for handling
   groups and functions.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmrafwgACgkQQRCzN7AZ
 XXNccg/9HoXbLL1lS1YOaEdY2UQR7bzXJpnh48uwDgp3wMkxJuKSoZCpdUV7BNiP
 P1+qGAr+exNuJeZItRfNsyezsu7vSv9tWTOizycW5HsXzBjLuX/4FQs4v6UmCf7i
 bUBeIVM1u3hYC57lTPH7bJTQT0sB5Gu0J7NnvHHWWigNODLDLc9TkFfiel1PfRAT
 0CYLpjuQ0W4/mA/FSOh7YMFMEpgK0Vr6iz9CQ2VP4IqhFf/zCEBT3H15zBHnkD7S
 kyw6ZJlsjO8cYoNQfDr+SSMC8m756IUs/UmrFeiHnTk1ekb6GdBgCavW+K1O7Org
 o4iVhwopKxuzb0xpRcZBmpIJDuMP7TERoKDpoR01yoOELxvwM9y04fp6yZpALzby
 baSXfW82NBFq6FTnqL+JfVTiBS0Kzh89irt2RJsSdXbkYYhk1TUF+cwmfuPEvR2E
 V1FcTlF0TiLOStli9cMOd7IL7jlJj99xnKTAfAgWBIolKbjRKPU8/OYo16BC4f7p
 niNBo96Lu6UBLWE6xnsQZ8TPzHYqaugL7JMay4KI5yZS8ZcjwfiYluVFLeMnUzBX
 kT6asASSxw67gMBpKw2ppYh6/+Ddc9ZljFQZY6aWwvhXPxI0h6aM+2wkP5/dvhow
 gZShW4Xosr9cPq/vtrqr/mSwvy1+jbpJ4LhkqAofgxT9060VpVo=
 =zD2E
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v7.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "Nothing special really, some new drivers, the usual trickle of fixes.

  Oddly not even vary many LLM-assisted fixes, I guess they haven't
  found their way into this subsystem yet.

  Core changes:

   - Support input-debounce-ns pin config property.

  New drivers:

   - Qualcomm:
       - Hawi SoC TLMM and LPASS LPI TLMM
       - Kuno (ARM32!) SoC TLMM
       - MSM8952 SoC TLMM
       - PMAU0102 SPMIO GPIO

   - Starfive JHB100 SoC sys0, sys0h, sys1, sys2, per0, per1,
     per2 per2pok and per3 (apparently strongly modularized silicon)

   - Ambarella CV75

   - Apple T8140 SoC used in iPhone 16 [Pro] and MacBook Neo

   - Econet EN7528

   - Allwinner Sunxi A733

   - Mediatek MT6735

  Improvements:

   - Renesas RZ/3GL: SD channel PoC, I2C power source etc

   - The SCMI pin controller uses generic helpers for handling
     groups and functions"

* tag 'pinctrl-v7.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits)
  pinctrl: stm32: program the EXTI mux from .alloc instead of .activate
  pinctrl: stm32: Fix the unit of the hwspinlock timeout
  pinctrl: stm32: Fix fwnode reference leak in stm32_gpiolib_register_bank()
  dt-bindings: pinctrl: brcm,nsp-gpio: Convert to DT schema
  pinctrl: mediatek: Add MT6735 pinctrl driver
  dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Add bindings for MT6735 pin controller
  dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Document MT6765 pin controller
  dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Add MT6795
  dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Improve pinctrl subnode and property descriptions
  dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Pull pinctrl node changes from MT6795 document
  pinctrl: tegra: xusb: free maps on DT map failure
  pinctrl: sprd: free maps on DT map failure
  pinctrl: kconfig: Select generic pinctrl helpers for scmi pinctrl
  pinctrl: scmi: Replace pinctrl ops get group info with generics
  pinctrl: scmi: Replace pinmux ops get function info with generics
  pinctrl: ambarella: fix NULL vs IS_ERR() bug in amb_pinctrl_register()
  pinctrl: starfive: fix missing CONFIG_OF dependencies
  pinctrl: ambarella: add CONFIG_OF dependency
  pinctrl: apple: Add t8140-pinctrl support
  dt-bindings: pinctrl: apple,pinctrl: Add t8140 compatible
  ...
This commit is contained in:
Linus Torvalds 2026-10-24 19:44:48 -10:00
commit a8c2facb7b
130 changed files with 18652 additions and 1646 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml
View File

@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/pinctrl/allwinner,sun55i-a523-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A523 Pin Controller
title: Allwinner A523 & A733 Pin Controller
maintainers:
- Andre Przywara <andre.przywara@arm.com>
@ -28,6 +28,8 @@ properties:
enum:
- allwinner,sun55i-a523-pinctrl
- allwinner,sun55i-a523-r-pinctrl
- allwinner,sun60i-a733-pinctrl
- allwinner,sun60i-a733-r-pinctrl
reg:
maxItems: 1
@ -126,6 +128,7 @@ allOf:
compatible:
enum:
- allwinner,sun55i-a523-pinctrl
- allwinner,sun60i-a733-pinctrl
then:
properties:
@ -138,6 +141,7 @@ allOf:
compatible:
enum:
- allwinner,sun55i-a523-r-pinctrl
- allwinner,sun60i-a733-r-pinctrl
then:
properties:

237
Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml Normal file
View File

@ -0,0 +1,237 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/ambarella,cv75-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ambarella CV75 Pin Controller
maintainers:
- Long Zhao <longzhao@ambarella.com>
description:
The Ambarella CV75 pin controller configures pin multiplexing, bias and
drive strength for the main GPIO banks. Pin groups and their mux settings
are defined by the pin controller driver and selected by function and group
names.
allOf:
- $ref: pinctrl.yaml#
properties:
compatible:
const: ambarella,cv75-pinctrl
reg:
maxItems: 1
description: IOMUX registers
ambarella,drive-strength-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description: RCT syscon containing the drive-strength registers.
ambarella,pull-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description: Secure scratchpad syscon containing the pull registers.
patternProperties:
"^[a-z0-9-]+-pins$":
type: object
allOf:
- $ref: pinmux-node.yaml#
- $ref: pincfg-node.yaml#
additionalProperties: false
properties:
function:
enum:
- can0
- can1
- dmic0
- enet0
- hsync0
- hsync1
- i2c0
- i2c1
- i2c2
- i2c3
- i2cs
- i2s0
- i2s1
- ir
- pwm0
- pwm1
- pwm2
- pwm3
- pwm4
- pwm5
- pwm6
- pwm7
- pwm8
- pwm9
- pwm10
- pwm11
- sdmmc0
- sdmmc1
- snand
- spi0
- spi1
- spi2
- spi3
- spi_slave
- spinor
- uart0
- uart1
- uart2
- uart3
- uart4
- vin_master_sync
- vsync0
- vsync1
- vsync2
- vsync3
- wdt
groups:
items:
enum:
- can0
- can1
- dmic0
- enet_2nd_ref_clk_a
- enet_2nd_ref_clk_b
- enet_ext_osc_clk
- enet0_ptp_pps_o
- hsync0
- hsync1
- i2c0_a
- i2c0_b
- i2c1_a
- i2c1_b
- i2c2
- i2c3_a
- i2c3_b
- i2c3_c
- i2cs_a
- i2cs_b
- i2cs_c
- i2cs_d
- i2s0
- i2s1
- ir
- pwm0
- pwm1
- pwm2
- pwm3
- pwm4_a
- pwm4_b
- pwm5_a
- pwm5_b
- pwm6_a
- pwm6_b
- pwm7_a
- pwm7_b
- pwm8_a
- pwm8_b
- pwm9_a
- pwm9_b
- pwm10_a
- pwm10_b
- pwm11_a
- pwm11_b
- rgmii0
- rmii0
- sdmmc0_1bit
- sdmmc0_4bit
- sdmmc0_cd
- sdmmc0_hs_sel
- sdmmc0_reset
- sdmmc0_wp
- sdmmc1_1bit
- sdmmc1_4bit
- sdmmc1_cd
- sdmmc1_hs_sel
- sdmmc1_reset
- sdmmc1_wp
- snand
- spi0
- spi1
- spi2
- spi3_a
- spi3_b
- spi3_c
- spi_slave_a
- spi_slave_b
- spi_slave_c
- spi_slave_d
- spi_slave_e
- spinor
- uart0
- uart1
- uart1_flow
- uart2_a
- uart2_b
- uart2_c
- uart2_flow_a
- uart2_flow_b
- uart3_a
- uart3_b
- uart3_flow_a
- uart3_flow_b
- uart4_a
- uart4_b
- uart4_flow_a
- uart4_flow_b
- vin_master_sync_a
- vin_master_sync_b
- vin_master_sync_c
- vin_master_sync_d
- vin_master_sync_e
- vsync0
- vsync1
- vsync2
- vsync3
- wdt_a
- wdt_b
- wdt_c
- wdt_d
- wdt_e
- wdt_f
minItems: 1
maxItems: 6
uniqueItems: true
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength:
enum: [3, 4, 5, 6, 7, 8, 9, 12]
required:
- function
- groups
required:
- compatible
- reg
- ambarella,drive-strength-syscon
- ambarella,pull-syscon
unevaluatedProperties: false
examples:
- |
pinctrl: pinctrl@e4010000 {
compatible = "ambarella,cv75-pinctrl";
reg = <0xe4010000 0x1000>;
ambarella,drive-strength-syscon = <&rct>;
ambarella,pull-syscon = <&scratchpad>;
uart0-pins {
function = "uart0";
groups = "uart0";
bias-disable;
drive-strength = <8>;
};
};

12
Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml
View File

@ -17,6 +17,7 @@ description: |
properties:
compatible:
oneOf:
- const: apple,t8140-pinctrl
- items:
- enum:
- apple,t6020-pinctrl
@ -52,6 +53,8 @@ properties:
gpio-ranges:
maxItems: 1
gpio-reserved-ranges: true
apple,npins:
$ref: /schemas/types.yaml#/definitions/uint32
description: The number of pins in this GPIO controller.
@ -90,6 +93,15 @@ patternProperties:
allOf:
- $ref: pinctrl.yaml#
- if:
not:
properties:
compatible:
contains:
const: apple,t8140-pinctrl
then:
properties:
gpio-reserved-ranges: false
required:
- compatible

50
Documentation/devicetree/bindings/pinctrl/awinic,aw9523-pinctrl.yaml
View File

@ -108,32 +108,32 @@ examples:
#size-cells = <0>;
aw9523: gpio-expander@58 {
compatible = "awinic,aw9523-pinctrl";
reg = <0x58>;
interrupt-parent = <&tlmm>;
interrupts = <50 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 16>;
interrupt-controller;
#interrupt-cells = <2>;
reset-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
compatible = "awinic,aw9523-pinctrl";
reg = <0x58>;
interrupt-parent = <&tlmm>;
interrupts = <50 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 16>;
interrupt-controller;
#interrupt-cells = <2>;
reset-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
keyboard-matrix-col-pins {
pins = "gpio8", "gpio9", "gpio10", "gpio11",
"gpio12", "gpio13", "gpio14", "gpio15";
function = "gpio";
input-disable;
output-low;
};
keyboard-matrix-col-pins {
pins = "gpio8", "gpio9", "gpio10", "gpio11",
"gpio12", "gpio13", "gpio14", "gpio15";
function = "gpio";
input-disable;
output-low;
};
keyboard-matrix-row-pins {
pins = "gpio0", "gpio1", "gpio2", "gpio3",
"gpio4", "gpio5", "gpio6", "gpio7";
function = "gpio";
bias-pull-up;
drive-open-drain;
input-enable;
};
keyboard-matrix-row-pins {
pins = "gpio0", "gpio1", "gpio2", "gpio3",
"gpio4", "gpio5", "gpio6", "gpio7";
function = "gpio";
bias-pull-up;
drive-open-drain;
input-enable;
};
};
};

80
Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt
View File

@ -1,80 +0,0 @@
Broadcom Northstar plus (NSP) GPIO/PINCONF Controller
Required properties:
- compatible:
Must be "brcm,nsp-gpio-a"
- reg:
Should contain the register physical address and length for each of
GPIO base, IO control registers
- #gpio-cells:
Must be two. The first cell is the GPIO pin number (within the
controller's pin space) and the second cell is used for the following:
bit[0]: polarity (0 for active high and 1 for active low)
- gpio-controller:
Specifies that the node is a GPIO controller
- ngpios:
Number of gpios supported (58x25 supports 32 and 58x23 supports 24)
Optional properties:
- interrupts:
Interrupt ID
- interrupt-controller:
Specifies that the node is an interrupt controller
- gpio-ranges:
Specifies the mapping between gpio controller and pin-controllers pins.
This requires 4 fields in cells defined as -
1. Phandle of pin-controller.
2. GPIO base pin offset.
3 Pin-control base pin offset.
4. number of gpio pins which are linearly mapped from pin base.
Supported generic PINCONF properties in child nodes:
- pins:
The list of pins (within the controller's own pin space) that properties
in the node apply to. Pin names are "gpio-<pin>"
- bias-disable:
Disable pin bias
- bias-pull-up:
Enable internal pull up resistor
- bias-pull-down:
Enable internal pull down resistor
- drive-strength:
Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA)
Example:
gpioa: gpio@18000020 {
compatible = "brcm,nsp-gpio-a";
reg = <0x18000020 0x100>,
<0x1803f1c4 0x1c>;
#gpio-cells = <2>;
gpio-controller;
ngpios = <32>;
gpio-ranges = <&pinctrl 0 0 31>;
interrupt-controller;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
/* Hog a few default settings */
pinctrl-names = "default";
pinctrl-0 = <&led>;
led: led {
pins = "gpio-1";
bias-pull-up;
};
pwr: pwr {
gpio-hog;
gpios = <3 1>;
output-high;
};
};

130
Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.yaml Normal file
View File

@ -0,0 +1,130 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,nsp-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Northstar Plus (NSP) GPIO/PINCONF Controller
maintainers:
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
description: |
The chipCommonA GPIO block also provides generic pin configuration for the
pins it controls: bias, pull up/down, slew rate and drive strength. Pin
configuration is described in '-pins' child nodes, referenced through the
standard pinctrl-0/pinctrl-names properties. Child nodes named '*-hog' are
treated as GPIO hogs.
properties:
compatible:
const: brcm,nsp-gpio-a
reg:
items:
- description: GPIO base registers
- description: IO control registers
"#gpio-cells":
const: 2
description: |
The first cell is the GPIO pin number (within the controller's pin
space) and the second cell is used for the following:
bit[0]: polarity (0 for active high and 1 for active low)
gpio-controller: true
ngpios:
description: Number of GPIOs supported (58x25 supports 32 and 58x23 supports 24)
maximum: 32
interrupts:
maxItems: 1
"#interrupt-cells":
const: 2
interrupt-controller: true
gpio-ranges: true
gpio-line-names: true
required:
- compatible
- reg
- "#gpio-cells"
- gpio-controller
- ngpios
dependencies:
interrupt-controller: ['#interrupt-cells']
patternProperties:
'-pins$':
type: object
$ref: pincfg-node.yaml#
properties:
pins:
$ref: /schemas/types.yaml#/definitions/string-array
items:
pattern: '^gpio-'
bias-disable: true
bias-pull-up: true
bias-pull-down: true
drive-strength:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ]
slew-rate:
description: 0 disables and 1 enables slew rate control
enum: [ 0, 1 ]
required:
- pins
additionalProperties: false
'-hog(-[0-9]+)?$':
type: object
required:
- gpio-hog
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpio@18000020 {
compatible = "brcm,nsp-gpio-a";
reg = <0x18000020 0x100>,
<0x1803f1c4 0x1c>;
#gpio-cells = <2>;
gpio-controller;
ngpios = <32>;
gpio-ranges = <&pinctrl 0 0 31>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
led_pins: led-pins {
pins = "gpio-1";
bias-pull-up;
drive-strength = <16>;
};
/* GPIO hog */
pwr-hog {
gpio-hog;
gpios = <3 1>;
output-high;
};
};

2
Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml
View File

@ -86,6 +86,6 @@ examples:
pinmux = <CIX_PAD_GPIO012_FUNC_GPIO012>;
bias-pull-up;
drive-strength = <8>;
};
};
};
};

190
Documentation/devicetree/bindings/pinctrl/econet,en7528-pinctrl.yaml Normal file
View File

@ -0,0 +1,190 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/econet,en7528-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: EcoNet EN7528 Pin Controller
maintainers:
- Lorenzo Bianconi <lorenzo@kernel.org>
description:
The EcoNet EN7528 pin controller is used to control SoC pins. It shares the
IP with the Airoha pin controllers, but its IOMUX and pin configuration
registers have a different layout.
properties:
compatible:
const: econet,en7528-pinctrl
airoha,chip-scu:
description: phandle to the chip SCU syscon
$ref: /schemas/types.yaml#/definitions/phandle
interrupts:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
patternProperties:
'-pins$':
type: object
patternProperties:
'^mux(-|$)':
type: object
description:
pinmux configuration nodes.
$ref: /schemas/pinctrl/pinmux-node.yaml
properties:
function:
description:
A string containing the name of the function to mux to the group.
enum: [gpio, jtag, pcie_reset, pcm, pcm_spi, phy1_led0,
phy1_led1, phy2_led0, phy2_led1, phy3_led0, phy3_led1,
phy4_led0, phy4_led1, pnand, pon, pwm, sipo, spi, uart]
groups:
description:
An array of strings. Each string contains the name of a group.
items:
enum: [pon, sipo, sipo_rclk, uart2, uart2_cts_rts, uart3,
ejtag, pcm1, pcm2, spi_quad, spi_cs1, pcm_spi,
pcm_spi_int, pcm_spi_rst, pcm_spi_cs1, pcm_spi_cs2,
pcm_spi_cs3, pcm_spi_cs4, pcm_spi_cs5, pcm_spi_cs6,
pcm_spi_cs7, pnand, gpio0, gpio1, gpio2, gpio3, gpio4,
gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11,
gpio12, gpio13, gpio14, gpio15, gpio16, gpio17,
gpio18, gpio19, gpio20, gpio21, gpio22, gpio23,
gpio24, gpio25, gpio26, gpio27, gpio28, gpio29,
gpio30, gpio31, gpio32, gpio33, gpio34, gpio35,
gpio36, gpio37, gpio38, gpio39, gpio40, gpio41,
pcie_reset0, pcie_reset1]
required:
- function
- groups
additionalProperties: false
'^conf(-|$)':
type: object
description:
pinconf configuration nodes.
$ref: /schemas/pinctrl/pincfg-node.yaml
properties:
pins:
description:
An array of strings. Each string contains the name of a pin.
items:
enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6,
gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13,
gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
gpio20, gpio21, gpio22, gpio23, gpio24, gpio25,
gpio26, gpio27, gpio28, gpio29, gpio30, gpio31,
gpio32, gpio33, gpio34, gpio35, gpio36, gpio37,
gpio38, gpio39, pcie_reset0, pcie_reset1, i2c_sda,
i2c_scl, uart_txd, uart_rxd, spi_cs0, spi_clk,
spi_mosi, spi_miso]
minItems: 1
maxItems: 50
bias-disable: true
bias-pull-up: true
bias-pull-down: true
input-enable: true
output-enable: true
output-low: true
output-high: true
drive-strength:
description:
Selects the drive strength for the pin, in mA.
enum: [2, 4]
required:
- pins
additionalProperties: false
additionalProperties: false
required:
- compatible
- airoha,chip-scu
- interrupts
- gpio-controller
- gpio-ranges
- "#gpio-cells"
- interrupt-controller
- "#interrupt-cells"
allOf:
- $ref: pinctrl.yaml#
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
pinctrl {
compatible = "econet,en7528-pinctrl";
airoha,chip-scu = <&chip_scu>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 10 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pinctrl 0 0 42>;
uart2-pins {
mux {
function = "uart";
groups = "uart2";
};
conf {
pins = "gpio28", "gpio29";
bias-pull-up;
};
};
pwm-pins {
mux {
function = "pwm";
groups = "gpio30";
};
};
};

4
Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml
View File

@ -179,7 +179,7 @@ examples:
pinctrl_uart4: uart4grp {
fsl,pins =
<0x288 0x658 0x000 0x3 0x0 0x140>,
<0x28c 0x65c 0x938 0x3 0x3 0x140>;
<0x288 0x658 0x000 0x3 0x0 0x140>,
<0x28c 0x65c 0x938 0x3 0x3 0x140>;
};
};

12
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml
View File

@ -95,8 +95,8 @@ examples:
pinctrl_uart5: uart5grp {
fsl,pins =
<0x0160 0x03D0 0x0714 0x1 0x0 0x7e>,
<0x0164 0x03D4 0x0000 0x1 0x0 0x76>;
<0x0160 0x03D0 0x0714 0x1 0x0 0x7e>,
<0x0164 0x03D4 0x0000 0x1 0x0 0x76>;
};
};
- |
@ -106,8 +106,8 @@ examples:
fsl,input-sel = <&iomuxc>;
pinctrl_gpio_lpsr: gpio1-grp {
fsl,pins =
<0x0008 0x0038 0x0000 0x0 0x0 0x59>,
<0x000C 0x003C 0x0000 0x0 0x0 0x59>;
};
fsl,pins =
<0x0008 0x0038 0x0000 0x0 0x0 0x59>,
<0x000C 0x003C 0x0000 0x0 0x0 0x59>;
};
};

4
Documentation/devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml
View File

@ -82,8 +82,8 @@ examples:
pinctrl_uart2: uart2grp {
fsl,pins =
<0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
<0x240 0x4A8 0x000 0x0 0x0 0x140>;
<0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
<0x240 0x4A8 0x000 0x0 0x0 0x140>;
};
};

4
Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml
View File

@ -74,8 +74,8 @@ examples:
pinctrl_lpuart5: lpuart5grp {
fsl,pins =
<0x0138 0x08F0 0x4 0x3 0x3>,
<0x013C 0x08EC 0x4 0x3 0x3>;
<0x0138 0x08F0 0x4 0x3 0x3>,
<0x013C 0x08EC 0x4 0x3 0x3>;
};
};

4
Documentation/devicetree/bindings/pinctrl/fsl,imx9-pinctrl.yaml
View File

@ -78,8 +78,8 @@ examples:
pinctrl_uart3: uart3grp {
fsl,pins =
<0x48 0x1f8 0x41c 0x1 0x0 0x49>,
<0x4c 0x1fc 0x418 0x1 0x0 0x49>;
<0x48 0x1f8 0x41c 0x1 0x0 0x49>,
<0x4c 0x1fc 0x418 0x1 0x0 0x49>;
};
};

4
Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml
View File

@ -73,7 +73,7 @@ examples:
pinctrl_lpuart1: lpuart1grp {
fsl,pins =
<0x0EC 0x2DC 0x000 0x2 0x0 0xf1>,
<0x0F0 0x2E0 0x000 0x2 0x0 0xf1>;
<0x0EC 0x2DC 0x000 0x2 0x0 0xf1>,
<0x0F0 0x2E0 0x000 0x2 0x0 0xf1>;
};
};

4
Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml
View File

@ -71,7 +71,7 @@ examples:
reg = <0x400e8000 0x4000>;
pinctrl_lpuart1: lpuart1grp {
fsl,pins =
<0x16C 0x3B0 0x620 0x0 0x0 0xf1>,
<0x170 0x3B4 0x61C 0x0 0x0 0xf1>;
<0x16C 0x3B0 0x620 0x0 0x0 0xf1>,
<0x170 0x3B4 0x61C 0x0 0x0 0xf1>;
};
};

14
Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml
View File

@ -64,13 +64,13 @@ examples:
reg = <0xe2880000 0x100000>;
uart0-pins {
pins = <64>, /* UART_RX0 */
<65>; /* UART_TX0 */
function = "CONSOLE_UART0";
pinmux = <1>,
<1>;
groups = "CONSOLE_UART0";
};
pins = <64>, /* UART_RX0 */
<65>; /* UART_TX0 */
function = "CONSOLE_UART0";
pinmux = <1>,
<1>;
groups = "CONSOLE_UART0";
};
};
...

194
Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
View File

@ -8,7 +8,9 @@ title: MediaTek MT6779 Pin Controller
maintainers:
- Andy Teng <andy.teng@mediatek.com>
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
- Sean Wang <sean.wang@kernel.org>
- Yassine Oudjana <y.oudjana@protonmail.com>
description:
The MediaTek pin controller on MT6779 is used to control pin functions, pull
@ -17,7 +19,11 @@ description:
properties:
compatible:
enum:
- mediatek,mt6735-pinctrl
- mediatek,mt6735m-pinctrl
- mediatek,mt6765-pinctrl
- mediatek,mt6779-pinctrl
- mediatek,mt6795-pinctrl
- mediatek,mt6797-pinctrl
reg:
@ -59,6 +65,77 @@ required:
allOf:
- $ref: pinctrl.yaml#
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt6735-pinctrl
- mediatek,mt6735m-pinctrl
then:
properties:
reg:
minItems: 8
maxItems: 8
reg-names:
items:
- const: gpio
- const: iocfg0
- const: iocfg1
- const: iocfg2
- const: iocfg3
- const: iocfg4
- const: iocfg5
- const: eint
interrupts:
items:
- description: EINT interrupt
patternProperties:
'-pins$':
patternProperties:
'^pins':
properties:
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
- if:
properties:
compatible:
contains:
const: mediatek,mt6765-pinctrl
then:
properties:
reg:
minItems: 9
maxItems: 9
reg-names:
items:
- const: iocfg0
- const: iocfg1
- const: iocfg2
- const: iocfg3
- const: iocfg4
- const: iocfg5
- const: iocfg6
- const: iocfg7
- const: eint
interrupts:
items:
- description: EINT interrupt
patternProperties:
'-pins$':
patternProperties:
'^pins':
properties:
drive-strength:
enum: [1, 2, 4, 16]
- if:
properties:
compatible:
@ -81,6 +158,45 @@ allOf:
- const: iocfg_lt
- const: iocfg_tl
- const: eint
patternProperties:
'-pins$':
patternProperties:
'^pins':
properties:
drive-strength:
enum: [2, 4, 8, 12, 16]
- if:
properties:
compatible:
contains:
const: mediatek,mt6795-pinctrl
then:
properties:
reg:
minItems: 2
maxItems: 2
reg-names:
items:
- const: base
- const: eint
interrupts:
minItems: 1
items:
- description: EINT interrupt
- description: EINT event_b interrupt
patternProperties:
'-pins$':
patternProperties:
'^pins':
properties:
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
- if:
properties:
compatible:
@ -99,6 +215,15 @@ allOf:
- const: iocfgb
- const: iocfgr
- const: iocfgt
patternProperties:
'-pins$':
patternProperties:
'^pins':
properties:
drive-strength:
enum: [2, 4, 8, 12, 16]
- if:
properties:
reg-names:
@ -111,33 +236,52 @@ allOf:
- "#interrupt-cells"
patternProperties:
'-[0-9]*$':
'-pins$':
type: object
additionalProperties: false
patternProperties:
'-pins*$':
'^pins':
type: object
description:
A pinctrl node should contain at least one subnodes representing the
A pinctrl node should contain at least one subnode representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
$ref: /schemas/pinctrl/pincfg-node.yaml
pins it needs, and how they should be configured, with regard to
muxer configuration, pullups, drive strength, input enable/disable
and input schmitt.
allOf:
- $ref: pinmux-node.yaml
- $ref: pincfg-node.yaml
properties:
pinmux:
description:
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
directly.
bias-disable: true
bias-pull-up: true
bias-pull-up:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: Pull up PUPD/R0/R1 type define value.
description:
For normal pull up type, it is not necessary to specify R1R0
values; When pull up type is PUPD/R0/R1, adding R1R0 defines
will set different resistance values.
bias-pull-down: true
bias-pull-down:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: Pull down PUPD/R0/R1 type define value.
description:
For normal pull down type, it is not necessary to specify R1R0
values; When pull down type is PUPD/R0/R1, adding R1R0 defines
will set different resistance values.
input-enable: true
@ -151,10 +295,14 @@ patternProperties:
input-schmitt-disable: true
drive-strength:
enum: [2, 4, 8, 12, 16]
drive-strength: true
slew-rate:
description: |
Set the slew rate. Valid arguments are described as below:
0: Normal slew rate
1: Slower slew
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
mediatek,pull-up-adv:
@ -221,8 +369,8 @@ examples:
#interrupt-cells = <2>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
mmc0_pins_default: mmc0-0 {
cmd-dat-pins {
mmc0_pins_default: mmc0-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
@ -235,14 +383,28 @@ examples:
input-enable;
mediatek,pull-up-adv = <1>;
};
clk-pins {
pins-clk {
pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
mediatek,pull-down-adv = <2>;
};
rst-pins {
pins-rst {
pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
mediatek,pull-up-adv = <0>;
};
};
/* GPIO0 set as multifunction GPIO0 */
gpio-pins {
pins {
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
};
};
/* GPIO52 set as multifunction SDA0 */
i2c0-pins {
pins {
pinmux = <PINMUX_GPIO52__FUNC_SDA0>;
};
};
};
};

236
Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml
View File

@ -1,236 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT6795 Pin Controller
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
- Sean Wang <sean.wang@kernel.org>
description:
The MediaTek's MT6795 Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt6795-pinctrl
gpio-controller: true
'#gpio-cells':
description:
Number of cells in GPIO specifier. Since the generic GPIO binding is used,
the amount of cells must be specified as 2. See the below mentioned gpio
binding representation for description of particular cells.
const: 2
gpio-ranges:
description: GPIO valid number range.
maxItems: 1
reg:
description:
Physical address base for GPIO base and eint registers.
minItems: 2
reg-names:
items:
- const: base
- const: eint
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
description: Interrupt outputs to the system interrupt controller (sysirq).
minItems: 1
items:
- description: EINT interrupt
- description: EINT event_b interrupt
# PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
additionalProperties: false
patternProperties:
'^pins':
type: object
additionalProperties: false
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
An example of using macro:
pincontroller {
/* GPIO0 set as multifunction GPIO0 */
gpio-pins {
pins {
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
}
};
/* GPIO45 set as multifunction SDA0 */
i2c0-pins {
pins {
pinmux = <PINMUX_GPIO45__FUNC_SDA0>;
}
};
};
$ref: pinmux-node.yaml
properties:
pinmux:
description:
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
bias-pull-down:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: mt6795 pull down PUPD/R0/R1 type define value.
description:
For normal pull down type, it is not necessary to specify R1R0
values; When pull down type is PUPD/R0/R1, adding R1R0 defines
will set different resistance values.
bias-pull-up:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: mt6795 pull up PUPD/R0/R1 type define value.
description:
For normal pull up type, it is not necessary to specify R1R0
values; When pull up type is PUPD/R0/R1, adding R1R0 defines will
set different resistance values.
bias-disable: true
output-high: true
output-low: true
input-enable: true
input-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
mediatek,pull-up-adv:
description: |
Pull up settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as
below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,pull-down-adv:
description: |
Pull down settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as
below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
slew-rate:
description: |
Set the slew rate. Valid arguments are described as below:
0: Normal slew rate
1: Slower slew
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
required:
- pinmux
allOf:
- $ref: pinctrl.yaml#
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pio: pinctrl@10005000 {
compatible = "mediatek,mt6795-pinctrl";
reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
reg-names = "base", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 196>;
interrupt-controller;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
i2c0-pins {
pins-sda-scl {
pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
<PINMUX_GPIO46__FUNC_SCL0>;
};
};
mmc0-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO155__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO156__FUNC_MSDC0_DAT2>,
<PINMUX_GPIO157__FUNC_MSDC0_DAT3>,
<PINMUX_GPIO158__FUNC_MSDC0_DAT4>,
<PINMUX_GPIO159__FUNC_MSDC0_DAT5>,
<PINMUX_GPIO160__FUNC_MSDC0_DAT6>,
<PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO162__FUNC_MSDC0_CMD>;
input-enable;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
};
};
};

4
Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml
View File

@ -221,8 +221,8 @@ examples:
i2c0_pins_a: i2c0-pins {
pins1 {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
drive-strength-microamp = <1000>;
};

2
Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml
View File

@ -234,7 +234,7 @@ examples:
- |
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#
pio: pinctrl@10005000 {
compatible = "mediatek,mt8195-pinctrl";
reg = <0x10005000 0x1000>,

11
Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
View File

@ -104,6 +104,10 @@ properties:
description: Takes the debounce time in usec as argument or 0 to disable
debouncing
input-debounce-ns:
description: Takes the debounce time in nsec as argument or 0 to disable
debouncing
power-source:
$ref: /schemas/types.yaml#/definitions/uint32
description: select between different power supplies
@ -214,6 +218,13 @@ allOf:
input-schmitt-enable: false
input-schmitt-microvolt: false
- if:
required:
- input-debounce
then:
properties:
input-debounce-ns: false
- if:
required:
- drive-strength

105
Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt
View File

@ -1,105 +0,0 @@
Palmas Pincontrol bindings
The pins of Palmas device can be set on different option and provides
the configuration for Pull UP/DOWN, open drain etc.
Required properties:
- compatible: It must be one of following:
- "ti,palmas-pinctrl" for Palma series of the pincontrol.
- "ti,tps65913-pinctrl" for Palma series device TPS65913.
- "ti,tps80036-pinctrl" for Palma series device TPS80036.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Palmas's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
list of pins. This configuration can include the mux function to select on
those pin(s), and various pin configuration parameters, such as pull-up,
open drain.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
Optional properties:
- ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode.
Selection primary or secondary function associated to I2C2_SCL_SCE,
I2C2_SDA_SDO pin/pad for DVFS1 interface
- ti,palmas-enable-dvfs2: Enable DVFS2. Configure pins for DVFS2 mode.
Selection primary or secondary function associated to GPADC_START
and SYSEN2 pin/pad for DVFS2 interface
- ti,palmas-override-powerhold: This is applicable for PMICs for which
GPIO7 is configured in POWERHOLD mode which has higher priority
over DEV_ON bit and keeps the PMIC supplies on even after the DEV_ON
bit is turned off. This property enables driver to over ride the
POWERHOLD value to GPIO7 so as to turn off the PMIC in power off
scenarios. So for GPIO7 if ti,palmas-override-powerhold is set
then the GPIO_7 field should never be muxed to anything else.
It should be set to POWERHOLD by default and only in case of
power off scenarios the driver will over ride the mux value.
This binding uses the following generic properties as defined in
pinctrl-bindings.txt:
Required: pins
Options: function, bias-disable, bias-pull-up, bias-pull-down,
drive-open-drain.
Note that many of these properties are only valid for certain specific pins.
See the Palmas device datasheet for complete details regarding which pins
support which functionality.
Valid values for pin names are:
gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, gpio9,
gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, vac, powergood,
nreswarm, pwrdown, gpadc_start, reset_in, nsleep, enable1, enable2,
int.
Valid value of function names are:
gpio, led, pwm, regen, sysen, clk32kgaudio, id, vbus_det, chrg_det,
vac, vacok, powergood, usb_psel, msecure, pwrhold, int, nreswarm,
simrsto, simrsti, low_vbat, wireless_chrg1, rcm, pwrdown, gpadc_start,
reset_in, nsleep, enable.
There are 4 special functions: opt0, opt1, opt2 and opt3. If any of these
functions is selected then directly pins register will be written with 0, 1, 2
or 3 respectively if it is valid for that pins or list of pins.
Example:
palmas: tps65913 {
....
pinctrl {
compatible = "ti,tps65913-pinctrl";
ti,palmas-enable-dvfs1;
pinctrl-names = "default";
pinctrl-0 = <&palmas_pins_state>;
palmas_pins_state: pinmux {
gpio0 {
pins = "gpio0";
function = "id";
bias-pull-up;
};
vac {
pins = "vac";
function = "vacok";
bias-pull-down;
};
gpio5 {
pins = "gpio5";
function = "opt0";
drive-open-drain = <1>;
};
};
};
....
};

109
Documentation/devicetree/bindings/pinctrl/qcom,hawi-lpass-lpi-pinctrl.yaml Normal file
View File

@ -0,0 +1,109 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,hawi-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Hawi SoC LPASS LPI TLMM
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
- Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
- Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
description:
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
(LPASS) Low Power Island (LPI) of Qualcomm Hawi SoC.
properties:
compatible:
const: qcom,hawi-lpass-lpi-pinctrl
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
clocks:
items:
- description: LPASS LPR(Low Power Resource) voting clock
- description: LPASS Audio voting clock
clock-names:
items:
- const: lpr
- const: audio
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-hawi-lpass-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-hawi-lpass-state"
additionalProperties: false
$defs:
qcom-hawi-lpass-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
function:
enum: [dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b,
ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk,
i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws,
lpass_lpi_dbg_clk, qca_swr_clk, qca_swr_data, slimbus_clk,
slimbus_data, swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_clk1,
swr_tx_data, va_i2s0_clk, va_i2s0_data, va_i2s0_ws,
wsa2_swr_clk, wsa2_swr_data, wsa_swr_clk, wsa_swr_data]
description:
Specify the alternative function to be configured for the specified
pins.
allOf:
- $ref: qcom,lpass-lpi-common.yaml#
required:
- compatible
- reg
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
lpass_tlmm: pinctrl@7f60000 {
compatible = "qcom,hawi-lpass-lpi-pinctrl";
reg = <0x07f60000 0x20000>;
clocks = <&q6prmcc LPASS_HW_LPR_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "lpr", "audio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 23>;
tx-swr-sleep-clk-state {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
bias-pull-down;
};
};

4
Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml
View File

@ -113,8 +113,8 @@ examples:
#interrupt-cells = <2>;
qup-uart7-state {
pins = "gpio62", "gpio63";
function = "qup1_se7";
pins = "gpio62", "gpio63";
function = "qup1_se7";
};
};
...

4
Documentation/devicetree/bindings/pinctrl/qcom,kaanapali-tlmm.yaml
View File

@ -120,8 +120,8 @@ examples:
#interrupt-cells = <2>;
qup-uart7-state {
pins = "gpio62", "gpio63";
function = "qup1_se7";
pins = "gpio62", "gpio63";
function = "qup1_se7";
};
};
...

110
Documentation/devicetree/bindings/pinctrl/qcom,kuno-tlmm.yaml Normal file
View File

@ -0,0 +1,110 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,kuno-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Kuno TLMM block
maintainers:
- Hardeep Sharma <hardeep.sharma@oss.qualcomm.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm Kuno SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,kuno-tlmm
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 55
gpio-line-names:
maxItems: 110
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-kuno-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-kuno-tlmm-state"
additionalProperties: false
$defs:
qcom-kuno-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9])$"
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, audio_ref_clk, coex_uart, ebi2_lcd_a,
ebi2_lcd_cs, ebi2_lcd_reset, ebi2_lcd_te, emac_mdc, emac_mdio,
emac_pps_in, emac_ptp_aux, emac_ptp_pps, gcc_gp1_clk,
gcc_gp2_clk, gcc_gp3_clk, mi2s0_data0, mi2s0_data1, mi2s0_sck,
mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
mi2s_mclk, nav_gpio, pci_e_rst,
pcie_clkreq_n, pll_bist_sync, pll_clk_aux, qdss_cti_trig0,
qdss_cti_trig1, qdss_cti_trig1_mire, qdss_gpio_traceclk,
qdss_gpio_tracectl,
qup0_se0, qup0_se1, qup0_se2, qup0_se3_mira, qup0_se3_mirb,
qup0_se4, sdc4_clk, sdc4_cmd,
sdc4_data, sdc4_tb_trig, sgmii_phy_intr, spmi_coex_clk,
spmi_coex_data, spmi_vgi_hwevent, uim1_clk, uim1_data,
uim1_present, uim1_reset, usb2phy_ac_en ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@f000000 {
compatible = "qcom,kuno-tlmm";
reg = <0x0f000000 0x400000>;
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 110>;
interrupt-controller;
#interrupt-cells = <2>;
spmi-state {
pins = "gpio78", "gpio79";
function = "spmi_vgi_hwevent";
};
};
...

4
Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml
View File

@ -113,8 +113,8 @@ examples:
#interrupt-cells = <2>;
qup-uart7-state {
pins = "gpio62", "gpio63";
function = "qup1_se7";
pins = "gpio62", "gpio63";
function = "qup1_se7";
};
};
...

146
Documentation/devicetree/bindings/pinctrl/qcom,msm8952-pinctrl.yaml Normal file
View File

@ -0,0 +1,146 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8952-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm MSM8952 TLMM pin controller
maintainers:
- Muzaffer Kadir <muzafferkadir@mainlining.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm MSM8952 SoC.
properties:
compatible:
const: qcom,msm8952-pinctrl
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 66
gpio-line-names:
maxItems: 134
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-msm8952-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-msm8952-tlmm-state"
additionalProperties: false
$defs:
qcom-msm8952-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-3])$"
- enum: [ qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
qdsd_data3, sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk,
sdc2_clk, sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, blsp_uart1, blsp_spi1, adsp_ext, blsp_i2c1, prng_rosc, qdss_cti_trig_out_b0,
qdss_cti_trig_out_a1, blsp_spi2, blsp_uart2, ldo_update, qdss_tracedata_b,
pbs1, pwr_modem_enabled_b, blsp_i2c3, gcc_gp2_clk_b, atest_combodac_to_gpio_native,
ldo_en, blsp_i2c2, gcc_gp1_clk_b, atest_gpsadc_dtest0_native, blsp_spi3,
blsp_uart3, sec_mi2s, pbs0, gcc_gp3_clk_b, blsp_spi4, blsp_uart4, pbs2,
pwr_nav_enabled_b, pwr_crypto_enabled_b, blsp_i2c4, blsp_spi5, blsp_uart5,
qdss_traceclk_a, atest_bbrx1, qdss_tracectl_b, qdss_cti_trig_in_b0, blsp_i2c6,
qdss_traceclk_b, atest_wlan0, m_voc, qdss_cti_trig_in_a0, atest_bbrx0, blsp_i2c5,
qdss_tracectl_a, atest_gpsadc_dtest1_native, qdss_tracedata_a, blsp_spi6,
blsp_uart6, atest_wlan1, mdp_vsync, pri_mi2s_mclk_a, sec_mi2s_mclk_a,
cam_mclk, cci_i2c, pwr_modem_enabled_a, cci_timer0, cci_timer1, pwr_nav_enabled_a,
pwr_crypto_enabled_a, cci_async, sd_write, qdss_cti_trig_out_a0, gcc_gp1_clk_a,
gcc_gp2_clk_a, gcc_gp3_clk_a, blsp6_spi, qdss_cti_trig_in_b1, uim_batt,
qdss_cti_trig_out_b1, uim1_data, uim1_clk, uim1_reset, uim1_present, uim2_data,
uim2_clk, uim2_reset, uim2_present, uim3_data, usb_fs, uim3_clk, uim3_reset,
uim3_present, atest_char3, dbg_out, bimc_dte0, sec_mi2s_mclk_b, pri_mi2s,
atest_char1, ebi_cdc, atest_char0, cdc_pdm0, pri_mi2s_mclk_b, lpass_slimbus,
lpass_slimbus0, lpass_slimbus1, wcss_bt, atest_char2, ebi_ch0, wcss_wlan2,
wcss_wlan1, wcss_wlan0, wcss_wlan, wcss_fm, ext_lpass, gcc_tlmm, dmic0_clk,
dmic0_data, qdss_cti_trig_in_a1, blsp_spi7, blsp_uart7, pri_mi2s_ws, wsa_io,
blsp_i2c7, blsp_spi8, blsp_uart8, blsp_i2c8, gcc_plltest, nav_pps_in_a,
pa_indicator, nav_pps_in_b, nav_pps, modem_tsync, nav_tsync, ssbi_wtr1,
gsm1_tx, gsm0_tx, atest_char, atest_tsens, bimc_dte1,
gp_mn, gp_pdm_0a, gp_pdm_0b, gp_pdm_1a, gp_pdm_1b,
gp_pdm_2a, gp_pdm_2b, gp0_clk, gp1_clk]
required:
- pins
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
msmgpio: pinctrl@1000000 {
compatible = "qcom,msm8952-pinctrl";
reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&msmgpio 0 0 134>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
blsp1-uart2-sleep-state {
pins = "gpio4", "gpio5";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
spi1-default-state {
spi-pins {
pins = "gpio0", "gpio1", "gpio3";
function = "blsp_spi1";
drive-strength = <12>;
bias-disable;
};
cs-pins {
pins = "gpio2";
function = "blsp_spi1";
drive-strength = <2>;
bias-disable;
};
};
};

3
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
View File

@ -57,6 +57,7 @@ properties:
- qcom,pm8994-gpio
- qcom,pm8998-gpio
- qcom,pma8084-gpio
- qcom,pmau0102-gpio
- qcom,pmc8180-gpio
- qcom,pmc8180c-gpio
- qcom,pmc8380-gpio
@ -281,6 +282,7 @@ allOf:
- qcom,pm8150l-gpio
- qcom,pm8550-gpio
- qcom,pm8550b-gpio
- qcom,pmau0102-gpio
- qcom,pmc8180c-gpio
- qcom,pmp8074-gpio
- qcom,pms405-gpio
@ -496,6 +498,7 @@ $defs:
- gpio1-gpio22 for pm8994
- gpio1-gpio26 for pm8998
- gpio1-gpio22 for pma8084
- gpio1-gpio12 for pmau0102
- gpio1-gpio14 for pmcx0102
- gpio1-gpio4 for pmd8028
- gpio1-gpio4 for pmg1110

3
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml
View File

@ -27,6 +27,9 @@ properties:
gpio-reserved-ranges: true
gpio-line-names:
maxItems: 230
patternProperties:
"-state$":
oneOf:

4
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
View File

@ -129,13 +129,15 @@ additionalProperties:
enum: [ 33, 50, 66, 100 ]
power-source:
description: I/O voltage in millivolt.
enum: [ 1800, 2500, 3300 ]
enum: [ 1200, 1800, 2500, 3300 ]
slew-rate: true
gpio-hog: true
gpios: true
input: true
input-enable: true
input-disable: true
output-enable: true
output-disable: true
output-high: true
output-low: true
line-name: true

4
Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml
View File

@ -244,8 +244,8 @@ examples:
interrupt-controller;
gpio1-cfg {
pins = "gpio1";
bias-pull-up;
pins = "gpio1";
bias-pull-up;
};
};
};

179
Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml Normal file
View File

@ -0,0 +1,179 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per0-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JHB100 Peripheral-0 Pin Controller
description: |
Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
per2, per2pok, per3, adc0, adc1, emmc, and vga.
This document provides an overview of the "per0" pinctrl domain.
The "per0" domain has a pin controller which provides
- function selection for GPIO pads.
- GPIO pad configuration.
- GPIO interrupt handling.
In the Peripheral-0 Pin Controller, there are 60 multi-function GPIO_PADs.
Each of them can be multiplexed to several hardware blocks through function
selection. Each iopad has a maximum of up to 3 functions - 0, 1, and 2.
Function 0 is the default function which is generally the GPIO function.
Function 1 and 2 are the alternate function or signal of an iopad. The
function 1 and function 2 are other optional functions or peripheral
signals that can be routed to an iopad. The function selection can be carried
out by writing the function number to the iopad function select register.
Each iopad is configurable with parameters such as input-enable, internal
pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
debounce nanoseconds, power source and drive type (open-drain or push-pull).
maintainers:
- Changhuang Liang <changhuang.liang@starfivetech.com>
properties:
compatible:
items:
- const: starfive,jhb100-per0-pinctrl
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges: true
gpio-line-names: true
patternProperties:
'-grp$':
type: object
additionalProperties: false
patternProperties:
'-pins$':
type: object
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl groups available in the domain. Each subnode will list the
pins it needs, and how they should be configured, with regard to
function selection, bias, input enable/disable, input schmitt
trigger enable/disable, slew-rate, input debounce nanoseconds,
drive-open-drain, drive-push-pull, power-source and drive-strength.
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- $ref: /schemas/pinctrl/pinmux-node.yaml
additionalProperties: false
properties:
pins:
description:
The list of IOs that properties in the pincfg node apply to.
function:
description:
A string containing the name of the function to mux for these
pins.
enum: [ gmac_mdio, gpio, i2c, i3c, smbalert, wdt ]
bias-disable: true
bias-pull-down:
type: boolean
bias-pull-up:
oneOf:
- type: boolean
- enum: [ 600, 900, 1200, 2000 ]
description: Pull up RSEL type resistance values (in ohms)
description:
For normal pull up type there is no need to specify a resistance
value, hence this can be specified as a boolean property.
For RSEL pull up type a resistance value (in ohms) can be added.
drive-open-drain: true
drive-push-pull: true
drive-strength:
enum: [ 2, 4, 8, 12 ]
drive-strength-microamp:
enum: [ 2000, 4000, 8000, 12000 ]
input-debounce-ns:
minimum: 0
maximum: 10485680
description:
Debounce time in nanoseconds. The hardware counts in 80 ns
stages with a 17-bit counter, so the maximum is 10485680 ns.
input-disable: true
input-enable: true
input-schmitt-enable: true
input-schmitt-disable: true
power-source:
enum: [ 1800, 3300 ]
description: I/O voltage in millivolt.
slew-rate:
enum: [ 0, 1 ]
default: 0
description: |
0: slow
1: fast
required:
- compatible
- reg
- resets
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pinctrl_per0: pinctrl@11a0a000 {
compatible = "starfive,jhb100-per0-pinctrl";
reg = <0x0 0x11a0a000 0x0 0x1000>;
resets = <&per0crg 0>;
interrupts = <60>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_per0 0 0 60>;
};
};

178
Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml Normal file
View File

@ -0,0 +1,178 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per1-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JHB100 Peripheral-1 Pin Controller
description: |
Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
per2, per2pok, per3, adc0, adc1, emmc, and vga.
This document provides an overview of the "per1" pinctrl domain.
The "per1" domain has a pin controller which provides
- function selection for GPIO pads.
- GPIO pad configuration.
- GPIO interrupt handling.
In the Peripheral-1 Pin Controller, there are 36 multi-function GPIO_PADs.
Each of them can be multiplexed to several peripherals through function
selection. Each iopad has a maximum of up to 3 functions - 0, 1, and 2.
Function 0 is the default function which is generally the GPIO function.
Function 1 and 2 are the alternate functions or peripheral signals that
can be routed to the iopad. The function selection can be carried out by
writing the function number to the iopad function select register.
Each iopad is configurable with parameters such as input-enable, internal
pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
debounce nanoseconds, power source and drive type (open-drain or push-pull).
maintainers:
- Changhuang Liang <changhuang.liang@starfivetech.com>
properties:
compatible:
items:
- const: starfive,jhb100-per1-pinctrl
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges: true
gpio-line-names: true
patternProperties:
'-grp$':
type: object
additionalProperties: false
patternProperties:
'-pins$':
type: object
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl groups available in the domain. Each subnode will list the
pins it needs, and how they should be configured, with regard to
function selection, bias, input enable/disable, input schmitt
trigger enable/disable, slew-rate, input debounce nanoseconds,
drive-open-drain, drive-push-pull, power-source and drive-strength.
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- $ref: /schemas/pinctrl/pinmux-node.yaml
additionalProperties: false
properties:
pins:
description:
The list of IOs that properties in the pincfg node apply to.
function:
description:
A string containing the name of the function to mux for these
pins.
enum: [ gpio, i2c, sfc, sgpio, spi ]
bias-disable: true
bias-pull-down:
type: boolean
bias-pull-up:
oneOf:
- type: boolean
- enum: [ 600, 900, 1200, 2000 ]
description: Pull up RSEL type resistance values (in ohms)
description:
For normal pull up type there is no need to specify a resistance
value, hence this can be specified as a boolean property.
For RSEL pull up type a resistance value (in ohms) can be added.
drive-open-drain: true
drive-push-pull: true
drive-strength:
enum: [ 2, 4, 8, 12 ]
drive-strength-microamp:
enum: [ 2000, 4000, 8000, 12000 ]
input-debounce-ns:
minimum: 0
maximum: 10485680
description:
Debounce time in nanoseconds. The hardware counts in 80 ns
stages with a 17-bit counter, so the maximum is 10485680 ns.
input-disable: true
input-enable: true
input-schmitt-enable: true
input-schmitt-disable: true
power-source:
enum: [ 1800, 3300 ]
description: I/O voltage in millivolt.
slew-rate:
enum: [ 0, 1 ]
default: 0
description: |
0: slow
1: fast
required:
- compatible
- reg
- resets
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pinctrl_per1: pinctrl@11b42000 {
compatible = "starfive,jhb100-per1-pinctrl";
reg = <0x0 0x11b42000 0x0 0x800>;
resets = <&per1crg 0>;
interrupts = <61>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_per1 0 0 36>;
};
};

168
Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml Normal file
View File

@ -0,0 +1,168 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per2-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JHB100 Peripheral-2 Pin Controller
description: |
Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
per2, per2pok, per3, adc0, adc1, emmc, and vga.
This document provides an overview of the "per2" pinctrl domain.
The "per2" domain has a pin controller which provides
- function selection for GPIO pads.
- GPIO pad configuration.
- GPIO interrupt handling.
In the Peripheral-2 Pin Controller, there are 31 multi-function GPIO_PADs.
Each of them can be multiplexed to several peripherals through function
selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3.
Function 0 is the default function which is generally the GPIO function.
Function 1, 2, and 3 are the alternate functions or peripheral signals
that can be routed to an iopad. The function selection can be carried
out by writing the function number to the iopad function select register.
Each iopad is configurable with parameters such as input-enable, internal
pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
debounce nanoseconds, power source.
maintainers:
- Changhuang Liang <changhuang.liang@starfivetech.com>
properties:
compatible:
items:
- const: starfive,jhb100-per2-pinctrl
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges: true
gpio-line-names: true
patternProperties:
'-grp$':
type: object
additionalProperties: false
patternProperties:
'-pins$':
type: object
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl groups available in the domain. Each subnode will list the
pins it needs, and how they should be configured, with regard to
function selection, bias, input enable/disable, input schmitt
trigger enable/disable, slew-rate, input debounce nanoseconds,
power-source and drive-strength.
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- $ref: /schemas/pinctrl/pinmux-node.yaml
additionalProperties: false
properties:
pins:
description:
The list of IOs that properties in the pincfg node apply to.
function:
description:
A string containing the name of the function to mux for these
pins.
enum: [ fan_tach, gmac_rgmii, gmac_rmii, gpio, host0_port80,
host1_port80 ]
bias-disable: true
bias-pull-down:
type: boolean
bias-pull-up:
type: boolean
drive-strength:
enum: [ 2, 4, 8, 12 ]
drive-strength-microamp:
enum: [ 2000, 4000, 8000, 12000 ]
input-debounce-ns:
minimum: 0
maximum: 10485680
description:
Debounce time in nanoseconds. The hardware counts in 80 ns
stages with a 17-bit counter, so the maximum is 10485680 ns.
input-disable: true
input-enable: true
input-schmitt-enable: true
input-schmitt-disable: true
power-source:
enum: [ 1800, 2500, 3300 ]
description: I/O voltage in millivolt.
slew-rate:
enum: [ 0, 1 ]
default: 0
description: |
0: slow
1: fast
required:
- compatible
- reg
- resets
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pinctrl_per2: pinctrl@11bc2000 {
compatible = "starfive,jhb100-per2-pinctrl";
reg = <0x0 0x11bc2000 0x0 0x400>;
resets = <&per2crg 0>;
interrupts = <62>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_per2 0 0 31>;
};
};

162
Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml Normal file
View File

@ -0,0 +1,162 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JHB100 Peripheral-2 Power OK Pin Controller
description: |
Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
per2, per2pok, per3, adc0, adc1, emmc, and vga.
This document provides an overview of the "per2pok" pinctrl domain.
The "per2pok" domain has a pin controller which provides
- function selection for GPIO pads.
- GPIO interrupt handling.
In the Peripheral-2 Power OK Pin Controller, there are 18 multi-function
GPIO_PADs. Each can be multiplexed to several peripherals through function
selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3.
Function 0 is the default function or generally the GPIO function.
Function 1, 2, and 3 are alternate functions or peripheral signals that can
be routed to an iopad. The function selection can be carried out by writing
the function number to the iopad function select register.
Each iopad is configurable with parameters such as input-enable, internal
pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
debounce nanoseconds.
maintainers:
- Changhuang Liang <changhuang.liang@starfivetech.com>
properties:
compatible:
items:
- const: starfive,jhb100-per2pok-pinctrl
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges: true
gpio-line-names: true
patternProperties:
'-grp$':
type: object
additionalProperties: false
patternProperties:
'-pins$':
type: object
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl groups available in the domain. Each subnode will list the
pins it needs, and how they should be configured, with regard to
function selection, bias, input enable/disable, input schmitt
trigger enable/disable, slew-rate, input debounce nanoseconds
and drive-strength.
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- $ref: /schemas/pinctrl/pinmux-node.yaml
additionalProperties: false
properties:
pins:
description:
The list of IOs that properties in the pincfg node apply to.
function:
description:
A string containing the name of the function to mux for these
pins.
enum: [ can, gpio, host0_port80, host1_port80, passthru, pwm ]
bias-disable: true
bias-pull-down:
type: boolean
bias-pull-up:
type: boolean
drive-strength:
enum: [ 2, 4, 8, 12 ]
drive-strength-microamp:
enum: [ 2000, 4000, 8000, 12000 ]
input-debounce-ns:
minimum: 0
maximum: 10485680
description:
Debounce time in nanoseconds. The hardware counts in 80 ns
stages with a 17-bit counter, so the maximum is 10485680 ns.
input-disable: true
input-enable: true
input-schmitt-enable: true
input-schmitt-disable: true
slew-rate:
enum: [ 0, 1 ]
default: 0
description: |
0: slow
1: fast
required:
- compatible
- reg
- resets
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pinctrl_per2pok: pinctrl@11bc2400 {
compatible = "starfive,jhb100-per2pok-pinctrl";
reg = <0x0 0x11bc2400 0x0 0x400>;
resets = <&per2crg 1>;
interrupts = <63>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_per2pok 0 0 18>;
};
};

166
Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml Normal file
View File

@ -0,0 +1,166 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per3-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JHB100 Peripheral-3 Pin Controller
description: |
Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
per2, per2pok, per3, adc0, adc1, emmc, and vga.
This document provides an overview of the "per3" pinctrl domain.
The "per3" domain has a pin controller which provides
- function selection for GPIO pads.
- GPIO interrupt handling.
In the Peripheral-3 Pin Controller, there are 11 multi-function GPIO_PADs.
Each of them can be multiplexed to several peripherals through function
selection. Each iopad has a maximum of up to 2 functions - 0 and 1.
Function 0 is the default function which is generally the GPIO function.
Function 1 is the alternate function or peripheral signal that can be
routed to an iopad. The function selection can be carried out by writing
the function number to the iopad function select register.
Each iopad is configurable with parameters such as input-enable, internal
pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
debounce nanoseconds, power source.
maintainers:
- Changhuang Liang <changhuang.liang@starfivetech.com>
properties:
compatible:
items:
- const: starfive,jhb100-per3-pinctrl
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges: true
gpio-line-names: true
patternProperties:
'-grp$':
type: object
additionalProperties: false
patternProperties:
'-pins$':
type: object
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl groups available in the domain. Each subnode will list the
pins it needs, and how they should be configured, with regard to
function selection, bias, input enable/disable, input schmitt
trigger enable/disable, slew-rate, input debounce nanoseconds,
power-source and drive-strength.
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- $ref: /schemas/pinctrl/pinmux-node.yaml
additionalProperties: false
properties:
pins:
description:
The list of IOs that properties in the pincfg node apply to.
function:
description:
A string containing the name of the function to mux for these
pins.
enum: [ gmac_mdio, gmac_rmii, gpio ]
bias-disable: true
bias-pull-down:
type: boolean
bias-pull-up:
type: boolean
drive-strength:
enum: [ 2, 4, 8, 12 ]
drive-strength-microamp:
enum: [ 2000, 4000, 8000, 12000 ]
input-debounce-ns:
minimum: 0
maximum: 10485680
description:
Debounce time in nanoseconds. The hardware counts in 80 ns
stages with a 17-bit counter, so the maximum is 10485680 ns.
input-disable: true
input-enable: true
input-schmitt-enable: true
input-schmitt-disable: true
power-source:
enum: [ 1800, 2500, 3300 ]
description: I/O voltage in millivolt.
slew-rate:
enum: [ 0, 1 ]
default: 0
description: |
0: slow
1: fast
required:
- compatible
- reg
- resets
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pinctrl_per3: pinctrl@11c42000 {
compatible = "starfive,jhb100-per3-pinctrl";
reg = <0x0 0x11c42000 0x0 0x1000>;
resets = <&per3crg 6>;
interrupts = <64>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_per3 0 0 11>;
};
};

164
Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml Normal file
View File

@ -0,0 +1,164 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys0-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JHB100 System-0 Pin Controller
description: |
Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
per2, per2pok, per3, adc0, adc1, emmc, and vga.
This document provides an overview of the "sys0" pinctrl domain.
The "sys0" domain has a pin controller which provides
- function selection for GPIO pads.
- GPIO pad configuration.
- GPIO interrupt handling.
In the SYS0 Pin Controller, there are 4 multi-function GPIO_PADs. Each of
them can be multiplexed to different hardware blocks through function
selection and each iopad has a maximum of up to 2 functions - 0 and 1.
Function 0 is the default function which is generally the GPIO function
(or occasionally, it can be a peripheral signal).
Function 1 is the alternate function or peripheral signal that can be
routed to the iopad. The function selection is carried out by writing
the function number to the iopad function select register.
Each iopad is configurable with parameters such as input-enable, internal
pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
debounce nanoseconds.
maintainers:
- Changhuang Liang <changhuang.liang@starfivetech.com>
properties:
compatible:
items:
- const: starfive,jhb100-sys0-pinctrl
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges: true
gpio-line-names: true
patternProperties:
'-grp$':
type: object
additionalProperties: false
patternProperties:
'-pins$':
type: object
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl groups available in the domain. Each subnode will list the
pins it needs, and how they should be configured, with regard to
function selection, bias, input enable/disable, input schmitt
trigger enable/disable, slew-rate, input debounce and
drive-strength.
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- $ref: /schemas/pinctrl/pinmux-node.yaml
additionalProperties: false
properties:
pins:
description:
The list of IOs that properties in the pincfg node apply to.
function:
description:
A string containing the name of the function to mux for these
pins.
enum: [ auxpwrgood, gpio, hbled, pe2rst_out ]
bias-disable: true
bias-pull-down:
type: boolean
bias-pull-up:
type: boolean
drive-strength:
enum: [ 2, 4, 8, 12 ]
drive-strength-microamp:
enum: [ 2000, 4000, 8000, 12000 ]
input-debounce-ns:
minimum: 0
maximum: 10485680
description:
Debounce time in nanoseconds. The hardware counts in 80 ns
stages with a 17-bit counter, so the maximum is 10485680 ns.
input-disable: true
input-enable: true
input-schmitt-enable: true
input-schmitt-disable: true
slew-rate:
enum: [ 0, 1 ]
default: 0
description: |
0: slow
1: fast
required:
- compatible
- reg
- resets
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pinctrl_sys0: pinctrl@13080000 {
compatible = "starfive,jhb100-sys0-pinctrl";
reg = <0x0 0x13080000 0x0 0x800>;
resets = <&sys0crg 2>;
interrupts = <56>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_sys0 0 0 4>;
};
};

162
Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml Normal file
View File

@ -0,0 +1,162 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JHB100 System-0 Host Pin Controller
description: |
Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
per2, per2pok, per3, adc0, adc1, emmc, and vga.
This document provides an overview of the "sys0h" pinctrl domain.
The "sys0h" domain has a pin controller which provides
- function selection for GPIO pads.
- GPIO pad configuration.
- GPIO interrupt handling.
In the SYS0H Pin Controller, there are 12 multi-function GPIO_PADs. Each of
them can be multiplexed to different hardware blocks through function
selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3.
Function 0 is the default function which is generally the GPIO function
(or occasionally, it can be a peripheral signal).
Functions 1, 2, and 3 are the alternate functions or peripheral signals that
can be routed to the iopad. The function selection can be carried out by
writing the function number to the iopad function select register.
Each iopad is configurable with parameters such as input-enable, internal
pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
debounce nanoseconds.
maintainers:
- Changhuang Liang <changhuang.liang@starfivetech.com>
properties:
compatible:
items:
- const: starfive,jhb100-sys0h-pinctrl
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges: true
gpio-line-names: true
patternProperties:
'-grp$':
type: object
additionalProperties: false
patternProperties:
'-pins$':
type: object
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl groups available in the domain. Each subnode will list the
pins it needs, and how they should be configured, with regard to
function selection, bias, input enable/disable, input schmitt
trigger enable/disable, slew-rate, input debounce nanoseconds and
drive-strength.
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- $ref: /schemas/pinctrl/pinmux-node.yaml
additionalProperties: false
properties:
pins:
description:
The list of IOs that properties in the pincfg node apply to.
function:
description:
A string containing the name of the function to mux for these
pins.
enum: [ espi, espi_reset, espi0_vw, espi1_vw, gpio, scap_trigger ]
bias-disable: true
bias-pull-down:
type: boolean
bias-pull-up:
type: boolean
drive-strength:
enum: [ 2, 4, 8, 12 ]
drive-strength-microamp:
enum: [ 2000, 4000, 8000, 12000 ]
input-debounce-ns:
minimum: 0
maximum: 10485680
description:
Debounce time in nanoseconds. The hardware counts in 80 ns
stages with a 17-bit counter, so the maximum is 10485680 ns.
input-disable: true
input-enable: true
input-schmitt-enable: true
input-schmitt-disable: true
slew-rate:
enum: [ 0, 1 ]
default: 0
description: |
0: slow
1: fast
required:
- compatible
- reg
- resets
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pinctrl_sys0h: pinctrl@13080800 {
compatible = "starfive,jhb100-sys0h-pinctrl";
reg = <0x0 0x13080800 0x0 0x800>;
resets = <&sys0crg 3>;
interrupts = <57>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_sys0h 0 0 12>;
};
};

164
Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys1-pinctrl.yaml Normal file
View File

@ -0,0 +1,164 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys1-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JHB100 System-1 Pin Controller
description: |
Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
per2, per2pok, per3, adc0, adc1, emmc, and vga.
This document provides an overview of the "sys1" pinctrl domain.
The "sys1" domain has a pin controller which provides
- function selection for GPIO pads.
- GPIO pad configuration.
- GPIO interrupt handling.
In the SYS1 Pin Controller, there are 8 multi-function GPIO_PADs. Each of
them can be multiplexed to different hardware blocks through function
selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3.
Function 0 is the default function which is generally the GPIO function
(or occasionally, it can be a peripheral signal).
Function 1, 2, and 3 are the alternate functions or peripheral signals that
can be routed to the iopad. The function selection can be carried out by
writing the function number to the iopad function select register.
Each iopad is configurable with parameters such as input-enable, internal
pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
debounce nanoseconds.
maintainers:
- Changhuang Liang <changhuang.liang@starfivetech.com>
properties:
compatible:
items:
- const: starfive,jhb100-sys1-pinctrl
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges: true
gpio-line-names: true
patternProperties:
'-grp$':
type: object
additionalProperties: false
patternProperties:
'-pins$':
type: object
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl groups available in the domain. Each subnode will list the
pins it needs, and how they should be configured, with regard to
function selection, bias, input enable/disable, input schmitt
trigger enable/disable, slew-rate, input debounce nanoseconds
and drive-strength.
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- $ref: /schemas/pinctrl/pinmux-node.yaml
additionalProperties: false
properties:
pins:
description:
The list of IOs that properties in the pincfg node apply to.
function:
description:
A string containing the name of the function to mux for these
pins.
enum: [ espi, espi_reset, gpio, host0_port80, host1_port80 ]
bias-disable: true
bias-pull-down:
type: boolean
bias-pull-up:
type: boolean
drive-strength:
enum: [ 2, 4, 8, 12 ]
drive-strength-microamp:
enum: [ 2000, 4000, 8000, 12000 ]
input-debounce-ns:
minimum: 0
maximum: 10485680
description:
Debounce time in nanoseconds. The hardware counts in 80 ns
stages with a 17-bit counter, so the maximum is 10485680 ns.
input-disable: true
input-enable: true
input-schmitt-enable: true
input-schmitt-disable: true
slew-rate:
enum: [ 0, 1 ]
default: 0
description: |
0: slow
1: fast
required:
- compatible
- reg
- resets
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pinctrl_sys1: pinctrl@13081000 {
compatible = "starfive,jhb100-sys1-pinctrl";
reg = <0x0 0x13081000 0x0 0x1000>;
resets = <&sys1crg 2>;
interrupts = <58>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_sys1 0 0 8>;
};
};

165
Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml Normal file
View File

@ -0,0 +1,165 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys2-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JHB100 System-2 Pin Controller
description: |
Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
per2, per2pok, per3, adc0, adc1, emmc, and vga.
This document provides an overview of the "sys2" pinctrl domain.
The "sys2" domain has a pin controller which provides
- function selection for GPIO pads.
- GPIO pad configuration.
- GPIO interrupt handling.
In the SYS2 Pin Controller, there are 37 multi-function GPIO_PADs. Each of
them can be multiplexed to different hardware blocks through function
selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3.
Function 0 is the default function which is the GPIO function.
Function 1, 2, and 3 are the alternate functions or peripheral signals that
can be routed to the iopad. The function selection can be carried out by
writing the function number to the iopad function select register.
Each iopad is configurable with parameters such as input-enable, internal
pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
debounce nanoseconds, power source.
maintainers:
- Changhuang Liang <changhuang.liang@starfivetech.com>
properties:
compatible:
items:
- const: starfive,jhb100-sys2-pinctrl
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges: true
gpio-line-names: true
patternProperties:
'-grp$':
type: object
additionalProperties: false
patternProperties:
'-pins$':
type: object
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl groups available in the domain. Each subnode will list the
pins it needs, and how they should be configured, with regard to
function selection, bias, input enable/disable, input schmitt
trigger enable/disable, slew-rate, input debounce nanoseconds,
power-source and drive-strength.
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- $ref: /schemas/pinctrl/pinmux-node.yaml
additionalProperties: false
properties:
pins:
description:
The list of IOs that properties in the pincfg node apply to.
function:
description:
A string containing the name of the function to mux for these
pins.
enum: [ gpio, host0_port80, host1_port80, jtag, smbalert, uart ]
bias-disable: true
bias-pull-down:
type: boolean
bias-pull-up:
type: boolean
drive-strength:
enum: [ 2, 4, 8, 12 ]
drive-strength-microamp:
enum: [ 2000, 4000, 8000, 12000 ]
input-debounce-ns:
minimum: 0
maximum: 10485680
description:
Debounce time in nanoseconds. The hardware counts in 80 ns
stages with a 17-bit counter, so the maximum is 10485680 ns.
input-disable: true
input-enable: true
input-schmitt-enable: true
input-schmitt-disable: true
power-source:
enum: [ 1800, 3300 ]
description: I/O voltage in millivolt.
slew-rate:
enum: [ 0, 1 ]
default: 0
description: |
0: slow
1: fast
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pinctrl_sys2: pinctrl@13082000 {
compatible = "starfive,jhb100-sys2-pinctrl";
reg = <0x0 0x13082000 0x0 0x1000>;
interrupts = <59>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_sys2 0 0 37>;
};
};

170
Documentation/devicetree/bindings/pinctrl/ti,palmas-pinctrl.yaml Normal file
View File

@ -0,0 +1,170 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/ti,palmas-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI Palmas Pincontrol
maintainers:
- Laxman Dewangan <ldewangan@nvidia.com>
description:
The pins of Palmas device can be set on different option and provides
the configuration for Pull UP/DOWN, open drain etc.
allOf:
- $ref: pinctrl.yaml#
properties:
compatible:
enum:
- ti,palmas-pinctrl
- ti,tps65913-pinctrl
- ti,tps80036-pinctrl
ti,palmas-enable-dvfs1:
type: boolean
description:
Enable DVFS1. Configure pins for DVFS1 mode.
Selection primary or secondary function associated to I2C2_SCL_SCE,
I2C2_SDA_SDO pin/pad for DVFS1 interface.
ti,palmas-enable-dvfs2:
type: boolean
description:
Enable DVFS2. Configure pins for DVFS2 mode.
Selection primary or secondary function associated to GPADC_START
and SYSEN2 pin/pad for DVFS2 interface.
ti,palmas-override-powerhold:
type: boolean
description:
This is applicable for PMICs for which GPIO7 is configured in POWERHOLD
mode which has higher priority over DEV_ON bit and keeps the PMIC
supplies on even after the DEV_ON bit is turned off. This property enables
driver to over ride the POWERHOLD value to GPIO7 so as to turn off the PMIC
in power off scenarios. So for GPIO7 if ti,palmas-override-powerhold is set
then the GPIO_7 field should never be muxed to anything else.
It should be set to POWERHOLD by default and only in case of
power off scenarios the driver will over ride the mux value.
patternProperties:
'^(pinmux|pins?-[a-z0-9-]+)$':
type: object
additionalProperties: false
patternProperties:
'^(pin.*|gpio[0-9]+|vac|powergood|nreswarm|pwrdown|gpadc_start|reset_in|nsleep|enable[12]|int)$':
type: object
allOf:
- $ref: /schemas/pinctrl/pinmux-node.yaml
- $ref: /schemas/pinctrl/pincfg-node.yaml
unevaluatedProperties: false
properties:
pins:
items:
enum:
- gpio0
- gpio1
- gpio2
- gpio3
- gpio4
- gpio5
- gpio6
- gpio7
- gpio8
- gpio9
- gpio10
- gpio11
- gpio12
- gpio13
- gpio14
- gpio15
- vac
- powergood
- nreswarm
- pwrdown
- gpadc_start
- reset_in
- nsleep
- enable1
- enable2
- int
function:
description:
Selects the mux function. There are 4 special functions opt0,
opt1, opt2 and opt3. If any of these functions is selected then
directly pins register will be written with 0, 1, 2 or 3
respectively if it is valid for that pin or list of pins.
enum:
- gpio
- led
- pwm
- regen
- sysen
- clk32kgaudio
- id
- vbus_det
- chrg_det
- vac
- vacok
- powergood
- usb_psel
- msecure
- pwrhold
- int
- nreswarm
- simrsto
- simrsti
- low_vbat
- wireless_chrg1
- rcm
- pwrdown
- gpadc_start
- reset_in
- nsleep
- enable
- opt0
- opt1
- opt2
- opt3
required:
- pins
required:
- compatible
unevaluatedProperties: false
examples:
- |
pmic {
pinctrl {
compatible = "ti,tps65913-pinctrl";
ti,palmas-enable-dvfs1;
pinctrl-names = "default";
pinctrl-0 = <&palmas_pins_state>;
pinmux {
gpio0 {
pins = "gpio0";
function = "id";
bias-pull-up;
};
vac {
pins = "vac";
function = "vacok";
bias-pull-down;
};
gpio5 {
pins = "gpio5";
function = "opt0";
drive-open-drain = <1>;
};
};
};
};

46
Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
View File

@ -317,37 +317,37 @@ examples:
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
zynqmp_firmware: zynqmp-firmware {
pinctrl0: pinctrl {
compatible = "xlnx,zynqmp-pinctrl";
compatible = "xlnx,zynqmp-pinctrl";
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart0_4_grp", "uart0_5_grp";
function = "uart0";
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart0_4_grp", "uart0_5_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO18";
bias-pull-up;
};
conf-rx {
pins = "MIO18";
bias-pull-up;
};
conf-tx {
pins = "MIO19";
bias-disable;
input-schmitt-disable;
};
};
conf-tx {
pins = "MIO19";
bias-disable;
input-schmitt-disable;
};
};
};
};
uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
...

18
MAINTAINERS
View File

@ -21917,6 +21917,15 @@ F: drivers/pinctrl/mediatek/pinctrl-rt2880.c
F: drivers/pinctrl/mediatek/pinctrl-rt305x.c
F: drivers/pinctrl/mediatek/pinctrl-rt3883.c
PIN CONTROLLER - MEDIATEK MT6735
M: Yassine Oudjana <y.oudjana@protonmail.com>
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
F: drivers/pinctrl/mediatek/pinctrl-mt6735.c
F: drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h
F: include/dt-bindings/pinctrl/mediatek,mt6735-pinfunc.h
PIN CONTROLLER - MICROCHIP AT91
M: Ludovic Desroches <ludovic.desroches@microchip.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -22988,6 +22997,7 @@ QUALCOMM PINCTRL DRIVERS
M: Bartosz Golaszewski <brgl@kernel.org>
L: linux-arm-msm@vger.kernel.org
S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git
F: Documentation/devicetree/bindings/pinctrl/qcom,*.yaml
F: drivers/pinctrl/qcom/
@ -26680,6 +26690,14 @@ S: Supported
F: Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml
F: drivers/irqchip/irq-starfive-jhb100-intc.c
STARFIVE JHB100 PINCTRL DRIVERS
M: Changhuang Liang <changhuang.liang@starfivetech.com>
M: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
L: linux-gpio@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pinctrl/starfive,jhb1*.yaml
F: drivers/pinctrl/starfive/pinctrl-starfive-jhb1*
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>

20
drivers/pinctrl/Kconfig
View File

@ -37,6 +37,24 @@ config DEBUG_PINCTRL
help
Say Y here to add some extra checks and diagnostics to PINCTRL calls.
config PINCTRL_AMB
bool "Ambarella pin controller support"
depends on ARCH_AMBARELLA || COMPILE_TEST
depends on HAS_IOMEM
depends on OF
default y if ARCH_AMBARELLA
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GPIOLIB
select GPIO_PL061
select MFD_SYSCON
select PINCONF
select PINMUX
help
Say Y here to enable the Ambarella pinmux/pinconf controller.
GPIO is provided by the PL061 driver.
config PINCTRL_AMD
bool "AMD GPIO pin control"
depends on HAS_IOMEM
@ -535,6 +553,8 @@ config PINCTRL_SCMI
tristate "Pinctrl driver using SCMI protocol interface"
depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
select PINMUX
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This driver provides support for pinctrl which is controlled

2
drivers/pinctrl/Makefile
View File

@ -10,6 +10,8 @@ obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
obj-$(CONFIG_GENERIC_PINCTRL) += pinctrl-generic.o
obj-$(CONFIG_OF) += devicetree.o
obj-$(CONFIG_PINCTRL_AMB) += pinctrl-ambarella.o
obj-$(CONFIG_PINCTRL_AMB) += pinctrl-ambarella-cv75.o
obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
obj-$(CONFIG_PINCTRL_AMDISP) += pinctrl-amdisp.o
obj-$(CONFIG_PINCTRL_APPLE_GPIO) += pinctrl-apple-gpio.o

15
drivers/pinctrl/airoha/Kconfig
View File

@ -1,11 +1,11 @@
# SPDX-License-Identifier: GPL-2.0-only
menu "Airoha pinctrl drivers"
depends on ARCH_AIROHA || COMPILE_TEST
depends on ARCH_AIROHA || ECONET || COMPILE_TEST
config PINCTRL_AIROHA
tristate "Airoha pin control"
depends on OF
depends on ARCH_AIROHA || COMPILE_TEST
depends on ARCH_AIROHA || ECONET || COMPILE_TEST
select PINMUX
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
@ -17,6 +17,7 @@ config PINCTRL_AIROHA
imply PINCTRL_AIROHA_AN7581
imply PINCTRL_AIROHA_AN7583
imply PINCTRL_AIROHA_EN7523
imply PINCTRL_AIROHA_EN7528
help
Shared pin controller and gpio driver code for different
Airoha SoCs.
@ -53,4 +54,14 @@ config PINCTRL_AIROHA_EN7523
Say yes here to support pin controller and gpio driver
on Airoha EN7523, EN7529, EN7562 and other compatible SoCs.
config PINCTRL_AIROHA_EN7528
tristate "EN7528 pinctrl"
depends on ECONET || COMPILE_TEST
depends on PINCTRL_AIROHA
help
Say yes here to support pin controller and gpio driver
on EcoNet EN7528 and other compatible SoCs. Unlike the
other variants, only the first sixteen GPIOs of this SoC
are wired to the interrupt controller.
endmenu

1
drivers/pinctrl/airoha/Makefile
View File

@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_AIROHA_AN7563) += pinctrl-an7563.o
obj-$(CONFIG_PINCTRL_AIROHA_AN7581) += pinctrl-an7581.o
obj-$(CONFIG_PINCTRL_AIROHA_AN7583) += pinctrl-an7583.o
obj-$(CONFIG_PINCTRL_AIROHA_EN7523) += pinctrl-en7523.o
obj-$(CONFIG_PINCTRL_AIROHA_EN7528) += pinctrl-en7528.o

3
drivers/pinctrl/airoha/airoha-common.h
View File

@ -127,6 +127,7 @@ struct airoha_pinctrl {
struct gpio_chip gpiochip;
struct airoha_gpiochip_regs *gpio_regs;
unsigned int num_irq_pins;
};
struct airoha_pinctrl_match_data {
@ -140,6 +141,8 @@ struct airoha_pinctrl_match_data {
const struct airoha_pinctrl_func *funcs;
const unsigned int num_funcs;
const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
/* number of GPIOs wired to the interrupt controller */
const unsigned int num_irq_pins;
};
int airoha_pinctrl_probe(struct platform_device *pdev);

33
drivers/pinctrl/airoha/pinctrl-airoha.c
View File

@ -213,7 +213,7 @@ static void airoha_irq_unmask(struct irq_data *data)
u32 mask = GENMASK(2 * offset + 1, 2 * offset);
u32 val = BIT(2 * offset);
if (WARN_ON_ONCE(data->hwirq >= AIROHA_NUM_PINS))
if (WARN_ON_ONCE(data->hwirq >= pinctrl->num_irq_pins))
return;
gpiochip_enable_irq(gc, irqd_to_hwirq(data));
@ -249,7 +249,7 @@ static void airoha_irq_mask(struct irq_data *data)
u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
u32 mask = GENMASK(2 * offset + 1, 2 * offset);
if (data->hwirq >= AIROHA_NUM_PINS)
if (data->hwirq >= pinctrl->num_irq_pins)
return;
regmap_clear_bits(pinctrl->regmap, gpio_regs->level[index], mask);
@ -265,7 +265,7 @@ static void airoha_irq_ack(struct irq_data *data)
u8 offset = data->hwirq % AIROHA_PIN_BANK_SIZE;
u8 index = data->hwirq / AIROHA_PIN_BANK_SIZE;
if (data->hwirq >= AIROHA_NUM_PINS)
if (data->hwirq >= pinctrl->num_irq_pins)
return;
regmap_write(pinctrl->regmap, gpio_regs->status[index], BIT(offset));
@ -273,7 +273,10 @@ static void airoha_irq_ack(struct irq_data *data)
static int airoha_irq_type(struct irq_data *data, unsigned int type)
{
if (data->hwirq >= AIROHA_NUM_PINS)
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
if (data->hwirq >= pinctrl->num_irq_pins)
return -EINVAL;
if (type == IRQ_TYPE_NONE) {
@ -304,9 +307,11 @@ static irqreturn_t airoha_irq_handler(int irq, void *data)
{
struct airoha_pinctrl *pinctrl = data;
bool handled = false;
unsigned int nbanks;
int i;
for (i = 0; i < ARRAY_SIZE(irq_status_regs); i++) {
nbanks = DIV_ROUND_UP(pinctrl->num_irq_pins, AIROHA_PIN_BANK_SIZE);
for (i = 0; i < nbanks; i++) {
struct gpio_irq_chip *girq = &pinctrl->gpiochip.irq;
u32 regmap;
unsigned long status;
@ -340,6 +345,22 @@ static const struct irq_chip airoha_gpio_irq_chip = {
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
/*
* Mark the GPIOs that are not wired to the interrupt controller as not
* valid, so that gpiod_to_irq() fails for them with -ENXIO instead of
* handing out an interrupt that can never fire.
*/
static void airoha_gpio_init_valid_mask(struct gpio_chip *gc,
unsigned long *valid_mask,
unsigned int ngpios)
{
struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
unsigned int num_irq_pins = pinctrl->num_irq_pins;
if (num_irq_pins < ngpios)
bitmap_clear(valid_mask, num_irq_pins, ngpios - num_irq_pins);
}
static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
struct platform_device *pdev)
{
@ -362,6 +383,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
girq->init_valid_mask = airoha_gpio_init_valid_mask;
gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip);
irq = platform_get_irq(pdev, 0);
@ -848,6 +870,7 @@ int airoha_pinctrl_probe(struct platform_device *pdev)
pinctrl->grps = data->grps;
pinctrl->funcs = data->funcs;
pinctrl->confs_info = data->confs_info;
pinctrl->num_irq_pins = data->num_irq_pins;
err = pinctrl_enable(pinctrl->ctrl);
if (err)

1
drivers/pinctrl/airoha/pinctrl-an7563.c
View File

@ -1069,6 +1069,7 @@ static const struct airoha_pinctrl_match_data pinctrl_match_data = {
.num_grps = ARRAY_SIZE(pinctrl_groups),
.funcs = pinctrl_funcs,
.num_funcs = ARRAY_SIZE(pinctrl_funcs),
.num_irq_pins = AIROHA_NUM_PINS,
.confs_info = {
[AIROHA_PINCTRL_CONFS_PULLUP] = {
.confs = pinctrl_pullup_conf,

1
drivers/pinctrl/airoha/pinctrl-an7581.c
View File

@ -1441,6 +1441,7 @@ static const struct airoha_pinctrl_match_data pinctrl_match_data = {
.num_grps = ARRAY_SIZE(pinctrl_groups),
.funcs = pinctrl_funcs,
.num_funcs = ARRAY_SIZE(pinctrl_funcs),
.num_irq_pins = AIROHA_NUM_PINS,
.confs_info = {
[AIROHA_PINCTRL_CONFS_PULLUP] = {
.confs = pinctrl_pullup_conf,

1
drivers/pinctrl/airoha/pinctrl-an7583.c
View File

@ -1471,6 +1471,7 @@ static const struct airoha_pinctrl_match_data pinctrl_match_data = {
.num_grps = ARRAY_SIZE(pinctrl_groups),
.funcs = pinctrl_funcs,
.num_funcs = ARRAY_SIZE(pinctrl_funcs),
.num_irq_pins = AIROHA_NUM_PINS,
.confs_info = {
[AIROHA_PINCTRL_CONFS_PULLUP] = {
.confs = pinctrl_pullup_conf,

1
drivers/pinctrl/airoha/pinctrl-en7523.c
View File

@ -1113,6 +1113,7 @@ static const struct airoha_pinctrl_match_data pinctrl_match_data = {
.num_grps = ARRAY_SIZE(pinctrl_groups),
.funcs = pinctrl_funcs,
.num_funcs = ARRAY_SIZE(pinctrl_funcs),
.num_irq_pins = AIROHA_NUM_PINS,
.confs_info = {
[AIROHA_PINCTRL_CONFS_PULLUP] = {
.confs = pinctrl_pullup_conf,

1204
drivers/pinctrl/airoha/pinctrl-en7528.c Normal file
View File

File diff suppressed because it is too large Load Diff

4
drivers/pinctrl/core.c
View File

@ -147,7 +147,7 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name)
{
unsigned int i, pin;
/* The pin number can be retrived from the pin controller descriptor */
/* The pin number can be retrieved from the pin controller descriptor */
for (i = 0; i < pctldev->desc->npins; i++) {
struct pin_desc *desc;
@ -1747,7 +1747,7 @@ static int pinctrl_pins_show(struct seq_file *s, void *what)
mutex_lock(&pctldev->mutex);
/* The pin number can be retrived from the pin controller descriptor */
/* The pin number can be retrieved from the pin controller descriptor */
for (i = 0; i < pctldev->desc->npins; i++) {
struct pin_desc *desc;

2
drivers/pinctrl/freescale/pinctrl-imx.c
View File

@ -646,7 +646,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
}
group_names = devm_kcalloc(ipctl->dev, func->ngroups,
sizeof(*func->groups), GFP_KERNEL);
sizeof(*group_names), GFP_KERNEL);
if (!group_names)
return -ENOMEM;
i = 0;

51
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -1702,35 +1702,42 @@ int intel_pinctrl_probe(struct platform_device *pdev,
}
EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe, "PINCTRL_INTEL");
static const struct intel_pinctrl_soc_data *
intel_pinctrl_get_soc_data_by_hid(const struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *data;
const struct device *dev = &pdev->dev;
const struct platform_device_id *id;
data = device_get_match_data(dev);
if (data)
return data;
id = platform_get_device_id(pdev);
if (!id)
return ERR_PTR(-ENODEV);
data = (const struct intel_pinctrl_soc_data *)id->driver_data;
return data ?: ERR_PTR(-ENODATA);
}
int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *data;
data = device_get_match_data(&pdev->dev);
if (!data)
return -ENODATA;
return intel_pinctrl_probe(pdev, data);
}
EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_hid, "PINCTRL_INTEL");
int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *data;
data = intel_pinctrl_get_soc_data(pdev);
data = intel_pinctrl_get_soc_data_by_hid(pdev);
if (IS_ERR(data))
return PTR_ERR(data);
return intel_pinctrl_probe(pdev, data);
}
EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_uid, "PINCTRL_INTEL");
EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_hid, "PINCTRL_INTEL");
const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(const struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data * const *table;
const struct intel_pinctrl_soc_data *data;
struct device *dev = &pdev->dev;
const struct device *dev = &pdev->dev;
table = device_get_match_data(dev);
if (table) {
@ -1757,6 +1764,18 @@ const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_
}
EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, "PINCTRL_INTEL");
int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *data;
data = intel_pinctrl_get_soc_data(pdev);
if (IS_ERR(data))
return PTR_ERR(data);
return intel_pinctrl_probe(pdev, data);
}
EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_uid, "PINCTRL_INTEL");
static bool __intel_gpio_is_direct_irq(u32 value)
{
return (value & PADCFG0_GPIROUTIOXAPIC) &&

2
drivers/pinctrl/intel/pinctrl-intel.h
View File

@ -225,7 +225,7 @@ struct intel_pinctrl_soc_data {
size_t ncommunities;
};
const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev);
const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(const struct platform_device *pdev);
struct intel_pad_context;
struct intel_community_context;

7
drivers/pinctrl/mediatek/Kconfig
View File

@ -133,6 +133,13 @@ config PINCTRL_MT2712
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK
config PINCTRL_MT6735
bool "MediaTek MT6735(M) pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT6765
tristate "MediaTek MT6765 pin control"
depends on OF

1
drivers/pinctrl/mediatek/Makefile
View File

@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT6735) += pinctrl-mt6735.o
obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o
obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o

1120
drivers/pinctrl/mediatek/pinctrl-mt6735.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/pinctrl/mediatek/pinctrl-mt7629.c
View File

@ -294,7 +294,7 @@ static int mt7629_pwm_1_funcs[] = { 2, };
/* WF 2G */
static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, };
/* WF 5G */
static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };

3
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
View File

@ -1032,7 +1032,8 @@ static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev)
pctl->eint->nbase = 1;
/* mtk-eint expects an array */
pctl->eint->base = devm_kzalloc(pctl->dev, sizeof(pctl->eint->base), GFP_KERNEL);
pctl->eint->base = devm_kzalloc(pctl->dev, sizeof(*pctl->eint->base),
GFP_KERNEL);
if (!pctl->eint->base)
return -ENOMEM;

3993
drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c
View File

@ -612,7 +612,7 @@ static void mpfs_pinctrl_pinconf_dbg_show(struct pinctrl_dev *pctrl_dev, struct
reg = mpfs_pinctrl_pin_to_iocfg_reg(pin);
offset = mpfs_pinctrl_pin_to_iocfg_offset(pin);
seq_printf(seq, "pin: %u ", pin);
seq_printf(seq, " pin: %u ", pin);
seq_printf(seq, "reg: %x offset: %u ", reg, offset);
if (reg < 0 || offset < 0)

8
drivers/pinctrl/nuvoton/pinctrl-ma35.c
View File

@ -557,6 +557,8 @@ static int ma35_gpiolib_register(struct platform_device *pdev, struct ma35_pinct
static int ma35_get_bank_data(struct ma35_pin_bank *bank)
{
int ret;
bank->reg_base = fwnode_iomap(bank->fwnode, 0);
if (!bank->reg_base)
return -ENOMEM;
@ -569,7 +571,11 @@ static int ma35_get_bank_data(struct ma35_pin_bank *bank)
if (IS_ERR(bank->clk))
return PTR_ERR(bank->clk);
return clk_prepare_enable(bank->clk);
ret = clk_prepare_enable(bank->clk);
if (ret)
clk_put(bank->clk);
return ret;
}
static int ma35_pinctrl_get_soc_data(struct ma35_pinctrl *pctl, struct platform_device *pdev)

2
drivers/pinctrl/nxp/pinctrl-s32cc.c
View File

@ -825,7 +825,7 @@ static int s32_pinctrl_parse_functions(struct device_node *np,
"No groups defined in %pOF\n", np);
groups = devm_kcalloc(info->dev, func->ngroups,
sizeof(*func->groups), GFP_KERNEL);
sizeof(*groups), GFP_KERNEL);
if (!groups)
return -ENOMEM;

2
drivers/pinctrl/pinconf-generic.c
View File

@ -43,6 +43,7 @@ static const struct pin_config_item conf_items[] = {
PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA", true),
PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH_UA, "output drive strength", "uA", true),
PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec", true),
PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE_NS, "input debounce", "nsec", true),
PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL, false),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_UV, "input schmitt threshold", "uV", true),
@ -185,6 +186,7 @@ static const struct pinconf_generic_params dt_params[] = {
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
{ "drive-strength-microamp", PIN_CONFIG_DRIVE_STRENGTH_UA, 0 },
{ "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
{ "input-debounce-ns", PIN_CONFIG_INPUT_DEBOUNCE_NS, 0 },
{ "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
{ "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
{ "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 },

2
drivers/pinctrl/pinconf.c
View File

@ -311,7 +311,7 @@ static int pinconf_pins_show(struct seq_file *s, void *what)
mutex_lock(&pctldev->mutex);
/* The pin number can be retrived from the pin controller descriptor */
/* The pin number can be retrieved from the pin controller descriptor */
for (i = 0; i < pctldev->desc->npins; i++) {
struct pin_desc *desc;

587
drivers/pinctrl/pinctrl-ambarella-cv75.c Normal file
View File

@ -0,0 +1,587 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Ambarella CV75 pinctrl data
*
* Copyright (C) 2026, Ambarella, Inc.
*/
#include <linux/array_size.h>
#include <linux/build_bug.h>
#include <linux/types.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-ambarella.h"
#define CV75_EXPAND(...) __VA_ARGS__
#define CV75_GROUP_PINS_ALTS(_name, _pin_list, _alt_list) \
static const unsigned int cv75_##_name##_pins[] = { CV75_EXPAND _pin_list }; \
static const u8 cv75_##_name##_alts[] = { CV75_EXPAND _alt_list }; \
static const struct pingroup cv75_##_name##_grp = \
PINCTRL_PINGROUP(#_name, cv75_##_name##_pins, \
ARRAY_SIZE(cv75_##_name##_pins)); \
static_assert(ARRAY_SIZE(cv75_##_name##_pins) == \
ARRAY_SIZE(cv75_##_name##_alts))
#define CV75_GROUP(_name) \
{ \
.grp = &cv75_##_name##_grp, \
.alts = cv75_##_name##_alts, \
}
#define CV75_FUNCTION(_name) \
PINCTRL_PINFUNCTION(#_name, cv75_##_name##_groups, ARRAY_SIZE(cv75_##_name##_groups))
/* UART */
CV75_GROUP_PINS_ALTS(uart0, (44, 45), (1, 1));
CV75_GROUP_PINS_ALTS(uart1, (46, 47), (1, 1));
CV75_GROUP_PINS_ALTS(uart1_flow, (48, 49), (1, 1));
CV75_GROUP_PINS_ALTS(uart2_a, (46, 47), (2, 2));
CV75_GROUP_PINS_ALTS(uart2_b, (50, 51), (2, 2));
CV75_GROUP_PINS_ALTS(uart2_c, (66, 68), (2, 2));
CV75_GROUP_PINS_ALTS(uart2_flow_a, (48, 49), (2, 2));
CV75_GROUP_PINS_ALTS(uart2_flow_b, (65, 67), (3, 3));
CV75_GROUP_PINS_ALTS(uart3_a, (70, 72), (3, 3));
CV75_GROUP_PINS_ALTS(uart3_b, (80, 79), (3, 3));
CV75_GROUP_PINS_ALTS(uart3_flow_a, (71, 69), (3, 3));
CV75_GROUP_PINS_ALTS(uart3_flow_b, (81, 82), (3, 3));
CV75_GROUP_PINS_ALTS(uart4_a, (29, 30), (3, 3));
CV75_GROUP_PINS_ALTS(uart4_b, (76, 77), (3, 3));
CV75_GROUP_PINS_ALTS(uart4_flow_a, (28, 31), (3, 3));
CV75_GROUP_PINS_ALTS(uart4_flow_b, (74, 75), (3, 3));
/* Flash */
CV75_GROUP_PINS_ALTS(snand, (79, 80, 81, 82, 83, 84), (1, 1, 1, 1, 1, 1));
CV75_GROUP_PINS_ALTS(spinor, (79, 80, 81, 82, 83, 84, 85),
(2, 2, 2, 2, 2, 2, 2));
/* SD/MMC */
CV75_GROUP_PINS_ALTS(sdmmc0_cd, (6), (1));
CV75_GROUP_PINS_ALTS(sdmmc0_wp, (7), (1));
CV75_GROUP_PINS_ALTS(sdmmc0_reset, (8), (1));
CV75_GROUP_PINS_ALTS(sdmmc0_hs_sel, (93), (1));
CV75_GROUP_PINS_ALTS(sdmmc0_1bit, (0, 4, 5), (1, 1, 1));
CV75_GROUP_PINS_ALTS(sdmmc0_4bit, (0, 1, 2, 3, 4, 5), (1, 1, 1, 1, 1, 1));
CV75_GROUP_PINS_ALTS(sdmmc1_cd, (15), (1));
CV75_GROUP_PINS_ALTS(sdmmc1_wp, (16), (1));
CV75_GROUP_PINS_ALTS(sdmmc1_reset, (17), (1));
CV75_GROUP_PINS_ALTS(sdmmc1_hs_sel, (94), (1));
CV75_GROUP_PINS_ALTS(sdmmc1_1bit, (9, 13, 14), (1, 1, 1));
CV75_GROUP_PINS_ALTS(sdmmc1_4bit, (9, 10, 11, 12, 13, 14), (1, 1, 1, 1, 1, 1));
/* Ethernet */
CV75_GROUP_PINS_ALTS(enet_ext_osc_clk, (77), (1));
CV75_GROUP_PINS_ALTS(enet_2nd_ref_clk_a, (78), (1));
CV75_GROUP_PINS_ALTS(enet_2nd_ref_clk_b, (76), (2));
CV75_GROUP_PINS_ALTS(enet0_ptp_pps_o, (74), (1));
CV75_GROUP_PINS_ALTS(rgmii0, (62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 75, 76),
(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1));
CV75_GROUP_PINS_ALTS(rmii0, (62, 63, 64, 67, 68, 71, 72, 73, 75),
(1, 1, 1, 1, 1, 1, 1, 1, 2));
/* I2C */
CV75_GROUP_PINS_ALTS(i2c0_a, (67, 68), (2, 2));
CV75_GROUP_PINS_ALTS(i2c0_b, (86, 87), (1, 1));
CV75_GROUP_PINS_ALTS(i2c1_a, (22, 23), (2, 2));
CV75_GROUP_PINS_ALTS(i2c1_b, (69, 70), (2, 2));
CV75_GROUP_PINS_ALTS(i2c2, (88, 89), (1, 1));
CV75_GROUP_PINS_ALTS(i2c3_a, (24, 25), (2, 2));
CV75_GROUP_PINS_ALTS(i2c3_b, (48, 49), (3, 3));
CV75_GROUP_PINS_ALTS(i2c3_c, (58, 59), (3, 3));
CV75_GROUP_PINS_ALTS(i2cs_a, (19, 21), (2, 2));
CV75_GROUP_PINS_ALTS(i2cs_b, (60, 61), (3, 3));
CV75_GROUP_PINS_ALTS(i2cs_c, (71, 72), (2, 2));
CV75_GROUP_PINS_ALTS(i2cs_d, (86, 87), (2, 2));
/* CAN, IR, WDT */
CV75_GROUP_PINS_ALTS(can0, (50, 51), (1, 1));
CV75_GROUP_PINS_ALTS(can1, (52, 53), (1, 1));
CV75_GROUP_PINS_ALTS(ir, (18), (1));
CV75_GROUP_PINS_ALTS(wdt_a, (20), (2));
CV75_GROUP_PINS_ALTS(wdt_b, (27), (3));
CV75_GROUP_PINS_ALTS(wdt_c, (39), (2));
CV75_GROUP_PINS_ALTS(wdt_d, (83), (3));
CV75_GROUP_PINS_ALTS(wdt_e, (85), (4));
CV75_GROUP_PINS_ALTS(wdt_f, (90), (1));
/* I2S */
CV75_GROUP_PINS_ALTS(i2s0, (54, 55, 56, 57), (1, 1, 1, 1));
CV75_GROUP_PINS_ALTS(i2s1, (58, 59, 60, 61), (1, 1, 1, 1));
CV75_GROUP_PINS_ALTS(dmic0, (54, 55), (2, 2));
/* PWM */
CV75_GROUP_PINS_ALTS(pwm0, (40), (1));
CV75_GROUP_PINS_ALTS(pwm1, (41), (1));
CV75_GROUP_PINS_ALTS(pwm2, (42), (1));
CV75_GROUP_PINS_ALTS(pwm3, (43), (1));
CV75_GROUP_PINS_ALTS(pwm4_a, (19), (3));
CV75_GROUP_PINS_ALTS(pwm4_b, (32), (4));
CV75_GROUP_PINS_ALTS(pwm5_a, (20), (3));
CV75_GROUP_PINS_ALTS(pwm5_b, (33), (4));
CV75_GROUP_PINS_ALTS(pwm6_a, (21), (3));
CV75_GROUP_PINS_ALTS(pwm6_b, (34), (4));
CV75_GROUP_PINS_ALTS(pwm7_a, (22), (3));
CV75_GROUP_PINS_ALTS(pwm7_b, (35), (4));
CV75_GROUP_PINS_ALTS(pwm8_a, (23), (3));
CV75_GROUP_PINS_ALTS(pwm8_b, (36), (4));
CV75_GROUP_PINS_ALTS(pwm9_a, (24), (3));
CV75_GROUP_PINS_ALTS(pwm9_b, (37), (4));
CV75_GROUP_PINS_ALTS(pwm10_a, (25), (3));
CV75_GROUP_PINS_ALTS(pwm10_b, (38), (4));
CV75_GROUP_PINS_ALTS(pwm11_a, (26), (3));
CV75_GROUP_PINS_ALTS(pwm11_b, (39), (4));
/* SPI */
CV75_GROUP_PINS_ALTS(spi0, (19, 20, 21), (1, 1, 1));
CV75_GROUP_PINS_ALTS(spi1, (24, 25, 26), (1, 1, 1));
CV75_GROUP_PINS_ALTS(spi2, (28, 29, 30), (1, 1, 1));
CV75_GROUP_PINS_ALTS(spi3_a, (32, 33, 34), (5, 5, 5));
CV75_GROUP_PINS_ALTS(spi3_b, (40, 41, 43), (2, 2, 2));
CV75_GROUP_PINS_ALTS(spi3_c, (58, 59, 60), (2, 2, 2));
CV75_GROUP_PINS_ALTS(spi_slave_a, (24, 25, 26, 27), (4, 4, 4, 4));
CV75_GROUP_PINS_ALTS(spi_slave_b, (28, 29, 30, 31), (2, 2, 2, 2));
CV75_GROUP_PINS_ALTS(spi_slave_c, (36, 37, 38, 39), (5, 5, 5, 5));
CV75_GROUP_PINS_ALTS(spi_slave_d, (50, 51, 52, 53), (3, 3, 3, 3));
CV75_GROUP_PINS_ALTS(spi_slave_e, (81, 82, 83, 84), (4, 4, 4, 4));
/* VIN master sync */
CV75_GROUP_PINS_ALTS(vin_master_sync_a, (91, 92), (1, 1));
CV75_GROUP_PINS_ALTS(vin_master_sync_b, (91, 92), (2, 2));
CV75_GROUP_PINS_ALTS(vin_master_sync_c, (40, 41), (3, 3));
CV75_GROUP_PINS_ALTS(vin_master_sync_d, (46, 47), (3, 3));
CV75_GROUP_PINS_ALTS(vin_master_sync_e, (79, 80), (4, 4));
CV75_GROUP_PINS_ALTS(vsync0, (32), (1));
CV75_GROUP_PINS_ALTS(vsync1, (33), (1));
CV75_GROUP_PINS_ALTS(vsync2, (34), (1));
CV75_GROUP_PINS_ALTS(vsync3, (35), (1));
CV75_GROUP_PINS_ALTS(hsync0, (36), (1));
CV75_GROUP_PINS_ALTS(hsync1, (37), (1));
static const struct amb_pinmux_group cv75_pin_groups[] = {
/* UART */
CV75_GROUP(uart0),
CV75_GROUP(uart1),
CV75_GROUP(uart1_flow),
CV75_GROUP(uart2_a),
CV75_GROUP(uart2_b),
CV75_GROUP(uart2_c),
CV75_GROUP(uart2_flow_a),
CV75_GROUP(uart2_flow_b),
CV75_GROUP(uart3_a),
CV75_GROUP(uart3_b),
CV75_GROUP(uart3_flow_a),
CV75_GROUP(uart3_flow_b),
CV75_GROUP(uart4_a),
CV75_GROUP(uart4_b),
CV75_GROUP(uart4_flow_a),
CV75_GROUP(uart4_flow_b),
/* Flash */
CV75_GROUP(snand),
CV75_GROUP(spinor),
/* SD/MMC */
CV75_GROUP(sdmmc0_cd),
CV75_GROUP(sdmmc0_wp),
CV75_GROUP(sdmmc0_reset),
CV75_GROUP(sdmmc0_hs_sel),
CV75_GROUP(sdmmc0_1bit),
CV75_GROUP(sdmmc0_4bit),
CV75_GROUP(sdmmc1_cd),
CV75_GROUP(sdmmc1_wp),
CV75_GROUP(sdmmc1_reset),
CV75_GROUP(sdmmc1_hs_sel),
CV75_GROUP(sdmmc1_1bit),
CV75_GROUP(sdmmc1_4bit),
/* Ethernet */
CV75_GROUP(enet_ext_osc_clk),
CV75_GROUP(enet_2nd_ref_clk_a),
CV75_GROUP(enet_2nd_ref_clk_b),
CV75_GROUP(enet0_ptp_pps_o),
CV75_GROUP(rgmii0),
CV75_GROUP(rmii0),
/* I2C */
CV75_GROUP(i2c0_a),
CV75_GROUP(i2c0_b),
CV75_GROUP(i2c1_a),
CV75_GROUP(i2c1_b),
CV75_GROUP(i2c2),
CV75_GROUP(i2c3_a),
CV75_GROUP(i2c3_b),
CV75_GROUP(i2c3_c),
CV75_GROUP(i2cs_a),
CV75_GROUP(i2cs_b),
CV75_GROUP(i2cs_c),
CV75_GROUP(i2cs_d),
/* CAN, IR, WDT */
CV75_GROUP(can0),
CV75_GROUP(can1),
CV75_GROUP(ir),
CV75_GROUP(wdt_a),
CV75_GROUP(wdt_b),
CV75_GROUP(wdt_c),
CV75_GROUP(wdt_d),
CV75_GROUP(wdt_e),
CV75_GROUP(wdt_f),
/* I2S */
CV75_GROUP(i2s0),
CV75_GROUP(i2s1),
CV75_GROUP(dmic0),
/* PWM */
CV75_GROUP(pwm0),
CV75_GROUP(pwm1),
CV75_GROUP(pwm2),
CV75_GROUP(pwm3),
CV75_GROUP(pwm4_a),
CV75_GROUP(pwm4_b),
CV75_GROUP(pwm5_a),
CV75_GROUP(pwm5_b),
CV75_GROUP(pwm6_a),
CV75_GROUP(pwm6_b),
CV75_GROUP(pwm7_a),
CV75_GROUP(pwm7_b),
CV75_GROUP(pwm8_a),
CV75_GROUP(pwm8_b),
CV75_GROUP(pwm9_a),
CV75_GROUP(pwm9_b),
CV75_GROUP(pwm10_a),
CV75_GROUP(pwm10_b),
CV75_GROUP(pwm11_a),
CV75_GROUP(pwm11_b),
/* SPI */
CV75_GROUP(spi0),
CV75_GROUP(spi1),
CV75_GROUP(spi2),
CV75_GROUP(spi3_a),
CV75_GROUP(spi3_b),
CV75_GROUP(spi3_c),
CV75_GROUP(spi_slave_a),
CV75_GROUP(spi_slave_b),
CV75_GROUP(spi_slave_c),
CV75_GROUP(spi_slave_d),
CV75_GROUP(spi_slave_e),
/* VIN master sync */
CV75_GROUP(vin_master_sync_a),
CV75_GROUP(vin_master_sync_b),
CV75_GROUP(vin_master_sync_c),
CV75_GROUP(vin_master_sync_d),
CV75_GROUP(vin_master_sync_e),
CV75_GROUP(vsync0),
CV75_GROUP(vsync1),
CV75_GROUP(vsync2),
CV75_GROUP(vsync3),
CV75_GROUP(hsync0),
CV75_GROUP(hsync1),
};
static const char * const cv75_uart0_groups[] = {
"uart0",
};
static const char * const cv75_uart1_groups[] = {
"uart1",
"uart1_flow",
};
static const char * const cv75_uart2_groups[] = {
"uart2_a",
"uart2_b",
"uart2_c",
"uart2_flow_a",
"uart2_flow_b",
};
static const char * const cv75_uart3_groups[] = {
"uart3_a",
"uart3_b",
"uart3_flow_a",
"uart3_flow_b",
};
static const char * const cv75_uart4_groups[] = {
"uart4_a",
"uart4_b",
"uart4_flow_a",
"uart4_flow_b",
};
static const char * const cv75_snand_groups[] = {
"snand",
};
static const char * const cv75_spinor_groups[] = {
"spinor",
};
static const char * const cv75_sdmmc0_groups[] = {
"sdmmc0_cd",
"sdmmc0_wp",
"sdmmc0_reset",
"sdmmc0_hs_sel",
"sdmmc0_1bit",
"sdmmc0_4bit",
};
static const char * const cv75_sdmmc1_groups[] = {
"sdmmc1_cd",
"sdmmc1_wp",
"sdmmc1_reset",
"sdmmc1_hs_sel",
"sdmmc1_1bit",
"sdmmc1_4bit",
};
static const char * const cv75_enet0_groups[] = {
"enet_ext_osc_clk",
"enet_2nd_ref_clk_a",
"enet_2nd_ref_clk_b",
"enet0_ptp_pps_o",
"rgmii0",
"rmii0",
};
static const char * const cv75_i2c0_groups[] = {
"i2c0_a",
"i2c0_b",
};
static const char * const cv75_i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
};
static const char * const cv75_i2c2_groups[] = {
"i2c2",
};
static const char * const cv75_i2c3_groups[] = {
"i2c3_a",
"i2c3_b",
"i2c3_c",
};
static const char * const cv75_i2cs_groups[] = {
"i2cs_a",
"i2cs_b",
"i2cs_c",
"i2cs_d",
};
static const char * const cv75_can0_groups[] = {
"can0",
};
static const char * const cv75_can1_groups[] = {
"can1",
};
static const char * const cv75_ir_groups[] = {
"ir",
};
static const char * const cv75_wdt_groups[] = {
"wdt_a",
"wdt_b",
"wdt_c",
"wdt_d",
"wdt_e",
"wdt_f",
};
static const char * const cv75_i2s0_groups[] = {
"i2s0",
};
static const char * const cv75_i2s1_groups[] = {
"i2s1",
};
static const char * const cv75_dmic0_groups[] = {
"dmic0",
};
static const char * const cv75_pwm0_groups[] = {
"pwm0",
};
static const char * const cv75_pwm1_groups[] = {
"pwm1",
};
static const char * const cv75_pwm2_groups[] = {
"pwm2",
};
static const char * const cv75_pwm3_groups[] = {
"pwm3",
};
static const char * const cv75_pwm4_groups[] = {
"pwm4_a",
"pwm4_b",
};
static const char * const cv75_pwm5_groups[] = {
"pwm5_a",
"pwm5_b",
};
static const char * const cv75_pwm6_groups[] = {
"pwm6_a",
"pwm6_b",
};
static const char * const cv75_pwm7_groups[] = {
"pwm7_a",
"pwm7_b",
};
static const char * const cv75_pwm8_groups[] = {
"pwm8_a",
"pwm8_b",
};
static const char * const cv75_pwm9_groups[] = {
"pwm9_a",
"pwm9_b",
};
static const char * const cv75_pwm10_groups[] = {
"pwm10_a",
"pwm10_b",
};
static const char * const cv75_pwm11_groups[] = {
"pwm11_a",
"pwm11_b",
};
static const char * const cv75_spi0_groups[] = {
"spi0",
};
static const char * const cv75_spi1_groups[] = {
"spi1",
};
static const char * const cv75_spi2_groups[] = {
"spi2",
};
static const char * const cv75_spi3_groups[] = {
"spi3_a",
"spi3_b",
"spi3_c",
};
static const char * const cv75_spi_slave_groups[] = {
"spi_slave_a",
"spi_slave_b",
"spi_slave_c",
"spi_slave_d",
"spi_slave_e",
};
static const char * const cv75_vin_master_sync_groups[] = {
"vin_master_sync_a",
"vin_master_sync_b",
"vin_master_sync_c",
"vin_master_sync_d",
"vin_master_sync_e",
};
static const char * const cv75_vsync0_groups[] = {
"vsync0",
};
static const char * const cv75_vsync1_groups[] = {
"vsync1",
};
static const char * const cv75_vsync2_groups[] = {
"vsync2",
};
static const char * const cv75_vsync3_groups[] = {
"vsync3",
};
static const char * const cv75_hsync0_groups[] = {
"hsync0",
};
static const char * const cv75_hsync1_groups[] = {
"hsync1",
};
static const struct pinfunction cv75_pin_functions[] = {
CV75_FUNCTION(uart0),
CV75_FUNCTION(uart1),
CV75_FUNCTION(uart2),
CV75_FUNCTION(uart3),
CV75_FUNCTION(uart4),
CV75_FUNCTION(snand),
CV75_FUNCTION(spinor),
CV75_FUNCTION(sdmmc0),
CV75_FUNCTION(sdmmc1),
CV75_FUNCTION(enet0),
CV75_FUNCTION(i2c0),
CV75_FUNCTION(i2c1),
CV75_FUNCTION(i2c2),
CV75_FUNCTION(i2c3),
CV75_FUNCTION(i2cs),
CV75_FUNCTION(can0),
CV75_FUNCTION(can1),
CV75_FUNCTION(ir),
CV75_FUNCTION(wdt),
CV75_FUNCTION(i2s0),
CV75_FUNCTION(i2s1),
CV75_FUNCTION(dmic0),
CV75_FUNCTION(pwm0),
CV75_FUNCTION(pwm1),
CV75_FUNCTION(pwm2),
CV75_FUNCTION(pwm3),
CV75_FUNCTION(pwm4),
CV75_FUNCTION(pwm5),
CV75_FUNCTION(pwm6),
CV75_FUNCTION(pwm7),
CV75_FUNCTION(pwm8),
CV75_FUNCTION(pwm9),
CV75_FUNCTION(pwm10),
CV75_FUNCTION(pwm11),
CV75_FUNCTION(spi0),
CV75_FUNCTION(spi1),
CV75_FUNCTION(spi2),
CV75_FUNCTION(spi3),
CV75_FUNCTION(spi_slave),
CV75_FUNCTION(vin_master_sync),
CV75_FUNCTION(vsync0),
CV75_FUNCTION(vsync1),
CV75_FUNCTION(vsync2),
CV75_FUNCTION(vsync3),
CV75_FUNCTION(hsync0),
CV75_FUNCTION(hsync1),
};
const struct amb_pinctrl_data ambarella_cv75_pinctrl_data = {
.groups = cv75_pin_groups,
.functions = cv75_pin_functions,
.ngroups = ARRAY_SIZE(cv75_pin_groups),
.nfunctions = ARRAY_SIZE(cv75_pin_functions),
.nr_banks = 3,
.npins = 96,
.ds0 = {
0x314, 0x320, 0x32c,
},
.ds1 = {
0x318, 0x324, 0x330,
},
.ds2 = {
0x31c, 0x328, 0x334,
},
.pull_en = {
0x60, 0x64, 0x68,
},
.pull_dir = {
0x7c, 0x80, 0x84,
},
.have_ds2 = true,
};

533
drivers/pinctrl/pinctrl-ambarella.c Normal file
View File

@ -0,0 +1,533 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Pinctrl driver for Ambarella SoCs
*
* Copyright (C) 2012-2026, Ambarella, Inc.
*/
#include <linux/array_size.h>
#include <linux/bitops.h>
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/string_helpers.h>
#include <linux/types.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinmux.h"
#include "pinctrl-ambarella.h"
#define IOMUX_REG(bank, n) (((bank) * 0xc) + ((n) * 4))
#define IOMUX_CTRL_SET 0xf0
#define PINID_TO_BANK(p) ((p) >> 5)
#define PINID_TO_OFFSET(p) ((p) & 0x1f)
struct amb_pinctrl {
struct pinctrl_desc desc;
void __iomem *iomux_base;
struct regmap *ds_regmap;
struct regmap *pull_regmap;
const struct amb_pinctrl_data *data;
struct device *dev;
struct pinctrl_dev *pctl;
spinlock_t lock;
};
static const int amb_ds1_ma[] = { 2, 4, 8, 12 };
static const int amb_ds2_ma[] = { 3, 4, 6, 8, 9, 12 };
static const struct pinctrl_ops amb_pctrl_ops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinconf_generic_dt_free_map,
};
static void amb_iomux_commit(struct amb_pinctrl *ipc)
{
writel(0x1, ipc->iomux_base + IOMUX_CTRL_SET);
writel(0x0, ipc->iomux_base + IOMUX_CTRL_SET);
}
static void amb_pinmux_set_altfunc(struct amb_pinctrl *ipc, u32 bank,
u32 offset, u32 altfunc)
{
if (bank >= ipc->data->nr_banks)
return;
for (unsigned int i = 0; i < 3; i++) {
unsigned long data;
data = readl_relaxed(ipc->iomux_base + IOMUX_REG(bank, i));
__assign_bit(offset, &data, altfunc & BIT(i));
writel_relaxed(data, ipc->iomux_base + IOMUX_REG(bank, i));
}
}
static int amb_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned int group)
{
struct amb_pinctrl *ipc = pinctrl_dev_get_drvdata(pctldev);
struct group_desc *grp;
const u8 *alts;
unsigned long flags;
(void)selector;
grp = pinctrl_generic_get_group(pctldev, group);
if (!grp || !grp->data)
return -EINVAL;
alts = grp->data;
spin_lock_irqsave(&ipc->lock, flags);
for (unsigned int i = 0; i < grp->grp.npins; i++) {
unsigned int pin = grp->grp.pins[i];
amb_pinmux_set_altfunc(ipc, PINID_TO_BANK(pin),
PINID_TO_OFFSET(pin), alts[i]);
}
amb_iomux_commit(ipc);
spin_unlock_irqrestore(&ipc->lock, flags);
return 0;
}
static int amb_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct amb_pinctrl *ipc = pinctrl_dev_get_drvdata(pctldev);
unsigned long flags;
if (!range || !range->gc)
return -EINVAL;
if (pin >= ipc->data->npins)
return -EINVAL;
spin_lock_irqsave(&ipc->lock, flags);
amb_pinmux_set_altfunc(ipc, PINID_TO_BANK(pin), PINID_TO_OFFSET(pin), 0);
amb_iomux_commit(ipc);
spin_unlock_irqrestore(&ipc->lock, flags);
return 0;
}
static const struct pinmux_ops amb_pinmux_ops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = amb_pinmux_set_mux,
.gpio_request_enable = amb_pinmux_gpio_request_enable,
.strict = true,
};
static int amb_drive_strength_to_reg_ds1(u32 strength)
{
for (unsigned int i = 0; i < ARRAY_SIZE(amb_ds1_ma); i++) {
if (amb_ds1_ma[i] == strength)
return i;
}
return -EINVAL;
}
static int amb_drive_strength_to_reg_ds2(u32 strength)
{
/* Hardware steps are 3, 4, 6, 8, 9, 12 mA; 5 and 7 are accepted aliases */
if (strength == 5)
strength = 4;
else if (strength == 7)
strength = 8;
for (unsigned int i = 0; i < ARRAY_SIZE(amb_ds2_ma); i++) {
if (amb_ds2_ma[i] == strength)
return i;
}
return -EINVAL;
}
static int amb_drive_strength_to_reg(const struct amb_pinctrl *ipc, u32 strength)
{
if (ipc->data->have_ds2)
return amb_drive_strength_to_reg_ds2(strength);
return amb_drive_strength_to_reg_ds1(strength);
}
static int amb_reg_to_drive_strength(const struct amb_pinctrl *ipc, u32 ds)
{
if (ipc->data->have_ds2) {
if (ds >= ARRAY_SIZE(amb_ds2_ma))
return -EINVAL;
return amb_ds2_ma[ds];
}
if (ds >= ARRAY_SIZE(amb_ds1_ma))
return -EINVAL;
return amb_ds1_ma[ds];
}
static int amb_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct amb_pinctrl *ipc = pinctrl_dev_get_drvdata(pctldev);
u32 bank = PINID_TO_BANK(pin);
u32 offset = PINID_TO_OFFSET(pin);
unsigned int mask = BIT(offset);
int ret;
if (bank >= ipc->data->nr_banks)
return -EINVAL;
for (unsigned int i = 0; i < num_configs; i++) {
enum pin_config_param param = pinconf_to_config_param(configs[i]);
u32 arg = pinconf_to_config_argument(configs[i]);
int ds;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ret = regmap_assign_bits(ipc->pull_regmap, ipc->data->pull_en[bank],
mask, false);
if (ret)
return ret;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_UP:
ret = regmap_assign_bits(ipc->pull_regmap, ipc->data->pull_dir[bank],
mask, param == PIN_CONFIG_BIAS_PULL_UP);
if (ret)
return ret;
ret = regmap_assign_bits(ipc->pull_regmap, ipc->data->pull_en[bank],
mask, true);
if (ret)
return ret;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
ds = amb_drive_strength_to_reg(ipc, arg);
if (ds < 0)
return ds;
if (ipc->data->have_ds2) {
ret = regmap_assign_bits(ipc->ds_regmap, ipc->data->ds0[bank],
mask, ds & BIT(0));
if (ret)
return ret;
ret = regmap_assign_bits(ipc->ds_regmap, ipc->data->ds1[bank],
mask, ds & BIT(1));
if (ret)
return ret;
ret = regmap_assign_bits(ipc->ds_regmap, ipc->data->ds2[bank],
mask, ds & BIT(2));
if (ret)
return ret;
} else {
ret = regmap_assign_bits(ipc->ds_regmap, ipc->data->ds0[bank],
mask, ds & BIT(1));
if (ret)
return ret;
ret = regmap_assign_bits(ipc->ds_regmap, ipc->data->ds1[bank],
mask, ds & BIT(0));
if (ret)
return ret;
}
break;
default:
return -ENOTSUPP;
}
}
return 0;
}
static int amb_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *configs,
unsigned int num_configs)
{
const unsigned int *pins;
unsigned int npins;
int ret;
ret = pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins);
if (ret)
return ret;
for (unsigned int i = 0; i < npins; i++) {
ret = amb_pinconf_set(pctldev, pins[i], configs, num_configs);
if (ret)
return ret;
}
return 0;
}
static int amb_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct amb_pinctrl *ipc = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
u32 bank = PINID_TO_BANK(pin);
u32 offset = PINID_TO_OFFSET(pin);
u32 pull_en, pull_dir, ds0, ds1, ds2, ds;
bool en, dir, b0, b1, b2;
int ret, strength;
if (bank >= ipc->data->nr_banks)
return -EINVAL;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_UP:
ret = regmap_read(ipc->pull_regmap, ipc->data->pull_en[bank],
&pull_en);
if (ret)
return ret;
ret = regmap_read(ipc->pull_regmap, ipc->data->pull_dir[bank],
&pull_dir);
if (ret)
return ret;
en = !!(pull_en & BIT(offset));
dir = !!(pull_dir & BIT(offset));
if (param == PIN_CONFIG_BIAS_DISABLE) {
if (en)
return -EINVAL;
*config = pinconf_to_config_packed(param, 0);
return 0;
}
if (!en)
return -EINVAL;
if (param == PIN_CONFIG_BIAS_PULL_UP && !dir)
return -EINVAL;
if (param == PIN_CONFIG_BIAS_PULL_DOWN && dir)
return -EINVAL;
*config = pinconf_to_config_packed(param, 1);
return 0;
case PIN_CONFIG_DRIVE_STRENGTH:
ret = regmap_read(ipc->ds_regmap, ipc->data->ds0[bank], &ds0);
if (ret)
return ret;
ret = regmap_read(ipc->ds_regmap, ipc->data->ds1[bank], &ds1);
if (ret)
return ret;
b0 = !!(ds0 & BIT(offset));
b1 = !!(ds1 & BIT(offset));
if (ipc->data->have_ds2) {
ret = regmap_read(ipc->ds_regmap, ipc->data->ds2[bank],
&ds2);
if (ret)
return ret;
b2 = !!(ds2 & BIT(offset));
ds = (b2 << 2) | (b1 << 1) | b0;
} else {
ds = (b0 << 1) | b1;
}
strength = amb_reg_to_drive_strength(ipc, ds);
if (strength < 0)
return strength;
*config = pinconf_to_config_packed(param, strength);
return 0;
default:
return -ENOTSUPP;
}
}
static const struct pinconf_ops amb_pinconf_ops = {
.is_generic = true,
.pin_config_get = amb_pinconf_get,
.pin_config_set = amb_pinconf_set,
.pin_config_group_set = amb_pinconf_group_set,
};
static int amb_pinctrl_add_groups(struct amb_pinctrl *ipc)
{
const struct amb_pinctrl_data *data = ipc->data;
for (unsigned int i = 0; i < data->ngroups; i++) {
const struct amb_pinmux_group *g = &data->groups[i];
int ret;
if (!g->grp || !g->grp->name || !g->grp->pins ||
!g->grp->npins || !g->alts)
return -EINVAL;
for (unsigned int j = 0; j < g->grp->npins; j++) {
if (g->grp->pins[j] >= data->npins)
return -EINVAL;
}
ret = pinctrl_generic_add_group(ipc->pctl, g->grp->name,
g->grp->pins, g->grp->npins,
(void *)g->alts);
if (ret < 0)
return ret;
}
return 0;
}
static int amb_pinctrl_add_functions(struct amb_pinctrl *ipc)
{
const struct amb_pinctrl_data *data = ipc->data;
for (unsigned int i = 0; i < data->nfunctions; i++) {
int ret;
ret = pinmux_generic_add_pinfunction(ipc->pctl,
&data->functions[i], NULL);
if (ret < 0)
return ret;
}
return 0;
}
static int amb_pinctrl_register(struct amb_pinctrl *ipc)
{
struct pinctrl_pin_desc *pindesc;
char **names;
int ret;
pindesc = devm_kcalloc(ipc->dev, ipc->data->npins, sizeof(*pindesc),
GFP_KERNEL);
if (!pindesc)
return -ENOMEM;
names = devm_kasprintf_strarray(ipc->dev, "io", ipc->data->npins);
if (IS_ERR(names))
return PTR_ERR(names);
for (unsigned int pin = 0; pin < ipc->data->npins; pin++) {
pindesc[pin].number = pin;
pindesc[pin].name = names[pin];
}
ipc->desc.name = dev_name(ipc->dev);
ipc->desc.pins = pindesc;
ipc->desc.npins = ipc->data->npins;
ipc->desc.pctlops = &amb_pctrl_ops;
ipc->desc.pmxops = &amb_pinmux_ops;
ipc->desc.confops = &amb_pinconf_ops;
ipc->desc.owner = THIS_MODULE;
ret = devm_pinctrl_register_and_init(ipc->dev, &ipc->desc, ipc, &ipc->pctl);
if (ret)
return ret;
ret = amb_pinctrl_add_groups(ipc);
if (ret)
return ret;
ret = amb_pinctrl_add_functions(ipc);
if (ret)
return ret;
return pinctrl_enable(ipc->pctl);
}
static int amb_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct amb_pinctrl *ipc;
int ret;
ipc = devm_kzalloc(dev, sizeof(*ipc), GFP_KERNEL);
if (!ipc)
return -ENOMEM;
ipc->dev = dev;
ipc->data = device_get_match_data(dev);
if (!ipc->data)
return dev_err_probe(dev, -ENODATA, "missing SoC data\n");
if (!ipc->data->nr_banks || ipc->data->nr_banks > AMBA_MAX_BANKS ||
!ipc->data->npins ||
!ipc->data->groups || !ipc->data->ngroups ||
!ipc->data->functions || !ipc->data->nfunctions)
return dev_err_probe(dev, -EINVAL, "invalid SoC data\n");
ipc->iomux_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ipc->iomux_base))
return PTR_ERR(ipc->iomux_base);
ipc->ds_regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev),
"ambarella,drive-strength-syscon");
if (IS_ERR(ipc->ds_regmap))
return dev_err_probe(dev, PTR_ERR(ipc->ds_regmap),
"missing drive-strength syscon\n");
ipc->pull_regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev),
"ambarella,pull-syscon");
if (IS_ERR(ipc->pull_regmap))
return dev_err_probe(dev, PTR_ERR(ipc->pull_regmap),
"missing pull syscon\n");
spin_lock_init(&ipc->lock);
ret = amb_pinctrl_register(ipc);
if (ret)
return dev_err_probe(dev, ret, "failed to register pinctrl\n");
platform_set_drvdata(pdev, ipc);
return 0;
}
static const struct of_device_id amb_pinctrl_dt_match[] = {
{
.compatible = "ambarella,cv75-pinctrl",
.data = &ambarella_cv75_pinctrl_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, amb_pinctrl_dt_match);
static struct platform_driver amb_pinctrl_driver = {
.probe = amb_pinctrl_probe,
.driver = {
.name = "ambarella-pinctrl",
.of_match_table = amb_pinctrl_dt_match,
},
};
static int __init amb_pinctrl_drv_register(void)
{
return platform_driver_register(&amb_pinctrl_driver);
}
arch_initcall(amb_pinctrl_drv_register);
MODULE_AUTHOR("Cao Rongrong <rrcao@ambarella.com>");
MODULE_DESCRIPTION("Ambarella SoC pinctrl driver");
MODULE_LICENSE("GPL");

40
drivers/pinctrl/pinctrl-ambarella.h Normal file
View File

@ -0,0 +1,40 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Ambarella pinctrl SoC data
*
* Copyright (C) 2012-2026, Ambarella, Inc.
*/
#ifndef _PINCTRL_AMBARELLA_H
#define _PINCTRL_AMBARELLA_H
#include <linux/types.h>
#define AMBA_MAX_BANKS 8
struct pingroup;
struct pinfunction;
struct amb_pinmux_group {
const struct pingroup *grp;
const u8 *alts;
};
struct amb_pinctrl_data {
const struct amb_pinmux_group *groups;
const struct pinfunction *functions;
unsigned int ngroups;
unsigned int nfunctions;
unsigned int nr_banks;
unsigned int npins;
unsigned int ds0[AMBA_MAX_BANKS];
unsigned int ds1[AMBA_MAX_BANKS];
unsigned int ds2[AMBA_MAX_BANKS];
unsigned int pull_en[AMBA_MAX_BANKS];
unsigned int pull_dir[AMBA_MAX_BANKS];
bool have_ds2;
};
extern const struct amb_pinctrl_data ambarella_cv75_pinctrl_data;
#endif /* _PINCTRL_AMBARELLA_H */

243
drivers/pinctrl/pinctrl-amd.c
View File

@ -18,6 +18,7 @@
#include <linux/errno.h>
#include <linux/log2.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
@ -39,6 +40,13 @@
static struct amd_gpio *pinctrl_dev;
#endif
static inline void __iomem *amd_gpio_pin_reg(struct amd_gpio *gpio_dev, unsigned int pin)
{
if (gpio_dev->base_rgpio && pin >= AMD_GPIO_RGPIO_PIN_BASE)
return gpio_dev->base_rgpio + (pin - AMD_GPIO_RGPIO_PIN_BASE) * 4;
return gpio_dev->base + pin * 4;
}
static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
{
unsigned long flags;
@ -46,7 +54,7 @@ static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
@ -62,9 +70,9 @@ static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset));
pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
writel(pin_reg, gpio_dev->base + offset * 4);
writel(pin_reg, amd_gpio_pin_reg(gpio_dev, offset));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return 0;
@ -78,13 +86,13 @@ static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset));
pin_reg |= BIT(OUTPUT_ENABLE_OFF);
if (value)
pin_reg |= BIT(OUTPUT_VALUE_OFF);
else
pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
writel(pin_reg, gpio_dev->base + offset * 4);
writel(pin_reg, amd_gpio_pin_reg(gpio_dev, offset));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return 0;
@ -97,7 +105,7 @@ static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return !!(pin_reg & BIT(PIN_STS_OFF));
@ -111,12 +119,12 @@ static int amd_gpio_set_value(struct gpio_chip *gc, unsigned int offset,
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset));
if (value)
pin_reg |= BIT(OUTPUT_VALUE_OFF);
else
pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
writel(pin_reg, gpio_dev->base + offset * 4);
writel(pin_reg, amd_gpio_pin_reg(gpio_dev, offset));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return 0;
@ -136,7 +144,7 @@ static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset,
debounce = 0;
}
pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset));
if (debounce) {
pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
@ -185,7 +193,7 @@ static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset,
pin_reg &= ~DB_TMR_OUT_MASK;
pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
}
writel(pin_reg, gpio_dev->base + offset * 4);
writel(pin_reg, amd_gpio_pin_reg(gpio_dev, offset));
return ret;
}
@ -238,6 +246,10 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
i = 192;
pin_num = AMD_GPIO_PINS_BANK3 + i;
break;
case 4:
i = AMD_GPIO_RGPIO_PIN_BASE;
pin_num = AMD_GPIO_PINS_BANK4 + i;
break;
default:
/* Illegal bank number, ignore */
continue;
@ -247,7 +259,7 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
for (; i < pin_num; i++) {
seq_printf(s, "#%d\t", i);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + i * 4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, i));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
@ -386,10 +398,10 @@ static void amd_gpio_irq_enable(struct irq_data *d)
gpiochip_enable_irq(gc, hwirq);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + hwirq * 4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq));
pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
pin_reg |= BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + hwirq * 4);
writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
@ -402,10 +414,10 @@ static void amd_gpio_irq_disable(struct irq_data *d)
irq_hw_number_t hwirq = irqd_to_hwirq(d);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + hwirq * 4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq));
pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + hwirq * 4);
writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
gpiochip_disable_irq(gc, hwirq);
@ -420,9 +432,9 @@ static void amd_gpio_irq_mask(struct irq_data *d)
irq_hw_number_t hwirq = irqd_to_hwirq(d);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + hwirq * 4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq));
pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + hwirq * 4);
writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
@ -435,9 +447,9 @@ static void amd_gpio_irq_unmask(struct irq_data *d)
irq_hw_number_t hwirq = irqd_to_hwirq(d);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + hwirq * 4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq));
pin_reg |= BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + hwirq * 4);
writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
@ -455,14 +467,14 @@ static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
hwirq, str_enable_disable(on));
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + hwirq * 4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq));
if (on)
pin_reg |= wake_mask;
else
pin_reg &= ~wake_mask;
writel(pin_reg, gpio_dev->base + hwirq * 4);
writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
if (on)
@ -494,14 +506,14 @@ static void amd_gpio_irq_eoi(struct irq_data *d)
static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
int ret = 0;
u32 pin_reg, pin_reg_irq_en, mask;
u32 pin_reg, pin_reg_irq_en, mask, reg;
unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + hwirq * 4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq));
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
@ -567,10 +579,11 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg_irq_en = pin_reg;
pin_reg_irq_en |= mask;
pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
writel(pin_reg_irq_en, gpio_dev->base + hwirq * 4);
while ((readl(gpio_dev->base + hwirq * 4) & mask) != mask)
continue;
writel(pin_reg, gpio_dev->base + hwirq * 4);
writel(pin_reg_irq_en, amd_gpio_pin_reg(gpio_dev, hwirq));
if (readl_poll_timeout_atomic(amd_gpio_pin_reg(gpio_dev, hwirq), reg,
(reg & mask) == mask, 1, 1000))
ret = -ETIMEDOUT;
writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return ret;
@ -613,7 +626,6 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
struct gpio_chip *gc = &gpio_dev->gc;
unsigned int i, irqnr;
unsigned long flags;
u32 __iomem *regs;
bool ret = false;
u32 regval;
u64 status, mask;
@ -627,15 +639,14 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
/* Bit 0-45 contain the relevant status bits */
status &= (1ULL << 46) - 1;
regs = gpio_dev->base;
for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
for (mask = 1, irqnr = 0; status; mask <<= 1, irqnr += 4) {
if (!(status & mask))
continue;
status &= ~mask;
/* Each status bit covers four pins */
for (i = 0; i < 4; i++) {
regval = readl(regs + i);
regval = readl(amd_gpio_pin_reg(gpio_dev, irqnr + i));
if (regval & PIN_IRQ_PENDING)
pm_pr_dbg("GPIO %d is active: 0x%x",
@ -658,7 +669,7 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
* avoid a system hang caused by an interrupt storm.
*/
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
regval = readl(regs + i);
regval = readl(amd_gpio_pin_reg(gpio_dev, irqnr + i));
if (!gpiochip_line_is_irq(gc, irqnr + i)) {
regval &= ~BIT(INTERRUPT_MASK_OFF);
dev_dbg(&gpio_dev->pdev->dev,
@ -667,10 +678,62 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
} else {
ret = true;
}
writel(regval, regs + i);
writel(regval, amd_gpio_pin_reg(gpio_dev, irqnr + i));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
}
/*
* Unlike WAKE_INT_STATUS_REG0/1, where each status bit covers four
* pins, the RGPIO status register uses one bit per pin. As with the
* main bank status registers, a bit is cleared by acknowledging the
* pending interrupt on its pin below (clearing PIN_IRQ_PENDING); no
* separate write to the RGPIO status register is required.
*/
if (gpio_dev->base_rgpio) {
u32 status_rgpio;
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
status_rgpio = readl(gpio_dev->base_rgpio + WAKE_INT_STATUS_REG_RGPIO);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
status_rgpio &= GENMASK(AMD_GPIO_PINS_BANK4 - 1, 0);
for (i = 0; i < AMD_GPIO_PINS_BANK4; i++) {
unsigned int pin = AMD_GPIO_RGPIO_PIN_BASE + i;
if (!(status_rgpio & BIT(i)))
continue;
regval = readl(amd_gpio_pin_reg(gpio_dev, pin));
if (regval & PIN_IRQ_PENDING)
pm_pr_dbg("GPIO %d is active: 0x%x", pin, regval);
/* caused wake on resume context for shared IRQ */
if (irq < 0 && (regval & BIT(WAKE_STS_OFF)))
return true;
if (!(regval & PIN_IRQ_PENDING) ||
!(regval & BIT(INTERRUPT_MASK_OFF)))
continue;
generic_handle_domain_irq_safe(gc->irq.domain, pin);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
regval = readl(amd_gpio_pin_reg(gpio_dev, pin));
if (!gpiochip_line_is_irq(gc, pin)) {
regval &= ~BIT(INTERRUPT_MASK_OFF);
dev_dbg(&gpio_dev->pdev->dev,
"Disabling spurious GPIO IRQ %d\n",
pin);
} else {
ret = true;
}
writel(regval, amd_gpio_pin_reg(gpio_dev, pin));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
}
/* did not cause wake on resume context for shared IRQ */
if (irq < 0)
return false;
@ -742,8 +805,11 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev,
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
if (pin >= AMD_GPIO_RGPIO_PIN_BASE && !gpio_dev->base_rgpio)
return -EOPNOTSUPP;
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + pin*4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, pin));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
switch (param) {
case PIN_CONFIG_INPUT_DEBOUNCE:
@ -784,11 +850,14 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
enum pin_config_param param;
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
if (pin >= AMD_GPIO_RGPIO_PIN_BASE && !gpio_dev->base_rgpio)
return -EOPNOTSUPP;
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
pin_reg = readl(gpio_dev->base + pin*4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, pin));
switch (param) {
case PIN_CONFIG_INPUT_DEBOUNCE:
@ -818,7 +887,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
ret = -ENOTSUPP;
}
writel(pin_reg, gpio_dev->base + pin*4);
writel(pin_reg, amd_gpio_pin_reg(gpio_dev, pin));
}
out_unlock:
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
@ -902,11 +971,14 @@ static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
if (!pd)
continue;
if (pin >= AMD_GPIO_RGPIO_PIN_BASE && !gpio_dev->base_rgpio)
continue;
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + pin * 4);
pin_reg = readl(amd_gpio_pin_reg(gpio_dev, pin));
pin_reg &= ~mask;
writel(pin_reg, gpio_dev->base + pin * 4);
writel(pin_reg, amd_gpio_pin_reg(gpio_dev, pin));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
@ -926,7 +998,10 @@ static void amd_gpio_check_pending(void)
int pin = desc->pins[i].number;
u32 tmp;
tmp = readl(gpio_dev->base + pin * 4);
if (pin >= AMD_GPIO_RGPIO_PIN_BASE && !gpio_dev->base_rgpio)
continue;
tmp = readl(amd_gpio_pin_reg(gpio_dev, pin));
if (tmp & PIN_IRQ_PENDING)
pm_pr_dbg("%s: GPIO %d is active: 0x%x.\n", __func__, pin, tmp);
}
@ -984,12 +1059,12 @@ static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend
continue;
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
gpio_dev->saved_regs[i] = readl(amd_gpio_pin_reg(gpio_dev, pin)) & ~PIN_IRQ_PENDING;
/* mask any interrupts not intended to be a wake source */
if (!(gpio_dev->saved_regs[i] & wake_mask)) {
writel(gpio_dev->saved_regs[i] & ~BIT(INTERRUPT_MASK_OFF),
gpio_dev->base + pin * 4);
amd_gpio_pin_reg(gpio_dev, pin));
pm_pr_dbg("Disabling GPIO #%d interrupt for %s.\n",
pin, is_suspend ? "suspend" : "hibernate");
}
@ -1038,8 +1113,8 @@ static int amd_gpio_resume(struct device *dev)
continue;
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
gpio_dev->saved_regs[i] |= readl(amd_gpio_pin_reg(gpio_dev, pin)) & PIN_IRQ_PENDING;
writel(gpio_dev->saved_regs[i], amd_gpio_pin_reg(gpio_dev, pin));
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
@ -1072,7 +1147,8 @@ static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector,
{
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
if (!gpio_dev->iomux_base) {
if (!gpio_dev->iomux_base &&
pmx_functions[selector].index < AMD_GPIO_RGPIO_PIN_BASE) {
dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector);
return -EINVAL;
}
@ -1088,6 +1164,34 @@ static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsi
struct device *dev = &gpio_dev->pdev->dev;
struct pin_desc *pd;
int ind, index;
unsigned int pin = gpio_dev->groups[group].pins[0];
if (pin >= AMD_GPIO_RGPIO_PIN_BASE) {
if (!gpio_dev->base_rgpio)
return -EINVAL;
for (index = 0; index < NSELECTS; index++)
if (!strcmp(gpio_dev->groups[group].name,
pmx_functions[function].groups[index]))
break;
if (index >= NSELECTS)
return -EINVAL;
writeb(index, gpio_dev->base_rgpio + AMD_GPIO_RGPIO_MUX_OFFSET +
(pin - AMD_GPIO_RGPIO_PIN_BASE));
if (index != (readb(gpio_dev->base_rgpio + AMD_GPIO_RGPIO_MUX_OFFSET +
(pin - AMD_GPIO_RGPIO_PIN_BASE)) & FUNCTION_MASK)) {
dev_err(dev, "RGPIO_GPIO %u mux not present or supported\n", pin);
return -EINVAL;
}
for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) {
pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]);
pd->mux_owner = gpio_dev->groups[group].name;
}
return 0;
}
if (!gpio_dev->iomux_base)
return -EINVAL;
@ -1141,28 +1245,31 @@ static struct pinctrl_desc amd_pinctrl_desc = {
.owner = THIS_MODULE,
};
static void amd_get_iomux_res(struct amd_gpio *gpio_dev)
static void __iomem *amd_get_named_res(struct device *dev, struct platform_device *pdev,
const char *name, resource_size_t minsz)
{
struct pinctrl_desc *desc = &amd_pinctrl_desc;
struct device *dev = &gpio_dev->pdev->dev;
struct resource *res;
void __iomem *base;
int index;
index = device_property_match_string(dev, "pinctrl-resource-names", "iomux");
index = device_property_match_string(dev, "pinctrl-resource-names", name);
if (index < 0) {
dev_dbg(dev, "iomux not supported\n");
goto out_no_pinmux;
dev_dbg(dev, "%s not supported\n", name);
return NULL;
}
gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index);
if (IS_ERR(gpio_dev->iomux_base)) {
dev_dbg(dev, "iomux not supported %d io resource\n", index);
goto out_no_pinmux;
base = devm_platform_get_and_ioremap_resource(pdev, index, &res);
if (IS_ERR(base)) {
dev_dbg(dev, "%s not supported %d io resource\n", name, index);
return NULL;
}
return;
if (resource_size(res) < minsz) {
dev_err(dev, "%s resource too small\n", name);
return NULL;
}
out_no_pinmux:
desc->pmxops = NULL;
return base;
}
static int amd_gpio_probe(struct platform_device *pdev)
@ -1185,6 +1292,19 @@ static int amd_gpio_probe(struct platform_device *pdev)
return PTR_ERR(gpio_dev->base);
}
gpio_dev->base_rgpio = amd_get_named_res(&pdev->dev, pdev, "rgpio",
WAKE_INT_STATUS_REG_RGPIO + sizeof(u32));
/*
* RGPIO pins are numbered from AMD_GPIO_RGPIO_PIN_BASE, so the main
* bank must span exactly that many register slots for the RGPIO pin
* numbering to line up. Disable RGPIO if the main bank is a different
* size.
*/
if (gpio_dev->base_rgpio && resource_size(res) / 4 != AMD_GPIO_RGPIO_PIN_BASE) {
dev_err(&pdev->dev, "unexpected GPIO bank size, disabling RGPIO\n");
gpio_dev->base_rgpio = NULL;
}
gpio_dev->irq = platform_get_irq(pdev, 0);
if (gpio_dev->irq < 0)
return gpio_dev->irq;
@ -1211,13 +1331,18 @@ static int amd_gpio_probe(struct platform_device *pdev)
gpio_dev->gc.owner = THIS_MODULE;
gpio_dev->gc.parent = &pdev->dev;
gpio_dev->gc.ngpio = resource_size(res) / 4;
gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
if (gpio_dev->base_rgpio) {
gpio_dev->gc.ngpio += AMD_GPIO_PINS_BANK4;
gpio_dev->hwbank_num++;
}
gpio_dev->groups = kerncz_groups;
gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
amd_pinctrl_desc.name = dev_name(&pdev->dev);
amd_get_iomux_res(gpio_dev);
gpio_dev->iomux_base = amd_get_named_res(&pdev->dev, pdev, "iomux", 0);
if (!gpio_dev->iomux_base && !gpio_dev->base_rgpio)
amd_pinctrl_desc.pmxops = NULL;
gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
gpio_dev);
if (IS_ERR(gpio_dev->pctrl)) {

174
drivers/pinctrl/pinctrl-amd.h
View File

@ -15,6 +15,18 @@
#define AMD_GPIO_PINS_BANK1 64
#define AMD_GPIO_PINS_BANK2 56
#define AMD_GPIO_PINS_BANK3 32
#define AMD_GPIO_PINS_BANK4 16
/*
* Remote GPIO (RGPIO) is a second GPIO bank on some AMD platforms. Firmware
* advertises its register region as an optional resource named "rgpio" (via
* the pinctrl-resource-names _DSD property). Relative to that region's base,
* RGPIO pin AMD_GPIO_RGPIO_PIN_BASE + n uses a per-pin control register at
* n * 4, a pinmux selector byte at AMD_GPIO_RGPIO_MUX_OFFSET + n, and one
* interrupt status bit (bit n) in WAKE_INT_STATUS_REG_RGPIO.
*/
#define AMD_GPIO_RGPIO_PIN_BASE 256
#define AMD_GPIO_RGPIO_MUX_OFFSET 0xC0
#define WAKE_INT_MASTER_REG 0xfc
#define INTERNAL_GPIO0_DEBOUNCE (1 << 15)
@ -22,6 +34,7 @@
#define WAKE_INT_STATUS_REG0 0x2f8
#define WAKE_INT_STATUS_REG1 0x2fc
#define WAKE_INT_STATUS_REG_RGPIO 0x0F4
#define DB_TMR_OUT_OFF 0
#define DB_TMR_OUT_UNIT_OFF 4
@ -94,6 +107,7 @@ struct amd_function {
struct amd_gpio {
raw_spinlock_t lock;
void __iomem *base;
void __iomem *base_rgpio;
void __iomem *iomux_base;
const struct pingroup *groups;
@ -292,6 +306,22 @@ static const struct pinctrl_pin_desc kerncz_pins[] = {
PINCTRL_PIN(181, "GPIO_181"),
PINCTRL_PIN(182, "GPIO_182"),
PINCTRL_PIN(183, "GPIO_183"),
PINCTRL_PIN(256, "GPIO_256"),
PINCTRL_PIN(257, "GPIO_257"),
PINCTRL_PIN(258, "GPIO_258"),
PINCTRL_PIN(259, "GPIO_259"),
PINCTRL_PIN(260, "GPIO_260"),
PINCTRL_PIN(261, "GPIO_261"),
PINCTRL_PIN(262, "GPIO_262"),
PINCTRL_PIN(263, "GPIO_263"),
PINCTRL_PIN(264, "GPIO_264"),
PINCTRL_PIN(265, "GPIO_265"),
PINCTRL_PIN(266, "GPIO_266"),
PINCTRL_PIN(267, "GPIO_267"),
PINCTRL_PIN(268, "GPIO_268"),
PINCTRL_PIN(269, "GPIO_269"),
PINCTRL_PIN(270, "GPIO_270"),
PINCTRL_PIN(271, "GPIO_271"),
};
#define AMD_PINS(...) (const unsigned int []){__VA_ARGS__}
@ -873,6 +903,70 @@ enum amd_functions {
IMX_F1_GPIO144,
IMX_F2_GPIO144,
IMX_F3_GPIO144,
IMX_F0_GPIO256,
IMX_F1_GPIO256,
IMX_F2_GPIO256,
IMX_F3_GPIO256,
IMX_F0_GPIO257,
IMX_F1_GPIO257,
IMX_F2_GPIO257,
IMX_F3_GPIO257,
IMX_F0_GPIO258,
IMX_F1_GPIO258,
IMX_F2_GPIO258,
IMX_F3_GPIO258,
IMX_F0_GPIO259,
IMX_F1_GPIO259,
IMX_F2_GPIO259,
IMX_F3_GPIO259,
IMX_F0_GPIO260,
IMX_F1_GPIO260,
IMX_F2_GPIO260,
IMX_F3_GPIO260,
IMX_F0_GPIO261,
IMX_F1_GPIO261,
IMX_F2_GPIO261,
IMX_F3_GPIO261,
IMX_F0_GPIO262,
IMX_F1_GPIO262,
IMX_F2_GPIO262,
IMX_F3_GPIO262,
IMX_F0_GPIO263,
IMX_F1_GPIO263,
IMX_F2_GPIO263,
IMX_F3_GPIO263,
IMX_F0_GPIO264,
IMX_F1_GPIO264,
IMX_F2_GPIO264,
IMX_F3_GPIO264,
IMX_F0_GPIO265,
IMX_F1_GPIO265,
IMX_F2_GPIO265,
IMX_F3_GPIO265,
IMX_F0_GPIO266,
IMX_F1_GPIO266,
IMX_F2_GPIO266,
IMX_F3_GPIO266,
IMX_F0_GPIO267,
IMX_F1_GPIO267,
IMX_F2_GPIO267,
IMX_F3_GPIO267,
IMX_F0_GPIO268,
IMX_F1_GPIO268,
IMX_F2_GPIO268,
IMX_F3_GPIO268,
IMX_F0_GPIO269,
IMX_F1_GPIO269,
IMX_F2_GPIO269,
IMX_F3_GPIO269,
IMX_F0_GPIO270,
IMX_F1_GPIO270,
IMX_F2_GPIO270,
IMX_F3_GPIO270,
IMX_F0_GPIO271,
IMX_F1_GPIO271,
IMX_F2_GPIO271,
IMX_F3_GPIO271,
};
#define AMD_PINCTRL_FUNC_GRP(_number, _func) \
@ -1456,6 +1550,70 @@ static const struct pingroup kerncz_groups[] = {
AMD_PINCTRL_FUNC_GRP(144, 1),
AMD_PINCTRL_FUNC_GRP(144, 2),
AMD_PINCTRL_FUNC_GRP(144, 3),
AMD_PINCTRL_FUNC_GRP(256, 0),
AMD_PINCTRL_FUNC_GRP(256, 1),
AMD_PINCTRL_FUNC_GRP(256, 2),
AMD_PINCTRL_FUNC_GRP(256, 3),
AMD_PINCTRL_FUNC_GRP(257, 0),
AMD_PINCTRL_FUNC_GRP(257, 1),
AMD_PINCTRL_FUNC_GRP(257, 2),
AMD_PINCTRL_FUNC_GRP(257, 3),
AMD_PINCTRL_FUNC_GRP(258, 0),
AMD_PINCTRL_FUNC_GRP(258, 1),
AMD_PINCTRL_FUNC_GRP(258, 2),
AMD_PINCTRL_FUNC_GRP(258, 3),
AMD_PINCTRL_FUNC_GRP(259, 0),
AMD_PINCTRL_FUNC_GRP(259, 1),
AMD_PINCTRL_FUNC_GRP(259, 2),
AMD_PINCTRL_FUNC_GRP(259, 3),
AMD_PINCTRL_FUNC_GRP(260, 0),
AMD_PINCTRL_FUNC_GRP(260, 1),
AMD_PINCTRL_FUNC_GRP(260, 2),
AMD_PINCTRL_FUNC_GRP(260, 3),
AMD_PINCTRL_FUNC_GRP(261, 0),
AMD_PINCTRL_FUNC_GRP(261, 1),
AMD_PINCTRL_FUNC_GRP(261, 2),
AMD_PINCTRL_FUNC_GRP(261, 3),
AMD_PINCTRL_FUNC_GRP(262, 0),
AMD_PINCTRL_FUNC_GRP(262, 1),
AMD_PINCTRL_FUNC_GRP(262, 2),
AMD_PINCTRL_FUNC_GRP(262, 3),
AMD_PINCTRL_FUNC_GRP(263, 0),
AMD_PINCTRL_FUNC_GRP(263, 1),
AMD_PINCTRL_FUNC_GRP(263, 2),
AMD_PINCTRL_FUNC_GRP(263, 3),
AMD_PINCTRL_FUNC_GRP(264, 0),
AMD_PINCTRL_FUNC_GRP(264, 1),
AMD_PINCTRL_FUNC_GRP(264, 2),
AMD_PINCTRL_FUNC_GRP(264, 3),
AMD_PINCTRL_FUNC_GRP(265, 0),
AMD_PINCTRL_FUNC_GRP(265, 1),
AMD_PINCTRL_FUNC_GRP(265, 2),
AMD_PINCTRL_FUNC_GRP(265, 3),
AMD_PINCTRL_FUNC_GRP(266, 0),
AMD_PINCTRL_FUNC_GRP(266, 1),
AMD_PINCTRL_FUNC_GRP(266, 2),
AMD_PINCTRL_FUNC_GRP(266, 3),
AMD_PINCTRL_FUNC_GRP(267, 0),
AMD_PINCTRL_FUNC_GRP(267, 1),
AMD_PINCTRL_FUNC_GRP(267, 2),
AMD_PINCTRL_FUNC_GRP(267, 3),
AMD_PINCTRL_FUNC_GRP(268, 0),
AMD_PINCTRL_FUNC_GRP(268, 1),
AMD_PINCTRL_FUNC_GRP(268, 2),
AMD_PINCTRL_FUNC_GRP(268, 3),
AMD_PINCTRL_FUNC_GRP(269, 0),
AMD_PINCTRL_FUNC_GRP(269, 1),
AMD_PINCTRL_FUNC_GRP(269, 2),
AMD_PINCTRL_FUNC_GRP(269, 3),
AMD_PINCTRL_FUNC_GRP(270, 0),
AMD_PINCTRL_FUNC_GRP(270, 1),
AMD_PINCTRL_FUNC_GRP(270, 2),
AMD_PINCTRL_FUNC_GRP(270, 3),
AMD_PINCTRL_FUNC_GRP(271, 0),
AMD_PINCTRL_FUNC_GRP(271, 1),
AMD_PINCTRL_FUNC_GRP(271, 2),
AMD_PINCTRL_FUNC_GRP(271, 3),
PINCTRL_PINGROUP("i2c0", AMD_PINS(145, 146), 2),
PINCTRL_PINGROUP("i2c1", AMD_PINS(147, 148), 2),
@ -1620,6 +1778,22 @@ static const struct amd_function pmx_functions[] = {
AMD_PMUX_FUNC(142),
AMD_PMUX_FUNC(143),
AMD_PMUX_FUNC(144),
AMD_PMUX_FUNC(256),
AMD_PMUX_FUNC(257),
AMD_PMUX_FUNC(258),
AMD_PMUX_FUNC(259),
AMD_PMUX_FUNC(260),
AMD_PMUX_FUNC(261),
AMD_PMUX_FUNC(262),
AMD_PMUX_FUNC(263),
AMD_PMUX_FUNC(264),
AMD_PMUX_FUNC(265),
AMD_PMUX_FUNC(266),
AMD_PMUX_FUNC(267),
AMD_PMUX_FUNC(268),
AMD_PMUX_FUNC(269),
AMD_PMUX_FUNC(270),
AMD_PMUX_FUNC(271),
};
#endif

21
drivers/pinctrl/pinctrl-apple-gpio.c
View File

@ -66,6 +66,13 @@ struct apple_gpio_pinctrl {
#define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22)
#define REG_IRQ(g, x) (0x800 + 0x40 * (g) + 4 * ((x) >> 5))
static bool apple_gpio_readable_register(struct device *dev, unsigned int reg)
{
struct apple_gpio_pinctrl *pctl = dev_get_drvdata(dev);
return gpiochip_line_is_valid(&pctl->gpio_chip, reg / 4);
}
static const struct regmap_config regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@ -75,6 +82,7 @@ static const struct regmap_config regmap_config = {
.num_reg_defaults_raw = 512,
.use_relaxed_mmio = true,
.use_raw_spinlock = true,
.readable_reg = apple_gpio_readable_register,
};
/* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */
@ -90,6 +98,13 @@ static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl,
int ret;
u32 val;
if (!pctl->map) {
pctl->map = devm_regmap_init_mmio(pctl->dev, pctl->base, &regmap_config);
if (IS_ERR(pctl->map))
return dev_err_probe(pctl->dev, PTR_ERR(pctl->map),
"Failed to create regmap\n");
}
ret = regmap_read(pctl->map, REG_GPIO(pin), &val);
if (ret)
return 0;
@ -475,11 +490,6 @@ static int apple_gpio_pinctrl_probe(struct platform_device *pdev)
if (IS_ERR(pctl->base))
return PTR_ERR(pctl->base);
pctl->map = devm_regmap_init_mmio(&pdev->dev, pctl->base, &regmap_config);
if (IS_ERR(pctl->map))
return dev_err_probe(&pdev->dev, PTR_ERR(pctl->map),
"Failed to create regmap\n");
for (i = 0; i < npins; i++) {
pins[i].number = i;
pins[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "PIN%u", i);
@ -522,6 +532,7 @@ static int apple_gpio_pinctrl_probe(struct platform_device *pdev)
}
static const struct of_device_id apple_gpio_pinctrl_of_match[] = {
{ .compatible = "apple,t8140-pinctrl", },
{ .compatible = "apple,t8103-pinctrl", },
{ .compatible = "apple,pinctrl", },
{ }

3
drivers/pinctrl/pinctrl-axp209.c
View File

@ -442,9 +442,6 @@ static int axp20x_pctl_probe(struct platform_device *pdev)
struct pinctrl_desc *pctrl_desc;
int ret;
if (!of_device_is_available(pdev->dev.of_node))
return -ENODEV;
if (!axp20x) {
dev_err(&pdev->dev, "Parent drvdata not set\n");
return -EINVAL;

2
drivers/pinctrl/pinctrl-equilibrium.c
View File

@ -618,7 +618,7 @@ static int funcs_utils(struct device *dev, struct pinfunction *funcs,
if (of_property_read_string(np, "function", &fn_name)) {
/* some groups may not have function, it's OK */
dev_dbg(dev, "Group %s: not function binded!\n",
dev_dbg(dev, "Group %s: not function bound!\n",
(char *)prop->value);
continue;
}

3
drivers/pinctrl/pinctrl-gemini.c
View File

@ -41,7 +41,7 @@ struct gemini_pin_conf {
/**
* struct gemini_pmx - state holder for the gemini pin controller
* @dev: a pointer back to containing device
* @virtbase: the offset to the controller in virtual memory
* @pctl: the pin controller device
* @map: regmap to access registers
* @is_3512: whether the SoC/package is the 3512 variant
* @is_3516: whether the SoC/package is the 3516 variant
@ -2031,6 +2031,7 @@ static const struct pinctrl_ops gemini_pctrl_ops = {
* struct gemini_pmx_func - describes Gemini pinmux functions
* @name: the name of this specific function
* @groups: corresponding pin groups
* @num_groups: the number of pin groups
*/
struct gemini_pmx_func {
const char *name;

76
drivers/pinctrl/pinctrl-generic-mux.c
View File

@ -10,13 +10,11 @@
#include <linux/mutex.h>
#include <linux/mux/consumer.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include "core.h"
#include "pinconf.h"
#include "pinmux.h"
#include "pinctrl-utils.h"
@ -38,39 +36,73 @@ mux_pinmux_dt_node_to_map(struct pinctrl_dev *pctldev,
struct pinctrl_map **maps, unsigned int *num_maps)
{
unsigned int num_reserved_maps = 0;
struct mux_pin_function *function;
const char **group_names;
int ret;
function = devm_kzalloc(pctldev->dev, sizeof(*function), GFP_KERNEL);
if (!function)
return -ENOMEM;
*maps = NULL;
*num_maps = 0;
group_names = devm_kcalloc(pctldev->dev, 1, sizeof(*group_names), GFP_KERNEL);
if (!group_names)
return -ENOMEM;
function->mux_state = devm_mux_state_get_from_np(pctldev->dev, NULL, np_config);
if (IS_ERR(function->mux_state))
return PTR_ERR(function->mux_state);
ret = pinctrl_generic_to_map(pctldev, np_config, np_config, maps,
num_maps, &num_reserved_maps, group_names,
0, &np_config->name, NULL, 0);
if (pinctrl_get_group_selector(pctldev, np_config->name) < 0)
return -ENODEV;
ret = pinctrl_utils_reserve_map(pctldev, maps, &num_reserved_maps,
num_maps, 1);
if (ret)
return ret;
ret = pinmux_generic_add_function(pctldev, np_config->name, group_names,
1, function);
ret = pinctrl_utils_add_map_mux(pctldev, maps, &num_reserved_maps,
num_maps, np_config->name,
np_config->name);
if (ret < 0) {
pinctrl_utils_free_map(pctldev, *maps, *num_maps);
*maps = NULL;
*num_maps = 0;
return ret;
}
return 0;
}
static int mux_pinctrl_probe_dt(struct pinctrl_dev *pctldev,
struct device_node *np)
{
struct device *dev = pctldev->dev;
for_each_available_child_of_node_scoped(np, grp) {
struct mux_pin_function *function;
const char **group_names;
int ret;
function = devm_kzalloc(dev, sizeof(*function), GFP_KERNEL);
if (!function)
return -ENOMEM;
group_names = devm_kcalloc(dev, 1, sizeof(*group_names), GFP_KERNEL);
if (!group_names)
return -ENOMEM;
group_names[0] = grp->name;
function->mux_state = devm_mux_state_get_from_np(dev, NULL, grp);
if (IS_ERR(function->mux_state))
return dev_err_probe(dev, PTR_ERR(function->mux_state),
"failed to get mux-state for %pOFn\n",
grp);
ret = pinctrl_generic_add_group(pctldev, grp->name, NULL, 0, NULL);
if (ret < 0)
return dev_err_probe(dev, ret,
"failed to add group %pOFn\n", grp);
ret = pinmux_generic_add_function(pctldev, grp->name, group_names,
1, function);
if (ret < 0)
return dev_err_probe(dev, ret,
"failed to add function %pOFn\n", grp);
}
return 0;
}
static const struct pinctrl_ops mux_pinctrl_ops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
@ -157,6 +189,10 @@ static int mux_pinctrl_probe(struct platform_device *pdev)
if (ret)
return dev_err_probe(dev, ret, "Failed to register pinctrl.\n");
ret = mux_pinctrl_probe_dt(mpctl->pctl, dev->of_node);
if (ret)
return ret;
ret = pinctrl_enable(mpctl->pctl);
if (ret)
return dev_err_probe(dev, ret, "Failed to enable pinctrl.\n");

232
drivers/pinctrl/pinctrl-scmi.c
View File

@ -24,6 +24,7 @@
#include "pinctrl-utils.h"
#include "core.h"
#include "pinconf.h"
#include "pinmux.h"
#define DRV_NAME "scmi-pinctrl"
@ -37,133 +38,18 @@ struct scmi_pinctrl {
struct scmi_protocol_handle *ph;
struct pinctrl_dev *pctldev;
struct pinctrl_desc pctl_desc;
struct pinfunction *functions;
unsigned int nr_functions;
};
static int pinctrl_scmi_get_groups_count(struct pinctrl_dev *pctldev)
{
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
return pinctrl_ops->count_get(pmx->ph, GROUP_TYPE);
}
static const char *pinctrl_scmi_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
int ret;
const char *name;
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
ret = pinctrl_ops->name_get(pmx->ph, selector, GROUP_TYPE, &name);
if (ret) {
dev_err(pmx->dev, "get name failed with err %d", ret);
return NULL;
}
return name;
}
static int pinctrl_scmi_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *num_pins)
{
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
return pinctrl_ops->group_pins_get(pmx->ph, selector, pins, num_pins);
}
static const struct pinctrl_ops pinctrl_scmi_pinctrl_ops = {
.get_groups_count = pinctrl_scmi_get_groups_count,
.get_group_name = pinctrl_scmi_get_group_name,
.get_group_pins = pinctrl_scmi_get_group_pins,
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
#ifdef CONFIG_OF
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinconf_generic_dt_free_map,
#endif
};
static int pinctrl_scmi_get_functions_count(struct pinctrl_dev *pctldev)
{
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
return pinctrl_ops->count_get(pmx->ph, FUNCTION_TYPE);
}
static const char *pinctrl_scmi_get_function_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
int ret;
const char *name;
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
ret = pinctrl_ops->name_get(pmx->ph, selector, FUNCTION_TYPE, &name);
if (ret) {
dev_err(pmx->dev, "get name failed with err %d", ret);
return NULL;
}
return name;
}
static int pinctrl_scmi_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **p_groups,
unsigned int * const p_num_groups)
{
struct pinfunction *func;
const unsigned int *group_ids;
unsigned int num_groups;
const char **groups;
int ret, i;
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
if (!p_groups || !p_num_groups)
return -EINVAL;
if (selector >= pmx->nr_functions)
return -EINVAL;
func = &pmx->functions[selector];
if (func->ngroups)
goto done;
ret = pinctrl_ops->function_groups_get(pmx->ph, selector, &num_groups,
&group_ids);
if (ret) {
dev_err(pmx->dev, "Unable to get function groups, err %d", ret);
return ret;
}
if (!num_groups)
return -EINVAL;
groups = kcalloc(num_groups, sizeof(*groups), GFP_KERNEL);
if (!groups)
return -ENOMEM;
for (i = 0; i < num_groups; i++) {
groups[i] = pinctrl_scmi_get_group_name(pctldev, group_ids[i]);
if (!groups[i]) {
ret = -EINVAL;
goto err_free;
}
}
func->ngroups = num_groups;
func->groups = groups;
done:
*p_groups = func->groups;
*p_num_groups = func->ngroups;
return 0;
err_free:
kfree(groups);
return ret;
}
static int pinctrl_scmi_func_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned int group)
{
@ -190,9 +76,9 @@ static int pinctrl_scmi_free(struct pinctrl_dev *pctldev, unsigned int offset)
static const struct pinmux_ops pinctrl_scmi_pinmux_ops = {
.request = pinctrl_scmi_request,
.free = pinctrl_scmi_free,
.get_functions_count = pinctrl_scmi_get_functions_count,
.get_function_name = pinctrl_scmi_get_function_name,
.get_function_groups = pinctrl_scmi_get_function_groups,
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = pinctrl_scmi_func_set_mux,
};
@ -487,6 +373,98 @@ static const struct pinconf_ops pinctrl_scmi_pinconf_ops = {
.pin_config_config_dbg_show = pinconf_generic_dump_config,
};
static int pinctrl_scmi_get_functions(struct scmi_pinctrl *pmx)
{
unsigned int nr_funcs, nr_groups, i, j;
const unsigned int *group_ids;
const char *fname;
const char **gnames;
int ret;
nr_funcs = pinctrl_ops->count_get(pmx->ph, FUNCTION_TYPE);
for (i = 0; i < nr_funcs; i++) {
ret = pinctrl_ops->name_get(pmx->ph, i, FUNCTION_TYPE,
&fname);
if (ret)
return ret;
ret = pinctrl_ops->function_groups_get(pmx->ph, i,
&nr_groups,
&group_ids);
if (ret)
return ret;
if (!nr_groups)
dev_warn(pmx->dev,
"Function %s contains no groups\n",
fname);
gnames = devm_kmalloc_array(pmx->dev, nr_groups,
sizeof(*gnames), GFP_KERNEL);
if (!gnames)
return -ENOMEM;
for (j = 0; j < nr_groups; j++) {
ret = pinctrl_ops->name_get(pmx->ph, group_ids[j],
GROUP_TYPE, &gnames[j]);
if (ret)
return ret;
}
ret = pinmux_generic_add_function(pmx->pctldev, fname, gnames,
nr_groups, NULL);
if (ret < 0)
return ret;
if (ret != i) {
dev_err(pmx->dev,
"Duplicate function name: %s index: %u selector: %d\n",
fname, i, ret);
return -EINVAL;
}
}
return 0;
}
static int pinctrl_scmi_get_groups(struct scmi_pinctrl *pmx)
{
unsigned int nr_groups, nr_pins, i;
const unsigned int *pins;
const char *gname;
int ret;
nr_groups = pinctrl_ops->count_get(pmx->ph, GROUP_TYPE);
for (i = 0; i < nr_groups; i++) {
ret = pinctrl_ops->name_get(pmx->ph, i, GROUP_TYPE, &gname);
if (ret)
return ret;
ret = pinctrl_ops->group_pins_get(pmx->ph, i, &pins,
&nr_pins);
if (ret)
return ret;
if (!nr_pins)
dev_warn(pmx->dev,
"Group %s contains no pins\n", gname);
ret = pinctrl_generic_add_group(pmx->pctldev, gname, pins,
nr_pins, NULL);
if (ret < 0)
return ret;
if (ret != i) {
dev_err(pmx->dev,
"Duplicate group name: %s index: %u selector: %d\n",
gname, i, ret);
return -EINVAL;
}
}
return 0;
}
static int pinctrl_scmi_get_pins(struct scmi_pinctrl *pmx,
struct pinctrl_desc *desc)
{
@ -571,11 +549,13 @@ static int scmi_pinctrl_probe(struct scmi_device *sdev)
if (ret)
return dev_err_probe(dev, ret, "Failed to register pinctrl\n");
pmx->nr_functions = pinctrl_scmi_get_functions_count(pmx->pctldev);
pmx->functions = devm_kcalloc(dev, pmx->nr_functions,
sizeof(*pmx->functions), GFP_KERNEL);
if (!pmx->functions)
return -ENOMEM;
ret = pinctrl_scmi_get_groups(pmx);
if (ret)
return dev_err_probe(dev, ret, "Failed to register groups\n");
ret = pinctrl_scmi_get_functions(pmx);
if (ret)
return dev_err_probe(dev, ret, "Failed to register functions\n");
return pinctrl_enable(pmx->pctldev);
}

2
drivers/pinctrl/pinctrl-st.c
View File

@ -1148,7 +1148,7 @@ static void st_parse_syscfgs(struct st_pinctrl *info, int bank,
pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);
pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);
/* retime avaiable for all pins by default */
/* retime available for all pins by default */
pc->rt_pin_mask = 0xff;
of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask);
st_pctl_dt_setup_retime(info, bank, pc);

2
drivers/pinctrl/pinmux.c
View File

@ -636,7 +636,7 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
mutex_lock(&pctldev->mutex);
/* The pin number can be retrived from the pin controller descriptor */
/* The pin number can be retrieved from the pin controller descriptor */
for (i = 0; i < pctldev->desc->npins; i++) {
struct pin_desc *desc;
bool is_hog = false;

10
drivers/pinctrl/qcom/Kconfig
View File

@ -62,6 +62,16 @@ config PINCTRL_LPASS_LPI
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SoCs.
config PINCTRL_HAWI_LPASS_LPI
tristate "Qualcomm Technologies Inc Hawi LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc Hawi
platform.
config PINCTRL_MILOS_LPASS_LPI
tristate "Qualcomm Milos LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST

19
drivers/pinctrl/qcom/Kconfig.msm
View File

@ -153,6 +153,17 @@ config PINCTRL_KAANAPALI
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc Kaanapali platform.
config PINCTRL_KUNO
tristate "Qualcomm Kuno pin controller driver"
depends on ARM || COMPILE_TEST
default ARCH_QCOM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc Kuno platform.
Say Y here to compile statically, or M here to compile it as a
module. If unsure, say N.
config PINCTRL_MAILI
tristate "Qualcomm Technologies Inc Maili pin controller driver"
depends on ARM64 || COMPILE_TEST
@ -232,6 +243,14 @@ config PINCTRL_MSM8917
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm MSM8917, MSM8937 platform.
config PINCTRL_MSM8952
tristate "Qualcomm 8952 pin controller driver"
depends on ARM64 || COMPILE_TEST
default ARCH_QCOM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm MSM8952 platform.
config PINCTRL_MSM8953
tristate "Qualcomm 8953 pin controller driver"
depends on ARM64 || COMPILE_TEST

3
drivers/pinctrl/qcom/Makefile
View File

@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_ELIZA) += pinctrl-eliza.o
obj-$(CONFIG_PINCTRL_GLYMUR) += pinctrl-glymur.o
obj-$(CONFIG_PINCTRL_HAWI) += pinctrl-hawi.o
obj-$(CONFIG_PINCTRL_HAWI_LPASS_LPI) += pinctrl-hawi-lpass-lpi.o
obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
@ -17,6 +18,7 @@ obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o
obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o
obj-$(CONFIG_PINCTRL_IPQ9650) += pinctrl-ipq9650.o
obj-$(CONFIG_PINCTRL_KAANAPALI) += pinctrl-kaanapali.o
obj-$(CONFIG_PINCTRL_KUNO) += pinctrl-kuno.o
obj-$(CONFIG_PINCTRL_MAILI) += pinctrl-maili.o
obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o
obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
@ -25,6 +27,7 @@ obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
obj-$(CONFIG_PINCTRL_MSM8909) += pinctrl-msm8909.o
obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o
obj-$(CONFIG_PINCTRL_MSM8917) += pinctrl-msm8917.o
obj-$(CONFIG_PINCTRL_MSM8952) += pinctrl-msm8952.o
obj-$(CONFIG_PINCTRL_MSM8953) += pinctrl-msm8953.o
obj-$(CONFIG_PINCTRL_MSM8976) += pinctrl-msm8976.o
obj-$(CONFIG_PINCTRL_MSM8994) += pinctrl-msm8994.o

188
drivers/pinctrl/qcom/pinctrl-apq8064.c
View File

@ -214,17 +214,17 @@ static const unsigned int sdc3_data_pins[] = { 95 };
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
APQ_MUX_gpio, \
APQ_MUX_##f1, \
APQ_MUX_##f2, \
APQ_MUX_##f3, \
APQ_MUX_##f4, \
APQ_MUX_##f5, \
APQ_MUX_##f6, \
APQ_MUX_##f7, \
APQ_MUX_##f8, \
APQ_MUX_##f9, \
APQ_MUX_##f10, \
msm_mux_gpio, \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9, \
msm_mux_##f10, \
}, \
.nfuncs = 11, \
.ctl_reg = 0x1000 + 0x10 * id, \
@ -276,48 +276,48 @@ static const unsigned int sdc3_data_pins[] = { 95 };
}
enum apq8064_functions {
APQ_MUX_cam_mclk,
APQ_MUX_codec_mic_i2s,
APQ_MUX_codec_spkr_i2s,
APQ_MUX_gp_clk_0a,
APQ_MUX_gp_clk_0b,
APQ_MUX_gp_clk_1a,
APQ_MUX_gp_clk_1b,
APQ_MUX_gp_clk_2a,
APQ_MUX_gp_clk_2b,
APQ_MUX_gpio,
APQ_MUX_gsbi1,
APQ_MUX_gsbi2,
APQ_MUX_gsbi3,
APQ_MUX_gsbi4,
APQ_MUX_gsbi4_cam_i2c,
APQ_MUX_gsbi5,
APQ_MUX_gsbi5_spi_cs1,
APQ_MUX_gsbi5_spi_cs2,
APQ_MUX_gsbi5_spi_cs3,
APQ_MUX_gsbi6,
APQ_MUX_gsbi6_spi_cs1,
APQ_MUX_gsbi6_spi_cs2,
APQ_MUX_gsbi6_spi_cs3,
APQ_MUX_gsbi7,
APQ_MUX_gsbi7_spi_cs1,
APQ_MUX_gsbi7_spi_cs2,
APQ_MUX_gsbi7_spi_cs3,
APQ_MUX_gsbi_cam_i2c,
APQ_MUX_hdmi,
APQ_MUX_mi2s,
APQ_MUX_riva_bt,
APQ_MUX_riva_fm,
APQ_MUX_riva_wlan,
APQ_MUX_sdc2,
APQ_MUX_sdc4,
APQ_MUX_slimbus,
APQ_MUX_spkr_i2s,
APQ_MUX_tsif1,
APQ_MUX_tsif2,
APQ_MUX_usb2_hsic,
APQ_MUX_ps_hold,
APQ_MUX_NA,
msm_mux_cam_mclk,
msm_mux_codec_mic_i2s,
msm_mux_codec_spkr_i2s,
msm_mux_gp_clk_0a,
msm_mux_gp_clk_0b,
msm_mux_gp_clk_1a,
msm_mux_gp_clk_1b,
msm_mux_gp_clk_2a,
msm_mux_gp_clk_2b,
msm_mux_gpio,
msm_mux_gsbi1,
msm_mux_gsbi2,
msm_mux_gsbi3,
msm_mux_gsbi4,
msm_mux_gsbi4_cam_i2c,
msm_mux_gsbi5,
msm_mux_gsbi5_spi_cs1,
msm_mux_gsbi5_spi_cs2,
msm_mux_gsbi5_spi_cs3,
msm_mux_gsbi6,
msm_mux_gsbi6_spi_cs1,
msm_mux_gsbi6_spi_cs2,
msm_mux_gsbi6_spi_cs3,
msm_mux_gsbi7,
msm_mux_gsbi7_spi_cs1,
msm_mux_gsbi7_spi_cs2,
msm_mux_gsbi7_spi_cs3,
msm_mux_gsbi_cam_i2c,
msm_mux_hdmi,
msm_mux_mi2s,
msm_mux_riva_bt,
msm_mux_riva_fm,
msm_mux_riva_wlan,
msm_mux_sdc2,
msm_mux_sdc4,
msm_mux_slimbus,
msm_mux_spkr_i2s,
msm_mux_tsif1,
msm_mux_tsif2,
msm_mux_usb2_hsic,
msm_mux_ps_hold,
msm_mux_NA,
};
static const char * const cam_mclk_groups[] = {
@ -457,47 +457,47 @@ static const char * const usb2_hsic_groups[] = {
};
static const struct pinfunction apq8064_functions[] = {
APQ_PIN_FUNCTION(cam_mclk),
APQ_PIN_FUNCTION(codec_mic_i2s),
APQ_PIN_FUNCTION(codec_spkr_i2s),
APQ_PIN_FUNCTION(gp_clk_0a),
APQ_PIN_FUNCTION(gp_clk_0b),
APQ_PIN_FUNCTION(gp_clk_1a),
APQ_PIN_FUNCTION(gp_clk_1b),
APQ_PIN_FUNCTION(gp_clk_2a),
APQ_PIN_FUNCTION(gp_clk_2b),
APQ_PIN_FUNCTION(gpio),
APQ_PIN_FUNCTION(gsbi1),
APQ_PIN_FUNCTION(gsbi2),
APQ_PIN_FUNCTION(gsbi3),
APQ_PIN_FUNCTION(gsbi4),
APQ_PIN_FUNCTION(gsbi4_cam_i2c),
APQ_PIN_FUNCTION(gsbi5),
APQ_PIN_FUNCTION(gsbi5_spi_cs1),
APQ_PIN_FUNCTION(gsbi5_spi_cs2),
APQ_PIN_FUNCTION(gsbi5_spi_cs3),
APQ_PIN_FUNCTION(gsbi6),
APQ_PIN_FUNCTION(gsbi6_spi_cs1),
APQ_PIN_FUNCTION(gsbi6_spi_cs2),
APQ_PIN_FUNCTION(gsbi6_spi_cs3),
APQ_PIN_FUNCTION(gsbi7),
APQ_PIN_FUNCTION(gsbi7_spi_cs1),
APQ_PIN_FUNCTION(gsbi7_spi_cs2),
APQ_PIN_FUNCTION(gsbi7_spi_cs3),
APQ_PIN_FUNCTION(gsbi_cam_i2c),
APQ_PIN_FUNCTION(hdmi),
APQ_PIN_FUNCTION(mi2s),
APQ_PIN_FUNCTION(riva_bt),
APQ_PIN_FUNCTION(riva_fm),
APQ_PIN_FUNCTION(riva_wlan),
APQ_PIN_FUNCTION(sdc2),
APQ_PIN_FUNCTION(sdc4),
APQ_PIN_FUNCTION(slimbus),
APQ_PIN_FUNCTION(spkr_i2s),
APQ_PIN_FUNCTION(tsif1),
APQ_PIN_FUNCTION(tsif2),
APQ_PIN_FUNCTION(usb2_hsic),
APQ_PIN_FUNCTION(ps_hold),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(codec_mic_i2s),
MSM_PIN_FUNCTION(codec_spkr_i2s),
MSM_PIN_FUNCTION(gp_clk_0a),
MSM_PIN_FUNCTION(gp_clk_0b),
MSM_PIN_FUNCTION(gp_clk_1a),
MSM_PIN_FUNCTION(gp_clk_1b),
MSM_PIN_FUNCTION(gp_clk_2a),
MSM_PIN_FUNCTION(gp_clk_2b),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gsbi1),
MSM_PIN_FUNCTION(gsbi2),
MSM_PIN_FUNCTION(gsbi3),
MSM_PIN_FUNCTION(gsbi4),
MSM_PIN_FUNCTION(gsbi4_cam_i2c),
MSM_PIN_FUNCTION(gsbi5),
MSM_PIN_FUNCTION(gsbi5_spi_cs1),
MSM_PIN_FUNCTION(gsbi5_spi_cs2),
MSM_PIN_FUNCTION(gsbi5_spi_cs3),
MSM_PIN_FUNCTION(gsbi6),
MSM_PIN_FUNCTION(gsbi6_spi_cs1),
MSM_PIN_FUNCTION(gsbi6_spi_cs2),
MSM_PIN_FUNCTION(gsbi6_spi_cs3),
MSM_PIN_FUNCTION(gsbi7),
MSM_PIN_FUNCTION(gsbi7_spi_cs1),
MSM_PIN_FUNCTION(gsbi7_spi_cs2),
MSM_PIN_FUNCTION(gsbi7_spi_cs3),
MSM_PIN_FUNCTION(gsbi_cam_i2c),
MSM_PIN_FUNCTION(hdmi),
MSM_PIN_FUNCTION(mi2s),
MSM_PIN_FUNCTION(riva_bt),
MSM_PIN_FUNCTION(riva_fm),
MSM_PIN_FUNCTION(riva_wlan),
MSM_PIN_FUNCTION(sdc2),
MSM_PIN_FUNCTION(sdc4),
MSM_PIN_FUNCTION(slimbus),
MSM_PIN_FUNCTION(spkr_i2s),
MSM_PIN_FUNCTION(tsif1),
MSM_PIN_FUNCTION(tsif2),
MSM_PIN_FUNCTION(usb2_hsic),
MSM_PIN_FUNCTION(ps_hold),
};
static const struct msm_pingroup apq8064_groups[] = {

502
drivers/pinctrl/qcom/pinctrl-apq8084.c
View File

@ -329,14 +329,14 @@ static const unsigned int sdc2_data_pins[] = { 152 };
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
APQ_MUX_gpio, \
APQ_MUX_##f1, \
APQ_MUX_##f2, \
APQ_MUX_##f3, \
APQ_MUX_##f4, \
APQ_MUX_##f5, \
APQ_MUX_##f6, \
APQ_MUX_##f7 \
msm_mux_gpio, \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7 \
}, \
.nfuncs = 8, \
.ctl_reg = 0x1000 + 0x10 * id, \
@ -386,128 +386,128 @@ static const unsigned int sdc2_data_pins[] = { 152 };
}
enum apq8084_functions {
APQ_MUX_adsp_ext,
APQ_MUX_audio_ref,
APQ_MUX_blsp_i2c1,
APQ_MUX_blsp_i2c2,
APQ_MUX_blsp_i2c3,
APQ_MUX_blsp_i2c4,
APQ_MUX_blsp_i2c5,
APQ_MUX_blsp_i2c6,
APQ_MUX_blsp_i2c7,
APQ_MUX_blsp_i2c8,
APQ_MUX_blsp_i2c9,
APQ_MUX_blsp_i2c10,
APQ_MUX_blsp_i2c11,
APQ_MUX_blsp_i2c12,
APQ_MUX_blsp_spi1,
APQ_MUX_blsp_spi1_cs1,
APQ_MUX_blsp_spi1_cs2,
APQ_MUX_blsp_spi1_cs3,
APQ_MUX_blsp_spi2,
APQ_MUX_blsp_spi3,
APQ_MUX_blsp_spi3_cs1,
APQ_MUX_blsp_spi3_cs2,
APQ_MUX_blsp_spi3_cs3,
APQ_MUX_blsp_spi4,
APQ_MUX_blsp_spi5,
APQ_MUX_blsp_spi6,
APQ_MUX_blsp_spi7,
APQ_MUX_blsp_spi8,
APQ_MUX_blsp_spi9,
APQ_MUX_blsp_spi10,
APQ_MUX_blsp_spi10_cs1,
APQ_MUX_blsp_spi10_cs2,
APQ_MUX_blsp_spi10_cs3,
APQ_MUX_blsp_spi11,
APQ_MUX_blsp_spi12,
APQ_MUX_blsp_uart1,
APQ_MUX_blsp_uart2,
APQ_MUX_blsp_uart3,
APQ_MUX_blsp_uart4,
APQ_MUX_blsp_uart5,
APQ_MUX_blsp_uart6,
APQ_MUX_blsp_uart7,
APQ_MUX_blsp_uart8,
APQ_MUX_blsp_uart9,
APQ_MUX_blsp_uart10,
APQ_MUX_blsp_uart11,
APQ_MUX_blsp_uart12,
APQ_MUX_blsp_uim1,
APQ_MUX_blsp_uim2,
APQ_MUX_blsp_uim3,
APQ_MUX_blsp_uim4,
APQ_MUX_blsp_uim5,
APQ_MUX_blsp_uim6,
APQ_MUX_blsp_uim7,
APQ_MUX_blsp_uim8,
APQ_MUX_blsp_uim9,
APQ_MUX_blsp_uim10,
APQ_MUX_blsp_uim11,
APQ_MUX_blsp_uim12,
APQ_MUX_cam_mclk0,
APQ_MUX_cam_mclk1,
APQ_MUX_cam_mclk2,
APQ_MUX_cam_mclk3,
APQ_MUX_cci_async,
APQ_MUX_cci_async_in0,
APQ_MUX_cci_i2c0,
APQ_MUX_cci_i2c1,
APQ_MUX_cci_timer0,
APQ_MUX_cci_timer1,
APQ_MUX_cci_timer2,
APQ_MUX_cci_timer3,
APQ_MUX_cci_timer4,
APQ_MUX_edp_hpd,
APQ_MUX_gcc_gp1,
APQ_MUX_gcc_gp2,
APQ_MUX_gcc_gp3,
APQ_MUX_gcc_obt,
APQ_MUX_gcc_vtt,
APQ_MUX_gp_mn,
APQ_MUX_gp_pdm0,
APQ_MUX_gp_pdm1,
APQ_MUX_gp_pdm2,
APQ_MUX_gp0_clk,
APQ_MUX_gp1_clk,
APQ_MUX_gpio,
APQ_MUX_hdmi_cec,
APQ_MUX_hdmi_ddc,
APQ_MUX_hdmi_dtest,
APQ_MUX_hdmi_hpd,
APQ_MUX_hdmi_rcv,
APQ_MUX_hsic,
APQ_MUX_ldo_en,
APQ_MUX_ldo_update,
APQ_MUX_mdp_vsync,
APQ_MUX_pci_e0,
APQ_MUX_pci_e0_n,
APQ_MUX_pci_e0_rst,
APQ_MUX_pci_e1,
APQ_MUX_pci_e1_rst,
APQ_MUX_pci_e1_rst_n,
APQ_MUX_pci_e1_clkreq_n,
APQ_MUX_pri_mi2s,
APQ_MUX_qua_mi2s,
APQ_MUX_sata_act,
APQ_MUX_sata_devsleep,
APQ_MUX_sata_devsleep_n,
APQ_MUX_sd_write,
APQ_MUX_sdc_emmc_mode,
APQ_MUX_sdc3,
APQ_MUX_sdc4,
APQ_MUX_sec_mi2s,
APQ_MUX_slimbus,
APQ_MUX_spdif_tx,
APQ_MUX_spkr_i2s,
APQ_MUX_spkr_i2s_ws,
APQ_MUX_spss_geni,
APQ_MUX_ter_mi2s,
APQ_MUX_tsif1,
APQ_MUX_tsif2,
APQ_MUX_uim,
APQ_MUX_uim_batt_alarm,
APQ_MUX_NA,
msm_mux_adsp_ext,
msm_mux_audio_ref,
msm_mux_blsp_i2c1,
msm_mux_blsp_i2c2,
msm_mux_blsp_i2c3,
msm_mux_blsp_i2c4,
msm_mux_blsp_i2c5,
msm_mux_blsp_i2c6,
msm_mux_blsp_i2c7,
msm_mux_blsp_i2c8,
msm_mux_blsp_i2c9,
msm_mux_blsp_i2c10,
msm_mux_blsp_i2c11,
msm_mux_blsp_i2c12,
msm_mux_blsp_spi1,
msm_mux_blsp_spi1_cs1,
msm_mux_blsp_spi1_cs2,
msm_mux_blsp_spi1_cs3,
msm_mux_blsp_spi2,
msm_mux_blsp_spi3,
msm_mux_blsp_spi3_cs1,
msm_mux_blsp_spi3_cs2,
msm_mux_blsp_spi3_cs3,
msm_mux_blsp_spi4,
msm_mux_blsp_spi5,
msm_mux_blsp_spi6,
msm_mux_blsp_spi7,
msm_mux_blsp_spi8,
msm_mux_blsp_spi9,
msm_mux_blsp_spi10,
msm_mux_blsp_spi10_cs1,
msm_mux_blsp_spi10_cs2,
msm_mux_blsp_spi10_cs3,
msm_mux_blsp_spi11,
msm_mux_blsp_spi12,
msm_mux_blsp_uart1,
msm_mux_blsp_uart2,
msm_mux_blsp_uart3,
msm_mux_blsp_uart4,
msm_mux_blsp_uart5,
msm_mux_blsp_uart6,
msm_mux_blsp_uart7,
msm_mux_blsp_uart8,
msm_mux_blsp_uart9,
msm_mux_blsp_uart10,
msm_mux_blsp_uart11,
msm_mux_blsp_uart12,
msm_mux_blsp_uim1,
msm_mux_blsp_uim2,
msm_mux_blsp_uim3,
msm_mux_blsp_uim4,
msm_mux_blsp_uim5,
msm_mux_blsp_uim6,
msm_mux_blsp_uim7,
msm_mux_blsp_uim8,
msm_mux_blsp_uim9,
msm_mux_blsp_uim10,
msm_mux_blsp_uim11,
msm_mux_blsp_uim12,
msm_mux_cam_mclk0,
msm_mux_cam_mclk1,
msm_mux_cam_mclk2,
msm_mux_cam_mclk3,
msm_mux_cci_async,
msm_mux_cci_async_in0,
msm_mux_cci_i2c0,
msm_mux_cci_i2c1,
msm_mux_cci_timer0,
msm_mux_cci_timer1,
msm_mux_cci_timer2,
msm_mux_cci_timer3,
msm_mux_cci_timer4,
msm_mux_edp_hpd,
msm_mux_gcc_gp1,
msm_mux_gcc_gp2,
msm_mux_gcc_gp3,
msm_mux_gcc_obt,
msm_mux_gcc_vtt,
msm_mux_gp_mn,
msm_mux_gp_pdm0,
msm_mux_gp_pdm1,
msm_mux_gp_pdm2,
msm_mux_gp0_clk,
msm_mux_gp1_clk,
msm_mux_gpio,
msm_mux_hdmi_cec,
msm_mux_hdmi_ddc,
msm_mux_hdmi_dtest,
msm_mux_hdmi_hpd,
msm_mux_hdmi_rcv,
msm_mux_hsic,
msm_mux_ldo_en,
msm_mux_ldo_update,
msm_mux_mdp_vsync,
msm_mux_pci_e0,
msm_mux_pci_e0_n,
msm_mux_pci_e0_rst,
msm_mux_pci_e1,
msm_mux_pci_e1_rst,
msm_mux_pci_e1_rst_n,
msm_mux_pci_e1_clkreq_n,
msm_mux_pri_mi2s,
msm_mux_qua_mi2s,
msm_mux_sata_act,
msm_mux_sata_devsleep,
msm_mux_sata_devsleep_n,
msm_mux_sd_write,
msm_mux_sdc_emmc_mode,
msm_mux_sdc3,
msm_mux_sdc4,
msm_mux_sec_mi2s,
msm_mux_slimbus,
msm_mux_spdif_tx,
msm_mux_spkr_i2s,
msm_mux_spkr_i2s_ws,
msm_mux_spss_geni,
msm_mux_ter_mi2s,
msm_mux_tsif1,
msm_mux_tsif2,
msm_mux_uim,
msm_mux_uim_batt_alarm,
msm_mux_NA,
};
static const char * const gpio_groups[] = {
@ -897,127 +897,127 @@ static const char * const uim_batt_alarm_groups[] = {
"gpio102"
};
static const struct pinfunction apq8084_functions[] = {
APQ_PIN_FUNCTION(adsp_ext),
APQ_PIN_FUNCTION(audio_ref),
APQ_PIN_FUNCTION(blsp_i2c1),
APQ_PIN_FUNCTION(blsp_i2c2),
APQ_PIN_FUNCTION(blsp_i2c3),
APQ_PIN_FUNCTION(blsp_i2c4),
APQ_PIN_FUNCTION(blsp_i2c5),
APQ_PIN_FUNCTION(blsp_i2c6),
APQ_PIN_FUNCTION(blsp_i2c7),
APQ_PIN_FUNCTION(blsp_i2c8),
APQ_PIN_FUNCTION(blsp_i2c9),
APQ_PIN_FUNCTION(blsp_i2c10),
APQ_PIN_FUNCTION(blsp_i2c11),
APQ_PIN_FUNCTION(blsp_i2c12),
APQ_PIN_FUNCTION(blsp_spi1),
APQ_PIN_FUNCTION(blsp_spi1_cs1),
APQ_PIN_FUNCTION(blsp_spi1_cs2),
APQ_PIN_FUNCTION(blsp_spi1_cs3),
APQ_PIN_FUNCTION(blsp_spi2),
APQ_PIN_FUNCTION(blsp_spi3),
APQ_PIN_FUNCTION(blsp_spi3_cs1),
APQ_PIN_FUNCTION(blsp_spi3_cs2),
APQ_PIN_FUNCTION(blsp_spi3_cs3),
APQ_PIN_FUNCTION(blsp_spi4),
APQ_PIN_FUNCTION(blsp_spi5),
APQ_PIN_FUNCTION(blsp_spi6),
APQ_PIN_FUNCTION(blsp_spi7),
APQ_PIN_FUNCTION(blsp_spi8),
APQ_PIN_FUNCTION(blsp_spi9),
APQ_PIN_FUNCTION(blsp_spi10),
APQ_PIN_FUNCTION(blsp_spi10_cs1),
APQ_PIN_FUNCTION(blsp_spi10_cs2),
APQ_PIN_FUNCTION(blsp_spi10_cs3),
APQ_PIN_FUNCTION(blsp_spi11),
APQ_PIN_FUNCTION(blsp_spi12),
APQ_PIN_FUNCTION(blsp_uart1),
APQ_PIN_FUNCTION(blsp_uart2),
APQ_PIN_FUNCTION(blsp_uart3),
APQ_PIN_FUNCTION(blsp_uart4),
APQ_PIN_FUNCTION(blsp_uart5),
APQ_PIN_FUNCTION(blsp_uart6),
APQ_PIN_FUNCTION(blsp_uart7),
APQ_PIN_FUNCTION(blsp_uart8),
APQ_PIN_FUNCTION(blsp_uart9),
APQ_PIN_FUNCTION(blsp_uart10),
APQ_PIN_FUNCTION(blsp_uart11),
APQ_PIN_FUNCTION(blsp_uart12),
APQ_PIN_FUNCTION(blsp_uim1),
APQ_PIN_FUNCTION(blsp_uim2),
APQ_PIN_FUNCTION(blsp_uim3),
APQ_PIN_FUNCTION(blsp_uim4),
APQ_PIN_FUNCTION(blsp_uim5),
APQ_PIN_FUNCTION(blsp_uim6),
APQ_PIN_FUNCTION(blsp_uim7),
APQ_PIN_FUNCTION(blsp_uim8),
APQ_PIN_FUNCTION(blsp_uim9),
APQ_PIN_FUNCTION(blsp_uim10),
APQ_PIN_FUNCTION(blsp_uim11),
APQ_PIN_FUNCTION(blsp_uim12),
APQ_PIN_FUNCTION(cam_mclk0),
APQ_PIN_FUNCTION(cam_mclk1),
APQ_PIN_FUNCTION(cam_mclk2),
APQ_PIN_FUNCTION(cam_mclk3),
APQ_PIN_FUNCTION(cci_async),
APQ_PIN_FUNCTION(cci_async_in0),
APQ_PIN_FUNCTION(cci_i2c0),
APQ_PIN_FUNCTION(cci_i2c1),
APQ_PIN_FUNCTION(cci_timer0),
APQ_PIN_FUNCTION(cci_timer1),
APQ_PIN_FUNCTION(cci_timer2),
APQ_PIN_FUNCTION(cci_timer3),
APQ_PIN_FUNCTION(cci_timer4),
APQ_PIN_FUNCTION(edp_hpd),
APQ_PIN_FUNCTION(gcc_gp1),
APQ_PIN_FUNCTION(gcc_gp2),
APQ_PIN_FUNCTION(gcc_gp3),
APQ_PIN_FUNCTION(gcc_obt),
APQ_PIN_FUNCTION(gcc_vtt),
APQ_PIN_FUNCTION(gp_mn),
APQ_PIN_FUNCTION(gp_pdm0),
APQ_PIN_FUNCTION(gp_pdm1),
APQ_PIN_FUNCTION(gp_pdm2),
APQ_PIN_FUNCTION(gp0_clk),
APQ_PIN_FUNCTION(gp1_clk),
APQ_PIN_FUNCTION(gpio),
APQ_PIN_FUNCTION(hdmi_cec),
APQ_PIN_FUNCTION(hdmi_ddc),
APQ_PIN_FUNCTION(hdmi_dtest),
APQ_PIN_FUNCTION(hdmi_hpd),
APQ_PIN_FUNCTION(hdmi_rcv),
APQ_PIN_FUNCTION(hsic),
APQ_PIN_FUNCTION(ldo_en),
APQ_PIN_FUNCTION(ldo_update),
APQ_PIN_FUNCTION(mdp_vsync),
APQ_PIN_FUNCTION(pci_e0),
APQ_PIN_FUNCTION(pci_e0_n),
APQ_PIN_FUNCTION(pci_e0_rst),
APQ_PIN_FUNCTION(pci_e1),
APQ_PIN_FUNCTION(pci_e1_rst),
APQ_PIN_FUNCTION(pci_e1_rst_n),
APQ_PIN_FUNCTION(pci_e1_clkreq_n),
APQ_PIN_FUNCTION(pri_mi2s),
APQ_PIN_FUNCTION(qua_mi2s),
APQ_PIN_FUNCTION(sata_act),
APQ_PIN_FUNCTION(sata_devsleep),
APQ_PIN_FUNCTION(sata_devsleep_n),
APQ_PIN_FUNCTION(sd_write),
APQ_PIN_FUNCTION(sdc_emmc_mode),
APQ_PIN_FUNCTION(sdc3),
APQ_PIN_FUNCTION(sdc4),
APQ_PIN_FUNCTION(sec_mi2s),
APQ_PIN_FUNCTION(slimbus),
APQ_PIN_FUNCTION(spdif_tx),
APQ_PIN_FUNCTION(spkr_i2s),
APQ_PIN_FUNCTION(spkr_i2s_ws),
APQ_PIN_FUNCTION(spss_geni),
APQ_PIN_FUNCTION(ter_mi2s),
APQ_PIN_FUNCTION(tsif1),
APQ_PIN_FUNCTION(tsif2),
APQ_PIN_FUNCTION(uim),
APQ_PIN_FUNCTION(uim_batt_alarm),
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_i2c2),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_i2c5),
MSM_PIN_FUNCTION(blsp_i2c6),
MSM_PIN_FUNCTION(blsp_i2c7),
MSM_PIN_FUNCTION(blsp_i2c8),
MSM_PIN_FUNCTION(blsp_i2c9),
MSM_PIN_FUNCTION(blsp_i2c10),
MSM_PIN_FUNCTION(blsp_i2c11),
MSM_PIN_FUNCTION(blsp_i2c12),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_spi1_cs1),
MSM_PIN_FUNCTION(blsp_spi1_cs2),
MSM_PIN_FUNCTION(blsp_spi1_cs3),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(blsp_spi3_cs1),
MSM_PIN_FUNCTION(blsp_spi3_cs2),
MSM_PIN_FUNCTION(blsp_spi3_cs3),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(blsp_spi5),
MSM_PIN_FUNCTION(blsp_spi6),
MSM_PIN_FUNCTION(blsp_spi7),
MSM_PIN_FUNCTION(blsp_spi8),
MSM_PIN_FUNCTION(blsp_spi9),
MSM_PIN_FUNCTION(blsp_spi10),
MSM_PIN_FUNCTION(blsp_spi10_cs1),
MSM_PIN_FUNCTION(blsp_spi10_cs2),
MSM_PIN_FUNCTION(blsp_spi10_cs3),
MSM_PIN_FUNCTION(blsp_spi11),
MSM_PIN_FUNCTION(blsp_spi12),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(blsp_uart2),
MSM_PIN_FUNCTION(blsp_uart3),
MSM_PIN_FUNCTION(blsp_uart4),
MSM_PIN_FUNCTION(blsp_uart5),
MSM_PIN_FUNCTION(blsp_uart6),
MSM_PIN_FUNCTION(blsp_uart7),
MSM_PIN_FUNCTION(blsp_uart8),
MSM_PIN_FUNCTION(blsp_uart9),
MSM_PIN_FUNCTION(blsp_uart10),
MSM_PIN_FUNCTION(blsp_uart11),
MSM_PIN_FUNCTION(blsp_uart12),
MSM_PIN_FUNCTION(blsp_uim1),
MSM_PIN_FUNCTION(blsp_uim2),
MSM_PIN_FUNCTION(blsp_uim3),
MSM_PIN_FUNCTION(blsp_uim4),
MSM_PIN_FUNCTION(blsp_uim5),
MSM_PIN_FUNCTION(blsp_uim6),
MSM_PIN_FUNCTION(blsp_uim7),
MSM_PIN_FUNCTION(blsp_uim8),
MSM_PIN_FUNCTION(blsp_uim9),
MSM_PIN_FUNCTION(blsp_uim10),
MSM_PIN_FUNCTION(blsp_uim11),
MSM_PIN_FUNCTION(blsp_uim12),
MSM_PIN_FUNCTION(cam_mclk0),
MSM_PIN_FUNCTION(cam_mclk1),
MSM_PIN_FUNCTION(cam_mclk2),
MSM_PIN_FUNCTION(cam_mclk3),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_async_in0),
MSM_PIN_FUNCTION(cci_i2c0),
MSM_PIN_FUNCTION(cci_i2c1),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(edp_hpd),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gcc_obt),
MSM_PIN_FUNCTION(gcc_vtt),
MSM_PIN_FUNCTION(gp_mn),
MSM_PIN_FUNCTION(gp_pdm0),
MSM_PIN_FUNCTION(gp_pdm1),
MSM_PIN_FUNCTION(gp_pdm2),
MSM_PIN_FUNCTION(gp0_clk),
MSM_PIN_FUNCTION(gp1_clk),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(hdmi_cec),
MSM_PIN_FUNCTION(hdmi_ddc),
MSM_PIN_FUNCTION(hdmi_dtest),
MSM_PIN_FUNCTION(hdmi_hpd),
MSM_PIN_FUNCTION(hdmi_rcv),
MSM_PIN_FUNCTION(hsic),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(pci_e0),
MSM_PIN_FUNCTION(pci_e0_n),
MSM_PIN_FUNCTION(pci_e0_rst),
MSM_PIN_FUNCTION(pci_e1),
MSM_PIN_FUNCTION(pci_e1_rst),
MSM_PIN_FUNCTION(pci_e1_rst_n),
MSM_PIN_FUNCTION(pci_e1_clkreq_n),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(qua_mi2s),
MSM_PIN_FUNCTION(sata_act),
MSM_PIN_FUNCTION(sata_devsleep),
MSM_PIN_FUNCTION(sata_devsleep_n),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sdc_emmc_mode),
MSM_PIN_FUNCTION(sdc3),
MSM_PIN_FUNCTION(sdc4),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(slimbus),
MSM_PIN_FUNCTION(spdif_tx),
MSM_PIN_FUNCTION(spkr_i2s),
MSM_PIN_FUNCTION(spkr_i2s_ws),
MSM_PIN_FUNCTION(spss_geni),
MSM_PIN_FUNCTION(ter_mi2s),
MSM_PIN_FUNCTION(tsif1),
MSM_PIN_FUNCTION(tsif2),
MSM_PIN_FUNCTION(uim),
MSM_PIN_FUNCTION(uim_batt_alarm),
};
static const struct msm_pingroup apq8084_groups[] = {

244
drivers/pinctrl/qcom/pinctrl-hawi-lpass-lpi.c Normal file
View File

@ -0,0 +1,244 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include "pinctrl-lpass-lpi.h"
enum lpass_lpi_functions {
LPI_MUX_dmic1_clk,
LPI_MUX_dmic1_data,
LPI_MUX_dmic2_clk,
LPI_MUX_dmic2_data,
LPI_MUX_dmic3_clk,
LPI_MUX_dmic3_data,
LPI_MUX_dmic4_clk,
LPI_MUX_dmic4_data,
LPI_MUX_ext_mclk1_a,
LPI_MUX_ext_mclk1_b,
LPI_MUX_ext_mclk1_c,
LPI_MUX_ext_mclk1_d,
LPI_MUX_ext_mclk1_e,
LPI_MUX_i2s0_clk,
LPI_MUX_i2s0_data,
LPI_MUX_i2s0_ws,
LPI_MUX_i2s1_clk,
LPI_MUX_i2s1_data,
LPI_MUX_i2s1_ws,
LPI_MUX_i2s2_clk,
LPI_MUX_i2s2_data,
LPI_MUX_i2s2_ws,
LPI_MUX_i2s3_clk,
LPI_MUX_i2s3_data,
LPI_MUX_i2s3_ws,
LPI_MUX_lpass_lpi_dbg_clk,
LPI_MUX_qca_swr_clk,
LPI_MUX_qca_swr_data,
LPI_MUX_slimbus_clk,
LPI_MUX_slimbus_data,
LPI_MUX_swr_rx_clk,
LPI_MUX_swr_rx_data,
LPI_MUX_swr_tx_clk,
LPI_MUX_swr_tx_clk1,
LPI_MUX_swr_tx_data,
LPI_MUX_va_i2s0_clk,
LPI_MUX_va_i2s0_data,
LPI_MUX_va_i2s0_ws,
LPI_MUX_wsa2_swr_clk,
LPI_MUX_wsa2_swr_data,
LPI_MUX_wsa_swr_clk,
LPI_MUX_wsa_swr_data,
LPI_MUX_gpio,
LPI_MUX__,
};
static const struct pinctrl_pin_desc hawi_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
PINCTRL_PIN(22, "gpio22"),
};
static const char * const gpio_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22",
};
static const char * const swr_tx_clk_groups[] = { "gpio0" };
static const char * const i2s0_clk_groups[] = { "gpio0" };
static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
static const char * const i2s0_ws_groups[] = { "gpio1" };
static const char * const swr_rx_clk_groups[] = { "gpio3" };
static const char * const i2s0_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" };
static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
static const char * const ext_mclk1_c_groups[] = { "gpio5" };
static const char * const dmic1_clk_groups[] = { "gpio6" };
static const char * const va_i2s0_clk_groups[] = { "gpio6" };
static const char * const dmic1_data_groups[] = { "gpio7" };
static const char * const va_i2s0_ws_groups[] = { "gpio7" };
static const char * const dmic2_clk_groups[] = { "gpio8" };
static const char * const va_i2s0_data_groups[] = { "gpio8", "gpio9" };
static const char * const dmic2_data_groups[] = { "gpio9" };
static const char * const ext_mclk1_b_groups[] = { "gpio9" };
static const char * const i2s1_clk_groups[] = { "gpio10" };
static const char * const wsa_swr_clk_groups[] = { "gpio10" };
static const char * const i2s1_ws_groups[] = { "gpio11" };
static const char * const wsa_swr_data_groups[] = { "gpio11", "gpio21" };
static const char * const dmic3_clk_groups[] = { "gpio12" };
static const char * const i2s3_clk_groups[] = { "gpio12" };
static const char * const dmic3_data_groups[] = { "gpio13" };
static const char * const i2s3_ws_groups[] = { "gpio13" };
static const char * const ext_mclk1_a_groups[] = { "gpio13" };
static const char * const lpass_lpi_dbg_clk_groups[] = { "gpio13" };
static const char * const swr_tx_clk1_groups[] = { "gpio14" };
static const char * const ext_mclk1_d_groups[] = { "gpio14" };
static const char * const i2s1_data_groups[] = { "gpio15", "gpio16", "gpio21", "gpio22" };
static const char * const wsa2_swr_clk_groups[] = { "gpio15" };
static const char * const wsa2_swr_data_groups[] = { "gpio16", "gpio22" };
static const char * const dmic4_clk_groups[] = { "gpio17" };
static const char * const i2s3_data_groups[] = { "gpio17", "gpio18" };
static const char * const dmic4_data_groups[] = { "gpio18" };
static const char * const i2s2_clk_groups[] = { "gpio19" };
static const char * const slimbus_clk_groups[] = { "gpio19" };
static const char * const qca_swr_clk_groups[] = { "gpio19" };
static const char * const i2s2_ws_groups[] = { "gpio20" };
static const char * const slimbus_data_groups[] = { "gpio20" };
static const char * const qca_swr_data_groups[] = { "gpio20" };
static const char * const i2s2_data_groups[] = { "gpio21", "gpio22" };
static const char * const ext_mclk1_e_groups[] = { "gpio22" };
static const struct lpi_pingroup hawi_groups[] = {
LPI_PINGROUP(0, 11, swr_tx_clk, i2s0_clk, _, _),
LPI_PINGROUP(1, 11, swr_tx_data, i2s0_ws, _, _),
LPI_PINGROUP(2, 11, swr_tx_data, i2s0_data, _, _),
LPI_PINGROUP(3, 11, swr_rx_clk, i2s0_data, _, _),
LPI_PINGROUP(4, 11, swr_rx_data, i2s0_data, _, _),
LPI_PINGROUP(5, 11, swr_rx_data, ext_mclk1_c, i2s0_data, _),
LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, va_i2s0_clk, _, _),
LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, va_i2s0_ws, _, _),
LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, va_i2s0_data, _, _),
LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, va_i2s0_data, ext_mclk1_b, _),
LPI_PINGROUP(10, 11, i2s1_clk, wsa_swr_clk, _, _),
LPI_PINGROUP(11, 11, i2s1_ws, wsa_swr_data, _, _),
LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s3_clk, _, _),
LPI_PINGROUP6(13, LPI_NO_SLEW, dmic3_data, i2s3_ws, ext_mclk1_a, _, lpass_lpi_dbg_clk),
LPI_PINGROUP(14, 11, swr_tx_data, swr_tx_clk1, ext_mclk1_d, _),
LPI_PINGROUP(15, 11, i2s1_data, wsa2_swr_clk, _, _),
LPI_PINGROUP(16, 11, i2s1_data, wsa2_swr_data, _, _),
LPI_PINGROUP(17, LPI_NO_SLEW, dmic4_clk, i2s3_data, _, _),
LPI_PINGROUP(18, LPI_NO_SLEW, dmic4_data, i2s3_data, _, _),
LPI_PINGROUP(19, LPI_NO_SLEW, i2s2_clk, slimbus_clk, qca_swr_clk, _),
LPI_PINGROUP(20, LPI_NO_SLEW, i2s2_ws, slimbus_data, qca_swr_data, _),
LPI_PINGROUP(21, 11, i2s2_data, _, wsa_swr_data, i2s1_data),
LPI_PINGROUP6(22, 11, i2s2_data, ext_mclk1_e, _, i2s1_data, wsa2_swr_data),
};
static const struct lpi_function hawi_functions[] = {
LPI_FUNCTION(gpio),
LPI_FUNCTION(dmic1_clk),
LPI_FUNCTION(dmic1_data),
LPI_FUNCTION(dmic2_clk),
LPI_FUNCTION(dmic2_data),
LPI_FUNCTION(dmic3_clk),
LPI_FUNCTION(dmic3_data),
LPI_FUNCTION(dmic4_clk),
LPI_FUNCTION(dmic4_data),
LPI_FUNCTION(ext_mclk1_a),
LPI_FUNCTION(ext_mclk1_b),
LPI_FUNCTION(ext_mclk1_c),
LPI_FUNCTION(ext_mclk1_d),
LPI_FUNCTION(ext_mclk1_e),
LPI_FUNCTION(i2s0_clk),
LPI_FUNCTION(i2s0_data),
LPI_FUNCTION(i2s0_ws),
LPI_FUNCTION(i2s1_clk),
LPI_FUNCTION(i2s1_data),
LPI_FUNCTION(i2s1_ws),
LPI_FUNCTION(i2s2_clk),
LPI_FUNCTION(i2s2_data),
LPI_FUNCTION(i2s2_ws),
LPI_FUNCTION(i2s3_clk),
LPI_FUNCTION(i2s3_data),
LPI_FUNCTION(i2s3_ws),
LPI_FUNCTION(lpass_lpi_dbg_clk),
LPI_FUNCTION(qca_swr_clk),
LPI_FUNCTION(qca_swr_data),
LPI_FUNCTION(slimbus_clk),
LPI_FUNCTION(slimbus_data),
LPI_FUNCTION(swr_rx_clk),
LPI_FUNCTION(swr_rx_data),
LPI_FUNCTION(swr_tx_clk),
LPI_FUNCTION(swr_tx_clk1),
LPI_FUNCTION(swr_tx_data),
LPI_FUNCTION(va_i2s0_clk),
LPI_FUNCTION(va_i2s0_data),
LPI_FUNCTION(va_i2s0_ws),
LPI_FUNCTION(wsa2_swr_clk),
LPI_FUNCTION(wsa2_swr_data),
LPI_FUNCTION(wsa_swr_clk),
LPI_FUNCTION(wsa_swr_data),
};
static const struct lpi_pinctrl_variant_data hawi_lpi_data = {
.pins = hawi_lpi_pins,
.npins = ARRAY_SIZE(hawi_lpi_pins),
.groups = hawi_groups,
.ngroups = ARRAY_SIZE(hawi_groups),
.functions = hawi_functions,
.nfunctions = ARRAY_SIZE(hawi_functions),
.flags = LPI_FLAG_SLEW_RATE_SAME_REG,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
{
.compatible = "qcom,hawi-lpass-lpi-pinctrl",
.data = &hawi_lpi_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
};
static struct platform_driver lpi_pinctrl_driver = {
.driver = {
.name = "qcom-hawi-lpass-lpi-pinctrl",
.of_match_table = lpi_pinctrl_of_match,
.pm = pm_ptr(&lpi_pinctrl_pm_ops),
},
.probe = lpi_pinctrl_probe,
.remove = lpi_pinctrl_remove,
};
module_platform_driver(lpi_pinctrl_driver);
MODULE_DESCRIPTION("Qualcomm Hawi LPI GPIO pin control driver");
MODULE_LICENSE("GPL");

208
drivers/pinctrl/qcom/pinctrl-ipq4019.c
View File

@ -221,21 +221,21 @@ DECLARE_QCA_GPIO_PINS(99);
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
qca_mux_gpio, /* gpio mode */ \
qca_mux_##f1, \
qca_mux_##f2, \
qca_mux_##f3, \
qca_mux_##f4, \
qca_mux_##f5, \
qca_mux_##f6, \
qca_mux_##f7, \
qca_mux_##f8, \
qca_mux_##f9, \
qca_mux_##f10, \
qca_mux_##f11, \
qca_mux_##f12, \
qca_mux_##f13, \
qca_mux_##f14 \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9, \
msm_mux_##f10, \
msm_mux_##f11, \
msm_mux_##f12, \
msm_mux_##f13, \
msm_mux_##f14 \
}, \
.nfuncs = 15, \
.ctl_reg = 0x0 + 0x1000 * id, \
@ -260,51 +260,51 @@ DECLARE_QCA_GPIO_PINS(99);
enum ipq4019_functions {
qca_mux_gpio,
qca_mux_aud_pin,
qca_mux_audio_pwm,
qca_mux_blsp_i2c0,
qca_mux_blsp_i2c1,
qca_mux_blsp_spi0,
qca_mux_blsp_spi1,
qca_mux_blsp_uart0,
qca_mux_blsp_uart1,
qca_mux_chip_rst,
qca_mux_i2s_rx,
qca_mux_i2s_spdif_in,
qca_mux_i2s_spdif_out,
qca_mux_i2s_td,
qca_mux_i2s_tx,
qca_mux_jtag,
qca_mux_led0,
qca_mux_led1,
qca_mux_led2,
qca_mux_led3,
qca_mux_led4,
qca_mux_led5,
qca_mux_led6,
qca_mux_led7,
qca_mux_led8,
qca_mux_led9,
qca_mux_led10,
qca_mux_led11,
qca_mux_mdc,
qca_mux_mdio,
qca_mux_pcie,
qca_mux_pmu,
qca_mux_prng_rosc,
qca_mux_qpic,
qca_mux_rgmii,
qca_mux_rmii,
qca_mux_sdio,
qca_mux_smart0,
qca_mux_smart1,
qca_mux_smart2,
qca_mux_smart3,
qca_mux_tm,
qca_mux_wifi0,
qca_mux_wifi1,
qca_mux_NA,
msm_mux_gpio,
msm_mux_aud_pin,
msm_mux_audio_pwm,
msm_mux_blsp_i2c0,
msm_mux_blsp_i2c1,
msm_mux_blsp_spi0,
msm_mux_blsp_spi1,
msm_mux_blsp_uart0,
msm_mux_blsp_uart1,
msm_mux_chip_rst,
msm_mux_i2s_rx,
msm_mux_i2s_spdif_in,
msm_mux_i2s_spdif_out,
msm_mux_i2s_td,
msm_mux_i2s_tx,
msm_mux_jtag,
msm_mux_led0,
msm_mux_led1,
msm_mux_led2,
msm_mux_led3,
msm_mux_led4,
msm_mux_led5,
msm_mux_led6,
msm_mux_led7,
msm_mux_led8,
msm_mux_led9,
msm_mux_led10,
msm_mux_led11,
msm_mux_mdc,
msm_mux_mdio,
msm_mux_pcie,
msm_mux_pmu,
msm_mux_prng_rosc,
msm_mux_qpic,
msm_mux_rgmii,
msm_mux_rmii,
msm_mux_sdio,
msm_mux_smart0,
msm_mux_smart1,
msm_mux_smart2,
msm_mux_smart3,
msm_mux_tm,
msm_mux_wifi0,
msm_mux_wifi1,
msm_mux_NA,
};
static const char * const gpio_groups[] = {
@ -470,50 +470,50 @@ static const char * const wifi1_groups[] = {
};
static const struct pinfunction ipq4019_functions[] = {
QCA_PIN_FUNCTION(aud_pin),
QCA_PIN_FUNCTION(audio_pwm),
QCA_PIN_FUNCTION(blsp_i2c0),
QCA_PIN_FUNCTION(blsp_i2c1),
QCA_PIN_FUNCTION(blsp_spi0),
QCA_PIN_FUNCTION(blsp_spi1),
QCA_PIN_FUNCTION(blsp_uart0),
QCA_PIN_FUNCTION(blsp_uart1),
QCA_PIN_FUNCTION(chip_rst),
QCA_GPIO_PIN_FUNCTION(gpio),
QCA_PIN_FUNCTION(i2s_rx),
QCA_PIN_FUNCTION(i2s_spdif_in),
QCA_PIN_FUNCTION(i2s_spdif_out),
QCA_PIN_FUNCTION(i2s_td),
QCA_PIN_FUNCTION(i2s_tx),
QCA_PIN_FUNCTION(jtag),
QCA_PIN_FUNCTION(led0),
QCA_PIN_FUNCTION(led1),
QCA_PIN_FUNCTION(led2),
QCA_PIN_FUNCTION(led3),
QCA_PIN_FUNCTION(led4),
QCA_PIN_FUNCTION(led5),
QCA_PIN_FUNCTION(led6),
QCA_PIN_FUNCTION(led7),
QCA_PIN_FUNCTION(led8),
QCA_PIN_FUNCTION(led9),
QCA_PIN_FUNCTION(led10),
QCA_PIN_FUNCTION(led11),
QCA_PIN_FUNCTION(mdc),
QCA_PIN_FUNCTION(mdio),
QCA_PIN_FUNCTION(pcie),
QCA_PIN_FUNCTION(pmu),
QCA_PIN_FUNCTION(prng_rosc),
QCA_PIN_FUNCTION(qpic),
QCA_PIN_FUNCTION(rgmii),
QCA_PIN_FUNCTION(rmii),
QCA_PIN_FUNCTION(sdio),
QCA_PIN_FUNCTION(smart0),
QCA_PIN_FUNCTION(smart1),
QCA_PIN_FUNCTION(smart2),
QCA_PIN_FUNCTION(smart3),
QCA_PIN_FUNCTION(tm),
QCA_PIN_FUNCTION(wifi0),
QCA_PIN_FUNCTION(wifi1),
MSM_PIN_FUNCTION(aud_pin),
MSM_PIN_FUNCTION(audio_pwm),
MSM_PIN_FUNCTION(blsp_i2c0),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_spi0),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_uart0),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(chip_rst),
MSM_GPIO_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(i2s_rx),
MSM_PIN_FUNCTION(i2s_spdif_in),
MSM_PIN_FUNCTION(i2s_spdif_out),
MSM_PIN_FUNCTION(i2s_td),
MSM_PIN_FUNCTION(i2s_tx),
MSM_PIN_FUNCTION(jtag),
MSM_PIN_FUNCTION(led0),
MSM_PIN_FUNCTION(led1),
MSM_PIN_FUNCTION(led2),
MSM_PIN_FUNCTION(led3),
MSM_PIN_FUNCTION(led4),
MSM_PIN_FUNCTION(led5),
MSM_PIN_FUNCTION(led6),
MSM_PIN_FUNCTION(led7),
MSM_PIN_FUNCTION(led8),
MSM_PIN_FUNCTION(led9),
MSM_PIN_FUNCTION(led10),
MSM_PIN_FUNCTION(led11),
MSM_PIN_FUNCTION(mdc),
MSM_PIN_FUNCTION(mdio),
MSM_PIN_FUNCTION(pcie),
MSM_PIN_FUNCTION(pmu),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qpic),
MSM_PIN_FUNCTION(rgmii),
MSM_PIN_FUNCTION(rmii),
MSM_PIN_FUNCTION(sdio),
MSM_PIN_FUNCTION(smart0),
MSM_PIN_FUNCTION(smart1),
MSM_PIN_FUNCTION(smart2),
MSM_PIN_FUNCTION(smart3),
MSM_PIN_FUNCTION(tm),
MSM_PIN_FUNCTION(wifi0),
MSM_PIN_FUNCTION(wifi1),
};
static const struct msm_pingroup ipq4019_groups[] = {

208
drivers/pinctrl/qcom/pinctrl-ipq8064.c
View File

@ -166,17 +166,17 @@ static const unsigned int sdc3_data_pins[] = { 71 };
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
IPQ_MUX_gpio, \
IPQ_MUX_##f1, \
IPQ_MUX_##f2, \
IPQ_MUX_##f3, \
IPQ_MUX_##f4, \
IPQ_MUX_##f5, \
IPQ_MUX_##f6, \
IPQ_MUX_##f7, \
IPQ_MUX_##f8, \
IPQ_MUX_##f9, \
IPQ_MUX_##f10, \
msm_mux_gpio, \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9, \
msm_mux_##f10, \
}, \
.nfuncs = 11, \
.ctl_reg = 0x1000 + 0x10 * id, \
@ -228,53 +228,53 @@ static const unsigned int sdc3_data_pins[] = { 71 };
}
enum ipq8064_functions {
IPQ_MUX_gpio,
IPQ_MUX_mdio,
IPQ_MUX_mi2s,
IPQ_MUX_pdm,
IPQ_MUX_ssbi,
IPQ_MUX_spmi,
IPQ_MUX_audio_pcm,
IPQ_MUX_gsbi1,
IPQ_MUX_gsbi2,
IPQ_MUX_gsbi4,
IPQ_MUX_gsbi5,
IPQ_MUX_gsbi5_spi_cs1,
IPQ_MUX_gsbi5_spi_cs2,
IPQ_MUX_gsbi5_spi_cs3,
IPQ_MUX_gsbi6,
IPQ_MUX_gsbi7,
IPQ_MUX_nss_spi,
IPQ_MUX_sdc1,
IPQ_MUX_spdif,
IPQ_MUX_nand,
IPQ_MUX_tsif1,
IPQ_MUX_tsif2,
IPQ_MUX_usb_fs_n,
IPQ_MUX_usb_fs,
IPQ_MUX_usb2_hsic,
IPQ_MUX_rgmii2,
IPQ_MUX_sata,
IPQ_MUX_pcie1_rst,
IPQ_MUX_pcie1_prsnt,
IPQ_MUX_pcie1_pwrflt,
IPQ_MUX_pcie1_pwren_n,
IPQ_MUX_pcie1_pwren,
IPQ_MUX_pcie1_clk_req,
IPQ_MUX_pcie2_rst,
IPQ_MUX_pcie2_prsnt,
IPQ_MUX_pcie2_pwrflt,
IPQ_MUX_pcie2_pwren_n,
IPQ_MUX_pcie2_pwren,
IPQ_MUX_pcie2_clk_req,
IPQ_MUX_pcie3_rst,
IPQ_MUX_pcie3_prsnt,
IPQ_MUX_pcie3_pwrflt,
IPQ_MUX_pcie3_pwren_n,
IPQ_MUX_pcie3_pwren,
IPQ_MUX_pcie3_clk_req,
IPQ_MUX_ps_hold,
IPQ_MUX_NA,
msm_mux_gpio,
msm_mux_mdio,
msm_mux_mi2s,
msm_mux_pdm,
msm_mux_ssbi,
msm_mux_spmi,
msm_mux_audio_pcm,
msm_mux_gsbi1,
msm_mux_gsbi2,
msm_mux_gsbi4,
msm_mux_gsbi5,
msm_mux_gsbi5_spi_cs1,
msm_mux_gsbi5_spi_cs2,
msm_mux_gsbi5_spi_cs3,
msm_mux_gsbi6,
msm_mux_gsbi7,
msm_mux_nss_spi,
msm_mux_sdc1,
msm_mux_spdif,
msm_mux_nand,
msm_mux_tsif1,
msm_mux_tsif2,
msm_mux_usb_fs_n,
msm_mux_usb_fs,
msm_mux_usb2_hsic,
msm_mux_rgmii2,
msm_mux_sata,
msm_mux_pcie1_rst,
msm_mux_pcie1_prsnt,
msm_mux_pcie1_pwrflt,
msm_mux_pcie1_pwren_n,
msm_mux_pcie1_pwren,
msm_mux_pcie1_clk_req,
msm_mux_pcie2_rst,
msm_mux_pcie2_prsnt,
msm_mux_pcie2_pwrflt,
msm_mux_pcie2_pwren_n,
msm_mux_pcie2_pwren,
msm_mux_pcie2_clk_req,
msm_mux_pcie3_rst,
msm_mux_pcie3_prsnt,
msm_mux_pcie3_pwrflt,
msm_mux_pcie3_pwren_n,
msm_mux_pcie3_pwren,
msm_mux_pcie3_clk_req,
msm_mux_ps_hold,
msm_mux_NA,
};
static const char * const gpio_groups[] = {
@ -480,52 +480,52 @@ static const char * const ps_hold_groups[] = {
};
static const struct pinfunction ipq8064_functions[] = {
IPQ_GPIO_PIN_FUNCTION(gpio),
IPQ_PIN_FUNCTION(mdio),
IPQ_PIN_FUNCTION(ssbi),
IPQ_PIN_FUNCTION(spmi),
IPQ_PIN_FUNCTION(mi2s),
IPQ_PIN_FUNCTION(pdm),
IPQ_PIN_FUNCTION(audio_pcm),
IPQ_PIN_FUNCTION(gsbi1),
IPQ_PIN_FUNCTION(gsbi2),
IPQ_PIN_FUNCTION(gsbi4),
IPQ_PIN_FUNCTION(gsbi5),
IPQ_PIN_FUNCTION(gsbi5_spi_cs1),
IPQ_PIN_FUNCTION(gsbi5_spi_cs2),
IPQ_PIN_FUNCTION(gsbi5_spi_cs3),
IPQ_PIN_FUNCTION(gsbi6),
IPQ_PIN_FUNCTION(gsbi7),
IPQ_PIN_FUNCTION(nss_spi),
IPQ_PIN_FUNCTION(sdc1),
IPQ_PIN_FUNCTION(spdif),
IPQ_PIN_FUNCTION(nand),
IPQ_PIN_FUNCTION(tsif1),
IPQ_PIN_FUNCTION(tsif2),
IPQ_PIN_FUNCTION(usb_fs_n),
IPQ_PIN_FUNCTION(usb_fs),
IPQ_PIN_FUNCTION(usb2_hsic),
IPQ_PIN_FUNCTION(rgmii2),
IPQ_PIN_FUNCTION(sata),
IPQ_GPIO_PIN_FUNCTION(pcie1_rst),
IPQ_PIN_FUNCTION(pcie1_prsnt),
IPQ_PIN_FUNCTION(pcie1_pwren_n),
IPQ_PIN_FUNCTION(pcie1_pwren),
IPQ_PIN_FUNCTION(pcie1_pwrflt),
IPQ_PIN_FUNCTION(pcie1_clk_req),
IPQ_GPIO_PIN_FUNCTION(pcie2_rst),
IPQ_PIN_FUNCTION(pcie2_prsnt),
IPQ_PIN_FUNCTION(pcie2_pwren_n),
IPQ_PIN_FUNCTION(pcie2_pwren),
IPQ_PIN_FUNCTION(pcie2_pwrflt),
IPQ_PIN_FUNCTION(pcie2_clk_req),
IPQ_GPIO_PIN_FUNCTION(pcie3_rst),
IPQ_PIN_FUNCTION(pcie3_prsnt),
IPQ_PIN_FUNCTION(pcie3_pwren_n),
IPQ_PIN_FUNCTION(pcie3_pwren),
IPQ_PIN_FUNCTION(pcie3_pwrflt),
IPQ_PIN_FUNCTION(pcie3_clk_req),
IPQ_PIN_FUNCTION(ps_hold),
MSM_GPIO_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(mdio),
MSM_PIN_FUNCTION(ssbi),
MSM_PIN_FUNCTION(spmi),
MSM_PIN_FUNCTION(mi2s),
MSM_PIN_FUNCTION(pdm),
MSM_PIN_FUNCTION(audio_pcm),
MSM_PIN_FUNCTION(gsbi1),
MSM_PIN_FUNCTION(gsbi2),
MSM_PIN_FUNCTION(gsbi4),
MSM_PIN_FUNCTION(gsbi5),
MSM_PIN_FUNCTION(gsbi5_spi_cs1),
MSM_PIN_FUNCTION(gsbi5_spi_cs2),
MSM_PIN_FUNCTION(gsbi5_spi_cs3),
MSM_PIN_FUNCTION(gsbi6),
MSM_PIN_FUNCTION(gsbi7),
MSM_PIN_FUNCTION(nss_spi),
MSM_PIN_FUNCTION(sdc1),
MSM_PIN_FUNCTION(spdif),
MSM_PIN_FUNCTION(nand),
MSM_PIN_FUNCTION(tsif1),
MSM_PIN_FUNCTION(tsif2),
MSM_PIN_FUNCTION(usb_fs_n),
MSM_PIN_FUNCTION(usb_fs),
MSM_PIN_FUNCTION(usb2_hsic),
MSM_PIN_FUNCTION(rgmii2),
MSM_PIN_FUNCTION(sata),
MSM_GPIO_PIN_FUNCTION(pcie1_rst),
MSM_PIN_FUNCTION(pcie1_prsnt),
MSM_PIN_FUNCTION(pcie1_pwren_n),
MSM_PIN_FUNCTION(pcie1_pwren),
MSM_PIN_FUNCTION(pcie1_pwrflt),
MSM_PIN_FUNCTION(pcie1_clk_req),
MSM_GPIO_PIN_FUNCTION(pcie2_rst),
MSM_PIN_FUNCTION(pcie2_prsnt),
MSM_PIN_FUNCTION(pcie2_pwren_n),
MSM_PIN_FUNCTION(pcie2_pwren),
MSM_PIN_FUNCTION(pcie2_pwrflt),
MSM_PIN_FUNCTION(pcie2_clk_req),
MSM_GPIO_PIN_FUNCTION(pcie3_rst),
MSM_PIN_FUNCTION(pcie3_prsnt),
MSM_PIN_FUNCTION(pcie3_pwren_n),
MSM_PIN_FUNCTION(pcie3_pwren),
MSM_PIN_FUNCTION(pcie3_pwrflt),
MSM_PIN_FUNCTION(pcie3_clk_req),
MSM_PIN_FUNCTION(ps_hold),
};
static const struct msm_pingroup ipq8064_groups[] = {

801
drivers/pinctrl/qcom/pinctrl-kuno.c Normal file
View File

@ -0,0 +1,801 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "pinctrl-msm.h"
#define REG_BASE 0x100000
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9 \
}, \
.nfuncs = 10, \
.ctl_reg = REG_BASE + REG_SIZE * id, \
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
.oe_bit = 9, \
.in_bit = 0, \
.out_bit = 1, \
.intr_enable_bit = 0, \
.intr_status_bit = 0, \
.intr_target_bit = 5, \
.intr_target_kpss_val = 3, \
.intr_raw_status_bit = 4, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_detection_width = 2, \
}
static const struct pinctrl_pin_desc kuno_pins[] = {
PINCTRL_PIN(0, "GPIO_0"),
PINCTRL_PIN(1, "GPIO_1"),
PINCTRL_PIN(2, "GPIO_2"),
PINCTRL_PIN(3, "GPIO_3"),
PINCTRL_PIN(4, "GPIO_4"),
PINCTRL_PIN(5, "GPIO_5"),
PINCTRL_PIN(6, "GPIO_6"),
PINCTRL_PIN(7, "GPIO_7"),
PINCTRL_PIN(8, "GPIO_8"),
PINCTRL_PIN(9, "GPIO_9"),
PINCTRL_PIN(10, "GPIO_10"),
PINCTRL_PIN(11, "GPIO_11"),
PINCTRL_PIN(12, "GPIO_12"),
PINCTRL_PIN(13, "GPIO_13"),
PINCTRL_PIN(14, "GPIO_14"),
PINCTRL_PIN(15, "GPIO_15"),
PINCTRL_PIN(16, "GPIO_16"),
PINCTRL_PIN(17, "GPIO_17"),
PINCTRL_PIN(18, "GPIO_18"),
PINCTRL_PIN(19, "GPIO_19"),
PINCTRL_PIN(20, "GPIO_20"),
PINCTRL_PIN(21, "GPIO_21"),
PINCTRL_PIN(22, "GPIO_22"),
PINCTRL_PIN(23, "GPIO_23"),
PINCTRL_PIN(24, "GPIO_24"),
PINCTRL_PIN(25, "GPIO_25"),
PINCTRL_PIN(26, "GPIO_26"),
PINCTRL_PIN(27, "GPIO_27"),
PINCTRL_PIN(28, "GPIO_28"),
PINCTRL_PIN(29, "GPIO_29"),
PINCTRL_PIN(30, "GPIO_30"),
PINCTRL_PIN(31, "GPIO_31"),
PINCTRL_PIN(32, "GPIO_32"),
PINCTRL_PIN(33, "GPIO_33"),
PINCTRL_PIN(34, "GPIO_34"),
PINCTRL_PIN(35, "GPIO_35"),
PINCTRL_PIN(36, "GPIO_36"),
PINCTRL_PIN(37, "GPIO_37"),
PINCTRL_PIN(38, "GPIO_38"),
PINCTRL_PIN(39, "GPIO_39"),
PINCTRL_PIN(40, "GPIO_40"),
PINCTRL_PIN(41, "GPIO_41"),
PINCTRL_PIN(42, "GPIO_42"),
PINCTRL_PIN(43, "GPIO_43"),
PINCTRL_PIN(44, "GPIO_44"),
PINCTRL_PIN(45, "GPIO_45"),
PINCTRL_PIN(46, "GPIO_46"),
PINCTRL_PIN(47, "GPIO_47"),
PINCTRL_PIN(48, "GPIO_48"),
PINCTRL_PIN(49, "GPIO_49"),
PINCTRL_PIN(50, "GPIO_50"),
PINCTRL_PIN(51, "GPIO_51"),
PINCTRL_PIN(52, "GPIO_52"),
PINCTRL_PIN(53, "GPIO_53"),
PINCTRL_PIN(54, "GPIO_54"),
PINCTRL_PIN(55, "GPIO_55"),
PINCTRL_PIN(56, "GPIO_56"),
PINCTRL_PIN(57, "GPIO_57"),
PINCTRL_PIN(58, "GPIO_58"),
PINCTRL_PIN(59, "GPIO_59"),
PINCTRL_PIN(60, "GPIO_60"),
PINCTRL_PIN(61, "GPIO_61"),
PINCTRL_PIN(62, "GPIO_62"),
PINCTRL_PIN(63, "GPIO_63"),
PINCTRL_PIN(64, "GPIO_64"),
PINCTRL_PIN(65, "GPIO_65"),
PINCTRL_PIN(66, "GPIO_66"),
PINCTRL_PIN(67, "GPIO_67"),
PINCTRL_PIN(68, "GPIO_68"),
PINCTRL_PIN(69, "GPIO_69"),
PINCTRL_PIN(70, "GPIO_70"),
PINCTRL_PIN(71, "GPIO_71"),
PINCTRL_PIN(72, "GPIO_72"),
PINCTRL_PIN(73, "GPIO_73"),
PINCTRL_PIN(74, "GPIO_74"),
PINCTRL_PIN(75, "GPIO_75"),
PINCTRL_PIN(76, "GPIO_76"),
PINCTRL_PIN(77, "GPIO_77"),
PINCTRL_PIN(78, "GPIO_78"),
PINCTRL_PIN(79, "GPIO_79"),
PINCTRL_PIN(80, "GPIO_80"),
PINCTRL_PIN(81, "GPIO_81"),
PINCTRL_PIN(82, "GPIO_82"),
PINCTRL_PIN(83, "GPIO_83"),
PINCTRL_PIN(84, "GPIO_84"),
PINCTRL_PIN(85, "GPIO_85"),
PINCTRL_PIN(86, "GPIO_86"),
PINCTRL_PIN(87, "GPIO_87"),
PINCTRL_PIN(88, "GPIO_88"),
PINCTRL_PIN(89, "GPIO_89"),
PINCTRL_PIN(90, "GPIO_90"),
PINCTRL_PIN(91, "GPIO_91"),
PINCTRL_PIN(92, "GPIO_92"),
PINCTRL_PIN(93, "GPIO_93"),
PINCTRL_PIN(94, "GPIO_94"),
PINCTRL_PIN(95, "GPIO_95"),
PINCTRL_PIN(96, "GPIO_96"),
PINCTRL_PIN(97, "GPIO_97"),
PINCTRL_PIN(98, "GPIO_98"),
PINCTRL_PIN(99, "GPIO_99"),
PINCTRL_PIN(100, "GPIO_100"),
PINCTRL_PIN(101, "GPIO_101"),
PINCTRL_PIN(102, "GPIO_102"),
PINCTRL_PIN(103, "GPIO_103"),
PINCTRL_PIN(104, "GPIO_104"),
PINCTRL_PIN(105, "GPIO_105"),
PINCTRL_PIN(106, "GPIO_106"),
PINCTRL_PIN(107, "GPIO_107"),
PINCTRL_PIN(108, "GPIO_108"),
PINCTRL_PIN(109, "GPIO_109"),
};
#define DECLARE_MSM_GPIO_PINS(pin) \
static const unsigned int gpio##pin##_pins[] = { pin }
DECLARE_MSM_GPIO_PINS(0);
DECLARE_MSM_GPIO_PINS(1);
DECLARE_MSM_GPIO_PINS(2);
DECLARE_MSM_GPIO_PINS(3);
DECLARE_MSM_GPIO_PINS(4);
DECLARE_MSM_GPIO_PINS(5);
DECLARE_MSM_GPIO_PINS(6);
DECLARE_MSM_GPIO_PINS(7);
DECLARE_MSM_GPIO_PINS(8);
DECLARE_MSM_GPIO_PINS(9);
DECLARE_MSM_GPIO_PINS(10);
DECLARE_MSM_GPIO_PINS(11);
DECLARE_MSM_GPIO_PINS(12);
DECLARE_MSM_GPIO_PINS(13);
DECLARE_MSM_GPIO_PINS(14);
DECLARE_MSM_GPIO_PINS(15);
DECLARE_MSM_GPIO_PINS(16);
DECLARE_MSM_GPIO_PINS(17);
DECLARE_MSM_GPIO_PINS(18);
DECLARE_MSM_GPIO_PINS(19);
DECLARE_MSM_GPIO_PINS(20);
DECLARE_MSM_GPIO_PINS(21);
DECLARE_MSM_GPIO_PINS(22);
DECLARE_MSM_GPIO_PINS(23);
DECLARE_MSM_GPIO_PINS(24);
DECLARE_MSM_GPIO_PINS(25);
DECLARE_MSM_GPIO_PINS(26);
DECLARE_MSM_GPIO_PINS(27);
DECLARE_MSM_GPIO_PINS(28);
DECLARE_MSM_GPIO_PINS(29);
DECLARE_MSM_GPIO_PINS(30);
DECLARE_MSM_GPIO_PINS(31);
DECLARE_MSM_GPIO_PINS(32);
DECLARE_MSM_GPIO_PINS(33);
DECLARE_MSM_GPIO_PINS(34);
DECLARE_MSM_GPIO_PINS(35);
DECLARE_MSM_GPIO_PINS(36);
DECLARE_MSM_GPIO_PINS(37);
DECLARE_MSM_GPIO_PINS(38);
DECLARE_MSM_GPIO_PINS(39);
DECLARE_MSM_GPIO_PINS(40);
DECLARE_MSM_GPIO_PINS(41);
DECLARE_MSM_GPIO_PINS(42);
DECLARE_MSM_GPIO_PINS(43);
DECLARE_MSM_GPIO_PINS(44);
DECLARE_MSM_GPIO_PINS(45);
DECLARE_MSM_GPIO_PINS(46);
DECLARE_MSM_GPIO_PINS(47);
DECLARE_MSM_GPIO_PINS(48);
DECLARE_MSM_GPIO_PINS(49);
DECLARE_MSM_GPIO_PINS(50);
DECLARE_MSM_GPIO_PINS(51);
DECLARE_MSM_GPIO_PINS(52);
DECLARE_MSM_GPIO_PINS(53);
DECLARE_MSM_GPIO_PINS(54);
DECLARE_MSM_GPIO_PINS(55);
DECLARE_MSM_GPIO_PINS(56);
DECLARE_MSM_GPIO_PINS(57);
DECLARE_MSM_GPIO_PINS(58);
DECLARE_MSM_GPIO_PINS(59);
DECLARE_MSM_GPIO_PINS(60);
DECLARE_MSM_GPIO_PINS(61);
DECLARE_MSM_GPIO_PINS(62);
DECLARE_MSM_GPIO_PINS(63);
DECLARE_MSM_GPIO_PINS(64);
DECLARE_MSM_GPIO_PINS(65);
DECLARE_MSM_GPIO_PINS(66);
DECLARE_MSM_GPIO_PINS(67);
DECLARE_MSM_GPIO_PINS(68);
DECLARE_MSM_GPIO_PINS(69);
DECLARE_MSM_GPIO_PINS(70);
DECLARE_MSM_GPIO_PINS(71);
DECLARE_MSM_GPIO_PINS(72);
DECLARE_MSM_GPIO_PINS(73);
DECLARE_MSM_GPIO_PINS(74);
DECLARE_MSM_GPIO_PINS(75);
DECLARE_MSM_GPIO_PINS(76);
DECLARE_MSM_GPIO_PINS(77);
DECLARE_MSM_GPIO_PINS(78);
DECLARE_MSM_GPIO_PINS(79);
DECLARE_MSM_GPIO_PINS(80);
DECLARE_MSM_GPIO_PINS(81);
DECLARE_MSM_GPIO_PINS(82);
DECLARE_MSM_GPIO_PINS(83);
DECLARE_MSM_GPIO_PINS(84);
DECLARE_MSM_GPIO_PINS(85);
DECLARE_MSM_GPIO_PINS(86);
DECLARE_MSM_GPIO_PINS(87);
DECLARE_MSM_GPIO_PINS(88);
DECLARE_MSM_GPIO_PINS(89);
DECLARE_MSM_GPIO_PINS(90);
DECLARE_MSM_GPIO_PINS(91);
DECLARE_MSM_GPIO_PINS(92);
DECLARE_MSM_GPIO_PINS(93);
DECLARE_MSM_GPIO_PINS(94);
DECLARE_MSM_GPIO_PINS(95);
DECLARE_MSM_GPIO_PINS(96);
DECLARE_MSM_GPIO_PINS(97);
DECLARE_MSM_GPIO_PINS(98);
DECLARE_MSM_GPIO_PINS(99);
DECLARE_MSM_GPIO_PINS(100);
DECLARE_MSM_GPIO_PINS(101);
DECLARE_MSM_GPIO_PINS(102);
DECLARE_MSM_GPIO_PINS(103);
DECLARE_MSM_GPIO_PINS(104);
DECLARE_MSM_GPIO_PINS(105);
DECLARE_MSM_GPIO_PINS(106);
DECLARE_MSM_GPIO_PINS(107);
DECLARE_MSM_GPIO_PINS(108);
DECLARE_MSM_GPIO_PINS(109);
enum kuno_functions {
msm_mux_gpio,
msm_mux_audio_ref_clk,
msm_mux_coex_uart,
msm_mux_ebi2_lcd_a,
msm_mux_ebi2_lcd_cs,
msm_mux_ebi2_lcd_reset,
msm_mux_ebi2_lcd_te,
msm_mux_emac_mdc,
msm_mux_emac_mdio,
msm_mux_emac_pps_in,
msm_mux_emac_ptp_aux,
msm_mux_emac_ptp_pps,
msm_mux_gcc_gp1_clk,
msm_mux_gcc_gp2_clk,
msm_mux_gcc_gp3_clk,
msm_mux_mi2s0_data0,
msm_mux_mi2s0_data1,
msm_mux_mi2s0_sck,
msm_mux_mi2s0_ws,
msm_mux_mi2s1_data0,
msm_mux_mi2s1_data1,
msm_mux_mi2s1_sck,
msm_mux_mi2s1_ws,
msm_mux_mi2s_mclk,
msm_mux_nav_gpio,
msm_mux_pci_e_rst,
msm_mux_pcie_clkreq_n,
msm_mux_pll_bist_sync,
msm_mux_pll_clk_aux,
msm_mux_qdss_cti_trig0,
msm_mux_qdss_cti_trig1,
msm_mux_qdss_cti_trig1_mire,
msm_mux_qdss_gpio_traceclk,
msm_mux_qdss_gpio_tracectl,
msm_mux_qup0_se0,
msm_mux_qup0_se1,
msm_mux_qup0_se2,
msm_mux_qup0_se3_mira,
msm_mux_qup0_se3_mirb,
msm_mux_qup0_se4,
msm_mux_sdc4_clk,
msm_mux_sdc4_cmd,
msm_mux_sdc4_data,
msm_mux_sdc4_tb_trig,
msm_mux_sgmii_phy_intr,
msm_mux_spmi_coex_clk,
msm_mux_spmi_coex_data,
msm_mux_spmi_vgi_hwevent,
msm_mux_uim1_clk,
msm_mux_uim1_data,
msm_mux_uim1_present,
msm_mux_uim1_reset,
msm_mux_usb2phy_ac_en,
msm_mux__,
};
static const char * const gpio_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
"gpio105", "gpio106", "gpio107", "gpio108", "gpio109",
};
static const char * const audio_ref_clk_groups[] = {
"gpio62",
};
static const char * const coex_uart_groups[] = {
"gpio44", "gpio45",
};
static const char * const ebi2_lcd_a_groups[] = {
"gpio93",
};
static const char * const ebi2_lcd_cs_groups[] = {
"gpio94",
};
static const char * const ebi2_lcd_reset_groups[] = {
"gpio89",
};
static const char * const ebi2_lcd_te_groups[] = {
"gpio88",
};
static const char * const emac_mdc_groups[] = {
"gpio98",
};
static const char * const emac_mdio_groups[] = {
"gpio99",
};
static const char * const emac_pps_in_groups[] = {
"gpio88",
};
static const char * const emac_ptp_aux_groups[] = {
"gpio93", "gpio94",
};
static const char * const emac_ptp_pps_groups[] = {
"gpio93", "gpio94",
};
static const char * const gcc_gp1_clk_groups[] = {
"gpio34",
};
static const char * const gcc_gp2_clk_groups[] = {
"gpio46",
};
static const char * const gcc_gp3_clk_groups[] = {
"gpio35",
};
static const char * const mi2s0_data0_groups[] = {
"gpio13",
};
static const char * const mi2s0_data1_groups[] = {
"gpio14",
};
static const char * const mi2s0_sck_groups[] = {
"gpio15",
};
static const char * const mi2s0_ws_groups[] = {
"gpio12",
};
static const char * const mi2s1_data0_groups[] = {
"gpio17",
};
static const char * const mi2s1_data1_groups[] = {
"gpio18",
};
static const char * const mi2s1_sck_groups[] = {
"gpio19",
};
static const char * const mi2s1_ws_groups[] = {
"gpio16",
};
static const char * const mi2s_mclk_groups[] = {
"gpio62",
};
static const char * const nav_gpio_groups[] = {
"gpio31", "gpio32", "gpio33",
};
static const char * const pci_e_rst_groups[] = {
"gpio57",
};
static const char * const pcie_clkreq_n_groups[] = {
"gpio56",
};
static const char * const pll_bist_sync_groups[] = {
"gpio47",
};
static const char * const pll_clk_aux_groups[] = {
"gpio54",
};
static const char * const qdss_cti_trig0_groups[] = {
"gpio16", "gpio17", "gpio54", "gpio55", "gpio60", "gpio84", "gpio101",
"gpio102",
};
static const char * const qdss_cti_trig1_groups[] = {
"gpio16", "gpio17", "gpio54", "gpio55", "gpio65", "gpio66", "gpio101",
"gpio102",
};
static const char * const qdss_cti_trig1_mire_groups[] = {
"gpio65", "gpio66",
};
static const char * const qdss_gpio_traceclk_groups[] = {
"gpio8",
};
static const char * const qdss_gpio_tracectl_groups[] = {
"gpio9",
};
static const char * const qup0_se0_groups[] = {
"gpio14", "gpio18", "gpio19", "gpio48", "gpio49", "gpio92", "gpio101",
};
static const char * const qup0_se1_groups[] = {
"gpio14", "gpio63", "gpio64", "gpio65", "gpio66", "gpio92", "gpio101",
};
static const char * const qup0_se2_groups[] = {
"gpio4", "gpio5", "gpio6", "gpio7", "gpio14", "gpio92", "gpio101",
};
static const char * const qup0_se3_mira_groups[] = {
"gpio8", "gpio9", "gpio14", "gpio16", "gpio17", "gpio92", "gpio101",
};
static const char * const qup0_se3_mirb_groups[] = {
"gpio12", "gpio13", "gpio14", "gpio15",
};
static const char * const qup0_se4_groups[] = {
"gpio10", "gpio11", "gpio14", "gpio80", "gpio81", "gpio92", "gpio101",
};
static const char * const sdc4_clk_groups[] = {
"gpio103",
};
static const char * const sdc4_cmd_groups[] = {
"gpio102",
};
static const char * const sdc4_data_groups[] = {
"gpio104", "gpio105", "gpio106", "gpio107",
};
static const char * const sdc4_tb_trig_groups[] = {
"gpio101",
};
static const char * const sgmii_phy_intr_groups[] = {
"gpio91",
};
static const char * const spmi_coex_clk_groups[] = {
"gpio76",
};
static const char * const spmi_coex_data_groups[] = {
"gpio75",
};
static const char * const spmi_vgi_hwevent_groups[] = {
"gpio78", "gpio79",
};
static const char * const uim1_clk_groups[] = {
"gpio3",
};
static const char * const uim1_data_groups[] = {
"gpio0",
};
static const char * const uim1_present_groups[] = {
"gpio1",
};
static const char * const uim1_reset_groups[] = {
"gpio2",
};
static const char * const usb2phy_ac_en_groups[] = {
"gpio90",
};
static const struct pinfunction kuno_functions[] = {
MSM_GPIO_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(audio_ref_clk),
MSM_PIN_FUNCTION(coex_uart),
MSM_PIN_FUNCTION(ebi2_lcd_a),
MSM_PIN_FUNCTION(ebi2_lcd_cs),
MSM_PIN_FUNCTION(ebi2_lcd_reset),
MSM_PIN_FUNCTION(ebi2_lcd_te),
MSM_PIN_FUNCTION(emac_mdc),
MSM_PIN_FUNCTION(emac_mdio),
MSM_PIN_FUNCTION(emac_pps_in),
MSM_PIN_FUNCTION(emac_ptp_aux),
MSM_PIN_FUNCTION(emac_ptp_pps),
MSM_PIN_FUNCTION(gcc_gp1_clk),
MSM_PIN_FUNCTION(gcc_gp2_clk),
MSM_PIN_FUNCTION(gcc_gp3_clk),
MSM_PIN_FUNCTION(mi2s0_data0),
MSM_PIN_FUNCTION(mi2s0_data1),
MSM_PIN_FUNCTION(mi2s0_sck),
MSM_PIN_FUNCTION(mi2s0_ws),
MSM_PIN_FUNCTION(mi2s1_data0),
MSM_PIN_FUNCTION(mi2s1_data1),
MSM_PIN_FUNCTION(mi2s1_sck),
MSM_PIN_FUNCTION(mi2s1_ws),
MSM_PIN_FUNCTION(mi2s_mclk),
MSM_PIN_FUNCTION(nav_gpio),
MSM_PIN_FUNCTION(pci_e_rst),
MSM_PIN_FUNCTION(pcie_clkreq_n),
MSM_PIN_FUNCTION(pll_bist_sync),
MSM_PIN_FUNCTION(pll_clk_aux),
MSM_PIN_FUNCTION(qdss_cti_trig0),
MSM_PIN_FUNCTION(qdss_cti_trig1),
MSM_PIN_FUNCTION(qdss_cti_trig1_mire),
MSM_PIN_FUNCTION(qdss_gpio_traceclk),
MSM_PIN_FUNCTION(qdss_gpio_tracectl),
MSM_PIN_FUNCTION(qup0_se0),
MSM_PIN_FUNCTION(qup0_se1),
MSM_PIN_FUNCTION(qup0_se2),
MSM_PIN_FUNCTION(qup0_se3_mira),
MSM_PIN_FUNCTION(qup0_se3_mirb),
MSM_PIN_FUNCTION(qup0_se4),
MSM_PIN_FUNCTION(sdc4_clk),
MSM_PIN_FUNCTION(sdc4_cmd),
MSM_PIN_FUNCTION(sdc4_data),
MSM_PIN_FUNCTION(sdc4_tb_trig),
MSM_PIN_FUNCTION(sgmii_phy_intr),
MSM_PIN_FUNCTION(spmi_coex_clk),
MSM_PIN_FUNCTION(spmi_coex_data),
MSM_PIN_FUNCTION(spmi_vgi_hwevent),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(usb2phy_ac_en),
};
/* Every pin is maintained as a single group, and missing or non-existing pin
* would be maintained as dummy group to synchronize pin group index with
* pin descriptor registered with pinctrl core.
* Clients would not be able to request these dummy pin groups.
*/
static const struct msm_pingroup kuno_groups[] = {
[0] = PINGROUP(0, uim1_data, _, _, _, _, _, _, _, _),
[1] = PINGROUP(1, uim1_present, _, _, _, _, _, _, _, _),
[2] = PINGROUP(2, uim1_reset, _, _, _, _, _, _, _, _),
[3] = PINGROUP(3, uim1_clk, _, _, _, _, _, _, _, _),
[4] = PINGROUP(4, qup0_se2, _, _, _, _, _, _, _, _),
[5] = PINGROUP(5, qup0_se2, _, _, _, _, _, _, _, _),
[6] = PINGROUP(6, qup0_se2, _, _, _, _, _, _, _, _),
[7] = PINGROUP(7, qup0_se2, _, _, _, _, _, _, _, _),
[8] = PINGROUP(8, qup0_se3_mira, _, qdss_gpio_traceclk, _, _, _, _, _, _),
[9] = PINGROUP(9, qup0_se3_mira, _, qdss_gpio_tracectl, _, _, _, _, _, _),
[10] = PINGROUP(10, qup0_se4, _, _, _, _, _, _, _, _),
[11] = PINGROUP(11, qup0_se4, _, _, _, _, _, _, _, _),
[12] = PINGROUP(12, mi2s0_ws, qup0_se3_mirb, _, _, _, _, _, _, _),
[13] = PINGROUP(13, mi2s0_data0, qup0_se3_mirb, _, _, _, _, _, _, _),
[14] = PINGROUP(14, mi2s0_data1, qup0_se3_mirb, qup0_se0, qup0_se1, qup0_se2,
qup0_se3_mira, qup0_se4, _, _),
[15] = PINGROUP(15, mi2s0_sck, qup0_se3_mirb, _, _, _, _, _, _, _),
[16] = PINGROUP(16, mi2s1_ws, qup0_se3_mira, qdss_cti_trig1, qdss_cti_trig0,
_, _, _, _, _),
[17] = PINGROUP(17, mi2s1_data0, qup0_se3_mira, qdss_cti_trig1, qdss_cti_trig0,
_, _, _, _, _),
[18] = PINGROUP(18, mi2s1_data1, qup0_se0, _, _, _, _, _, _, _),
[19] = PINGROUP(19, mi2s1_sck, qup0_se0, _, _, _, _, _, _, _),
[20] = PINGROUP(20, _, _, _, _, _, _, _, _, _),
[21] = PINGROUP(21, _, _, _, _, _, _, _, _, _),
[22] = PINGROUP(22, _, _, _, _, _, _, _, _, _),
[23] = PINGROUP(23, _, _, _, _, _, _, _, _, _),
[24] = PINGROUP(24, _, _, _, _, _, _, _, _, _),
[25] = PINGROUP(25, _, _, _, _, _, _, _, _, _),
[26] = PINGROUP(26, _, _, _, _, _, _, _, _, _),
[27] = PINGROUP(27, _, _, _, _, _, _, _, _, _),
[28] = PINGROUP(28, _, _, _, _, _, _, _, _, _),
[29] = PINGROUP(29, _, _, _, _, _, _, _, _, _),
[30] = PINGROUP(30, _, _, _, _, _, _, _, _, _),
[31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _),
[32] = PINGROUP(32, nav_gpio, _, _, _, _, _, _, _, _),
[33] = PINGROUP(33, nav_gpio, _, _, _, _, _, _, _, _),
[34] = PINGROUP(34, _, gcc_gp1_clk, _, _, _, _, _, _, _),
[35] = PINGROUP(35, _, _, gcc_gp3_clk, _, _, _, _, _, _),
[36] = PINGROUP(36, _, _, _, _, _, _, _, _, _),
[37] = PINGROUP(37, _, _, _, _, _, _, _, _, _),
[38] = PINGROUP(38, _, _, _, _, _, _, _, _, _),
[39] = PINGROUP(39, _, _, _, _, _, _, _, _, _),
[40] = PINGROUP(40, _, _, _, _, _, _, _, _, _),
[41] = PINGROUP(41, _, _, _, _, _, _, _, _, _),
[42] = PINGROUP(42, _, _, _, _, _, _, _, _, _),
[43] = PINGROUP(43, _, _, _, _, _, _, _, _, _),
[44] = PINGROUP(44, coex_uart, _, _, _, _, _, _, _, _),
[45] = PINGROUP(45, coex_uart, _, _, _, _, _, _, _, _),
[46] = PINGROUP(46, _, _, _, gcc_gp2_clk, _, _, _, _, _),
[47] = PINGROUP(47, _, pll_bist_sync, _, _, _, _, _, _, _),
[48] = PINGROUP(48, qup0_se0, _, _, _, _, _, _, _, _),
[49] = PINGROUP(49, qup0_se0, _, _, _, _, _, _, _, _),
[50] = PINGROUP(50, _, _, _, _, _, _, _, _, _),
[51] = PINGROUP(51, _, _, _, _, _, _, _, _, _),
[52] = PINGROUP(52, _, _, _, _, _, _, _, _, _),
[53] = PINGROUP(53, _, _, _, _, _, _, _, _, _),
[54] = PINGROUP(54, qdss_cti_trig1, qdss_cti_trig0, pll_clk_aux, _, _, _, _, _, _),
[55] = PINGROUP(55, qdss_cti_trig1, qdss_cti_trig0, _, _, _, _, _, _, _),
[56] = PINGROUP(56, pcie_clkreq_n, _, _, _, _, _, _, _, _),
[57] = PINGROUP(57, pci_e_rst, _, _, _, _, _, _, _, _),
[58] = PINGROUP(58, _, _, _, _, _, _, _, _, _),
[59] = PINGROUP(59, _, _, _, _, _, _, _, _, _),
[60] = PINGROUP(60, qdss_cti_trig0, _, _, _, _, _, _, _, _),
[61] = PINGROUP(61, _, _, _, _, _, _, _, _, _),
[62] = PINGROUP(62, mi2s_mclk, audio_ref_clk, _, _, _, _, _, _, _),
[63] = PINGROUP(63, qup0_se1, _, _, _, _, _, _, _, _),
[64] = PINGROUP(64, qup0_se1, _, _, _, _, _, _, _, _),
[65] = PINGROUP(65, qup0_se1, qdss_cti_trig1, qdss_cti_trig1_mire, _, _, _, _, _, _),
[66] = PINGROUP(66, qup0_se1, qdss_cti_trig1, qdss_cti_trig1_mire, _, _, _, _, _, _),
[67] = PINGROUP(67, _, _, _, _, _, _, _, _, _),
[68] = PINGROUP(68, _, _, _, _, _, _, _, _, _),
[69] = PINGROUP(69, _, _, _, _, _, _, _, _, _),
[70] = PINGROUP(70, _, _, _, _, _, _, _, _, _),
[71] = PINGROUP(71, _, _, _, _, _, _, _, _, _),
[72] = PINGROUP(72, _, _, _, _, _, _, _, _, _),
[73] = PINGROUP(73, _, _, _, _, _, _, _, _, _),
[74] = PINGROUP(74, _, _, _, _, _, _, _, _, _),
[75] = PINGROUP(75, spmi_coex_data, _, _, _, _, _, _, _, _),
[76] = PINGROUP(76, spmi_coex_clk, _, _, _, _, _, _, _, _),
[77] = PINGROUP(77, _, _, _, _, _, _, _, _, _),
[78] = PINGROUP(78, spmi_vgi_hwevent, _, _, _, _, _, _, _, _),
[79] = PINGROUP(79, spmi_vgi_hwevent, _, _, _, _, _, _, _, _),
[80] = PINGROUP(80, qup0_se4, _, _, _, _, _, _, _, _),
[81] = PINGROUP(81, qup0_se4, _, _, _, _, _, _, _, _),
[82] = PINGROUP(82, _, _, _, _, _, _, _, _, _),
[83] = PINGROUP(83, _, _, _, _, _, _, _, _, _),
[84] = PINGROUP(84, qdss_cti_trig0, _, _, _, _, _, _, _, _),
[85] = PINGROUP(85, _, _, _, _, _, _, _, _, _),
[86] = PINGROUP(86, _, _, _, _, _, _, _, _, _),
[87] = PINGROUP(87, _, _, _, _, _, _, _, _, _),
[88] = PINGROUP(88, ebi2_lcd_te, emac_pps_in, _, _, _, _, _, _, _),
[89] = PINGROUP(89, ebi2_lcd_reset, _, _, _, _, _, _, _, _),
[90] = PINGROUP(90, usb2phy_ac_en, _, _, _, _, _, _, _, _),
[91] = PINGROUP(91, sgmii_phy_intr, _, _, _, _, _, _, _, _),
[92] = PINGROUP(92, qup0_se0, qup0_se1, qup0_se2, qup0_se3_mira, qup0_se4, _, _, _, _),
[93] = PINGROUP(93, ebi2_lcd_a, emac_ptp_pps, emac_ptp_aux, _, _, _, _, _, _),
[94] = PINGROUP(94, ebi2_lcd_cs, emac_ptp_pps, emac_ptp_aux, _, _, _, _, _, _),
[95] = PINGROUP(95, _, _, _, _, _, _, _, _, _),
[96] = PINGROUP(96, _, _, _, _, _, _, _, _, _),
[97] = PINGROUP(97, _, _, _, _, _, _, _, _, _),
[98] = PINGROUP(98, emac_mdc, _, _, _, _, _, _, _, _),
[99] = PINGROUP(99, emac_mdio, _, _, _, _, _, _, _, _),
[100] = PINGROUP(100, _, _, _, _, _, _, _, _, _),
[101] = PINGROUP(101, sdc4_tb_trig, qdss_cti_trig1, qdss_cti_trig0, qup0_se0,
qup0_se1, qup0_se2, qup0_se3_mira, qup0_se4, _),
[102] = PINGROUP(102, sdc4_cmd, qdss_cti_trig1, qdss_cti_trig0, _, _, _, _, _, _),
[103] = PINGROUP(103, sdc4_clk, _, _, _, _, _, _, _, _),
[104] = PINGROUP(104, sdc4_data, _, _, _, _, _, _, _, _),
[105] = PINGROUP(105, sdc4_data, _, _, _, _, _, _, _, _),
[106] = PINGROUP(106, sdc4_data, _, _, _, _, _, _, _, _),
[107] = PINGROUP(107, sdc4_data, _, _, _, _, _, _, _, _),
[108] = PINGROUP(108, _, _, _, _, _, _, _, _, _),
[109] = PINGROUP(109, _, _, _, _, _, _, _, _, _),
};
static const struct msm_gpio_wakeirq_map kuno_pdc_map[] = {
{ 1, 62 }, { 2, 83 }, { 4, 59 }, { 5, 107 }, { 6, 112 }, { 7, 119 },
{ 8, 123 }, { 10, 52 }, { 11, 73 }, { 12, 74 }, { 13, 75 }, { 14, 76 },
{ 15, 77 }, { 16, 81 }, { 17, 82 }, { 18, 80 }, { 19, 100 }, { 21, 88 },
{ 22, 99 }, { 23, 84 }, { 24, 85 }, { 25, 97 }, { 26, 86 }, { 27, 102 },
{ 28, 87 }, { 35, 103 }, { 43, 90 }, { 44, 60 }, { 45, 61 }, { 46, 104 },
{ 47, 89 }, { 48, 105 }, { 49, 106 }, { 50, 101 }, { 52, 109 }, { 53, 79 },
{ 54, 110 }, { 55, 111 }, { 56, 78 }, { 57, 71 }, { 60, 113 }, { 61, 114 },
{ 63, 115 }, { 64, 116 }, { 65, 57 }, { 66, 117 }, { 68, 64 }, { 69, 118 },
{ 71, 108 }, { 73, 120 }, { 74, 121 }, { 76, 47 }, { 77, 122 }, { 78, 65 },
{ 79, 66 }, { 80, 124 }, { 81, 125 }, { 82, 126 }, { 83, 127 }, { 84, 93 },
{ 85, 128 }, { 86, 129 }, { 87, 70 }, { 88, 130 }, { 96, 68 }, { 98, 50 },
{ 99, 67 }, { 100, 51 }, { 101, 53 }, { 102, 54 }, { 103, 98 }, { 104, 91 },
{ 105, 69 }, { 106, 55 }, { 107, 56 }, { 109, 72 },
};
static const struct msm_pinctrl_soc_data kuno_tlmm = {
.pins = kuno_pins,
.npins = ARRAY_SIZE(kuno_pins),
.functions = kuno_functions,
.nfunctions = ARRAY_SIZE(kuno_functions),
.groups = kuno_groups,
.ngroups = ARRAY_SIZE(kuno_groups),
.ngpios = 110,
.wakeirq_map = kuno_pdc_map,
.nwakeirq_map = ARRAY_SIZE(kuno_pdc_map),
};
static int kuno_tlmm_probe(struct platform_device *pdev)
{
return msm_pinctrl_probe(pdev, &kuno_tlmm);
}
static const struct of_device_id kuno_tlmm_of_match[] = {
{ .compatible = "qcom,kuno-tlmm", },
{ },
};
MODULE_DEVICE_TABLE(of, kuno_tlmm_of_match);
static struct platform_driver kuno_tlmm_driver = {
.driver = {
.name = "kuno-tlmm",
.of_match_table = kuno_tlmm_of_match,
},
.probe = kuno_tlmm_probe,
};
static int __init kuno_tlmm_init(void)
{
return platform_driver_register(&kuno_tlmm_driver);
}
arch_initcall(kuno_tlmm_init);
static void __exit kuno_tlmm_exit(void)
{
platform_driver_unregister(&kuno_tlmm_driver);
}
module_exit(kuno_tlmm_exit);
MODULE_DESCRIPTION("QTI Kuno TLMM driver");
MODULE_LICENSE("GPL");

6
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
View File

@ -421,6 +421,7 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s,
struct pinctrl_pin_desc pindesc;
unsigned int func;
int is_out;
int value;
int drive;
int pull;
u32 ctl_reg;
@ -443,7 +444,10 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s,
drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg);
pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func);
value = lpi_gpio_get(chip, offset);
seq_printf(s, " %-8s: %-3s", pindesc.name, is_out ? "out" : "in");
seq_printf(s, " %-4s func%d", str_high_low(value), func);
seq_printf(s, " %dmA", lpi_regval_to_drive(drive));
seq_printf(s, " %s", pulls[pull]);
}

17
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
View File

@ -92,6 +92,23 @@ struct pinctrl_pin_desc;
.pin_offset = 0, \
}
#define LPI_PINGROUP6(id, soff, f1, f2, f3, f4, f5) \
{ \
.pin = id, \
.slew_offset = soff, \
.slew_base_spare_1 = false, \
.funcs = (int[]){ \
LPI_MUX_gpio, \
LPI_MUX_##f1, \
LPI_MUX_##f2, \
LPI_MUX_##f3, \
LPI_MUX_##f4, \
LPI_MUX_##f5, \
}, \
.nfuncs = 6, \
.pin_offset = 0, \
}
/*
* Slew rate control is done in the same register as rest of the
* pin configuration.

25
drivers/pinctrl/qcom/pinctrl-msm.h
View File

@ -14,21 +14,6 @@ struct platform_device;
struct pinctrl_pin_desc;
#define APQ_PIN_FUNCTION(fname) \
[APQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \
fname##_groups, \
ARRAY_SIZE(fname##_groups))
#define IPQ_PIN_FUNCTION(fname) \
[IPQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \
fname##_groups, \
ARRAY_SIZE(fname##_groups))
#define IPQ_GPIO_PIN_FUNCTION(fname) \
[IPQ_MUX_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \
fname##_groups, \
ARRAY_SIZE(fname##_groups))
#define MSM_PIN_FUNCTION(fname) \
[msm_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \
fname##_groups, \
@ -39,16 +24,6 @@ struct pinctrl_pin_desc;
fname##_groups, \
ARRAY_SIZE(fname##_groups))
#define QCA_PIN_FUNCTION(fname) \
[qca_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \
fname##_groups, \
ARRAY_SIZE(fname##_groups))
#define QCA_GPIO_PIN_FUNCTION(fname) \
[qca_mux_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \
fname##_groups, \
ARRAY_SIZE(fname##_groups))
/**
* struct msm_pingroup - Qualcomm pingroup definition
* @grp: Generic data of the pin group (name and pins)

1257
drivers/pinctrl/qcom/pinctrl-msm8952.c Normal file
View File

File diff suppressed because it is too large Load Diff

1
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View File

@ -1280,6 +1280,7 @@ static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
{ .compatible = "qcom,pmau0102-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pmc8380-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pmcx0102-gpio", .data = (void *)14 },
{ .compatible = "qcom,pmd8028-gpio", .data = (void *) 4 },

2
drivers/pinctrl/qcom/tlmm-test.c
View File

@ -587,7 +587,7 @@ static int tlmm_reg_base(struct device_node *tlmm, struct resource *res)
return count;
}
reg_names = kcalloc(count, sizeof(char *), GFP_KERNEL);
reg_names = kcalloc(count, sizeof(*reg_names), GFP_KERNEL);
if (!reg_names)
return -ENOMEM;

412
drivers/pinctrl/renesas/pinctrl-rzg2l.c
View File

@ -69,6 +69,8 @@
#define PIN_CFG_PVDD1833_OTH_AWO_POC BIT(19) /* known on RZ/G3L only */
#define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */
#define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */
#define PIN_CFG_IO_VMC_SD2 BIT(22) /* known on RZ/G3L only */
#define PIN_CFG_IO_VMC_I3C BIT(23)
#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */
#define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */
@ -180,12 +182,8 @@
#define SMT(off) (0x3400 + (off) * 8)
#define SD_CH(off, ch) ((off) + (ch) * 4)
#define ETH_POC(off, ch) ((off) + (ch) * 4)
#define QSPI (0x3008) /* known on RZ/{G2L,G2LC,G2UL,Five} only */
#define OTHER_POC (0x3028) /* known on RZ/G3L only */
#define PVDD_2500 2 /* I/O domain voltage 2.5V */
#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
#define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
#define PVDD_MASK 0x3
#define PWPR_B0WI BIT(7) /* Bit Write Disable */
#define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
@ -254,28 +252,57 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = {
* struct rzg2l_register_offsets - specific register offsets
* @pwpr: PWPR register offset
* @sd_ch: SD_CH register offset
* @sd_ch2: SD_CH2_POC register offset
* @eth_poc: ETH_POC register offset
* @oen: OEN register offset
* @qspi: QSPI register offset
* @other_poc: OTHER_POC register offset
* @i3c_set: I3C_SET register offset
*/
struct rzg2l_register_offsets {
u16 pwpr;
u16 sd_ch;
u16 sd_ch2;
u16 eth_poc;
u16 oen;
u16 qspi;
u16 other_poc;
u16 i3c_set;
};
/**
* struct rzg2l_register_masks - Masks for different RZ/G2L pinctrl functionalities
* @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask
* @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask
* @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask
* @i3c_set_poc: I3C_SET_POC mask
*/
struct rzg2l_register_masks {
union {
/* RZ/G3L masks */
struct {
u8 other_poc_pvdd1833_oth_awo_poc;
u8 other_poc_pvdd1833_oth_iso_poc;
u8 other_poc_wdtovf_n_poc;
};
/* RZ/G3S masks */
struct {
u8 i3c_set_poc;
};
};
};
/**
* enum rzg2l_iolh_index - starting indices in IOLH specific arrays
* @RZG2L_IOLH_IDX_NA: index N/A (to be used for error checking)
* @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source
* @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source
* @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source
* @RZG2L_IOLH_IDX_MAX: maximum index
*/
enum rzg2l_iolh_index {
RZG2L_IOLH_IDX_NA = -1,
RZG2L_IOLH_IDX_1V8 = 0,
RZG2L_IOLH_IDX_2V5 = 4,
RZG2L_IOLH_IDX_3V3 = 8,
@ -288,6 +315,8 @@ enum rzg2l_iolh_index {
/**
* struct rzg2l_hwcfg - hardware configuration data structure
* @regs: hardware specific register offsets
* @masks: hardware specific masks for various functionalities available in
* the registers described by regs
* @iolh_groupa_ua: IOLH group A uA specific values
* @iolh_groupb_ua: IOLH group B uA specific values
* @iolh_groupc_ua: IOLH group C uA specific values
@ -301,6 +330,7 @@ enum rzg2l_iolh_index {
*/
struct rzg2l_hwcfg {
const struct rzg2l_register_offsets regs;
const struct rzg2l_register_masks masks;
u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX];
u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX];
u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX];
@ -368,10 +398,12 @@ struct rzg2l_pinctrl_pin_settings {
* @nod: NOD registers cache
* @clone: Clone register cache
* @sd_ch: SD_CH registers cache
* @sd_ch2: SD_CH2_POC registers cache
* @eth_poc: ET_POC registers cache
* @oen: Output Enable register cache
* @other_poc: OTHER_POC register cache
* @qspi: QSPI registers cache
* @i3c_set: I3C_SET register cache
*/
struct rzg2l_pinctrl_reg_cache {
u8 *p;
@ -386,10 +418,12 @@ struct rzg2l_pinctrl_reg_cache {
u32 *nod[2];
u32 clone;
u8 sd_ch[2];
u8 sd_ch2;
u8 eth_poc[2];
u8 oen;
u8 other_poc;
u8 qspi;
u8 i3c_set;
};
struct rzg2l_pinctrl {
@ -421,7 +455,89 @@ struct rzg2l_pinctrl {
u32 clone_offset;
};
static const u16 available_ps[] = { 1800, 2500, 3300 };
/**
* struct rzg2l_pinctrl_ps_desc - RZ/G2L power source descriptor
* @caps: Capabilities that applies to the power source
* @iolh_index: IOLH index
* @ps: Power source value
* @pwr_reg_val: Power source register value
*/
struct rzg2l_pinctrl_ps_desc {
u32 caps;
enum rzg2l_iolh_index iolh_index;
u16 ps;
u16 pwr_reg_val;
};
#define RZG2L_PINCTRL_PS_DESC(_ps, _pwr_reg_val, _caps, _iolh_index) \
{ \
.ps = _ps, \
.pwr_reg_val = _pwr_reg_val, \
.caps = _caps, \
.iolh_index = _iolh_index, \
}
static const struct rzg2l_pinctrl_ps_desc available_ps[] = {
/* Ethernet I/O voltage domains */
RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1,
RZG2L_IOLH_IDX_1V8),
RZG2L_PINCTRL_PS_DESC(2500, 2, PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1,
RZG2L_IOLH_IDX_2V5),
RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1,
RZG2L_IOLH_IDX_3V3),
/* SD I/O voltage domains */
RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_IO_VMC_SD0 | PIN_CFG_IO_VMC_SD1 |
PIN_CFG_IO_VMC_SD2, RZG2L_IOLH_IDX_1V8),
RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_IO_VMC_SD0 | PIN_CFG_IO_VMC_SD1 |
PIN_CFG_IO_VMC_SD2, RZG2L_IOLH_IDX_3V3),
/* QSPI I/O voltage domains */
RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_IO_VMC_QSPI, RZG2L_IOLH_IDX_1V8),
RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_IO_VMC_QSPI, RZG2L_IOLH_IDX_3V3),
/* AWO I/O voltage domains */
RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_PVDD1833_OTH_AWO_POC,
RZG2L_IOLH_IDX_1V8),
RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_PVDD1833_OTH_AWO_POC,
RZG2L_IOLH_IDX_3V3),
/* ISO I/O voltage domains */
RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_PVDD1833_OTH_ISO_POC,
RZG2L_IOLH_IDX_1V8),
RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_PVDD1833_OTH_ISO_POC,
RZG2L_IOLH_IDX_3V3),
/* WDTOVF I/O voltage domains */
RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_WDTOVF_N_POC, RZG2L_IOLH_IDX_1V8),
RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_WDTOVF_N_POC, RZG2L_IOLH_IDX_3V3),
/* I3C I/O voltage domains */
RZG2L_PINCTRL_PS_DESC(1200, 1, PIN_CFG_IO_VMC_I3C, RZG2L_IOLH_IDX_NA),
RZG2L_PINCTRL_PS_DESC(1800, 0, PIN_CFG_IO_VMC_I3C, RZG2L_IOLH_IDX_NA),
/* Software voltage domains */
RZG2L_PINCTRL_PS_DESC(1800, 0, PIN_CFG_SOFT_PS, RZG2L_IOLH_IDX_1V8),
RZG2L_PINCTRL_PS_DESC(2500, 0, PIN_CFG_SOFT_PS, RZG2L_IOLH_IDX_2V5),
RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_SOFT_PS, RZG2L_IOLH_IDX_3V3),
};
#define RZG2L_PINCTRL_PS_DESC_MEMBER_TO_DESC_FUNC(_name, _desc_member, _caps) \
static const struct rzg2l_pinctrl_ps_desc *_name(u16 _desc_member, u32 _caps) \
{ \
for (unsigned int i = 0; i < ARRAY_SIZE(available_ps); i++) { \
if (available_ps[i]._desc_member != _desc_member) \
continue; \
\
if (available_ps[i].caps & _caps) \
return &available_ps[i]; \
} \
\
return NULL; \
}
RZG2L_PINCTRL_PS_DESC_MEMBER_TO_DESC_FUNC(rzg2l_ps_to_desc, ps, caps)
RZG2L_PINCTRL_PS_DESC_MEMBER_TO_DESC_FUNC(rzg2l_pwr_reg_val_to_desc, pwr_reg_val, caps)
static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
u64 pincfg,
@ -474,20 +590,32 @@ static const u64 r9a08g046_variable_pin_cfg[] = {
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG3L_MPXED_PIN_FUNCS(B)),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG2L_MPXED_COMMON_PIN_FUNCS(B) |
PIN_CFG_IO_VMC_SD1),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG2L_MPXED_COMMON_PIN_FUNCS(B) |
PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG2L_MPXED_COMMON_PIN_FUNCS(B) |
PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | PIN_CFG_IEN |
PIN_CFG_IO_VMC_SD1),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG2L_MPXED_COMMON_PIN_FUNCS(B) |
PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG2L_MPXED_COMMON_PIN_FUNCS(B) |
PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 6, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 7, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG3L_MPXED_PIN_FUNCS(B)),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG2L_MPXED_COMMON_PIN_FUNCS(B) |
PIN_CFG_IO_VMC_SD2),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG2L_MPXED_COMMON_PIN_FUNCS(B) |
PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG2L_MPXED_COMMON_PIN_FUNCS(B) |
PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG2L_MPXED_COMMON_PIN_FUNCS(B) |
PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG2L_MPXED_COMMON_PIN_FUNCS(B) |
PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG2L_MPXED_COMMON_PIN_FUNCS(B) |
PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 0, RZG3L_MPXED_PIN_FUNCS(A) | PIN_CFG_IEN),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 1, RZG3L_MPXED_PIN_FUNCS(A)),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 2, RZG3L_MPXED_PIN_FUNCS(A)),
@ -1047,106 +1175,125 @@ static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
}
static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs,
u32 caps, u8 *mask)
const struct rzg2l_register_masks *masks,
u32 caps, u16 *offset, u8 *mask)
{
if (caps & PIN_CFG_IO_VMC_SD0)
return SD_CH(regs->sd_ch, 0);
if (caps & PIN_CFG_IO_VMC_SD1)
return SD_CH(regs->sd_ch, 1);
if (caps & PIN_CFG_IO_VMC_ETH0)
return ETH_POC(regs->eth_poc, 0);
if (caps & PIN_CFG_IO_VMC_ETH1)
return ETH_POC(regs->eth_poc, 1);
if (caps & PIN_CFG_IO_VMC_QSPI)
return QSPI;
if (caps & PIN_CFG_OTHER_POC_MASK) {
if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC)
*mask = BIT(0);
else if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC)
*mask = BIT(1);
else
*mask = BIT(2);
*mask = PVDD_MASK;
return OTHER_POC;
if (caps & PIN_CFG_IO_VMC_SD0) {
*offset = SD_CH(regs->sd_ch, 0);
return 0;
}
if (caps & PIN_CFG_IO_VMC_SD1) {
*offset = SD_CH(regs->sd_ch, 1);
return 0;
}
if (caps & PIN_CFG_IO_VMC_SD2) {
*offset = regs->sd_ch2;
return 0;
}
if (caps & PIN_CFG_IO_VMC_ETH0) {
*offset = ETH_POC(regs->eth_poc, 0);
return 0;
}
if (caps & PIN_CFG_IO_VMC_ETH1) {
*offset = ETH_POC(regs->eth_poc, 1);
return 0;
}
if (caps & PIN_CFG_IO_VMC_QSPI) {
*offset = regs->qspi;
return 0;
}
if (caps & PIN_CFG_OTHER_POC_MASK) {
*offset = regs->other_poc;
if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC)
*mask = masks->other_poc_pvdd1833_oth_awo_poc;
else if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC)
*mask = masks->other_poc_pvdd1833_oth_iso_poc;
else
*mask = masks->other_poc_wdtovf_n_poc;
return 0;
}
if (caps & PIN_CFG_IO_VMC_I3C) {
*offset = regs->i3c_set;
*mask = masks->i3c_set_poc;
return 0;
}
return -EINVAL;
}
static int rzg2l_pwr_reg_val_to_ps(u16 pwr_reg_val, u32 caps)
{
const struct rzg2l_pinctrl_ps_desc *desc;
desc = rzg2l_pwr_reg_val_to_desc(pwr_reg_val, caps);
if (!desc)
return -EINVAL;
return desc->ps;
}
static int rzg2l_ps_to_pwr_reg_val(u16 ps, u32 caps)
{
const struct rzg2l_pinctrl_ps_desc *desc;
desc = rzg2l_ps_to_desc(ps, caps);
if (!desc)
return -EINVAL;
return desc->pwr_reg_val;
}
static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps)
{
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
const struct rzg2l_register_offsets *regs = &hwcfg->regs;
u8 val, mask;
int pwr_reg;
const struct rzg2l_register_masks *masks = &hwcfg->masks;
u8 mask, val;
u16 offset;
int ret;
if (caps & PIN_CFG_SOFT_PS)
return pctrl->settings[pin].power_source;
pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask);
if (pwr_reg < 0)
return pwr_reg;
ret = rzg2l_caps_to_pwr_reg(regs, masks, caps, &offset, &mask);
if (ret)
return ret;
val = readb(pctrl->base + pwr_reg);
if (pwr_reg == OTHER_POC)
val = field_get(mask, val);
val = readb(pctrl->base + offset);
switch (val) {
case PVDD_1800:
return 1800;
case PVDD_2500:
return 2500;
case PVDD_3300:
return 3300;
default:
/* Should not happen. */
return -EINVAL;
}
return rzg2l_pwr_reg_val_to_ps(field_get(mask, val), caps);
}
static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps)
{
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
const struct rzg2l_register_offsets *regs = &hwcfg->regs;
u8 poc_val, val, mask;
int pwr_reg;
const struct rzg2l_register_masks *masks = &hwcfg->masks;
u16 offset;
u8 mask;
int ret;
if (caps & PIN_CFG_SOFT_PS) {
pctrl->settings[pin].power_source = ps;
return 0;
}
switch (ps) {
case 1800:
poc_val = PVDD_1800;
break;
case 2500:
if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1)))
return -EINVAL;
poc_val = PVDD_2500;
break;
case 3300:
poc_val = PVDD_3300;
break;
default:
return -EINVAL;
}
ret = rzg2l_caps_to_pwr_reg(regs, masks, caps, &offset, &mask);
if (ret)
return ret;
pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask);
if (pwr_reg < 0)
return pwr_reg;
ret = rzg2l_ps_to_pwr_reg_val(ps, caps);
if (ret < 0)
return ret;
if (pwr_reg == OTHER_POC) {
scoped_guard(raw_spinlock_irqsave, &pctrl->lock) {
val = readb(pctrl->base + pwr_reg);
if (poc_val)
val |= mask;
else
val &= ~mask;
writeb(val, pctrl->base + pwr_reg);
}
} else {
writeb(poc_val, pctrl->base + pwr_reg);
scoped_guard(raw_spinlock_irqsave, &pctrl->lock) {
u8 tmp = readb(pctrl->base + offset);
tmp &= ~mask;
tmp |= field_prep(mask, ret);
writeb(tmp, pctrl->base + offset);
}
pctrl->settings[pin].power_source = ps;
@ -1154,32 +1301,11 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps
return 0;
}
static bool rzg2l_ps_is_supported(u16 ps)
static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps, u32 caps)
{
unsigned int i;
const struct rzg2l_pinctrl_ps_desc *desc = rzg2l_ps_to_desc(ps, caps);
for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
if (available_ps[i] == ps)
return true;
}
return false;
}
static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
if (available_ps[i] == ps)
break;
}
/*
* We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have
* RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source
*/
return i * RZG2L_IOLH_MAX_DS_ENTRIES;
return desc ? desc->iolh_index : RZG2L_IOLH_IDX_NA;
}
static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val)
@ -1564,7 +1690,11 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
ret = rzg2l_get_power_source(pctrl, _pin, cfg);
if (ret < 0)
return ret;
iolh_idx = rzg2l_ps_to_iolh_idx(ret);
iolh_idx = rzg2l_ps_to_iolh_idx(ret, cfg);
if (iolh_idx == RZG2L_IOLH_IDX_NA)
return -EINVAL;
val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val);
break;
@ -1760,8 +1890,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
/* Apply power source. */
if (settings.power_source != pctrl->settings[_pin].power_source) {
ret = rzg2l_ps_is_supported(settings.power_source);
if (!ret)
if (!rzg2l_ps_to_desc(settings.power_source, cfg))
return -EINVAL;
/* Apply power source. */
@ -1775,7 +1904,10 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
enum rzg2l_iolh_index iolh_idx;
int val;
iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source);
iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source, cfg);
if (iolh_idx == RZG2L_IOLH_IDX_NA)
return -EINVAL;
ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx,
settings.drive_strength_ua);
if (!ret)
@ -2458,6 +2590,8 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
{ "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) },
{ "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) },
{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
{ "I3C_SDA", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IEN | PIN_CFG_IO_VMC_I3C)) },
{ "I3C_SCL", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IEN | PIN_CFG_IO_VMC_I3C)) },
{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
PIN_CFG_IO_VMC_SD0)) },
@ -2677,28 +2811,28 @@ static const struct rzg2l_dedicated_configs rzg3l_dedicated_pins[] = {
(PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) },
{ "SCIF0_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
(PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) },
{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, PIN_CFG_IOLH_B) },
{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0) },
{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1,
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
{ "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x9, 2, PIN_CFG_IOLH_B) },
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) },
{ "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x9, 2, PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0) },
{ "SD0_DS", RZG2L_SINGLE_PIN_PACK(0x9, 5,
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) },
{ "SD0_DAT0", RZG2L_SINGLE_PIN_PACK(0x0a, 0,
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) },
{ "SD0_DAT1", RZG2L_SINGLE_PIN_PACK(0x0a, 1,
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) },
{ "SD0_DAT2", RZG2L_SINGLE_PIN_PACK(0x0a, 2,
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) },
{ "SD0_DAT3", RZG2L_SINGLE_PIN_PACK(0x0a, 3,
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) },
{ "SD0_DAT4", RZG2L_SINGLE_PIN_PACK(0x0a, 4,
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) },
{ "SD0_DAT5", RZG2L_SINGLE_PIN_PACK(0x0a, 5,
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) },
{ "SD0_DAT6", RZG2L_SINGLE_PIN_PACK(0x0a, 6,
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) },
{ "SD0_DAT7", RZG2L_SINGLE_PIN_PACK(0x0a, 7,
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) },
};
static const u32 r9a08g046_clone_channel_data[] = {
@ -3672,11 +3806,16 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i));
}
if (regs->sd_ch2)
cache->sd_ch2 = readb(pctrl->base + regs->sd_ch2);
if (regs->qspi)
cache->qspi = readb(pctrl->base + regs->qspi);
cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);
if (regs->other_poc)
cache->other_poc = readb(pctrl->base + regs->other_poc);
if (regs->i3c_set)
cache->i3c_set = readb(pctrl->base + regs->i3c_set);
if (pctrl->syscon) {
int ret;
@ -3719,11 +3858,16 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
writeb(cache->qspi, pctrl->base + regs->qspi);
if (regs->other_poc)
writeb(cache->other_poc, pctrl->base + regs->other_poc);
if (regs->i3c_set)
writeb(cache->i3c_set, pctrl->base + regs->i3c_set);
raw_spin_lock_irqsave(&pctrl->lock, flags);
rzg2l_oen_write_with_pwpr(pctrl, cache->oen);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
if (regs->sd_ch2)
writeb(cache->sd_ch2, pctrl->base + regs->sd_ch2);
for (u8 i = 0; i < 2; i++) {
if (regs->sd_ch)
writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
@ -3774,9 +3918,9 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
.regs = {
.pwpr = 0x3014,
.sd_ch = 0x3000,
.qspi = 0x3008,
.eth_poc = 0x300c,
.oen = 0x3018,
.qspi = QSPI,
},
.iolh_groupa_ua = {
/* 3v3 power source */
@ -3791,9 +3935,15 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg = {
.regs = {
.pwpr = 0x3000,
.sd_ch = 0x3004,
.sd_ch2 = 0x3024,
.eth_poc = 0x3010,
.oen = 0x3018,
.other_poc = OTHER_POC,
.other_poc = 0x3028,
},
.masks = {
.other_poc_pvdd1833_oth_awo_poc = BIT(0),
.other_poc_pvdd1833_oth_iso_poc = BIT(1),
.other_poc_wdtovf_n_poc = BIT(2),
},
.iolh_groupa_ua = {
/* 1v8 power source */
@ -3826,8 +3976,12 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = {
.pwpr = 0x3000,
.sd_ch = 0x3004,
.eth_poc = 0x3010,
.i3c_set = 0x301c,
.oen = 0x3018,
},
.masks = {
.i3c_set_poc = BIT(2),
},
.iolh_groupa_ua = {
/* 1v8 power source */
[RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,

182
drivers/pinctrl/renesas/pinctrl-rzt2h.c
View File

@ -94,8 +94,8 @@ struct rzt2h_pinctrl {
void __iomem *base0, *base1;
struct device *dev;
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range gpio_range;
DECLARE_BITMAP(used_irqs, RZT2H_INTERRUPTS_NUM);
u8 saved_pm[RZT2H_INTERRUPTS_NUM];
raw_spinlock_t lock; /* lock read/write registers */
struct mutex mutex; /* serialize adding groups and functions */
bool safety_port_enabled;
@ -170,6 +170,43 @@ static int rzt2h_validate_pin(struct rzt2h_pinctrl *pctrl, unsigned int offset)
return (pincfg & BIT(pin)) ? 0 : -EINVAL;
}
static bool rzt2h_pin_mode_is_peripheral(struct rzt2h_pinctrl *pctrl, u8 port, u8 bit)
{
return rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit);
}
static u8 rzt2h_pin_read_pfc(struct rzt2h_pinctrl *pctrl, u8 port, u8 pin)
{
u64 reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port));
return field_get(PFC_PIN_MASK(pin), reg64);
}
static bool rzt2h_pin_read_input(struct rzt2h_pinctrl *pctrl, u8 port, u8 bit)
{
return rzt2h_pinctrl_readb(pctrl, port, PIN(port)) & BIT(bit);
}
static u8 rzt2h_pin_read_pm(struct rzt2h_pinctrl *pctrl, u8 port, u8 pin)
{
u16 reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
return field_get(PM_PIN_MASK(pin), reg);
}
static void rzt2h_pin_write_pm(struct rzt2h_pinctrl *pctrl, u8 port, u8 pin,
unsigned int pm)
{
u16 reg;
guard(raw_spinlock_irqsave)(&pctrl->lock);
reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
reg &= ~PM_PIN_MASK(pin);
reg |= pm << (pin * 2);
rzt2h_pinctrl_writew(pctrl, port, reg, PM(port));
}
static void rzt2h_pinctrl_set_gpio_en(struct rzt2h_pinctrl *pctrl,
u8 port, u8 pin, bool en)
{
@ -193,7 +230,7 @@ static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl,
reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port));
/* Check if pin is already configured to the desired function */
if ((rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(pin)) &&
if (rzt2h_pin_mode_is_peripheral(pctrl, port, pin) &&
field_get(PFC_PIN_MASK(pin), reg64) == func)
return;
@ -747,15 +784,7 @@ static int rzt2h_gpio_request(struct gpio_chip *chip, unsigned int offset)
static void rzt2h_gpio_set_direction(struct rzt2h_pinctrl *pctrl, u32 port,
u8 bit, bool output)
{
u16 reg;
guard(raw_spinlock_irqsave)(&pctrl->lock);
reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
reg &= ~PM_PIN_MASK(bit);
reg |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2);
rzt2h_pinctrl_writew(pctrl, port, reg, PM(port));
rzt2h_pin_write_pm(pctrl, port, bit, output ? PM_OUTPUT : PM_INPUT);
}
static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
@ -763,9 +792,8 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
u8 port = RZT2H_PIN_ID_TO_PORT(offset);
u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
u64 reg64;
u16 reg;
int ret;
u8 pm;
ret = rzt2h_validate_pin(pctrl, offset);
if (ret)
@ -773,7 +801,7 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
guard(raw_spinlock_irqsave)(&pctrl->lock);
if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) {
if (rzt2h_pin_mode_is_peripheral(pctrl, port, bit)) {
/*
* When a GPIO is being requested as an IRQ, the pinctrl
* framework expects to be able to read the GPIO's direction.
@ -783,19 +811,16 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
* called to enable the IRQ function.
* Default to input direction for IRQ function.
*/
reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port));
reg64 = (reg64 >> (bit * 8)) & PFC_MASK;
if (reg64 == PFC_FUNC_INTERRUPT)
if (rzt2h_pin_read_pfc(pctrl, port, bit) == PFC_FUNC_INTERRUPT)
return GPIO_LINE_DIRECTION_IN;
return -EINVAL;
}
reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
reg = (reg >> (bit * 2)) & PM_MASK;
if (reg & PM_OUTPUT)
pm = rzt2h_pin_read_pm(pctrl, port, bit);
if (pm & PM_OUTPUT)
return GPIO_LINE_DIRECTION_OUT;
if (reg & PM_INPUT)
if (pm & PM_INPUT)
return GPIO_LINE_DIRECTION_IN;
return -EINVAL;
@ -825,13 +850,15 @@ static int rzt2h_gpio_get(struct gpio_chip *chip, unsigned int offset)
struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
u8 port = RZT2H_PIN_ID_TO_PORT(offset);
u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
u16 reg;
u8 pm;
reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
reg = (reg >> (bit * 2)) & PM_MASK;
if (reg & PM_INPUT)
return !!(rzt2h_pinctrl_readb(pctrl, port, PIN(port)) & BIT(bit));
if (reg & PM_OUTPUT)
if (rzt2h_pin_mode_is_peripheral(pctrl, port, bit))
return rzt2h_pin_read_input(pctrl, port, bit);
pm = rzt2h_pin_read_pm(pctrl, port, bit);
if (pm & PM_INPUT)
return rzt2h_pin_read_input(pctrl, port, bit);
if (pm & PM_OUTPUT)
return !!(rzt2h_pinctrl_readb(pctrl, port, P(port)) & BIT(bit));
return -EINVAL;
@ -1000,6 +1027,66 @@ static int rzt2h_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
return 0;
}
static int rzt2h_gpio_irq_request_resources(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct rzt2h_pinctrl *pctrl = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u8 port = RZT2H_PIN_ID_TO_PORT(hwirq);
u8 pin = RZT2H_PIN_ID_TO_PIN(hwirq);
u8 parent_irq, irq_idx;
int ret;
parent_irq = rzt2h_gpio_irq_map[hwirq];
if (parent_irq < RZT2H_INTERRUPTS_START)
return -EINVAL;
irq_idx = parent_irq - RZT2H_INTERRUPTS_START;
if (test_and_set_bit(irq_idx, pctrl->used_irqs))
return -EBUSY;
/*
* rzt2h_pinctrl_set_pfc_mode() sets PM to Hi-Z before switching to the
* interrupt function, losing the previous PM value.
* Save it so it can be restored when the IRQ is freed.
*/
pctrl->saved_pm[irq_idx] = rzt2h_pin_read_pm(pctrl, port, pin);
rzt2h_pinctrl_set_pfc_mode(pctrl, port, pin, PFC_FUNC_INTERRUPT);
ret = gpiochip_lock_as_irq(gc, hwirq);
if (ret) {
clear_bit(irq_idx, pctrl->used_irqs);
rzt2h_pin_write_pm(pctrl, port, pin, pctrl->saved_pm[irq_idx]);
rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, true);
return ret;
}
return 0;
}
static void rzt2h_gpio_irq_release_resources(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct rzt2h_pinctrl *pctrl = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u8 port = RZT2H_PIN_ID_TO_PORT(hwirq);
u8 pin = RZT2H_PIN_ID_TO_PIN(hwirq);
u8 parent_irq, irq_idx;
parent_irq = rzt2h_gpio_irq_map[hwirq];
if (parent_irq < RZT2H_INTERRUPTS_START)
return;
irq_idx = parent_irq - RZT2H_INTERRUPTS_START;
if (test_and_clear_bit(irq_idx, pctrl->used_irqs)) {
rzt2h_pin_write_pm(pctrl, port, pin, pctrl->saved_pm[irq_idx]);
rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, true);
}
gpiochip_unlock_as_irq(gc, hwirq);
}
static const struct irq_chip rzt2h_gpio_irqchip = {
.name = "rzt2h-gpio",
.irq_disable = rzt2h_gpio_irq_disable,
@ -1009,9 +1096,10 @@ static const struct irq_chip rzt2h_gpio_irqchip = {
.irq_set_type = irq_chip_set_type_parent,
.irq_set_wake = rzt2h_gpio_irq_set_wake,
.irq_eoi = irq_chip_eoi_parent,
.irq_request_resources = rzt2h_gpio_irq_request_resources,
.irq_release_resources = rzt2h_gpio_irq_release_resources,
.irq_set_affinity = irq_chip_set_affinity_parent,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int rzt2h_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
@ -1020,43 +1108,17 @@ static int rzt2h_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
unsigned int *parent,
unsigned int *parent_type)
{
struct rzt2h_pinctrl *pctrl = gpiochip_get_data(gc);
u8 port = RZT2H_PIN_ID_TO_PORT(child);
u8 pin = RZT2H_PIN_ID_TO_PIN(child);
u8 parent_irq;
u8 parent_irq = rzt2h_gpio_irq_map[child];
parent_irq = rzt2h_gpio_irq_map[child];
if (parent_irq < RZT2H_INTERRUPTS_START)
return -EINVAL;
if (test_and_set_bit(parent_irq - RZT2H_INTERRUPTS_START,
pctrl->used_irqs))
return -EBUSY;
rzt2h_pinctrl_set_pfc_mode(pctrl, port, pin, PFC_FUNC_INTERRUPT);
*parent = parent_irq;
*parent_type = child_type;
return 0;
}
static void rzt2h_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs)
{
struct irq_data *d = irq_domain_get_irq_data(domain, virq);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct rzt2h_pinctrl *pctrl = container_of(gc, struct rzt2h_pinctrl, gpio_chip);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u8 port = RZT2H_PIN_ID_TO_PORT(hwirq);
u8 pin = RZT2H_PIN_ID_TO_PIN(hwirq);
if (test_and_clear_bit(hwirq - RZT2H_INTERRUPTS_START, pctrl->used_irqs))
rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, false);
irq_domain_free_irqs_common(domain, virq, nr_irqs);
}
static void rzt2h_gpio_init_irq_valid_mask(struct gpio_chip *gc,
unsigned long *valid_mask,
unsigned int ngpios)
@ -1072,7 +1134,6 @@ static void rzt2h_gpio_init_irq_valid_mask(struct gpio_chip *gc,
static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl)
{
struct pinctrl_gpio_range *range = &pctrl->gpio_range;
struct gpio_chip *chip = &pctrl->gpio_chip;
struct device_node *np = pctrl->dev->of_node;
struct irq_domain *parent_domain;
@ -1113,6 +1174,7 @@ static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl)
chip->direction_output = rzt2h_gpio_direction_output;
chip->get = rzt2h_gpio_get;
chip->set = rzt2h_gpio_set;
chip->set_config = gpiochip_generic_config;
chip->label = dev_name(dev);
if (of_property_present(np, "interrupt-controller")) {
@ -1122,17 +1184,9 @@ static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl)
girq->parent_domain = parent_domain;
girq->child_to_parent_hwirq = rzt2h_gpio_child_to_parent_hwirq;
girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell;
girq->child_irq_domain_ops.free = rzt2h_gpio_irq_domain_free;
girq->init_valid_mask = rzt2h_gpio_init_irq_valid_mask;
}
range->id = 0;
range->pin_base = 0;
range->base = 0;
range->npins = chip->ngpio;
range->name = chip->label;
range->gc = chip;
ret = devm_gpiochip_add_data(dev, chip, pctrl);
if (ret)
return dev_err_probe(dev, ret, "gpiochip registration failed\n");

Some files were not shown because too many files have changed in this diff Show More