From d48a308fabd6dc7676d570f0bc971817e39d824c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 23 Jul 2026 16:41:47 +0100 Subject: [PATCH 001/106] pinctrl: renesas: rzg2l: Add SD channel POC support for RZ/G3L MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add power-on control (POC) support for SD channels 1 and 2 on the RZ/G3L SoC (r9a08g046). Introduce PIN_CFG_IO_VMC_SD2 capability flag (bit 22) and SD_CH2_POC register offset (0x3024). Extend rzg2l_caps_to_pwr_reg() to return SD_CH2_POC when PIN_CFG_IO_VMC_SD2 is set. Replace RZG3L_MPXED_PIN_FUNCS() with RZG2L_MPXED_COMMON_PIN_FUNCS() for port PG and PH pins, dropping PIN_CFG_SOFT_PS which is inappropriate for SD pins, and annotate them with PIN_CFG_IO_VMC_SD1 and PIN_CFG_IO_VMC_SD2 respectively. Annotate all RZ/G3L SD0 dedicated pins (CLK, CMD, RST#, DS, DAT0–DAT7) with PIN_CFG_IO_VMC_SD0 so that power-source register lookups work correctly for those pins. Add sd_ch2 field to rzg2l_register_offsets and rzg2l_pinctrl_reg_cache to save and restore the SD_CH2_POC register across suspend/resume cycles. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260723154154.319674-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 74 +++++++++++++++++-------- 1 file changed, 50 insertions(+), 24 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index be52d47d77ae..e3e24ce917c9 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -69,6 +69,7 @@ #define PIN_CFG_PVDD1833_OTH_AWO_POC BIT(19) /* known on RZ/G3L only */ #define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ #define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ +#define PIN_CFG_IO_VMC_SD2 BIT(22) /* known on RZ/G3L only */ #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ @@ -254,6 +255,7 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = { * struct rzg2l_register_offsets - specific register offsets * @pwpr: PWPR register offset * @sd_ch: SD_CH register offset + * @sd_ch2: SD_CH2_POC register offset * @eth_poc: ETH_POC register offset * @oen: OEN register offset * @qspi: QSPI register offset @@ -262,6 +264,7 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = { struct rzg2l_register_offsets { u16 pwpr; u16 sd_ch; + u16 sd_ch2; u16 eth_poc; u16 oen; u16 qspi; @@ -368,6 +371,7 @@ struct rzg2l_pinctrl_pin_settings { * @nod: NOD registers cache * @clone: Clone register cache * @sd_ch: SD_CH registers cache + * @sd_ch2: SD_CH2_POC registers cache * @eth_poc: ET_POC registers cache * @oen: Output Enable register cache * @other_poc: OTHER_POC register cache @@ -386,6 +390,7 @@ struct rzg2l_pinctrl_reg_cache { u32 *nod[2]; u32 clone; u8 sd_ch[2]; + u8 sd_ch2; u8 eth_poc[2]; u8 oen; u8 other_poc; @@ -474,20 +479,32 @@ static const u64 r9a08g046_variable_pin_cfg[] = { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG3L_MPXED_PIN_FUNCS(B)), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IO_VMC_SD1), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD1), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 6, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 7, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG3L_MPXED_PIN_FUNCS(B)), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IO_VMC_SD2), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 0, RZG3L_MPXED_PIN_FUNCS(A) | PIN_CFG_IEN), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 1, RZG3L_MPXED_PIN_FUNCS(A)), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 2, RZG3L_MPXED_PIN_FUNCS(A)), @@ -1053,6 +1070,8 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, return SD_CH(regs->sd_ch, 0); if (caps & PIN_CFG_IO_VMC_SD1) return SD_CH(regs->sd_ch, 1); + if (caps & PIN_CFG_IO_VMC_SD2) + return regs->sd_ch2; if (caps & PIN_CFG_IO_VMC_ETH0) return ETH_POC(regs->eth_poc, 0); if (caps & PIN_CFG_IO_VMC_ETH1) @@ -2677,28 +2696,28 @@ static const struct rzg2l_dedicated_configs rzg3l_dedicated_pins[] = { (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, { "SCIF0_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, - { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, PIN_CFG_IOLH_B) }, + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0) }, { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x9, 2, PIN_CFG_IOLH_B) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x9, 2, PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0) }, { "SD0_DS", RZG2L_SINGLE_PIN_PACK(0x9, 5, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT0", RZG2L_SINGLE_PIN_PACK(0x0a, 0, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT1", RZG2L_SINGLE_PIN_PACK(0x0a, 1, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT2", RZG2L_SINGLE_PIN_PACK(0x0a, 2, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT3", RZG2L_SINGLE_PIN_PACK(0x0a, 3, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT4", RZG2L_SINGLE_PIN_PACK(0x0a, 4, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT5", RZG2L_SINGLE_PIN_PACK(0x0a, 5, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT6", RZG2L_SINGLE_PIN_PACK(0x0a, 6, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT7", RZG2L_SINGLE_PIN_PACK(0x0a, 7, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, }; static const u32 r9a08g046_clone_channel_data[] = { @@ -3672,6 +3691,9 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev) cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); } + if (regs->sd_ch2) + cache->sd_ch2 = readb(pctrl->base + regs->sd_ch2); + if (regs->qspi) cache->qspi = readb(pctrl->base + regs->qspi); cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen); @@ -3724,6 +3746,9 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) rzg2l_oen_write_with_pwpr(pctrl, cache->oen); raw_spin_unlock_irqrestore(&pctrl->lock, flags); + if (regs->sd_ch2) + writeb(cache->sd_ch2, pctrl->base + regs->sd_ch2); + for (u8 i = 0; i < 2; i++) { if (regs->sd_ch) writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); @@ -3791,6 +3816,7 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg = { .regs = { .pwpr = 0x3000, .sd_ch = 0x3004, + .sd_ch2 = 0x3024, .eth_poc = 0x3010, .oen = 0x3018, .other_poc = OTHER_POC, From a67c78364f8b3312d36c3518fe839af8f8385101 Mon Sep 17 00:00:00 2001 From: Prasad Kumpatla Date: Fri, 21 Aug 2026 17:05:47 +0530 Subject: [PATCH 002/106] dt-bindings: pinctrl: qcom,hawi-lpass-lpi-pinctrl: Add Hawi LPI pinctrl Add bindings for the pin controller in Low Power Audio SubSystem (LPASS) of Qualcomm Hawi SoC. The controller has 23 GPIOs (gpio0-gpio22) with functions including SoundWire, I2S, DMIC, VA I2S, ext_mclk1, slimbus and lpass_lpi_dbg_clk. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Prasad Kumpatla Link: https://patch.msgid.link/20260821113548.2686650-2-prasad.kumpatla@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- .../pinctrl/qcom,hawi-lpass-lpi-pinctrl.yaml | 109 ++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,hawi-lpass-lpi-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,hawi-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..af68581750cf --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-lpass-lpi-pinctrl.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,hawi-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Hawi SoC LPASS LPI TLMM + +maintainers: + - Krzysztof Kozlowski + - Srinivas Kandagatla + - Prasad Kumpatla + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm Hawi SoC. + +properties: + compatible: + const: qcom,hawi-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + + clocks: + items: + - description: LPASS LPR(Low Power Resource) voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: lpr + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-hawi-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-hawi-lpass-state" + additionalProperties: false + +$defs: + qcom-hawi-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" + + function: + enum: [dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b, + ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk, + i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, + lpass_lpi_dbg_clk, qca_swr_clk, qca_swr_data, slimbus_clk, + slimbus_data, swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_clk1, + swr_tx_data, va_i2s0_clk, va_i2s0_data, va_i2s0_ws, + wsa2_swr_clk, wsa2_swr_data, wsa_swr_clk, wsa_swr_data] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + lpass_tlmm: pinctrl@7f60000 { + compatible = "qcom,hawi-lpass-lpi-pinctrl"; + reg = <0x07f60000 0x20000>; + + clocks = <&q6prmcc LPASS_HW_LPR_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "lpr", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + tx-swr-sleep-clk-state { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + bias-pull-down; + }; + }; From 6f168dea0db7bf35089a7fe942f1df6214464fcc Mon Sep 17 00:00:00 2001 From: Prasad Kumpatla Date: Fri, 21 Aug 2026 17:05:48 +0530 Subject: [PATCH 003/106] pinctrl: qcom: hawi-lpass-lpi: add Hawi LPASS LPI TLMM Add pin controller driver for the Low Power Audio SubSystem (LPASS) Low Power Island (LPI) of Qualcomm Hawi SoC. The controller has 23 GPIOs with SoundWire, I2S, DMIC, VA I2S, ext_mclk1 and slimbus mux functions. Two pins (gpio13, gpio22) require 6 mux slots due to a test_bus entry occupying a middle hardware slot. Add LPI_PINGROUP6 macro to pinctrl-lpass-lpi.h to support pins with 5 alternate functions. Reviewed-by: Konrad Dybcio Signed-off-by: Prasad Kumpatla Link: https://patch.msgid.link/20260821113548.2686650-3-prasad.kumpatla@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-hawi-lpass-lpi.c | 244 ++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 17 ++ 4 files changed, 272 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-hawi-lpass-lpi.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 18db350222b9..707067b9251f 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -62,6 +62,16 @@ config PINCTRL_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SoCs. +config PINCTRL_HAWI_LPASS_LPI + tristate "Qualcomm Technologies Inc Hawi LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc Hawi + platform. + config PINCTRL_MILOS_LPASS_LPI tristate "Qualcomm Milos LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 43ecd246afe8..987a79f9d4c4 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o obj-$(CONFIG_PINCTRL_ELIZA) += pinctrl-eliza.o obj-$(CONFIG_PINCTRL_GLYMUR) += pinctrl-glymur.o obj-$(CONFIG_PINCTRL_HAWI) += pinctrl-hawi.o +obj-$(CONFIG_PINCTRL_HAWI_LPASS_LPI) += pinctrl-hawi-lpass-lpi.o obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o diff --git a/drivers/pinctrl/qcom/pinctrl-hawi-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-hawi-lpass-lpi.c new file mode 100644 index 000000000000..7036bf4c6692 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-hawi-lpass-lpi.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_dmic4_clk, + LPI_MUX_dmic4_data, + LPI_MUX_ext_mclk1_a, + LPI_MUX_ext_mclk1_b, + LPI_MUX_ext_mclk1_c, + LPI_MUX_ext_mclk1_d, + LPI_MUX_ext_mclk1_e, + LPI_MUX_i2s0_clk, + LPI_MUX_i2s0_data, + LPI_MUX_i2s0_ws, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_lpass_lpi_dbg_clk, + LPI_MUX_qca_swr_clk, + LPI_MUX_qca_swr_data, + LPI_MUX_slimbus_clk, + LPI_MUX_slimbus_data, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_clk1, + LPI_MUX_swr_tx_data, + LPI_MUX_va_i2s0_clk, + LPI_MUX_va_i2s0_data, + LPI_MUX_va_i2s0_ws, + LPI_MUX_wsa2_swr_clk, + LPI_MUX_wsa2_swr_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const struct pinctrl_pin_desc hawi_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", +}; + +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const i2s0_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; +static const char * const i2s0_ws_groups[] = { "gpio1" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const i2s0_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const ext_mclk1_c_groups[] = { "gpio5" }; +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const va_i2s0_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const va_i2s0_ws_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const va_i2s0_data_groups[] = { "gpio8", "gpio9" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const ext_mclk1_b_groups[] = { "gpio9" }; +static const char * const i2s1_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const i2s1_ws_groups[] = { "gpio11" }; +static const char * const wsa_swr_data_groups[] = { "gpio11", "gpio21" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const i2s3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const i2s3_ws_groups[] = { "gpio13" }; +static const char * const ext_mclk1_a_groups[] = { "gpio13" }; +static const char * const lpass_lpi_dbg_clk_groups[] = { "gpio13" }; +static const char * const swr_tx_clk1_groups[] = { "gpio14" }; +static const char * const ext_mclk1_d_groups[] = { "gpio14" }; +static const char * const i2s1_data_groups[] = { "gpio15", "gpio16", "gpio21", "gpio22" }; +static const char * const wsa2_swr_clk_groups[] = { "gpio15" }; +static const char * const wsa2_swr_data_groups[] = { "gpio16", "gpio22" }; +static const char * const dmic4_clk_groups[] = { "gpio17" }; +static const char * const i2s3_data_groups[] = { "gpio17", "gpio18" }; +static const char * const dmic4_data_groups[] = { "gpio18" }; +static const char * const i2s2_clk_groups[] = { "gpio19" }; +static const char * const slimbus_clk_groups[] = { "gpio19" }; +static const char * const qca_swr_clk_groups[] = { "gpio19" }; +static const char * const i2s2_ws_groups[] = { "gpio20" }; +static const char * const slimbus_data_groups[] = { "gpio20" }; +static const char * const qca_swr_data_groups[] = { "gpio20" }; +static const char * const i2s2_data_groups[] = { "gpio21", "gpio22" }; +static const char * const ext_mclk1_e_groups[] = { "gpio22" }; + +static const struct lpi_pingroup hawi_groups[] = { + LPI_PINGROUP(0, 11, swr_tx_clk, i2s0_clk, _, _), + LPI_PINGROUP(1, 11, swr_tx_data, i2s0_ws, _, _), + LPI_PINGROUP(2, 11, swr_tx_data, i2s0_data, _, _), + LPI_PINGROUP(3, 11, swr_rx_clk, i2s0_data, _, _), + LPI_PINGROUP(4, 11, swr_rx_data, i2s0_data, _, _), + LPI_PINGROUP(5, 11, swr_rx_data, ext_mclk1_c, i2s0_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, va_i2s0_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, va_i2s0_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, va_i2s0_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, va_i2s0_data, ext_mclk1_b, _), + LPI_PINGROUP(10, 11, i2s1_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 11, i2s1_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s3_clk, _, _), + LPI_PINGROUP6(13, LPI_NO_SLEW, dmic3_data, i2s3_ws, ext_mclk1_a, _, lpass_lpi_dbg_clk), + LPI_PINGROUP(14, 11, swr_tx_data, swr_tx_clk1, ext_mclk1_d, _), + LPI_PINGROUP(15, 11, i2s1_data, wsa2_swr_clk, _, _), + LPI_PINGROUP(16, 11, i2s1_data, wsa2_swr_data, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, dmic4_clk, i2s3_data, _, _), + LPI_PINGROUP(18, LPI_NO_SLEW, dmic4_data, i2s3_data, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, i2s2_clk, slimbus_clk, qca_swr_clk, _), + LPI_PINGROUP(20, LPI_NO_SLEW, i2s2_ws, slimbus_data, qca_swr_data, _), + LPI_PINGROUP(21, 11, i2s2_data, _, wsa_swr_data, i2s1_data), + LPI_PINGROUP6(22, 11, i2s2_data, ext_mclk1_e, _, i2s1_data, wsa2_swr_data), +}; + +static const struct lpi_function hawi_functions[] = { + LPI_FUNCTION(gpio), + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(dmic4_clk), + LPI_FUNCTION(dmic4_data), + LPI_FUNCTION(ext_mclk1_a), + LPI_FUNCTION(ext_mclk1_b), + LPI_FUNCTION(ext_mclk1_c), + LPI_FUNCTION(ext_mclk1_d), + LPI_FUNCTION(ext_mclk1_e), + LPI_FUNCTION(i2s0_clk), + LPI_FUNCTION(i2s0_data), + LPI_FUNCTION(i2s0_ws), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(lpass_lpi_dbg_clk), + LPI_FUNCTION(qca_swr_clk), + LPI_FUNCTION(qca_swr_data), + LPI_FUNCTION(slimbus_clk), + LPI_FUNCTION(slimbus_data), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_clk1), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(va_i2s0_clk), + LPI_FUNCTION(va_i2s0_data), + LPI_FUNCTION(va_i2s0_ws), + LPI_FUNCTION(wsa2_swr_clk), + LPI_FUNCTION(wsa2_swr_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), +}; + +static const struct lpi_pinctrl_variant_data hawi_lpi_data = { + .pins = hawi_lpi_pins, + .npins = ARRAY_SIZE(hawi_lpi_pins), + .groups = hawi_groups, + .ngroups = ARRAY_SIZE(hawi_groups), + .functions = hawi_functions, + .nfunctions = ARRAY_SIZE(hawi_functions), + .flags = LPI_FLAG_SLEW_RATE_SAME_REG, +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,hawi-lpass-lpi-pinctrl", + .data = &hawi_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-hawi-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("Qualcomm Hawi LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h index 6ba0c4eba984..056c4a774389 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -92,6 +92,23 @@ struct pinctrl_pin_desc; .pin_offset = 0, \ } +#define LPI_PINGROUP6(id, soff, f1, f2, f3, f4, f5) \ + { \ + .pin = id, \ + .slew_offset = soff, \ + .slew_base_spare_1 = false, \ + .funcs = (int[]){ \ + LPI_MUX_gpio, \ + LPI_MUX_##f1, \ + LPI_MUX_##f2, \ + LPI_MUX_##f3, \ + LPI_MUX_##f4, \ + LPI_MUX_##f5, \ + }, \ + .nfuncs = 6, \ + .pin_offset = 0, \ + } + /* * Slew rate control is done in the same register as rest of the * pin configuration. From 44993896813659d9adc8c0a0ba3986bdbda748ab Mon Sep 17 00:00:00 2001 From: Ahmed Naseef Date: Fri, 28 Aug 2026 19:35:13 +0400 Subject: [PATCH 004/106] pinctrl: airoha: limit GPIO interrupts to interrupt-capable pins The driver assumes that every one of the AIROHA_NUM_PINS GPIOs can raise an interrupt. That holds for the SoCs supported so far, but not for every member of the family: on EN7528 only GPIO0-GPIO15 are wired to the interrupt controller. Without this the driver hands out interrupts for GPIOs that can never fire, and the interrupt handler reads status registers that are not backed by any pin. Add a num_irq_pins field to the per-SoC match data and use it to bound the interrupt callbacks and to size the loop in the interrupt handler. Feed it to gpiolib through gpio_irq_chip::init_valid_mask as well, so that gpiod_to_irq() fails for a pin that cannot be an interrupt source instead of deferring the failure to request_irq(). Signed-off-by: Ahmed Naseef Reviewed-by: Benjamin Larsson Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/airoha-common.h | 3 +++ drivers/pinctrl/airoha/pinctrl-airoha.c | 33 +++++++++++++++++++++---- drivers/pinctrl/airoha/pinctrl-an7563.c | 1 + drivers/pinctrl/airoha/pinctrl-an7581.c | 1 + drivers/pinctrl/airoha/pinctrl-an7583.c | 1 + drivers/pinctrl/airoha/pinctrl-en7523.c | 1 + 6 files changed, 35 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h index c1acbfb7426e..16f7abcdfb83 100644 --- a/drivers/pinctrl/airoha/airoha-common.h +++ b/drivers/pinctrl/airoha/airoha-common.h @@ -127,6 +127,7 @@ struct airoha_pinctrl { struct gpio_chip gpiochip; struct airoha_gpiochip_regs *gpio_regs; + unsigned int num_irq_pins; }; struct airoha_pinctrl_match_data { @@ -140,6 +141,8 @@ struct airoha_pinctrl_match_data { const struct airoha_pinctrl_func *funcs; const unsigned int num_funcs; const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX]; + /* number of GPIOs wired to the interrupt controller */ + const unsigned int num_irq_pins; }; int airoha_pinctrl_probe(struct platform_device *pdev); diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index f505a3f69c5d..52a768c859b7 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -213,7 +213,7 @@ static void airoha_irq_unmask(struct irq_data *data) u32 mask = GENMASK(2 * offset + 1, 2 * offset); u32 val = BIT(2 * offset); - if (WARN_ON_ONCE(data->hwirq >= AIROHA_NUM_PINS)) + if (WARN_ON_ONCE(data->hwirq >= pinctrl->num_irq_pins)) return; gpiochip_enable_irq(gc, irqd_to_hwirq(data)); @@ -249,7 +249,7 @@ static void airoha_irq_mask(struct irq_data *data) u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN; u32 mask = GENMASK(2 * offset + 1, 2 * offset); - if (data->hwirq >= AIROHA_NUM_PINS) + if (data->hwirq >= pinctrl->num_irq_pins) return; regmap_clear_bits(pinctrl->regmap, gpio_regs->level[index], mask); @@ -265,7 +265,7 @@ static void airoha_irq_ack(struct irq_data *data) u8 offset = data->hwirq % AIROHA_PIN_BANK_SIZE; u8 index = data->hwirq / AIROHA_PIN_BANK_SIZE; - if (data->hwirq >= AIROHA_NUM_PINS) + if (data->hwirq >= pinctrl->num_irq_pins) return; regmap_write(pinctrl->regmap, gpio_regs->status[index], BIT(offset)); @@ -273,7 +273,10 @@ static void airoha_irq_ack(struct irq_data *data) static int airoha_irq_type(struct irq_data *data, unsigned int type) { - if (data->hwirq >= AIROHA_NUM_PINS) + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc); + + if (data->hwirq >= pinctrl->num_irq_pins) return -EINVAL; if (type == IRQ_TYPE_NONE) { @@ -304,9 +307,11 @@ static irqreturn_t airoha_irq_handler(int irq, void *data) { struct airoha_pinctrl *pinctrl = data; bool handled = false; + unsigned int nbanks; int i; - for (i = 0; i < ARRAY_SIZE(irq_status_regs); i++) { + nbanks = DIV_ROUND_UP(pinctrl->num_irq_pins, AIROHA_PIN_BANK_SIZE); + for (i = 0; i < nbanks; i++) { struct gpio_irq_chip *girq = &pinctrl->gpiochip.irq; u32 regmap; unsigned long status; @@ -340,6 +345,22 @@ static const struct irq_chip airoha_gpio_irq_chip = { GPIOCHIP_IRQ_RESOURCE_HELPERS, }; +/* + * Mark the GPIOs that are not wired to the interrupt controller as not + * valid, so that gpiod_to_irq() fails for them with -ENXIO instead of + * handing out an interrupt that can never fire. + */ +static void airoha_gpio_init_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc); + unsigned int num_irq_pins = pinctrl->num_irq_pins; + + if (num_irq_pins < ngpios) + bitmap_clear(valid_mask, num_irq_pins, ngpios - num_irq_pins); +} + static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, struct platform_device *pdev) { @@ -362,6 +383,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_bad_irq; + girq->init_valid_mask = airoha_gpio_init_valid_mask; gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip); irq = platform_get_irq(pdev, 0); @@ -848,6 +870,7 @@ int airoha_pinctrl_probe(struct platform_device *pdev) pinctrl->grps = data->grps; pinctrl->funcs = data->funcs; pinctrl->confs_info = data->confs_info; + pinctrl->num_irq_pins = data->num_irq_pins; err = pinctrl_enable(pinctrl->ctrl); if (err) diff --git a/drivers/pinctrl/airoha/pinctrl-an7563.c b/drivers/pinctrl/airoha/pinctrl-an7563.c index 40cbbe90cc46..f011c6c9ccce 100644 --- a/drivers/pinctrl/airoha/pinctrl-an7563.c +++ b/drivers/pinctrl/airoha/pinctrl-an7563.c @@ -1069,6 +1069,7 @@ static const struct airoha_pinctrl_match_data pinctrl_match_data = { .num_grps = ARRAY_SIZE(pinctrl_groups), .funcs = pinctrl_funcs, .num_funcs = ARRAY_SIZE(pinctrl_funcs), + .num_irq_pins = AIROHA_NUM_PINS, .confs_info = { [AIROHA_PINCTRL_CONFS_PULLUP] = { .confs = pinctrl_pullup_conf, diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c index 2fcf88106e11..bfb777594811 100644 --- a/drivers/pinctrl/airoha/pinctrl-an7581.c +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c @@ -1441,6 +1441,7 @@ static const struct airoha_pinctrl_match_data pinctrl_match_data = { .num_grps = ARRAY_SIZE(pinctrl_groups), .funcs = pinctrl_funcs, .num_funcs = ARRAY_SIZE(pinctrl_funcs), + .num_irq_pins = AIROHA_NUM_PINS, .confs_info = { [AIROHA_PINCTRL_CONFS_PULLUP] = { .confs = pinctrl_pullup_conf, diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c index 2c3a75c35915..1cd0f442ddc1 100644 --- a/drivers/pinctrl/airoha/pinctrl-an7583.c +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c @@ -1471,6 +1471,7 @@ static const struct airoha_pinctrl_match_data pinctrl_match_data = { .num_grps = ARRAY_SIZE(pinctrl_groups), .funcs = pinctrl_funcs, .num_funcs = ARRAY_SIZE(pinctrl_funcs), + .num_irq_pins = AIROHA_NUM_PINS, .confs_info = { [AIROHA_PINCTRL_CONFS_PULLUP] = { .confs = pinctrl_pullup_conf, diff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airoha/pinctrl-en7523.c index 5aa39bacf460..b0c5e60f0aeb 100644 --- a/drivers/pinctrl/airoha/pinctrl-en7523.c +++ b/drivers/pinctrl/airoha/pinctrl-en7523.c @@ -1113,6 +1113,7 @@ static const struct airoha_pinctrl_match_data pinctrl_match_data = { .num_grps = ARRAY_SIZE(pinctrl_groups), .funcs = pinctrl_funcs, .num_funcs = ARRAY_SIZE(pinctrl_funcs), + .num_irq_pins = AIROHA_NUM_PINS, .confs_info = { [AIROHA_PINCTRL_CONFS_PULLUP] = { .confs = pinctrl_pullup_conf, From ce80938ecae4dc7eec8fb1e21229f4cf3f1aebab Mon Sep 17 00:00:00 2001 From: Ahmed Naseef Date: Fri, 28 Aug 2026 19:35:14 +0400 Subject: [PATCH 005/106] dt-bindings: pinctrl: Add EcoNet EN7528 pin controller Add the binding for the pin controller found on the EcoNet EN7528 MIPS SoC. It shares the IP with the Airoha pin controllers, but its IOMUX and pin configuration registers have a different layout, so it gets its own compatible. The CHIP SCU holding those registers is referenced by the airoha,chip-scu phandle. Signed-off-by: Ahmed Naseef Reviewed-by: Conor Dooley Signed-off-by: Linus Walleij --- .../pinctrl/econet,en7528-pinctrl.yaml | 190 ++++++++++++++++++ 1 file changed, 190 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/econet,en7528-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/econet,en7528-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/econet,en7528-pinctrl.yaml new file mode 100644 index 000000000000..3ce1a5309d09 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/econet,en7528-pinctrl.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/econet,en7528-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet EN7528 Pin Controller + +maintainers: + - Lorenzo Bianconi + +description: + The EcoNet EN7528 pin controller is used to control SoC pins. It shares the + IP with the Airoha pin controllers, but its IOMUX and pin configuration + registers have a different layout. + +properties: + compatible: + const: econet,en7528-pinctrl + + airoha,chip-scu: + description: phandle to the chip SCU syscon + $ref: /schemas/types.yaml#/definitions/phandle + + interrupts: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +patternProperties: + '-pins$': + type: object + + patternProperties: + '^mux(-|$)': + type: object + + description: + pinmux configuration nodes. + + $ref: /schemas/pinctrl/pinmux-node.yaml + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [gpio, jtag, pcie_reset, pcm, pcm_spi, phy1_led0, + phy1_led1, phy2_led0, phy2_led1, phy3_led0, phy3_led1, + phy4_led0, phy4_led1, pnand, pon, pwm, sipo, spi, uart] + + groups: + description: + An array of strings. Each string contains the name of a group. + items: + enum: [pon, sipo, sipo_rclk, uart2, uart2_cts_rts, uart3, + ejtag, pcm1, pcm2, spi_quad, spi_cs1, pcm_spi, + pcm_spi_int, pcm_spi_rst, pcm_spi_cs1, pcm_spi_cs2, + pcm_spi_cs3, pcm_spi_cs4, pcm_spi_cs5, pcm_spi_cs6, + pcm_spi_cs7, pnand, gpio0, gpio1, gpio2, gpio3, gpio4, + gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, + gpio12, gpio13, gpio14, gpio15, gpio16, gpio17, + gpio18, gpio19, gpio20, gpio21, gpio22, gpio23, + gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, + gpio30, gpio31, gpio32, gpio33, gpio34, gpio35, + gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, + pcie_reset0, pcie_reset1] + + required: + - function + - groups + + additionalProperties: false + + '^conf(-|$)': + type: object + + description: + pinconf configuration nodes. + + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, + gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, + gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, + gpio26, gpio27, gpio28, gpio29, gpio30, gpio31, + gpio32, gpio33, gpio34, gpio35, gpio36, gpio37, + gpio38, gpio39, pcie_reset0, pcie_reset1, i2c_sda, + i2c_scl, uart_txd, uart_rxd, spi_cs0, spi_clk, + spi_mosi, spi_miso] + minItems: 1 + maxItems: 50 + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-enable: true + + output-low: true + + output-high: true + + drive-strength: + description: + Selects the drive strength for the pin, in mA. + enum: [2, 4] + + required: + - pins + + additionalProperties: false + + additionalProperties: false + +required: + - compatible + - airoha,chip-scu + - interrupts + - gpio-controller + - gpio-ranges + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + + pinctrl { + compatible = "econet,en7528-pinctrl"; + + airoha,chip-scu = <&chip_scu>; + + interrupt-parent = <&gic>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&pinctrl 0 0 42>; + + uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + + conf { + pins = "gpio28", "gpio29"; + bias-pull-up; + }; + }; + + pwm-pins { + mux { + function = "pwm"; + groups = "gpio30"; + }; + }; + }; From 0619b18afa8849cfc4f39de0da079982e707bdd4 Mon Sep 17 00:00:00 2001 From: Benjamin Larsson Date: Fri, 28 Aug 2026 19:35:15 +0400 Subject: [PATCH 006/106] pinctrl: airoha: add support of en7528 SoC The EcoNet EN7528 MIPS SoC uses the same pin controller and GPIO IP as the Airoha SoCs, so it can reuse the shared driver code. Its register layout differs from every existing variant though: all IOMUX mode bits live in a single CHIP SCU register (RG_PON_I2C_MODE at 0x15c) plus the spill-over bits in IOMUX Control 3 (0x224), EJTAG has its own enable register at 0x1ac, the LED mapping registers sit at 0x1b0/0x1b4 and all pin configuration registers are at different offsets than on EN7523. Pin numbering follows the GPIO line numbering, so pins 0-41 map to GPIO0-GPIO41. Pins 42-49 are the standalone I2C/UART/SPI pads, which have no GPIO function and are only referenced by the pinconf tables. Only GPIO0-GPIO15 are wired to the interrupt controller, so num_irq_pins is 16. EN7528 has no PCIe reset open drain register, so AIROHA_PINCTRL_CONFS_PCIE_RST_OD is left empty and PIN_CONFIG_DRIVE_OPEN_DRAIN is rejected for all pins. Signed-off-by: Benjamin Larsson Signed-off-by: Ahmed Naseef Signed-off-by: Linus Walleij --- drivers/pinctrl/airoha/Kconfig | 15 +- drivers/pinctrl/airoha/Makefile | 1 + drivers/pinctrl/airoha/pinctrl-en7528.c | 1204 +++++++++++++++++++++++ 3 files changed, 1218 insertions(+), 2 deletions(-) create mode 100644 drivers/pinctrl/airoha/pinctrl-en7528.c diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig index 22b8f850cee1..0f0986c81219 100644 --- a/drivers/pinctrl/airoha/Kconfig +++ b/drivers/pinctrl/airoha/Kconfig @@ -1,11 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-only menu "Airoha pinctrl drivers" - depends on ARCH_AIROHA || COMPILE_TEST + depends on ARCH_AIROHA || ECONET || COMPILE_TEST config PINCTRL_AIROHA tristate "Airoha pin control" depends on OF - depends on ARCH_AIROHA || COMPILE_TEST + depends on ARCH_AIROHA || ECONET || COMPILE_TEST select PINMUX select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS @@ -17,6 +17,7 @@ config PINCTRL_AIROHA imply PINCTRL_AIROHA_AN7581 imply PINCTRL_AIROHA_AN7583 imply PINCTRL_AIROHA_EN7523 + imply PINCTRL_AIROHA_EN7528 help Shared pin controller and gpio driver code for different Airoha SoCs. @@ -53,4 +54,14 @@ config PINCTRL_AIROHA_EN7523 Say yes here to support pin controller and gpio driver on Airoha EN7523, EN7529, EN7562 and other compatible SoCs. +config PINCTRL_AIROHA_EN7528 + tristate "EN7528 pinctrl" + depends on ECONET || COMPILE_TEST + depends on PINCTRL_AIROHA + help + Say yes here to support pin controller and gpio driver + on EcoNet EN7528 and other compatible SoCs. Unlike the + other variants, only the first sixteen GPIOs of this SoC + are wired to the interrupt controller. + endmenu diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile index 30e4bee57a4a..4dc7c556ce4d 100644 --- a/drivers/pinctrl/airoha/Makefile +++ b/drivers/pinctrl/airoha/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_AIROHA_AN7563) += pinctrl-an7563.o obj-$(CONFIG_PINCTRL_AIROHA_AN7581) += pinctrl-an7581.o obj-$(CONFIG_PINCTRL_AIROHA_AN7583) += pinctrl-an7583.o obj-$(CONFIG_PINCTRL_AIROHA_EN7523) += pinctrl-en7523.o +obj-$(CONFIG_PINCTRL_AIROHA_EN7528) += pinctrl-en7528.o diff --git a/drivers/pinctrl/airoha/pinctrl-en7528.c b/drivers/pinctrl/airoha/pinctrl-en7528.c new file mode 100644 index 000000000000..f6c8f834421f --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-en7528.c @@ -0,0 +1,1204 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Benjamin Larsson + * + * EcoNet EN7528 SoC pinctrl driver. + * + * Sources: EN7528 External Programming Guide V1.3 chapter 1.2.2/1.3.2 + * (CHIP SCU, base 0x1fa20000), chapter 12 (GPIO controller, base + * 0x1fbf0200) and EN7528DU/EN7528HU datasheets chapter 4.3 (pin sharing + * schemes; both packages use the same GPIO mapping). + * + * Unlike the later SoCs, all IOMUX mode bits live in a single register + * (RG_PON_I2C_MODE at 0x15c) plus the spill-over bits in IOMUX Control 3 + * (RG_FORCE_GPIO22_EN at 0x224). EJTAG has its own enable register at + * 0x1ac. + * + * Pin numbering follows the GPIO line numbering of the SoC: + * pins 0-11 -> GPIO0-GPIO11 (dedicated GPIO pads) + * pins 12-15 -> ZSYNC1/ZCLK1/ZMOSI1/ZMISO1 pads (GPIO12-GPIO15) + * pins 16-21 -> PON I/O pads (GPIO16-GPIO21, GPIO21 = PON_RX_DIS) + * pins 22-39 -> GPIO22-GPIO39 (dedicated GPIO pads) + * pins 40/41 -> PCIE_RESET0/PCIE_RESET1 pads (GPIO40/GPIO41) + * Pins 42-49 are the standalone pads (I2C, UART, SPI). They have no + * GPIO function and are only referenced by the pinconf tables. + * + * Note: the RG_PON_I2C_MODE register description in the programming + * guide carries stale "GPIO30/GPIO31" text for the PCIE_RESET pads; the + * EN7528 datasheets (table 4-10) map them to GPIO40/GPIO41. + * + * The PCM SPI chip select register bit names are offset by two against + * the datasheet signal names: rg_gpio_pcm_spi_cs3_mode drives + * PCM_SPI_CS1 (spelled out in datasheet table 4-6). + */ +#include "airoha-common.h" + +/* MUX */ +#define REG_PON_I2C_MODE 0x015c +#define SIPO_RCLK_MODE_MASK BIT(30) +/* + * A set PCIE_RESET{0,1}_GPIO bit routes the pad to its GPIO function + * (GPIO40/GPIO41), a cleared bit selects the PCIe reset function. + */ +#define GPIO_PCIE_RESET1_MASK BIT(29) /* GPIO41 */ +#define GPIO_PCIE_RESET0_MASK BIT(28) /* GPIO40 */ +#define GPIO_SPI_QUAD_MODE_MASK BIT(27) +#define GPIO_UART3_MODE_MASK BIT(26) +#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(25) +#define GPIO_UART2_MODE_MASK BIT(24) +#define GPIO_SIPO_MODE_MASK BIT(23) +#define GPIO_PON_MODE_MASK BIT(21) +#define GPIO_PCM2_MODE_MASK BIT(20) +#define GPIO_PCM1_MODE_MASK BIT(19) +#define GPIO_PCM_SPI_MODE_MASK BIT(18) /* RG_GPIO_SPI2_MODE */ +#define GPIO_PCM_INT_MODE_MASK BIT(17) +#define GPIO_PCM_RESET_MODE_MASK BIT(16) +#define GPIO_SPI_CS1_MODE_MASK BIT(15) +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(14) /* RG ..._CS3 */ +#define GPIO_LAN3_LED1_MODE_MASK BIT(11) +#define GPIO_LAN3_LED0_MODE_MASK BIT(10) +#define GPIO_LAN2_LED1_MODE_MASK BIT(9) +#define GPIO_LAN2_LED0_MODE_MASK BIT(8) +#define GPIO_LAN1_LED1_MODE_MASK BIT(7) +#define GPIO_LAN1_LED0_MODE_MASK BIT(6) +#define GPIO_LAN0_LED1_MODE_MASK BIT(5) +#define GPIO_LAN0_LED0_MODE_MASK BIT(4) +#define PON_TOD_1PPS_MODE_MASK BIT(2) +#define GSW_TOD_1PPS_MODE_MASK BIT(1) + +#define REG_FORCE_GPIO22_EN 0x0224 +#define GPIO_PCM_SPI_CS7_MODE_MASK BIT(15) /* RG ..._CS9 */ +#define GPIO_PCM_SPI_CS6_MODE_MASK BIT(14) /* RG ..._CS8 */ +#define GPIO_PCM_SPI_CS5_MODE_MASK BIT(13) /* RG ..._CS7 */ +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(12) /* RG ..._CS6 */ +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(11) /* RG ..._CS5 */ +#define GPIO_PCM_SPI_CS2_MODE_MASK BIT(10) /* RG ..._CS4 */ +#define GPIO_PNAND_MODE_MASK BIT(9) /* RG_GPIO_NFD_MODE */ + +#define REG_CPU_EJTAG_EN 0x01ac +#define CPU_EJTAG_EN_MASK BIT(0) + +/* LED MAP */ +#define REG_LAN_LED0_MAPPING 0x01b0 +#define REG_LAN_LED1_MAPPING 0x01b4 + +/* shared */ +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) + +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) + +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) + +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) + +/* + * CONF. + * The EN7528 documentation names the two drive strength stages E4/E8; + * they fill the DRIVE_E2/DRIVE_E4 pinconf slots. All conf register + * offsets differ from the later SoCs. + */ +#define REG_I2C_SDA_E2 0x0014 /* RG_I2C_SDA_E4 */ +#define REG_I2C_SDA_E4 0x0018 /* RG_I2C_SDA_E8 */ +#define REG_GPIO_L_E2 0x001c /* RG_GPIO_L_E4 */ +#define REG_GPIO_H_E2 0x0020 /* RG_GPIO_H_E4 */ +#define REG_GPIO_L_E4 0x0024 /* RG_GPIO_L_E8 */ +#define REG_GPIO_H_E4 0x0028 /* RG_GPIO_H_E8 */ + +#define REG_I2C_SDA_PU 0x003c +#define REG_I2C_SDA_PD 0x0040 +#define REG_GPIO_L_PU 0x0044 +#define REG_GPIO_H_PU 0x0048 +#define REG_GPIO_L_PD 0x004c +#define REG_GPIO_H_PD 0x0050 + +/* standalone IO conf bit layout, common to E4/E8/PU/PD registers */ +#define SPI_MISO_CONF_MASK BIT(13) +#define SPI_MOSI_CONF_MASK BIT(12) +#define SPI_CLK_CONF_MASK BIT(11) +#define SPI_CS0_CONF_MASK BIT(10) +#define PCIE1_RESET_CONF_MASK BIT(9) +#define PCIE0_RESET_CONF_MASK BIT(8) +#define UART_RXD_CONF_MASK BIT(3) +#define UART_TXD_CONF_MASK BIT(2) +#define I2C_SCL_CONF_MASK BIT(1) +#define I2C_SDA_CONF_MASK BIT(0) + +/* + * PWM MODE CONF - the flash mode registers match EN7580: EXT bit 16 + * maps to GPIO32 and EXT bits 17+ to GPIO37+. GPIO33-GPIO36 have no + * flash mode configuration bit. + */ +#define REG_GPIO_FLASH_MODE_CFG 0x0034 +#define GPIO15_FLASH_MODE_CFG BIT(15) +#define GPIO14_FLASH_MODE_CFG BIT(14) +#define GPIO13_FLASH_MODE_CFG BIT(13) +#define GPIO12_FLASH_MODE_CFG BIT(12) +#define GPIO11_FLASH_MODE_CFG BIT(11) +#define GPIO10_FLASH_MODE_CFG BIT(10) +#define GPIO9_FLASH_MODE_CFG BIT(9) +#define GPIO8_FLASH_MODE_CFG BIT(8) +#define GPIO7_FLASH_MODE_CFG BIT(7) +#define GPIO6_FLASH_MODE_CFG BIT(6) +#define GPIO5_FLASH_MODE_CFG BIT(5) +#define GPIO4_FLASH_MODE_CFG BIT(4) +#define GPIO3_FLASH_MODE_CFG BIT(3) +#define GPIO2_FLASH_MODE_CFG BIT(2) +#define GPIO1_FLASH_MODE_CFG BIT(1) +#define GPIO0_FLASH_MODE_CFG BIT(0) + +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 +#define GPIO41_FLASH_MODE_CFG BIT(21) +#define GPIO40_FLASH_MODE_CFG BIT(20) +#define GPIO39_FLASH_MODE_CFG BIT(19) +#define GPIO38_FLASH_MODE_CFG BIT(18) +#define GPIO37_FLASH_MODE_CFG BIT(17) +#define GPIO32_FLASH_MODE_CFG BIT(16) /* GPIO36 on EN7581 */ +#define GPIO31_FLASH_MODE_CFG BIT(15) +#define GPIO30_FLASH_MODE_CFG BIT(14) +#define GPIO29_FLASH_MODE_CFG BIT(13) +#define GPIO28_FLASH_MODE_CFG BIT(12) +#define GPIO27_FLASH_MODE_CFG BIT(11) +#define GPIO26_FLASH_MODE_CFG BIT(10) +#define GPIO25_FLASH_MODE_CFG BIT(9) +#define GPIO24_FLASH_MODE_CFG BIT(8) +#define GPIO23_FLASH_MODE_CFG BIT(7) +#define GPIO22_FLASH_MODE_CFG BIT(6) +#define GPIO21_FLASH_MODE_CFG BIT(5) +#define GPIO20_FLASH_MODE_CFG BIT(4) +#define GPIO19_FLASH_MODE_CFG BIT(3) +#define GPIO18_FLASH_MODE_CFG BIT(2) +#define GPIO17_FLASH_MODE_CFG BIT(1) +#define GPIO16_FLASH_MODE_CFG BIT(0) + +static const struct pinctrl_pin_desc pinctrl_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), /* PCM_INT */ + PINCTRL_PIN(2, "gpio2"), /* PCM_RESET */ + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), /* ZSYNC1 */ + PINCTRL_PIN(13, "gpio13"), /* ZCLK1 */ + PINCTRL_PIN(14, "gpio14"), /* ZMOSI1 */ + PINCTRL_PIN(15, "gpio15"), /* ZMISO1 */ + PINCTRL_PIN(16, "gpio16"), /* PON_TX_DIS */ + PINCTRL_PIN(17, "gpio17"), /* PON_TX_FAULT */ + PINCTRL_PIN(18, "gpio18"), /* PON_TX_SD */ + PINCTRL_PIN(19, "gpio19"), /* PON_RX_SD */ + PINCTRL_PIN(20, "gpio20"), /* PON_BURST_EN */ + PINCTRL_PIN(21, "gpio21"), /* PON_RX_DIS */ + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "gpio28"), + PINCTRL_PIN(29, "gpio29"), + PINCTRL_PIN(30, "gpio30"), + PINCTRL_PIN(31, "gpio31"), + PINCTRL_PIN(32, "gpio32"), + PINCTRL_PIN(33, "gpio33"), + PINCTRL_PIN(34, "gpio34"), + PINCTRL_PIN(35, "gpio35"), + PINCTRL_PIN(36, "gpio36"), + PINCTRL_PIN(37, "gpio37"), + PINCTRL_PIN(38, "gpio38"), + PINCTRL_PIN(39, "gpio39"), + PINCTRL_PIN(40, "pcie_reset0"), /* GPIO40 */ + PINCTRL_PIN(41, "pcie_reset1"), /* GPIO41 */ + /* standalone pads, pinconf only */ + PINCTRL_PIN(42, "i2c_sda"), + PINCTRL_PIN(43, "i2c_scl"), + PINCTRL_PIN(44, "uart_txd"), + PINCTRL_PIN(45, "uart_rxd"), + PINCTRL_PIN(46, "spi_cs0"), + PINCTRL_PIN(47, "spi_clk"), + PINCTRL_PIN(48, "spi_mosi"), + PINCTRL_PIN(49, "spi_miso"), +}; + +static const int pon_pins[] = { 17, 18, 19, 20 }; +static const int sipo_pins[] = { 8, 11 }; +static const int sipo_rclk_pins[] = { 8, 9, 11 }; +static const int uart2_pins[] = { 28, 29 }; +static const int uart2_cts_rts_pins[] = { 12, 13 }; +static const int uart3_pins[] = { 38, 39 }; +static const int ejtag_pins[] = { 31, 33, 35, 37, 39 }; +static const int pcm1_pins[] = { 12, 13, 14, 15 }; +static const int pcm2_pins[] = { 24, 25, 26, 27 }; +static const int spi_quad_pins[] = { 10, 23 }; +static const int spi_cs1_pins[] = { 9 }; +static const int pcm_spi_pins[] = { 4, 5, 6, 7 }; +static const int pcm_spi_int_pins[] = { 1 }; +static const int pcm_spi_rst_pins[] = { 2 }; +static const int pcm_spi_cs1_pins[] = { 3 }; +static const int pcm_spi_cs2_pins[] = { 10 }; +static const int pcm_spi_cs3_pins[] = { 23 }; +static const int pcm_spi_cs4_pins[] = { 21 }; +static const int pcm_spi_cs5_pins[] = { 9 }; +static const int pcm_spi_cs6_pins[] = { 28 }; +static const int pcm_spi_cs7_pins[] = { 29 }; +static const int pnand_pins[] = { 3, 8, 10, 11, 21, 22, 23, 24, 25, 26, 27, + 28, 29, 46, 47, 48, 49 }; +static const int gpio0_pins[] = { 0 }; +static const int gpio1_pins[] = { 1 }; +static const int gpio2_pins[] = { 2 }; +static const int gpio3_pins[] = { 3 }; +static const int gpio4_pins[] = { 4 }; +static const int gpio5_pins[] = { 5 }; +static const int gpio6_pins[] = { 6 }; +static const int gpio7_pins[] = { 7 }; +static const int gpio8_pins[] = { 8 }; +static const int gpio9_pins[] = { 9 }; +static const int gpio10_pins[] = { 10 }; +static const int gpio11_pins[] = { 11 }; +static const int gpio12_pins[] = { 12 }; +static const int gpio13_pins[] = { 13 }; +static const int gpio14_pins[] = { 14 }; +static const int gpio15_pins[] = { 15 }; +static const int gpio16_pins[] = { 16 }; +static const int gpio17_pins[] = { 17 }; +static const int gpio18_pins[] = { 18 }; +static const int gpio19_pins[] = { 19 }; +static const int gpio20_pins[] = { 20 }; +static const int gpio21_pins[] = { 21 }; +static const int gpio22_pins[] = { 22 }; +static const int gpio23_pins[] = { 23 }; +static const int gpio24_pins[] = { 24 }; +static const int gpio25_pins[] = { 25 }; +static const int gpio26_pins[] = { 26 }; +static const int gpio27_pins[] = { 27 }; +static const int gpio28_pins[] = { 28 }; +static const int gpio29_pins[] = { 29 }; +static const int gpio30_pins[] = { 30 }; +static const int gpio31_pins[] = { 31 }; +static const int gpio32_pins[] = { 32 }; +static const int gpio33_pins[] = { 33 }; +static const int gpio34_pins[] = { 34 }; +static const int gpio35_pins[] = { 35 }; +static const int gpio36_pins[] = { 36 }; +static const int gpio37_pins[] = { 37 }; +static const int gpio38_pins[] = { 38 }; +static const int gpio39_pins[] = { 39 }; +static const int gpio40_pins[] = { 40 }; +static const int gpio41_pins[] = { 41 }; +static const int pcie_reset0_pins[] = { 40 }; +static const int pcie_reset1_pins[] = { 41 }; + +static const struct pingroup pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("sipo", sipo), + PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), + PINCTRL_PIN_GROUP("uart2", uart2), + PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts), + PINCTRL_PIN_GROUP("uart3", uart3), + PINCTRL_PIN_GROUP("ejtag", ejtag), + PINCTRL_PIN_GROUP("pcm1", pcm1), + PINCTRL_PIN_GROUP("pcm2", pcm2), + PINCTRL_PIN_GROUP("spi_quad", spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int), + PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi_cs2", pcm_spi_cs2), + PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3), + PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4), + PINCTRL_PIN_GROUP("pcm_spi_cs5", pcm_spi_cs5), + PINCTRL_PIN_GROUP("pcm_spi_cs6", pcm_spi_cs6), + PINCTRL_PIN_GROUP("pcm_spi_cs7", pcm_spi_cs7), + PINCTRL_PIN_GROUP("pnand", pnand), + PINCTRL_PIN_GROUP("gpio0", gpio0), + PINCTRL_PIN_GROUP("gpio1", gpio1), + PINCTRL_PIN_GROUP("gpio2", gpio2), + PINCTRL_PIN_GROUP("gpio3", gpio3), + PINCTRL_PIN_GROUP("gpio4", gpio4), + PINCTRL_PIN_GROUP("gpio5", gpio5), + PINCTRL_PIN_GROUP("gpio6", gpio6), + PINCTRL_PIN_GROUP("gpio7", gpio7), + PINCTRL_PIN_GROUP("gpio8", gpio8), + PINCTRL_PIN_GROUP("gpio9", gpio9), + PINCTRL_PIN_GROUP("gpio10", gpio10), + PINCTRL_PIN_GROUP("gpio11", gpio11), + PINCTRL_PIN_GROUP("gpio12", gpio12), + PINCTRL_PIN_GROUP("gpio13", gpio13), + PINCTRL_PIN_GROUP("gpio14", gpio14), + PINCTRL_PIN_GROUP("gpio15", gpio15), + PINCTRL_PIN_GROUP("gpio16", gpio16), + PINCTRL_PIN_GROUP("gpio17", gpio17), + PINCTRL_PIN_GROUP("gpio18", gpio18), + PINCTRL_PIN_GROUP("gpio19", gpio19), + PINCTRL_PIN_GROUP("gpio20", gpio20), + PINCTRL_PIN_GROUP("gpio21", gpio21), + PINCTRL_PIN_GROUP("gpio22", gpio22), + PINCTRL_PIN_GROUP("gpio23", gpio23), + PINCTRL_PIN_GROUP("gpio24", gpio24), + PINCTRL_PIN_GROUP("gpio25", gpio25), + PINCTRL_PIN_GROUP("gpio26", gpio26), + PINCTRL_PIN_GROUP("gpio27", gpio27), + PINCTRL_PIN_GROUP("gpio28", gpio28), + PINCTRL_PIN_GROUP("gpio29", gpio29), + PINCTRL_PIN_GROUP("gpio30", gpio30), + PINCTRL_PIN_GROUP("gpio31", gpio31), + PINCTRL_PIN_GROUP("gpio32", gpio32), + PINCTRL_PIN_GROUP("gpio33", gpio33), + PINCTRL_PIN_GROUP("gpio34", gpio34), + PINCTRL_PIN_GROUP("gpio35", gpio35), + PINCTRL_PIN_GROUP("gpio36", gpio36), + PINCTRL_PIN_GROUP("gpio37", gpio37), + PINCTRL_PIN_GROUP("gpio38", gpio38), + PINCTRL_PIN_GROUP("gpio39", gpio39), + PINCTRL_PIN_GROUP("gpio40", gpio40), + PINCTRL_PIN_GROUP("gpio41", gpio41), + PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), +}; + +static const char *const pon_groups[] = { "pon" }; +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; +static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", + "uart3" }; +static const char *const jtag_groups[] = { "ejtag" }; +static const char *const pcm_groups[] = { "pcm1", "pcm2" }; +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; +static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int", + "pcm_spi_rst", + "pcm_spi_cs1", + "pcm_spi_cs2", + "pcm_spi_cs3", + "pcm_spi_cs4", + "pcm_spi_cs5", + "pcm_spi_cs6", + "pcm_spi_cs7" }; +static const char *const pnand_groups[] = { "pnand" }; +static const char *const pcie_reset_groups[] = { "pcie_reset0", + "pcie_reset1" }; +static const char *const gpio_groups[] = { "gpio40", "gpio41" }; +static const char *const pwm_groups[] = { "gpio0", "gpio1", + "gpio2", "gpio3", + "gpio4", "gpio5", + "gpio6", "gpio7", + "gpio8", "gpio9", + "gpio10", "gpio11", + "gpio12", "gpio13", + "gpio14", "gpio15", + "gpio16", "gpio17", + "gpio18", "gpio19", + "gpio20", "gpio21", + "gpio22", "gpio23", + "gpio24", "gpio25", + "gpio26", "gpio27", + "gpio28", "gpio29", + "gpio30", "gpio31", + "gpio32", "gpio37", + "gpio38", "gpio39", + "gpio40", "gpio41" }; +static const char *const phy1_led0_groups[] = { "gpio30", "gpio32", + "gpio34", "gpio36" }; +static const char *const phy2_led0_groups[] = { "gpio30", "gpio32", + "gpio34", "gpio36" }; +static const char *const phy3_led0_groups[] = { "gpio30", "gpio32", + "gpio34", "gpio36" }; +static const char *const phy4_led0_groups[] = { "gpio30", "gpio32", + "gpio34", "gpio36" }; +static const char *const phy1_led1_groups[] = { "gpio31", "gpio33", + "gpio35", "gpio37" }; +static const char *const phy2_led1_groups[] = { "gpio31", "gpio33", + "gpio35", "gpio37" }; +static const char *const phy3_led1_groups[] = { "gpio31", "gpio33", + "gpio35", "gpio37" }; +static const char *const phy4_led1_groups[] = { "gpio31", "gpio33", + "gpio35", "gpio37" }; + +static const struct airoha_pinctrl_func_group pon_func_group[] = { + { + .name = "pon", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_PON_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group sipo_func_group[] = { + { + .name = "sipo", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "sipo_rclk", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] = { + { + .name = "uart2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_UART2_MODE_MASK | + GPIO_UART2_CTS_RTS_MODE_MASK, + GPIO_UART2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart2_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_UART2_MODE_MASK | + GPIO_UART2_CTS_RTS_MODE_MASK, + GPIO_UART2_MODE_MASK | + GPIO_UART2_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_UART3_MODE_MASK, + GPIO_UART3_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group jtag_func_group[] = { + { + .name = "ejtag", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_CPU_EJTAG_EN, + CPU_EJTAG_EN_MASK, + CPU_EJTAG_EN_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_func_group[] = { + { + .name = "pcm1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group spi_func_group[] = { + { + .name = "spi_quad", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { + { + .name = "pcm_spi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_PCM_SPI_MODE_MASK, + GPIO_PCM_SPI_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_int", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_PCM_INT_MODE_MASK, + GPIO_PCM_INT_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_rst", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_PCM_RESET_MODE_MASK, + GPIO_PCM_RESET_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_PCM_SPI_CS1_MODE_MASK, + GPIO_PCM_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_FORCE_GPIO22_EN, + GPIO_PCM_SPI_CS2_MODE_MASK, + GPIO_PCM_SPI_CS2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_FORCE_GPIO22_EN, + GPIO_PCM_SPI_CS3_MODE_MASK, + GPIO_PCM_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_FORCE_GPIO22_EN, + GPIO_PCM_SPI_CS4_MODE_MASK, + GPIO_PCM_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs5", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_FORCE_GPIO22_EN, + GPIO_PCM_SPI_CS5_MODE_MASK, + GPIO_PCM_SPI_CS5_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs6", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_FORCE_GPIO22_EN, + GPIO_PCM_SPI_CS6_MODE_MASK, + GPIO_PCM_SPI_CS6_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs7", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_FORCE_GPIO22_EN, + GPIO_PCM_SPI_CS7_MODE_MASK, + GPIO_PCM_SPI_CS7_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pnand_func_group[] = { + { + .name = "pnand", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_FORCE_GPIO22_EN, + GPIO_PNAND_MODE_MASK, + GPIO_PNAND_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +/* + * On EN7528 a set PCIE_RESET{0,1}_GPIO bit routes the pad to its GPIO + * function, so the PCIe reset function must clear it. + */ +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { + { + .name = "pcie_reset0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_PCIE_RESET0_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "pcie_reset1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_PON_I2C_MODE, + GPIO_PCIE_RESET1_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +/* GPIO */ +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_PON_I2C_MODE, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } \ + +static const struct airoha_pinctrl_func_group gpio_func_group[] = { + AIROHA_PINCTRL_GPIO("gpio40", GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_GPIO("gpio41", GPIO_PCIE_RESET1_MASK), +}; + +/* PWM - AIROHA_PINCTRL_PWM and AIROHA_PINCTRL_PWM_EXT are shared */ +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_MUX, \ + REG_GPIO_FLASH_MODE_CFG, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } \ + +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } \ + +/* + * PWM on the PCIE_RESET pads additionally requires the pad to be + * routed to its GPIO function via the IOMUX. + */ +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_PON_I2C_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +static const struct airoha_pinctrl_func_group pwm_func_group[] = { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio32", GPIO32_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), +}; + +#define PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_PON_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED0_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +#define PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_PON_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED1_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +/* + * LED pad mapping (datasheet table 4-12): + * GPIO30: LAN0_LED0, GPIO32: LAN1_LED0, GPIO34: LAN2_LED0, GPIO36: LAN3_LED0 + * GPIO31: LAN0_LED1, GPIO33: LAN1_LED1, GPIO35: LAN2_LED1, GPIO37: LAN3_LED1 + */ +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { + PINCTRL_PHY_LED0("gpio30", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + PINCTRL_PHY_LED0("gpio32", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + PINCTRL_PHY_LED0("gpio34", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + PINCTRL_PHY_LED0("gpio36", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { + PINCTRL_PHY_LED0("gpio30", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + PINCTRL_PHY_LED0("gpio32", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + PINCTRL_PHY_LED0("gpio34", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + PINCTRL_PHY_LED0("gpio36", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { + PINCTRL_PHY_LED0("gpio30", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + PINCTRL_PHY_LED0("gpio32", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + PINCTRL_PHY_LED0("gpio34", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + PINCTRL_PHY_LED0("gpio36", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { + PINCTRL_PHY_LED0("gpio30", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + PINCTRL_PHY_LED0("gpio32", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + PINCTRL_PHY_LED0("gpio34", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + PINCTRL_PHY_LED0("gpio36", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { + PINCTRL_PHY_LED1("gpio31", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + PINCTRL_PHY_LED1("gpio33", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + PINCTRL_PHY_LED1("gpio35", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + PINCTRL_PHY_LED1("gpio37", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { + PINCTRL_PHY_LED1("gpio31", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + PINCTRL_PHY_LED1("gpio33", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + PINCTRL_PHY_LED1("gpio35", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + PINCTRL_PHY_LED1("gpio37", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { + PINCTRL_PHY_LED1("gpio31", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + PINCTRL_PHY_LED1("gpio33", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + PINCTRL_PHY_LED1("gpio35", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + PINCTRL_PHY_LED1("gpio37", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { + PINCTRL_PHY_LED1("gpio31", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + PINCTRL_PHY_LED1("gpio33", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + PINCTRL_PHY_LED1("gpio35", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + PINCTRL_PHY_LED1("gpio37", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func pinctrl_funcs[] = { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), + PINCTRL_FUNC_DESC("pnand", pnand), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("gpio", gpio), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), +}; + +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { + PINCTRL_CONF_DESC(0, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(1, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(19)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(28)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(29)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(30)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(31)), + PINCTRL_CONF_DESC(32, REG_GPIO_H_PU, BIT(0)), + PINCTRL_CONF_DESC(33, REG_GPIO_H_PU, BIT(1)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(2)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(3)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(4)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(5)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(6)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(7)), + PINCTRL_CONF_DESC(40, REG_I2C_SDA_PU, PCIE0_RESET_CONF_MASK), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, PCIE1_RESET_CONF_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_CONF_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, I2C_SCL_CONF_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, UART_TXD_CONF_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, UART_RXD_CONF_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_CONF_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_CLK_CONF_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MOSI_CONF_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, SPI_MISO_CONF_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { + PINCTRL_CONF_DESC(0, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(1, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(19)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(28)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(29)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(30)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(31)), + PINCTRL_CONF_DESC(32, REG_GPIO_H_PD, BIT(0)), + PINCTRL_CONF_DESC(33, REG_GPIO_H_PD, BIT(1)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(2)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(3)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(4)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(5)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(6)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(7)), + PINCTRL_CONF_DESC(40, REG_I2C_SDA_PD, PCIE0_RESET_CONF_MASK), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, PCIE1_RESET_CONF_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_CONF_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, I2C_SCL_CONF_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, UART_TXD_CONF_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, UART_RXD_CONF_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_CONF_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_CLK_CONF_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MOSI_CONF_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, SPI_MISO_CONF_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { + PINCTRL_CONF_DESC(0, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(1, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(19)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(28)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(29)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(30)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(31)), + PINCTRL_CONF_DESC(32, REG_GPIO_H_E2, BIT(0)), + PINCTRL_CONF_DESC(33, REG_GPIO_H_E2, BIT(1)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(2)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(3)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(4)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(5)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(6)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(7)), + PINCTRL_CONF_DESC(40, REG_I2C_SDA_E2, PCIE0_RESET_CONF_MASK), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, PCIE1_RESET_CONF_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_CONF_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, I2C_SCL_CONF_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, UART_TXD_CONF_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, UART_RXD_CONF_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_CONF_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_CLK_CONF_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MOSI_CONF_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, SPI_MISO_CONF_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { + PINCTRL_CONF_DESC(0, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(1, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(19)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(28)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(29)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(30)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(31)), + PINCTRL_CONF_DESC(32, REG_GPIO_H_E4, BIT(0)), + PINCTRL_CONF_DESC(33, REG_GPIO_H_E4, BIT(1)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(2)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(3)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(4)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(5)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(6)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(7)), + PINCTRL_CONF_DESC(40, REG_I2C_SDA_E4, PCIE0_RESET_CONF_MASK), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, PCIE1_RESET_CONF_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_CONF_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, I2C_SCL_CONF_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, UART_TXD_CONF_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, UART_RXD_CONF_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_CONF_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_CLK_CONF_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MOSI_CONF_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, SPI_MISO_CONF_MASK), +}; + +static const struct airoha_pinctrl_match_data pinctrl_match_data = { + .chip_scu_compatible = "econet,en7528-chip-scu", + .pinctrl_name = KBUILD_MODNAME, + .pinctrl_owner = THIS_MODULE, + .pins = pinctrl_pins, + .num_pins = ARRAY_SIZE(pinctrl_pins), + .grps = pinctrl_groups, + .num_grps = ARRAY_SIZE(pinctrl_groups), + .funcs = pinctrl_funcs, + .num_funcs = ARRAY_SIZE(pinctrl_funcs), + /* only GPIO0-GPIO15 can raise an interrupt */ + .num_irq_pins = 16, + .confs_info = { + [AIROHA_PINCTRL_CONFS_PULLUP] = { + .confs = pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] = { + .confs = pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { + .confs = pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { + .confs = pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), + }, + /* no PCIe reset open drain register on EN7528 */ + }, +}; + +static const struct of_device_id airoha_pinctrl_of_match[] = { + { .compatible = "econet,en7528-pinctrl", .data = &pinctrl_match_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); + +static struct platform_driver airoha_pinctrl_driver = { + .probe = airoha_pinctrl_probe, + .driver = { + .name = "pinctrl-airoha-en7528", + .of_match_table = airoha_pinctrl_of_match, + }, +}; +module_platform_driver(airoha_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Benjamin Larsson "); +MODULE_DESCRIPTION("Pinctrl driver for EcoNet EN7528 SoC"); From 25f42a33ecf914e6d8da6eed2cdf7ad86c9a904b Mon Sep 17 00:00:00 2001 From: Dhruvin Rajpura Date: Sun, 30 Aug 2026 12:29:38 +0800 Subject: [PATCH 007/106] dt-bindings: pinctrl: qcom,pmic-gpio: Document PMAU0102 GPIO support Add compatible string for the PMAU0102 PMIC GPIO block, which has 12 GPIOs, used on Nord platform. Signed-off-by: Dhruvin Rajpura Signed-off-by: Shawn Guo Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260830042939.144376-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index c27e24cb206f..77be0690c751 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -57,6 +57,7 @@ properties: - qcom,pm8994-gpio - qcom,pm8998-gpio - qcom,pma8084-gpio + - qcom,pmau0102-gpio - qcom,pmc8180-gpio - qcom,pmc8180c-gpio - qcom,pmc8380-gpio @@ -281,6 +282,7 @@ allOf: - qcom,pm8150l-gpio - qcom,pm8550-gpio - qcom,pm8550b-gpio + - qcom,pmau0102-gpio - qcom,pmc8180c-gpio - qcom,pmp8074-gpio - qcom,pms405-gpio @@ -496,6 +498,7 @@ $defs: - gpio1-gpio22 for pm8994 - gpio1-gpio26 for pm8998 - gpio1-gpio22 for pma8084 + - gpio1-gpio12 for pmau0102 - gpio1-gpio14 for pmcx0102 - gpio1-gpio4 for pmd8028 - gpio1-gpio4 for pmg1110 From 1cc8b87bd9719f5c496d27a1b4d2892947ba70d5 Mon Sep 17 00:00:00 2001 From: Dhruvin Rajpura Date: Sun, 30 Aug 2026 12:29:39 +0800 Subject: [PATCH 008/106] pinctrl: qcom: spmi-gpio: Add PMAU0102 GPIO support Add support for the PMAU0102 PMIC GPIO block, which has 12 GPIOs, used on Nord platform. Signed-off-by: Dhruvin Rajpura Signed-off-by: Shawn Guo Link: https://patch.msgid.link/20260830042939.144376-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 922c27177b5a..f6dc43e27b38 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1259,6 +1259,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8994-gpio", .data = (void *) 22 }, { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 }, { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 }, + { .compatible = "qcom,pmau0102-gpio", .data = (void *) 12 }, { .compatible = "qcom,pmc8380-gpio", .data = (void *) 10 }, { .compatible = "qcom,pmcx0102-gpio", .data = (void *)14 }, { .compatible = "qcom,pmd8028-gpio", .data = (void *) 4 }, From 7d65a9c8fa31e04f41bec15fc4a4f51e207d2aba Mon Sep 17 00:00:00 2001 From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:11 +0530 Subject: [PATCH 009/106] dt-bindings: pinctrl: qcom: Add Kuno TLMM Add device tree bindings for the Top Level Mode Multiplexer (TLMM) pin controller block found on the Qualcomm Kuno platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Hardeep Sharma Link: https://patch.msgid.link/20260827-kuno-soc-support-v5-8-6d47636a8f09@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- .../bindings/pinctrl/qcom,kuno-tlmm.yaml | 110 ++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,kuno-tlmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,kuno-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,kuno-tlmm.yaml new file mode 100644 index 000000000000..2250526dfae2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,kuno-tlmm.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,kuno-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Kuno TLMM block + +maintainers: + - Hardeep Sharma + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Kuno SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,kuno-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 55 + + gpio-line-names: + maxItems: 110 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-kuno-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-kuno-tlmm-state" + additionalProperties: false + +$defs: + qcom-kuno-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, audio_ref_clk, coex_uart, ebi2_lcd_a, + ebi2_lcd_cs, ebi2_lcd_reset, ebi2_lcd_te, emac_mdc, emac_mdio, + emac_pps_in, emac_ptp_aux, emac_ptp_pps, gcc_gp1_clk, + gcc_gp2_clk, gcc_gp3_clk, mi2s0_data0, mi2s0_data1, mi2s0_sck, + mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, + mi2s_mclk, nav_gpio, pci_e_rst, + pcie_clkreq_n, pll_bist_sync, pll_clk_aux, qdss_cti_trig0, + qdss_cti_trig1, qdss_cti_trig1_mire, qdss_gpio_traceclk, + qdss_gpio_tracectl, + qup0_se0, qup0_se1, qup0_se2, qup0_se3_mira, qup0_se3_mirb, + qup0_se4, sdc4_clk, sdc4_cmd, + sdc4_data, sdc4_tb_trig, sgmii_phy_intr, spmi_coex_clk, + spmi_coex_data, spmi_vgi_hwevent, uim1_clk, uim1_data, + uim1_present, uim1_reset, usb2phy_ac_en ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@f000000 { + compatible = "qcom,kuno-tlmm"; + reg = <0x0f000000 0x400000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 110>; + interrupt-controller; + #interrupt-cells = <2>; + + spmi-state { + pins = "gpio78", "gpio79"; + function = "spmi_vgi_hwevent"; + }; + }; +... From d0344c6510d050ee79c6aa3997f2c641168ebf08 Mon Sep 17 00:00:00 2001 From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:12 +0530 Subject: [PATCH 010/106] pinctrl: qcom: Add Kuno pinctrl driver Add the TLMM pinctrl driver for the Qualcomm Kuno platform, supporting 110 GPIOs and their pin multiplexing, pin configuration and gpiolib interface through the common pinctrl-msm driver. Signed-off-by: Hardeep Sharma Reviewed-by: Linus Walleij Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260827-kuno-soc-support-v5-9-6d47636a8f09@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/Kconfig.msm | 11 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-kuno.c | 801 ++++++++++++++++++++++++++++ 3 files changed, 813 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-kuno.c diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index 42875457b5fc..9b95bf8ecb22 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -153,6 +153,17 @@ config PINCTRL_KAANAPALI Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc Kaanapali platform. +config PINCTRL_KUNO + tristate "Qualcomm Kuno pin controller driver" + depends on ARM || COMPILE_TEST + default ARCH_QCOM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc Kuno platform. + Say Y here to compile statically, or M here to compile it as a + module. If unsure, say N. + config PINCTRL_MAILI tristate "Qualcomm Technologies Inc Maili pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 987a79f9d4c4..a29cbb55316b 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o obj-$(CONFIG_PINCTRL_IPQ9650) += pinctrl-ipq9650.o obj-$(CONFIG_PINCTRL_KAANAPALI) += pinctrl-kaanapali.o +obj-$(CONFIG_PINCTRL_KUNO) += pinctrl-kuno.o obj-$(CONFIG_PINCTRL_MAILI) += pinctrl-maili.o obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o diff --git a/drivers/pinctrl/qcom/pinctrl-kuno.c b/drivers/pinctrl/qcom/pinctrl-kuno.c new file mode 100644 index 000000000000..404065df2b9f --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-kuno.c @@ -0,0 +1,801 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_BASE 0x100000 +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_BASE + REG_SIZE * id, \ + .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +static const struct pinctrl_pin_desc kuno_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); + +enum kuno_functions { + msm_mux_gpio, + msm_mux_audio_ref_clk, + msm_mux_coex_uart, + msm_mux_ebi2_lcd_a, + msm_mux_ebi2_lcd_cs, + msm_mux_ebi2_lcd_reset, + msm_mux_ebi2_lcd_te, + msm_mux_emac_mdc, + msm_mux_emac_mdio, + msm_mux_emac_pps_in, + msm_mux_emac_ptp_aux, + msm_mux_emac_ptp_pps, + msm_mux_gcc_gp1_clk, + msm_mux_gcc_gp2_clk, + msm_mux_gcc_gp3_clk, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s_mclk, + msm_mux_nav_gpio, + msm_mux_pci_e_rst, + msm_mux_pcie_clkreq_n, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_qdss_cti_trig0, + msm_mux_qdss_cti_trig1, + msm_mux_qdss_cti_trig1_mire, + msm_mux_qdss_gpio_traceclk, + msm_mux_qdss_gpio_tracectl, + msm_mux_qup0_se0, + msm_mux_qup0_se1, + msm_mux_qup0_se2, + msm_mux_qup0_se3_mira, + msm_mux_qup0_se3_mirb, + msm_mux_qup0_se4, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_sdc4_tb_trig, + msm_mux_sgmii_phy_intr, + msm_mux_spmi_coex_clk, + msm_mux_spmi_coex_data, + msm_mux_spmi_vgi_hwevent, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb2phy_ac_en, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", +}; + +static const char * const audio_ref_clk_groups[] = { + "gpio62", +}; + +static const char * const coex_uart_groups[] = { + "gpio44", "gpio45", +}; + +static const char * const ebi2_lcd_a_groups[] = { + "gpio93", +}; + +static const char * const ebi2_lcd_cs_groups[] = { + "gpio94", +}; + +static const char * const ebi2_lcd_reset_groups[] = { + "gpio89", +}; + +static const char * const ebi2_lcd_te_groups[] = { + "gpio88", +}; + +static const char * const emac_mdc_groups[] = { + "gpio98", +}; + +static const char * const emac_mdio_groups[] = { + "gpio99", +}; + +static const char * const emac_pps_in_groups[] = { + "gpio88", +}; + +static const char * const emac_ptp_aux_groups[] = { + "gpio93", "gpio94", +}; + +static const char * const emac_ptp_pps_groups[] = { + "gpio93", "gpio94", +}; + +static const char * const gcc_gp1_clk_groups[] = { + "gpio34", +}; + +static const char * const gcc_gp2_clk_groups[] = { + "gpio46", +}; + +static const char * const gcc_gp3_clk_groups[] = { + "gpio35", +}; + +static const char * const mi2s0_data0_groups[] = { + "gpio13", +}; + +static const char * const mi2s0_data1_groups[] = { + "gpio14", +}; + +static const char * const mi2s0_sck_groups[] = { + "gpio15", +}; + +static const char * const mi2s0_ws_groups[] = { + "gpio12", +}; + +static const char * const mi2s1_data0_groups[] = { + "gpio17", +}; + +static const char * const mi2s1_data1_groups[] = { + "gpio18", +}; + +static const char * const mi2s1_sck_groups[] = { + "gpio19", +}; + +static const char * const mi2s1_ws_groups[] = { + "gpio16", +}; + +static const char * const mi2s_mclk_groups[] = { + "gpio62", +}; + +static const char * const nav_gpio_groups[] = { + "gpio31", "gpio32", "gpio33", +}; + +static const char * const pci_e_rst_groups[] = { + "gpio57", +}; + +static const char * const pcie_clkreq_n_groups[] = { + "gpio56", +}; + +static const char * const pll_bist_sync_groups[] = { + "gpio47", +}; + +static const char * const pll_clk_aux_groups[] = { + "gpio54", +}; + +static const char * const qdss_cti_trig0_groups[] = { + "gpio16", "gpio17", "gpio54", "gpio55", "gpio60", "gpio84", "gpio101", + "gpio102", +}; + +static const char * const qdss_cti_trig1_groups[] = { + "gpio16", "gpio17", "gpio54", "gpio55", "gpio65", "gpio66", "gpio101", + "gpio102", +}; +static const char * const qdss_cti_trig1_mire_groups[] = { + "gpio65", "gpio66", +}; + +static const char * const qdss_gpio_traceclk_groups[] = { + "gpio8", +}; + +static const char * const qdss_gpio_tracectl_groups[] = { + "gpio9", +}; + +static const char * const qup0_se0_groups[] = { + "gpio14", "gpio18", "gpio19", "gpio48", "gpio49", "gpio92", "gpio101", +}; + +static const char * const qup0_se1_groups[] = { + "gpio14", "gpio63", "gpio64", "gpio65", "gpio66", "gpio92", "gpio101", +}; + +static const char * const qup0_se2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio14", "gpio92", "gpio101", +}; + +static const char * const qup0_se3_mira_groups[] = { + "gpio8", "gpio9", "gpio14", "gpio16", "gpio17", "gpio92", "gpio101", +}; + +static const char * const qup0_se3_mirb_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char * const qup0_se4_groups[] = { + "gpio10", "gpio11", "gpio14", "gpio80", "gpio81", "gpio92", "gpio101", +}; + +static const char * const sdc4_clk_groups[] = { + "gpio103", +}; + +static const char * const sdc4_cmd_groups[] = { + "gpio102", +}; + +static const char * const sdc4_data_groups[] = { + "gpio104", "gpio105", "gpio106", "gpio107", +}; + +static const char * const sdc4_tb_trig_groups[] = { + "gpio101", +}; + +static const char * const sgmii_phy_intr_groups[] = { + "gpio91", +}; + +static const char * const spmi_coex_clk_groups[] = { + "gpio76", +}; + +static const char * const spmi_coex_data_groups[] = { + "gpio75", +}; + +static const char * const spmi_vgi_hwevent_groups[] = { + "gpio78", "gpio79", +}; + +static const char * const uim1_clk_groups[] = { + "gpio3", +}; + +static const char * const uim1_data_groups[] = { + "gpio0", +}; + +static const char * const uim1_present_groups[] = { + "gpio1", +}; + +static const char * const uim1_reset_groups[] = { + "gpio2", +}; + +static const char * const usb2phy_ac_en_groups[] = { + "gpio90", +}; + +static const struct pinfunction kuno_functions[] = { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(coex_uart), + MSM_PIN_FUNCTION(ebi2_lcd_a), + MSM_PIN_FUNCTION(ebi2_lcd_cs), + MSM_PIN_FUNCTION(ebi2_lcd_reset), + MSM_PIN_FUNCTION(ebi2_lcd_te), + MSM_PIN_FUNCTION(emac_mdc), + MSM_PIN_FUNCTION(emac_mdio), + MSM_PIN_FUNCTION(emac_pps_in), + MSM_PIN_FUNCTION(emac_ptp_aux), + MSM_PIN_FUNCTION(emac_ptp_pps), + MSM_PIN_FUNCTION(gcc_gp1_clk), + MSM_PIN_FUNCTION(gcc_gp2_clk), + MSM_PIN_FUNCTION(gcc_gp3_clk), + MSM_PIN_FUNCTION(mi2s0_data0), + MSM_PIN_FUNCTION(mi2s0_data1), + MSM_PIN_FUNCTION(mi2s0_sck), + MSM_PIN_FUNCTION(mi2s0_ws), + MSM_PIN_FUNCTION(mi2s1_data0), + MSM_PIN_FUNCTION(mi2s1_data1), + MSM_PIN_FUNCTION(mi2s1_sck), + MSM_PIN_FUNCTION(mi2s1_ws), + MSM_PIN_FUNCTION(mi2s_mclk), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(pci_e_rst), + MSM_PIN_FUNCTION(pcie_clkreq_n), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(qdss_cti_trig0), + MSM_PIN_FUNCTION(qdss_cti_trig1), + MSM_PIN_FUNCTION(qdss_cti_trig1_mire), + MSM_PIN_FUNCTION(qdss_gpio_traceclk), + MSM_PIN_FUNCTION(qdss_gpio_tracectl), + MSM_PIN_FUNCTION(qup0_se0), + MSM_PIN_FUNCTION(qup0_se1), + MSM_PIN_FUNCTION(qup0_se2), + MSM_PIN_FUNCTION(qup0_se3_mira), + MSM_PIN_FUNCTION(qup0_se3_mirb), + MSM_PIN_FUNCTION(qup0_se4), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sdc4_data), + MSM_PIN_FUNCTION(sdc4_tb_trig), + MSM_PIN_FUNCTION(sgmii_phy_intr), + MSM_PIN_FUNCTION(spmi_coex_clk), + MSM_PIN_FUNCTION(spmi_coex_data), + MSM_PIN_FUNCTION(spmi_vgi_hwevent), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(usb2phy_ac_en), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup kuno_groups[] = { + [0] = PINGROUP(0, uim1_data, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, uim1_present, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, uim1_reset, _, _, _, _, _, _, _, _), + [3] = PINGROUP(3, uim1_clk, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, qup0_se2, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, qup0_se2, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, qup0_se2, _, _, _, _, _, _, _, _), + [7] = PINGROUP(7, qup0_se2, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, qup0_se3_mira, _, qdss_gpio_traceclk, _, _, _, _, _, _), + [9] = PINGROUP(9, qup0_se3_mira, _, qdss_gpio_tracectl, _, _, _, _, _, _), + [10] = PINGROUP(10, qup0_se4, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup0_se4, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, mi2s0_ws, qup0_se3_mirb, _, _, _, _, _, _, _), + [13] = PINGROUP(13, mi2s0_data0, qup0_se3_mirb, _, _, _, _, _, _, _), + [14] = PINGROUP(14, mi2s0_data1, qup0_se3_mirb, qup0_se0, qup0_se1, qup0_se2, + qup0_se3_mira, qup0_se4, _, _), + [15] = PINGROUP(15, mi2s0_sck, qup0_se3_mirb, _, _, _, _, _, _, _), + [16] = PINGROUP(16, mi2s1_ws, qup0_se3_mira, qdss_cti_trig1, qdss_cti_trig0, + _, _, _, _, _), + [17] = PINGROUP(17, mi2s1_data0, qup0_se3_mira, qdss_cti_trig1, qdss_cti_trig0, + _, _, _, _, _), + [18] = PINGROUP(18, mi2s1_data1, qup0_se0, _, _, _, _, _, _, _), + [19] = PINGROUP(19, mi2s1_sck, qup0_se0, _, _, _, _, _, _, _), + [20] = PINGROUP(20, _, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, _, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, _, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, _, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, _, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, _, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, _, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, _, _, _, _, _, _, _, _, _), + [29] = PINGROUP(29, _, _, _, _, _, _, _, _, _), + [30] = PINGROUP(30, _, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, nav_gpio, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, nav_gpio, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, _, gcc_gp1_clk, _, _, _, _, _, _, _), + [35] = PINGROUP(35, _, _, gcc_gp3_clk, _, _, _, _, _, _), + [36] = PINGROUP(36, _, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, _, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, _, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, _, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, _, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, coex_uart, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, coex_uart, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, _, _, _, gcc_gp2_clk, _, _, _, _, _), + [47] = PINGROUP(47, _, pll_bist_sync, _, _, _, _, _, _, _), + [48] = PINGROUP(48, qup0_se0, _, _, _, _, _, _, _, _), + [49] = PINGROUP(49, qup0_se0, _, _, _, _, _, _, _, _), + [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, _, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, qdss_cti_trig1, qdss_cti_trig0, pll_clk_aux, _, _, _, _, _, _), + [55] = PINGROUP(55, qdss_cti_trig1, qdss_cti_trig0, _, _, _, _, _, _, _), + [56] = PINGROUP(56, pcie_clkreq_n, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, pci_e_rst, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, _, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, qdss_cti_trig0, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, mi2s_mclk, audio_ref_clk, _, _, _, _, _, _, _), + [63] = PINGROUP(63, qup0_se1, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, qup0_se1, _, _, _, _, _, _, _, _), + [65] = PINGROUP(65, qup0_se1, qdss_cti_trig1, qdss_cti_trig1_mire, _, _, _, _, _, _), + [66] = PINGROUP(66, qup0_se1, qdss_cti_trig1, qdss_cti_trig1_mire, _, _, _, _, _, _), + [67] = PINGROUP(67, _, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, _, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, _, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, _, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, _, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, _, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, _, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, _, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, spmi_coex_data, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, spmi_coex_clk, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, spmi_vgi_hwevent, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, spmi_vgi_hwevent, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, qup0_se4, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, qup0_se4, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, _, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, _, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, qdss_cti_trig0, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, _, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, ebi2_lcd_te, emac_pps_in, _, _, _, _, _, _, _), + [89] = PINGROUP(89, ebi2_lcd_reset, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, usb2phy_ac_en, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, sgmii_phy_intr, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, qup0_se0, qup0_se1, qup0_se2, qup0_se3_mira, qup0_se4, _, _, _, _), + [93] = PINGROUP(93, ebi2_lcd_a, emac_ptp_pps, emac_ptp_aux, _, _, _, _, _, _), + [94] = PINGROUP(94, ebi2_lcd_cs, emac_ptp_pps, emac_ptp_aux, _, _, _, _, _, _), + [95] = PINGROUP(95, _, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, _, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, emac_mdc, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, emac_mdio, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, sdc4_tb_trig, qdss_cti_trig1, qdss_cti_trig0, qup0_se0, + qup0_se1, qup0_se2, qup0_se3_mira, qup0_se4, _), + [102] = PINGROUP(102, sdc4_cmd, qdss_cti_trig1, qdss_cti_trig0, _, _, _, _, _, _), + [103] = PINGROUP(103, sdc4_clk, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, sdc4_data, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, sdc4_data, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, sdc4_data, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, sdc4_data, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, _, _, _, _, _, _, _, _, _), +}; + +static const struct msm_gpio_wakeirq_map kuno_pdc_map[] = { + { 1, 62 }, { 2, 83 }, { 4, 59 }, { 5, 107 }, { 6, 112 }, { 7, 119 }, + { 8, 123 }, { 10, 52 }, { 11, 73 }, { 12, 74 }, { 13, 75 }, { 14, 76 }, + { 15, 77 }, { 16, 81 }, { 17, 82 }, { 18, 80 }, { 19, 100 }, { 21, 88 }, + { 22, 99 }, { 23, 84 }, { 24, 85 }, { 25, 97 }, { 26, 86 }, { 27, 102 }, + { 28, 87 }, { 35, 103 }, { 43, 90 }, { 44, 60 }, { 45, 61 }, { 46, 104 }, + { 47, 89 }, { 48, 105 }, { 49, 106 }, { 50, 101 }, { 52, 109 }, { 53, 79 }, + { 54, 110 }, { 55, 111 }, { 56, 78 }, { 57, 71 }, { 60, 113 }, { 61, 114 }, + { 63, 115 }, { 64, 116 }, { 65, 57 }, { 66, 117 }, { 68, 64 }, { 69, 118 }, + { 71, 108 }, { 73, 120 }, { 74, 121 }, { 76, 47 }, { 77, 122 }, { 78, 65 }, + { 79, 66 }, { 80, 124 }, { 81, 125 }, { 82, 126 }, { 83, 127 }, { 84, 93 }, + { 85, 128 }, { 86, 129 }, { 87, 70 }, { 88, 130 }, { 96, 68 }, { 98, 50 }, + { 99, 67 }, { 100, 51 }, { 101, 53 }, { 102, 54 }, { 103, 98 }, { 104, 91 }, + { 105, 69 }, { 106, 55 }, { 107, 56 }, { 109, 72 }, +}; + +static const struct msm_pinctrl_soc_data kuno_tlmm = { + .pins = kuno_pins, + .npins = ARRAY_SIZE(kuno_pins), + .functions = kuno_functions, + .nfunctions = ARRAY_SIZE(kuno_functions), + .groups = kuno_groups, + .ngroups = ARRAY_SIZE(kuno_groups), + .ngpios = 110, + .wakeirq_map = kuno_pdc_map, + .nwakeirq_map = ARRAY_SIZE(kuno_pdc_map), +}; + +static int kuno_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &kuno_tlmm); +} + +static const struct of_device_id kuno_tlmm_of_match[] = { + { .compatible = "qcom,kuno-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, kuno_tlmm_of_match); + +static struct platform_driver kuno_tlmm_driver = { + .driver = { + .name = "kuno-tlmm", + .of_match_table = kuno_tlmm_of_match, + }, + .probe = kuno_tlmm_probe, +}; + +static int __init kuno_tlmm_init(void) +{ + return platform_driver_register(&kuno_tlmm_driver); +} +arch_initcall(kuno_tlmm_init); + +static void __exit kuno_tlmm_exit(void) +{ + platform_driver_unregister(&kuno_tlmm_driver); +} +module_exit(kuno_tlmm_exit); + +MODULE_DESCRIPTION("QTI Kuno TLMM driver"); +MODULE_LICENSE("GPL"); From 5f29a103f2755afa4486da9cb7dc314f45ff8fa8 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 3 Sep 2026 13:46:12 +0200 Subject: [PATCH 011/106] pinctrl: intel: Move intel_pinctrl_get_soc_data() upper in the code While it's exported function, move it upper in the code to be on top of the local user. This brings a consistency to the follow change that will introduce similar helper for the intel_pinctrl_probe_by_hid(). Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 261ec2ee63ef..fd02409a2415 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1714,18 +1714,6 @@ int intel_pinctrl_probe_by_hid(struct platform_device *pdev) } EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_hid, "PINCTRL_INTEL"); -int intel_pinctrl_probe_by_uid(struct platform_device *pdev) -{ - const struct intel_pinctrl_soc_data *data; - - data = intel_pinctrl_get_soc_data(pdev); - if (IS_ERR(data)) - return PTR_ERR(data); - - return intel_pinctrl_probe(pdev, data); -} -EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_uid, "PINCTRL_INTEL"); - const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) { const struct intel_pinctrl_soc_data * const *table; @@ -1757,6 +1745,18 @@ const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_ } EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, "PINCTRL_INTEL"); +int intel_pinctrl_probe_by_uid(struct platform_device *pdev) +{ + const struct intel_pinctrl_soc_data *data; + + data = intel_pinctrl_get_soc_data(pdev); + if (IS_ERR(data)) + return PTR_ERR(data); + + return intel_pinctrl_probe(pdev, data); +} +EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_uid, "PINCTRL_INTEL"); + static bool __intel_gpio_is_direct_irq(u32 value) { return (value & PADCFG0_GPIROUTIOXAPIC) && From c824f2278af4e072ce7b796189af72315c195cf3 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 3 Sep 2026 13:46:13 +0200 Subject: [PATCH 012/106] pinctrl: intel: constify parameter in intel_pinctrl_get_soc_data() The parameter of intel_pinctrl_get_soc_data() is not going to be modified. Mark it with const qualifier. Suggested-by: Mika Westerberg Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 4 ++-- drivers/pinctrl/intel/pinctrl-intel.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index fd02409a2415..08790bff2951 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1714,11 +1714,11 @@ int intel_pinctrl_probe_by_hid(struct platform_device *pdev) } EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_hid, "PINCTRL_INTEL"); -const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) +const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(const struct platform_device *pdev) { const struct intel_pinctrl_soc_data * const *table; const struct intel_pinctrl_soc_data *data; - struct device *dev = &pdev->dev; + const struct device *dev = &pdev->dev; table = device_get_match_data(dev); if (table) { diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index b5476b9de0db..b7ee7fd0c5f2 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -225,7 +225,7 @@ struct intel_pinctrl_soc_data { size_t ncommunities; }; -const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev); +const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(const struct platform_device *pdev); struct intel_pad_context; struct intel_community_context; From c016587866e573fa8dff50c3bdae9734c4418099 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 3 Sep 2026 13:46:14 +0200 Subject: [PATCH 013/106] pinctrl: intel: Try to retrieve driver data for pure platform drivers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Denverton pinctrl device can be instantiated by the Intel LPC driver as an MFD platform device named "denverton-pinctrl". On affected systems the platform device does not carry the INTC3000 ACPI match data itself. As a result, intel_pinctrl_probe_by_hid() fails to obtain the SoC data using device_get_match_data() and returns -ENODATA. This might be also true for other platforms that can be enumerated by ACPI _HID. Fix the above by trying the pure platform driver data in case the firmware node is not set or doesn't carry the necessary information. Reported-by: Radek Válko Closes: https://lore.kernel.org/r/20260827184259.32386-1-rvalko@lipicko.cz Tested-by: Radek Válko Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 08790bff2951..1363301098d5 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1702,13 +1702,32 @@ int intel_pinctrl_probe(struct platform_device *pdev, } EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe, "PINCTRL_INTEL"); +static const struct intel_pinctrl_soc_data * +intel_pinctrl_get_soc_data_by_hid(const struct platform_device *pdev) +{ + const struct intel_pinctrl_soc_data *data; + const struct device *dev = &pdev->dev; + const struct platform_device_id *id; + + data = device_get_match_data(dev); + if (data) + return data; + + id = platform_get_device_id(pdev); + if (!id) + return ERR_PTR(-ENODEV); + + data = (const struct intel_pinctrl_soc_data *)id->driver_data; + return data ?: ERR_PTR(-ENODATA); +} + int intel_pinctrl_probe_by_hid(struct platform_device *pdev) { const struct intel_pinctrl_soc_data *data; - data = device_get_match_data(&pdev->dev); - if (!data) - return -ENODATA; + data = intel_pinctrl_get_soc_data_by_hid(pdev); + if (IS_ERR(data)) + return PTR_ERR(data); return intel_pinctrl_probe(pdev, data); } From d4f74023be11eb9aea9a8c0b0582f20aa2c2640b Mon Sep 17 00:00:00 2001 From: Xilin Wu Date: Tue, 1 Sep 2026 16:47:58 +0800 Subject: [PATCH 014/106] dt-bindings: pinctrl: qcom,sc8280xp-tlmm: allow gpio-line-names The SC8280XP TLMM GPIO controller exposes 230 GPIO lines. Allow boards to provide descriptive names for these lines and constrain the list to the number of GPIOs exposed by the controller. Reviewed-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Signed-off-by: Xilin Wu Link: https://patch.msgid.link/20260901-q8b-dts-v1-5-7de0b6a73d08@radxa.com Signed-off-by: Bartosz Golaszewski --- .../devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml index ed344deaf8b9..ebc3a8b34a4c 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml @@ -27,6 +27,9 @@ properties: gpio-reserved-ranges: true + gpio-line-names: + maxItems: 230 + patternProperties: "-state$": oneOf: From 11e4c9251295b4513a244cb73bc902b5f6a34f8e Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Fri, 4 Sep 2026 13:56:21 +0200 Subject: [PATCH 015/106] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input/output-disable The list of allowed pinconf properties already includes input-enable and output-enable, but omits their -disable counterparts. Each pair controls the same bit. Where enable (set) is supported so is disable (clear). Add input-disable and output-disable to the list. Reviewed-by: Linus Walleij Reviewed-by: Geert Uytterhoeven Signed-off-by: Josua Mayer Link: https://patch.msgid.link/20260904-rzg2-sr-boards-v8-2-94c4674927e8@solid-run.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index fb1fe1ea759f..a551996623c0 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -135,7 +135,9 @@ additionalProperties: gpios: true input: true input-enable: true + input-disable: true output-enable: true + output-disable: true output-high: true output-low: true line-name: true From 342a7ce6d2f7b13037f0f993ca760779c53834d9 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 4 Sep 2026 15:54:21 +0300 Subject: [PATCH 016/106] pinctrl: renesas: rzg2l: Generalize power source code The current functions used to get/set the pin power source check the OTHER_POC register, which is specific to the RZ/G3L SoC only. To allow the code to be extended for other power source functionalities (e.g. I3C on RZ/G3S), generalize the functions used to get/set the pin power source. For this, introduce the struct rzg2l_register_masks data structure whose purpose is to store SoC specific register bit masks. The members of this structure are then used in rzg2l_caps_to_pwr_reg() to retrieve the bitmask corresponding to a SoC specific power source capability. The conversion between HW specific power source values and SW specific power source values is now handled through rzg2l_pwr_reg_val_to_ps() and rzg2l_ps_to_pwr_reg_val(). Finally, to keep the code generic, the register update in rzg2l_set_power_source() was changed to a read-modify-write approach to cover all cases. Reviewed-by: Geert Uytterhoeven Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea Link: https://patch.msgid.link/20260904125425.412632-2-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 188 +++++++++++++++--------- 1 file changed, 117 insertions(+), 71 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index e3e24ce917c9..40bf8f9e8f2f 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -187,6 +187,7 @@ #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ +#define PVDD_MASK 0x3 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ @@ -271,6 +272,23 @@ struct rzg2l_register_offsets { u16 other_poc; }; +/** + * struct rzg2l_register_masks - Masks for different RZ/G2L pinctrl functionalities + * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask + * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask + * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask + */ +struct rzg2l_register_masks { + union { + /* RZ/G3L masks */ + struct { + u8 other_poc_pvdd1833_oth_awo_poc; + u8 other_poc_pvdd1833_oth_iso_poc; + u8 other_poc_wdtovf_n_poc; + }; + }; +}; + /** * enum rzg2l_iolh_index - starting indices in IOLH specific arrays * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source @@ -291,6 +309,8 @@ enum rzg2l_iolh_index { /** * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets + * @masks: hardware specific masks for various functionalities available in + * the registers described by regs * @iolh_groupa_ua: IOLH group A uA specific values * @iolh_groupb_ua: IOLH group B uA specific values * @iolh_groupc_ua: IOLH group C uA specific values @@ -304,6 +324,7 @@ enum rzg2l_iolh_index { */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; + const struct rzg2l_register_masks masks; u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; @@ -1064,29 +1085,74 @@ static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, } static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, - u32 caps, u8 *mask) + const struct rzg2l_register_masks *masks, + u32 caps, u16 *offset, u8 *mask) { - if (caps & PIN_CFG_IO_VMC_SD0) - return SD_CH(regs->sd_ch, 0); - if (caps & PIN_CFG_IO_VMC_SD1) - return SD_CH(regs->sd_ch, 1); - if (caps & PIN_CFG_IO_VMC_SD2) - return regs->sd_ch2; - if (caps & PIN_CFG_IO_VMC_ETH0) - return ETH_POC(regs->eth_poc, 0); - if (caps & PIN_CFG_IO_VMC_ETH1) - return ETH_POC(regs->eth_poc, 1); - if (caps & PIN_CFG_IO_VMC_QSPI) - return QSPI; - if (caps & PIN_CFG_OTHER_POC_MASK) { - if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC) - *mask = BIT(0); - else if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC) - *mask = BIT(1); - else - *mask = BIT(2); + *mask = PVDD_MASK; - return OTHER_POC; + if (caps & PIN_CFG_IO_VMC_SD0) { + *offset = SD_CH(regs->sd_ch, 0); + return 0; + } + if (caps & PIN_CFG_IO_VMC_SD1) { + *offset = SD_CH(regs->sd_ch, 1); + return 0; + } + if (caps & PIN_CFG_IO_VMC_SD2) { + *offset = regs->sd_ch2; + return 0; + } + if (caps & PIN_CFG_IO_VMC_ETH0) { + *offset = ETH_POC(regs->eth_poc, 0); + return 0; + } + if (caps & PIN_CFG_IO_VMC_ETH1) { + *offset = ETH_POC(regs->eth_poc, 1); + return 0; + } + if (caps & PIN_CFG_IO_VMC_QSPI) { + *offset = regs->qspi; + return 0; + } + if (caps & PIN_CFG_OTHER_POC_MASK) { + *offset = regs->other_poc; + if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC) + *mask = masks->other_poc_pvdd1833_oth_awo_poc; + else if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC) + *mask = masks->other_poc_pvdd1833_oth_iso_poc; + else + *mask = masks->other_poc_wdtovf_n_poc; + return 0; + } + + return -EINVAL; +} + +static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps) +{ + switch (val) { + case PVDD_1800: + return 1800; + case PVDD_2500: + return 2500; + case PVDD_3300: + return 3300; + } + + return -EINVAL; +} + +static int rzg2l_ps_to_pwr_reg_val(u32 ps, u32 caps) +{ + switch (ps) { + case 1800: + return PVDD_1800; + case 2500: + if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) + return -EINVAL; + return PVDD_2500; + case 3300: + return PVDD_3300; } return -EINVAL; @@ -1096,76 +1162,51 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps { const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs = &hwcfg->regs; - u8 val, mask; - int pwr_reg; + const struct rzg2l_register_masks *masks = &hwcfg->masks; + u8 mask, val; + u16 offset; + int ret; if (caps & PIN_CFG_SOFT_PS) return pctrl->settings[pin].power_source; - pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask); - if (pwr_reg < 0) - return pwr_reg; + ret = rzg2l_caps_to_pwr_reg(regs, masks, caps, &offset, &mask); + if (ret) + return ret; - val = readb(pctrl->base + pwr_reg); - if (pwr_reg == OTHER_POC) - val = field_get(mask, val); + val = readb(pctrl->base + offset); - switch (val) { - case PVDD_1800: - return 1800; - case PVDD_2500: - return 2500; - case PVDD_3300: - return 3300; - default: - /* Should not happen. */ - return -EINVAL; - } + return rzg2l_pwr_reg_val_to_ps(field_get(mask, val), caps); } static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) { const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs = &hwcfg->regs; - u8 poc_val, val, mask; - int pwr_reg; + const struct rzg2l_register_masks *masks = &hwcfg->masks; + u16 offset; + u8 mask; + int ret; if (caps & PIN_CFG_SOFT_PS) { pctrl->settings[pin].power_source = ps; return 0; } - switch (ps) { - case 1800: - poc_val = PVDD_1800; - break; - case 2500: - if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) - return -EINVAL; - poc_val = PVDD_2500; - break; - case 3300: - poc_val = PVDD_3300; - break; - default: - return -EINVAL; - } + ret = rzg2l_caps_to_pwr_reg(regs, masks, caps, &offset, &mask); + if (ret) + return ret; - pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask); - if (pwr_reg < 0) - return pwr_reg; + ret = rzg2l_ps_to_pwr_reg_val(ps, caps); + if (ret < 0) + return ret; - if (pwr_reg == OTHER_POC) { - scoped_guard(raw_spinlock_irqsave, &pctrl->lock) { - val = readb(pctrl->base + pwr_reg); - if (poc_val) - val |= mask; - else - val &= ~mask; - writeb(val, pctrl->base + pwr_reg); - } - } else { - writeb(poc_val, pctrl->base + pwr_reg); + scoped_guard(raw_spinlock_irqsave, &pctrl->lock) { + u8 tmp = readb(pctrl->base + offset); + + tmp &= ~mask; + tmp |= field_prep(mask, ret); + writeb(tmp, pctrl->base + offset); } pctrl->settings[pin].power_source = ps; @@ -3821,6 +3862,11 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg = { .oen = 0x3018, .other_poc = OTHER_POC, }, + .masks = { + .other_poc_pvdd1833_oth_awo_poc = BIT(0), + .other_poc_pvdd1833_oth_iso_poc = BIT(1), + .other_poc_wdtovf_n_poc = BIT(2), + }, .iolh_groupa_ua = { /* 1v8 power source */ [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000, From 382ec4d1e27a95ef23080c9e3bca8b44d31736f9 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 4 Sep 2026 15:54:22 +0300 Subject: [PATCH 017/106] pinctrl: renesas: rzg2l: Drop defines present in struct rzg2l_hwcfg Drop the QSPI and OTHER_POC register defines, which are SoC specific and accessible through struct rzg2l_hwcfg::{qspi, other_poc}. While at it move the assignement of rzg2l_hwcfg->regs->qspi upper to have the initializations as sorted (by offsets) as possible. Reviewed-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea Link: https://patch.msgid.link/20260904125425.412632-3-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 40bf8f9e8f2f..c17983aafcf5 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -181,8 +181,6 @@ #define SMT(off) (0x3400 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) -#define QSPI (0x3008) /* known on RZ/{G2L,G2LC,G2UL,Five} only */ -#define OTHER_POC (0x3028) /* known on RZ/G3L only */ #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ @@ -3840,9 +3838,9 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { .regs = { .pwpr = 0x3014, .sd_ch = 0x3000, + .qspi = 0x3008, .eth_poc = 0x300c, .oen = 0x3018, - .qspi = QSPI, }, .iolh_groupa_ua = { /* 3v3 power source */ @@ -3860,7 +3858,7 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg = { .sd_ch2 = 0x3024, .eth_poc = 0x3010, .oen = 0x3018, - .other_poc = OTHER_POC, + .other_poc = 0x3028, }, .masks = { .other_poc_pvdd1833_oth_awo_poc = BIT(0), From 5e1e9d0cd8f366cedac88b7463126da989704e35 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 4 Sep 2026 15:54:23 +0300 Subject: [PATCH 018/106] pinctrl: renesas: rzg2l: Unify power source handling The previous code handled power sources using a mixture of power source specific definitions and lookups in the available_ps[] array. Unify the power source handling by introducing struct rzg2l_pinctrl_ps_desc, whose purpose is to describe a power source through its power source value, associated register value, associated capabilities (e.g. Ethernet), and associated IOLH index. Introduce two new functions, rzg2l_ps_to_desc() and rzg2l_pwr_reg_val_to_desc(), using the RZG2L_PINCTRL_PS_DESC_MEMBER_TO_DESC_FUNC() macro, as their implementations are similar. These functions retrieve a power source descriptor based on either a power source value or a power source register value. Other functions that need to perform power source specific operations can call them to retrieve the corresponding power source descriptor. The register values for the soft power sources were kept to zero since they are not used across the driver's code. Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260904125425.412632-4-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 162 ++++++++++++++++-------- 1 file changed, 108 insertions(+), 54 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index c17983aafcf5..6696e32909c3 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -182,9 +182,6 @@ #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) -#define PVDD_2500 2 /* I/O domain voltage 2.5V */ -#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ -#define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ #define PVDD_MASK 0x3 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ @@ -289,12 +286,14 @@ struct rzg2l_register_masks { /** * enum rzg2l_iolh_index - starting indices in IOLH specific arrays + * @RZG2L_IOLH_IDX_NA: index N/A (to be used for error checking) * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source * @RZG2L_IOLH_IDX_MAX: maximum index */ enum rzg2l_iolh_index { + RZG2L_IOLH_IDX_NA = -1, RZG2L_IOLH_IDX_1V8 = 0, RZG2L_IOLH_IDX_2V5 = 4, RZG2L_IOLH_IDX_3V3 = 8, @@ -445,7 +444,85 @@ struct rzg2l_pinctrl { u32 clone_offset; }; -static const u16 available_ps[] = { 1800, 2500, 3300 }; +/** + * struct rzg2l_pinctrl_ps_desc - RZ/G2L power source descriptor + * @caps: Capabilities that applies to the power source + * @iolh_index: IOLH index + * @ps: Power source value + * @pwr_reg_val: Power source register value + */ +struct rzg2l_pinctrl_ps_desc { + u32 caps; + enum rzg2l_iolh_index iolh_index; + u16 ps; + u16 pwr_reg_val; +}; + +#define RZG2L_PINCTRL_PS_DESC(_ps, _pwr_reg_val, _caps, _iolh_index) \ + { \ + .ps = _ps, \ + .pwr_reg_val = _pwr_reg_val, \ + .caps = _caps, \ + .iolh_index = _iolh_index, \ + } + +static const struct rzg2l_pinctrl_ps_desc available_ps[] = { + /* Ethernet I/O voltage domains */ + RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1, + RZG2L_IOLH_IDX_1V8), + RZG2L_PINCTRL_PS_DESC(2500, 2, PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1, + RZG2L_IOLH_IDX_2V5), + RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1, + RZG2L_IOLH_IDX_3V3), + + /* SD I/O voltage domains */ + RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_IO_VMC_SD0 | PIN_CFG_IO_VMC_SD1 | + PIN_CFG_IO_VMC_SD2, RZG2L_IOLH_IDX_1V8), + RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_IO_VMC_SD0 | PIN_CFG_IO_VMC_SD1 | + PIN_CFG_IO_VMC_SD2, RZG2L_IOLH_IDX_3V3), + + /* QSPI I/O voltage domains */ + RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_IO_VMC_QSPI, RZG2L_IOLH_IDX_1V8), + RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_IO_VMC_QSPI, RZG2L_IOLH_IDX_3V3), + + /* AWO I/O voltage domains */ + RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_PVDD1833_OTH_AWO_POC, + RZG2L_IOLH_IDX_1V8), + RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_PVDD1833_OTH_AWO_POC, + RZG2L_IOLH_IDX_3V3), + + /* ISO I/O voltage domains */ + RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_PVDD1833_OTH_ISO_POC, + RZG2L_IOLH_IDX_1V8), + RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_PVDD1833_OTH_ISO_POC, + RZG2L_IOLH_IDX_3V3), + + /* WDTOVF I/O voltage domains */ + RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_WDTOVF_N_POC, RZG2L_IOLH_IDX_1V8), + RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_WDTOVF_N_POC, RZG2L_IOLH_IDX_3V3), + + /* Software voltage domains */ + RZG2L_PINCTRL_PS_DESC(1800, 0, PIN_CFG_SOFT_PS, RZG2L_IOLH_IDX_1V8), + RZG2L_PINCTRL_PS_DESC(2500, 0, PIN_CFG_SOFT_PS, RZG2L_IOLH_IDX_2V5), + RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_SOFT_PS, RZG2L_IOLH_IDX_3V3), +}; + +#define RZG2L_PINCTRL_PS_DESC_MEMBER_TO_DESC_FUNC(_name, _desc_member, _caps) \ +static const struct rzg2l_pinctrl_ps_desc *_name(u16 _desc_member, u32 _caps) \ +{ \ + for (unsigned int i = 0; i < ARRAY_SIZE(available_ps); i++) { \ + if (available_ps[i]._desc_member != _desc_member) \ + continue; \ + \ + if (available_ps[i].caps & _caps) \ + return &available_ps[i]; \ + } \ + \ + return NULL; \ +} + +RZG2L_PINCTRL_PS_DESC_MEMBER_TO_DESC_FUNC(rzg2l_ps_to_desc, ps, caps) +RZG2L_PINCTRL_PS_DESC_MEMBER_TO_DESC_FUNC(rzg2l_pwr_reg_val_to_desc, pwr_reg_val, caps) static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, u64 pincfg, @@ -1126,34 +1203,26 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, return -EINVAL; } -static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps) +static int rzg2l_pwr_reg_val_to_ps(u16 pwr_reg_val, u32 caps) { - switch (val) { - case PVDD_1800: - return 1800; - case PVDD_2500: - return 2500; - case PVDD_3300: - return 3300; - } + const struct rzg2l_pinctrl_ps_desc *desc; - return -EINVAL; + desc = rzg2l_pwr_reg_val_to_desc(pwr_reg_val, caps); + if (!desc) + return -EINVAL; + + return desc->ps; } -static int rzg2l_ps_to_pwr_reg_val(u32 ps, u32 caps) +static int rzg2l_ps_to_pwr_reg_val(u16 ps, u32 caps) { - switch (ps) { - case 1800: - return PVDD_1800; - case 2500: - if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) - return -EINVAL; - return PVDD_2500; - case 3300: - return PVDD_3300; - } + const struct rzg2l_pinctrl_ps_desc *desc; - return -EINVAL; + desc = rzg2l_ps_to_desc(ps, caps); + if (!desc) + return -EINVAL; + + return desc->pwr_reg_val; } static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) @@ -1212,32 +1281,11 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps return 0; } -static bool rzg2l_ps_is_supported(u16 ps) +static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps, u32 caps) { - unsigned int i; + const struct rzg2l_pinctrl_ps_desc *desc = rzg2l_ps_to_desc(ps, caps); - for (i = 0; i < ARRAY_SIZE(available_ps); i++) { - if (available_ps[i] == ps) - return true; - } - - return false; -} - -static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(available_ps); i++) { - if (available_ps[i] == ps) - break; - } - - /* - * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have - * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source - */ - return i * RZG2L_IOLH_MAX_DS_ENTRIES; + return desc ? desc->iolh_index : RZG2L_IOLH_IDX_NA; } static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val) @@ -1622,7 +1670,11 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, ret = rzg2l_get_power_source(pctrl, _pin, cfg); if (ret < 0) return ret; - iolh_idx = rzg2l_ps_to_iolh_idx(ret); + + iolh_idx = rzg2l_ps_to_iolh_idx(ret, cfg); + if (iolh_idx == RZG2L_IOLH_IDX_NA) + return -EINVAL; + val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val); break; @@ -1818,8 +1870,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, /* Apply power source. */ if (settings.power_source != pctrl->settings[_pin].power_source) { - ret = rzg2l_ps_is_supported(settings.power_source); - if (!ret) + if (!rzg2l_ps_to_desc(settings.power_source, cfg)) return -EINVAL; /* Apply power source. */ @@ -1833,7 +1884,10 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, enum rzg2l_iolh_index iolh_idx; int val; - iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source); + iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source, cfg); + if (iolh_idx == RZG2L_IOLH_IDX_NA) + return -EINVAL; + ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx, settings.drive_strength_ua); if (!ret) From 16a06509a9b7754e2ebd7a66c47abd00e5fbc5a6 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 4 Sep 2026 15:54:24 +0300 Subject: [PATCH 019/106] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document missing I3C power source option The I3C pins on the Renesas RZ/G3S SoC can be powered at either 1.2V or 1.8V. Document the missing 1.2V power source option. Acked-by: Conor Dooley Reviewed-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Tested-by: Wolfram Sang Link: https://patch.msgid.link/20260904125425.412632-5-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index a551996623c0..ec5d6d52f07b 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -129,7 +129,7 @@ additionalProperties: enum: [ 33, 50, 66, 100 ] power-source: description: I/O voltage in millivolt. - enum: [ 1800, 2500, 3300 ] + enum: [ 1200, 1800, 2500, 3300 ] slew-rate: true gpio-hog: true gpios: true From ec5202ccfa24791acf64146d5bac6b63ce234f95 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 4 Sep 2026 15:54:25 +0300 Subject: [PATCH 020/106] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting I3C power source The Renesas RZ/G3S I3C pins can be powered at either 1.8V or 1.2V. The pin controller provides a register to select between these two options. Update the Renesas RZ/G2L pin controller driver to allow selecting the I3C power source on RZ/G3S SoC. Tested-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://patch.msgid.link/20260904125425.412632-6-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 6696e32909c3..9bf3743dc1ce 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -70,6 +70,7 @@ #define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ #define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ #define PIN_CFG_IO_VMC_SD2 BIT(22) /* known on RZ/G3L only */ +#define PIN_CFG_IO_VMC_I3C BIT(23) #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ @@ -256,6 +257,7 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = { * @oen: OEN register offset * @qspi: QSPI register offset * @other_poc: OTHER_POC register offset + * @i3c_set: I3C_SET register offset */ struct rzg2l_register_offsets { u16 pwpr; @@ -265,6 +267,7 @@ struct rzg2l_register_offsets { u16 oen; u16 qspi; u16 other_poc; + u16 i3c_set; }; /** @@ -272,6 +275,7 @@ struct rzg2l_register_offsets { * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask + * @i3c_set_poc: I3C_SET_POC mask */ struct rzg2l_register_masks { union { @@ -281,6 +285,11 @@ struct rzg2l_register_masks { u8 other_poc_pvdd1833_oth_iso_poc; u8 other_poc_wdtovf_n_poc; }; + + /* RZ/G3S masks */ + struct { + u8 i3c_set_poc; + }; }; }; @@ -394,6 +403,7 @@ struct rzg2l_pinctrl_pin_settings { * @oen: Output Enable register cache * @other_poc: OTHER_POC register cache * @qspi: QSPI registers cache + * @i3c_set: I3C_SET register cache */ struct rzg2l_pinctrl_reg_cache { u8 *p; @@ -413,6 +423,7 @@ struct rzg2l_pinctrl_reg_cache { u8 oen; u8 other_poc; u8 qspi; + u8 i3c_set; }; struct rzg2l_pinctrl { @@ -501,6 +512,10 @@ static const struct rzg2l_pinctrl_ps_desc available_ps[] = { RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_WDTOVF_N_POC, RZG2L_IOLH_IDX_1V8), RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_WDTOVF_N_POC, RZG2L_IOLH_IDX_3V3), + /* I3C I/O voltage domains */ + RZG2L_PINCTRL_PS_DESC(1200, 1, PIN_CFG_IO_VMC_I3C, RZG2L_IOLH_IDX_NA), + RZG2L_PINCTRL_PS_DESC(1800, 0, PIN_CFG_IO_VMC_I3C, RZG2L_IOLH_IDX_NA), + /* Software voltage domains */ RZG2L_PINCTRL_PS_DESC(1800, 0, PIN_CFG_SOFT_PS, RZG2L_IOLH_IDX_1V8), RZG2L_PINCTRL_PS_DESC(2500, 0, PIN_CFG_SOFT_PS, RZG2L_IOLH_IDX_2V5), @@ -1199,6 +1214,11 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, *mask = masks->other_poc_wdtovf_n_poc; return 0; } + if (caps & PIN_CFG_IO_VMC_I3C) { + *offset = regs->i3c_set; + *mask = masks->i3c_set_poc; + return 0; + } return -EINVAL; } @@ -2570,6 +2590,8 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) }, { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) }, { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) }, + { "I3C_SDA", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IEN | PIN_CFG_IO_VMC_I3C)) }, + { "I3C_SCL", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IEN | PIN_CFG_IO_VMC_I3C)) }, { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, @@ -3792,6 +3814,8 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev) cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen); if (regs->other_poc) cache->other_poc = readb(pctrl->base + regs->other_poc); + if (regs->i3c_set) + cache->i3c_set = readb(pctrl->base + regs->i3c_set); if (pctrl->syscon) { int ret; @@ -3834,6 +3858,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) writeb(cache->qspi, pctrl->base + regs->qspi); if (regs->other_poc) writeb(cache->other_poc, pctrl->base + regs->other_poc); + if (regs->i3c_set) + writeb(cache->i3c_set, pctrl->base + regs->i3c_set); raw_spin_lock_irqsave(&pctrl->lock, flags); rzg2l_oen_write_with_pwpr(pctrl, cache->oen); @@ -3950,8 +3976,12 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = { .pwpr = 0x3000, .sd_ch = 0x3004, .eth_poc = 0x3010, + .i3c_set = 0x301c, .oen = 0x3018, }, + .masks = { + .i3c_set_poc = BIT(2), + }, .iolh_groupa_ua = { /* 1v8 power source */ [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000, From fd702f895c5addaf9dea1a9d765209592e469cf0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Sep 2026 10:11:31 +0200 Subject: [PATCH 021/106] pinctrl: qcom: Drop marketing name-prefixed duplicate defines They are identical and of no use. Drop them and use the common MSM prefix. Assisted-by: LLM Signed-off-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://patch.msgid.link/20260907-topic-tlmm_define_cleanup-v1-1-accdf7859e4b@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/pinctrl-apq8064.c | 188 ++++----- drivers/pinctrl/qcom/pinctrl-apq8084.c | 502 ++++++++++++------------- drivers/pinctrl/qcom/pinctrl-ipq4019.c | 208 +++++----- drivers/pinctrl/qcom/pinctrl-ipq8064.c | 208 +++++----- drivers/pinctrl/qcom/pinctrl-msm.h | 25 -- 5 files changed, 553 insertions(+), 578 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c index a47f3d4f1ea5..acfe1c554162 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c @@ -214,17 +214,17 @@ static const unsigned int sdc3_data_pins[] = { 95 }; gpio##id##_pins, \ ARRAY_SIZE(gpio##id##_pins)), \ .funcs = (int[]){ \ - APQ_MUX_gpio, \ - APQ_MUX_##f1, \ - APQ_MUX_##f2, \ - APQ_MUX_##f3, \ - APQ_MUX_##f4, \ - APQ_MUX_##f5, \ - APQ_MUX_##f6, \ - APQ_MUX_##f7, \ - APQ_MUX_##f8, \ - APQ_MUX_##f9, \ - APQ_MUX_##f10, \ + msm_mux_gpio, \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ }, \ .nfuncs = 11, \ .ctl_reg = 0x1000 + 0x10 * id, \ @@ -276,48 +276,48 @@ static const unsigned int sdc3_data_pins[] = { 95 }; } enum apq8064_functions { - APQ_MUX_cam_mclk, - APQ_MUX_codec_mic_i2s, - APQ_MUX_codec_spkr_i2s, - APQ_MUX_gp_clk_0a, - APQ_MUX_gp_clk_0b, - APQ_MUX_gp_clk_1a, - APQ_MUX_gp_clk_1b, - APQ_MUX_gp_clk_2a, - APQ_MUX_gp_clk_2b, - APQ_MUX_gpio, - APQ_MUX_gsbi1, - APQ_MUX_gsbi2, - APQ_MUX_gsbi3, - APQ_MUX_gsbi4, - APQ_MUX_gsbi4_cam_i2c, - APQ_MUX_gsbi5, - APQ_MUX_gsbi5_spi_cs1, - APQ_MUX_gsbi5_spi_cs2, - APQ_MUX_gsbi5_spi_cs3, - APQ_MUX_gsbi6, - APQ_MUX_gsbi6_spi_cs1, - APQ_MUX_gsbi6_spi_cs2, - APQ_MUX_gsbi6_spi_cs3, - APQ_MUX_gsbi7, - APQ_MUX_gsbi7_spi_cs1, - APQ_MUX_gsbi7_spi_cs2, - APQ_MUX_gsbi7_spi_cs3, - APQ_MUX_gsbi_cam_i2c, - APQ_MUX_hdmi, - APQ_MUX_mi2s, - APQ_MUX_riva_bt, - APQ_MUX_riva_fm, - APQ_MUX_riva_wlan, - APQ_MUX_sdc2, - APQ_MUX_sdc4, - APQ_MUX_slimbus, - APQ_MUX_spkr_i2s, - APQ_MUX_tsif1, - APQ_MUX_tsif2, - APQ_MUX_usb2_hsic, - APQ_MUX_ps_hold, - APQ_MUX_NA, + msm_mux_cam_mclk, + msm_mux_codec_mic_i2s, + msm_mux_codec_spkr_i2s, + msm_mux_gp_clk_0a, + msm_mux_gp_clk_0b, + msm_mux_gp_clk_1a, + msm_mux_gp_clk_1b, + msm_mux_gp_clk_2a, + msm_mux_gp_clk_2b, + msm_mux_gpio, + msm_mux_gsbi1, + msm_mux_gsbi2, + msm_mux_gsbi3, + msm_mux_gsbi4, + msm_mux_gsbi4_cam_i2c, + msm_mux_gsbi5, + msm_mux_gsbi5_spi_cs1, + msm_mux_gsbi5_spi_cs2, + msm_mux_gsbi5_spi_cs3, + msm_mux_gsbi6, + msm_mux_gsbi6_spi_cs1, + msm_mux_gsbi6_spi_cs2, + msm_mux_gsbi6_spi_cs3, + msm_mux_gsbi7, + msm_mux_gsbi7_spi_cs1, + msm_mux_gsbi7_spi_cs2, + msm_mux_gsbi7_spi_cs3, + msm_mux_gsbi_cam_i2c, + msm_mux_hdmi, + msm_mux_mi2s, + msm_mux_riva_bt, + msm_mux_riva_fm, + msm_mux_riva_wlan, + msm_mux_sdc2, + msm_mux_sdc4, + msm_mux_slimbus, + msm_mux_spkr_i2s, + msm_mux_tsif1, + msm_mux_tsif2, + msm_mux_usb2_hsic, + msm_mux_ps_hold, + msm_mux_NA, }; static const char * const cam_mclk_groups[] = { @@ -457,47 +457,47 @@ static const char * const usb2_hsic_groups[] = { }; static const struct pinfunction apq8064_functions[] = { - APQ_PIN_FUNCTION(cam_mclk), - APQ_PIN_FUNCTION(codec_mic_i2s), - APQ_PIN_FUNCTION(codec_spkr_i2s), - APQ_PIN_FUNCTION(gp_clk_0a), - APQ_PIN_FUNCTION(gp_clk_0b), - APQ_PIN_FUNCTION(gp_clk_1a), - APQ_PIN_FUNCTION(gp_clk_1b), - APQ_PIN_FUNCTION(gp_clk_2a), - APQ_PIN_FUNCTION(gp_clk_2b), - APQ_PIN_FUNCTION(gpio), - APQ_PIN_FUNCTION(gsbi1), - APQ_PIN_FUNCTION(gsbi2), - APQ_PIN_FUNCTION(gsbi3), - APQ_PIN_FUNCTION(gsbi4), - APQ_PIN_FUNCTION(gsbi4_cam_i2c), - APQ_PIN_FUNCTION(gsbi5), - APQ_PIN_FUNCTION(gsbi5_spi_cs1), - APQ_PIN_FUNCTION(gsbi5_spi_cs2), - APQ_PIN_FUNCTION(gsbi5_spi_cs3), - APQ_PIN_FUNCTION(gsbi6), - APQ_PIN_FUNCTION(gsbi6_spi_cs1), - APQ_PIN_FUNCTION(gsbi6_spi_cs2), - APQ_PIN_FUNCTION(gsbi6_spi_cs3), - APQ_PIN_FUNCTION(gsbi7), - APQ_PIN_FUNCTION(gsbi7_spi_cs1), - APQ_PIN_FUNCTION(gsbi7_spi_cs2), - APQ_PIN_FUNCTION(gsbi7_spi_cs3), - APQ_PIN_FUNCTION(gsbi_cam_i2c), - APQ_PIN_FUNCTION(hdmi), - APQ_PIN_FUNCTION(mi2s), - APQ_PIN_FUNCTION(riva_bt), - APQ_PIN_FUNCTION(riva_fm), - APQ_PIN_FUNCTION(riva_wlan), - APQ_PIN_FUNCTION(sdc2), - APQ_PIN_FUNCTION(sdc4), - APQ_PIN_FUNCTION(slimbus), - APQ_PIN_FUNCTION(spkr_i2s), - APQ_PIN_FUNCTION(tsif1), - APQ_PIN_FUNCTION(tsif2), - APQ_PIN_FUNCTION(usb2_hsic), - APQ_PIN_FUNCTION(ps_hold), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(codec_mic_i2s), + MSM_PIN_FUNCTION(codec_spkr_i2s), + MSM_PIN_FUNCTION(gp_clk_0a), + MSM_PIN_FUNCTION(gp_clk_0b), + MSM_PIN_FUNCTION(gp_clk_1a), + MSM_PIN_FUNCTION(gp_clk_1b), + MSM_PIN_FUNCTION(gp_clk_2a), + MSM_PIN_FUNCTION(gp_clk_2b), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gsbi1), + MSM_PIN_FUNCTION(gsbi2), + MSM_PIN_FUNCTION(gsbi3), + MSM_PIN_FUNCTION(gsbi4), + MSM_PIN_FUNCTION(gsbi4_cam_i2c), + MSM_PIN_FUNCTION(gsbi5), + MSM_PIN_FUNCTION(gsbi5_spi_cs1), + MSM_PIN_FUNCTION(gsbi5_spi_cs2), + MSM_PIN_FUNCTION(gsbi5_spi_cs3), + MSM_PIN_FUNCTION(gsbi6), + MSM_PIN_FUNCTION(gsbi6_spi_cs1), + MSM_PIN_FUNCTION(gsbi6_spi_cs2), + MSM_PIN_FUNCTION(gsbi6_spi_cs3), + MSM_PIN_FUNCTION(gsbi7), + MSM_PIN_FUNCTION(gsbi7_spi_cs1), + MSM_PIN_FUNCTION(gsbi7_spi_cs2), + MSM_PIN_FUNCTION(gsbi7_spi_cs3), + MSM_PIN_FUNCTION(gsbi_cam_i2c), + MSM_PIN_FUNCTION(hdmi), + MSM_PIN_FUNCTION(mi2s), + MSM_PIN_FUNCTION(riva_bt), + MSM_PIN_FUNCTION(riva_fm), + MSM_PIN_FUNCTION(riva_wlan), + MSM_PIN_FUNCTION(sdc2), + MSM_PIN_FUNCTION(sdc4), + MSM_PIN_FUNCTION(slimbus), + MSM_PIN_FUNCTION(spkr_i2s), + MSM_PIN_FUNCTION(tsif1), + MSM_PIN_FUNCTION(tsif2), + MSM_PIN_FUNCTION(usb2_hsic), + MSM_PIN_FUNCTION(ps_hold), }; static const struct msm_pingroup apq8064_groups[] = { diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c index e3c1f86aba7d..67d06f6988ef 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8084.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c @@ -329,14 +329,14 @@ static const unsigned int sdc2_data_pins[] = { 152 }; gpio##id##_pins, \ ARRAY_SIZE(gpio##id##_pins)), \ .funcs = (int[]){ \ - APQ_MUX_gpio, \ - APQ_MUX_##f1, \ - APQ_MUX_##f2, \ - APQ_MUX_##f3, \ - APQ_MUX_##f4, \ - APQ_MUX_##f5, \ - APQ_MUX_##f6, \ - APQ_MUX_##f7 \ + msm_mux_gpio, \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7 \ }, \ .nfuncs = 8, \ .ctl_reg = 0x1000 + 0x10 * id, \ @@ -386,128 +386,128 @@ static const unsigned int sdc2_data_pins[] = { 152 }; } enum apq8084_functions { - APQ_MUX_adsp_ext, - APQ_MUX_audio_ref, - APQ_MUX_blsp_i2c1, - APQ_MUX_blsp_i2c2, - APQ_MUX_blsp_i2c3, - APQ_MUX_blsp_i2c4, - APQ_MUX_blsp_i2c5, - APQ_MUX_blsp_i2c6, - APQ_MUX_blsp_i2c7, - APQ_MUX_blsp_i2c8, - APQ_MUX_blsp_i2c9, - APQ_MUX_blsp_i2c10, - APQ_MUX_blsp_i2c11, - APQ_MUX_blsp_i2c12, - APQ_MUX_blsp_spi1, - APQ_MUX_blsp_spi1_cs1, - APQ_MUX_blsp_spi1_cs2, - APQ_MUX_blsp_spi1_cs3, - APQ_MUX_blsp_spi2, - APQ_MUX_blsp_spi3, - APQ_MUX_blsp_spi3_cs1, - APQ_MUX_blsp_spi3_cs2, - APQ_MUX_blsp_spi3_cs3, - APQ_MUX_blsp_spi4, - APQ_MUX_blsp_spi5, - APQ_MUX_blsp_spi6, - APQ_MUX_blsp_spi7, - APQ_MUX_blsp_spi8, - APQ_MUX_blsp_spi9, - APQ_MUX_blsp_spi10, - APQ_MUX_blsp_spi10_cs1, - APQ_MUX_blsp_spi10_cs2, - APQ_MUX_blsp_spi10_cs3, - APQ_MUX_blsp_spi11, - APQ_MUX_blsp_spi12, - APQ_MUX_blsp_uart1, - APQ_MUX_blsp_uart2, - APQ_MUX_blsp_uart3, - APQ_MUX_blsp_uart4, - APQ_MUX_blsp_uart5, - APQ_MUX_blsp_uart6, - APQ_MUX_blsp_uart7, - APQ_MUX_blsp_uart8, - APQ_MUX_blsp_uart9, - APQ_MUX_blsp_uart10, - APQ_MUX_blsp_uart11, - APQ_MUX_blsp_uart12, - APQ_MUX_blsp_uim1, - APQ_MUX_blsp_uim2, - APQ_MUX_blsp_uim3, - APQ_MUX_blsp_uim4, - APQ_MUX_blsp_uim5, - APQ_MUX_blsp_uim6, - APQ_MUX_blsp_uim7, - APQ_MUX_blsp_uim8, - APQ_MUX_blsp_uim9, - APQ_MUX_blsp_uim10, - APQ_MUX_blsp_uim11, - APQ_MUX_blsp_uim12, - APQ_MUX_cam_mclk0, - APQ_MUX_cam_mclk1, - APQ_MUX_cam_mclk2, - APQ_MUX_cam_mclk3, - APQ_MUX_cci_async, - APQ_MUX_cci_async_in0, - APQ_MUX_cci_i2c0, - APQ_MUX_cci_i2c1, - APQ_MUX_cci_timer0, - APQ_MUX_cci_timer1, - APQ_MUX_cci_timer2, - APQ_MUX_cci_timer3, - APQ_MUX_cci_timer4, - APQ_MUX_edp_hpd, - APQ_MUX_gcc_gp1, - APQ_MUX_gcc_gp2, - APQ_MUX_gcc_gp3, - APQ_MUX_gcc_obt, - APQ_MUX_gcc_vtt, - APQ_MUX_gp_mn, - APQ_MUX_gp_pdm0, - APQ_MUX_gp_pdm1, - APQ_MUX_gp_pdm2, - APQ_MUX_gp0_clk, - APQ_MUX_gp1_clk, - APQ_MUX_gpio, - APQ_MUX_hdmi_cec, - APQ_MUX_hdmi_ddc, - APQ_MUX_hdmi_dtest, - APQ_MUX_hdmi_hpd, - APQ_MUX_hdmi_rcv, - APQ_MUX_hsic, - APQ_MUX_ldo_en, - APQ_MUX_ldo_update, - APQ_MUX_mdp_vsync, - APQ_MUX_pci_e0, - APQ_MUX_pci_e0_n, - APQ_MUX_pci_e0_rst, - APQ_MUX_pci_e1, - APQ_MUX_pci_e1_rst, - APQ_MUX_pci_e1_rst_n, - APQ_MUX_pci_e1_clkreq_n, - APQ_MUX_pri_mi2s, - APQ_MUX_qua_mi2s, - APQ_MUX_sata_act, - APQ_MUX_sata_devsleep, - APQ_MUX_sata_devsleep_n, - APQ_MUX_sd_write, - APQ_MUX_sdc_emmc_mode, - APQ_MUX_sdc3, - APQ_MUX_sdc4, - APQ_MUX_sec_mi2s, - APQ_MUX_slimbus, - APQ_MUX_spdif_tx, - APQ_MUX_spkr_i2s, - APQ_MUX_spkr_i2s_ws, - APQ_MUX_spss_geni, - APQ_MUX_ter_mi2s, - APQ_MUX_tsif1, - APQ_MUX_tsif2, - APQ_MUX_uim, - APQ_MUX_uim_batt_alarm, - APQ_MUX_NA, + msm_mux_adsp_ext, + msm_mux_audio_ref, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, + msm_mux_blsp_i2c7, + msm_mux_blsp_i2c8, + msm_mux_blsp_i2c9, + msm_mux_blsp_i2c10, + msm_mux_blsp_i2c11, + msm_mux_blsp_i2c12, + msm_mux_blsp_spi1, + msm_mux_blsp_spi1_cs1, + msm_mux_blsp_spi1_cs2, + msm_mux_blsp_spi1_cs3, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi3_cs1, + msm_mux_blsp_spi3_cs2, + msm_mux_blsp_spi3_cs3, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_spi6, + msm_mux_blsp_spi7, + msm_mux_blsp_spi8, + msm_mux_blsp_spi9, + msm_mux_blsp_spi10, + msm_mux_blsp_spi10_cs1, + msm_mux_blsp_spi10_cs2, + msm_mux_blsp_spi10_cs3, + msm_mux_blsp_spi11, + msm_mux_blsp_spi12, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uart3, + msm_mux_blsp_uart4, + msm_mux_blsp_uart5, + msm_mux_blsp_uart6, + msm_mux_blsp_uart7, + msm_mux_blsp_uart8, + msm_mux_blsp_uart9, + msm_mux_blsp_uart10, + msm_mux_blsp_uart11, + msm_mux_blsp_uart12, + msm_mux_blsp_uim1, + msm_mux_blsp_uim2, + msm_mux_blsp_uim3, + msm_mux_blsp_uim4, + msm_mux_blsp_uim5, + msm_mux_blsp_uim6, + msm_mux_blsp_uim7, + msm_mux_blsp_uim8, + msm_mux_blsp_uim9, + msm_mux_blsp_uim10, + msm_mux_blsp_uim11, + msm_mux_blsp_uim12, + msm_mux_cam_mclk0, + msm_mux_cam_mclk1, + msm_mux_cam_mclk2, + msm_mux_cam_mclk3, + msm_mux_cci_async, + msm_mux_cci_async_in0, + msm_mux_cci_i2c0, + msm_mux_cci_i2c1, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_edp_hpd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gcc_obt, + msm_mux_gcc_vtt, + msm_mux_gp_mn, + msm_mux_gp_pdm0, + msm_mux_gp_pdm1, + msm_mux_gp_pdm2, + msm_mux_gp0_clk, + msm_mux_gp1_clk, + msm_mux_gpio, + msm_mux_hdmi_cec, + msm_mux_hdmi_ddc, + msm_mux_hdmi_dtest, + msm_mux_hdmi_hpd, + msm_mux_hdmi_rcv, + msm_mux_hsic, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_mdp_vsync, + msm_mux_pci_e0, + msm_mux_pci_e0_n, + msm_mux_pci_e0_rst, + msm_mux_pci_e1, + msm_mux_pci_e1_rst, + msm_mux_pci_e1_rst_n, + msm_mux_pci_e1_clkreq_n, + msm_mux_pri_mi2s, + msm_mux_qua_mi2s, + msm_mux_sata_act, + msm_mux_sata_devsleep, + msm_mux_sata_devsleep_n, + msm_mux_sd_write, + msm_mux_sdc_emmc_mode, + msm_mux_sdc3, + msm_mux_sdc4, + msm_mux_sec_mi2s, + msm_mux_slimbus, + msm_mux_spdif_tx, + msm_mux_spkr_i2s, + msm_mux_spkr_i2s_ws, + msm_mux_spss_geni, + msm_mux_ter_mi2s, + msm_mux_tsif1, + msm_mux_tsif2, + msm_mux_uim, + msm_mux_uim_batt_alarm, + msm_mux_NA, }; static const char * const gpio_groups[] = { @@ -897,127 +897,127 @@ static const char * const uim_batt_alarm_groups[] = { "gpio102" }; static const struct pinfunction apq8084_functions[] = { - APQ_PIN_FUNCTION(adsp_ext), - APQ_PIN_FUNCTION(audio_ref), - APQ_PIN_FUNCTION(blsp_i2c1), - APQ_PIN_FUNCTION(blsp_i2c2), - APQ_PIN_FUNCTION(blsp_i2c3), - APQ_PIN_FUNCTION(blsp_i2c4), - APQ_PIN_FUNCTION(blsp_i2c5), - APQ_PIN_FUNCTION(blsp_i2c6), - APQ_PIN_FUNCTION(blsp_i2c7), - APQ_PIN_FUNCTION(blsp_i2c8), - APQ_PIN_FUNCTION(blsp_i2c9), - APQ_PIN_FUNCTION(blsp_i2c10), - APQ_PIN_FUNCTION(blsp_i2c11), - APQ_PIN_FUNCTION(blsp_i2c12), - APQ_PIN_FUNCTION(blsp_spi1), - APQ_PIN_FUNCTION(blsp_spi1_cs1), - APQ_PIN_FUNCTION(blsp_spi1_cs2), - APQ_PIN_FUNCTION(blsp_spi1_cs3), - APQ_PIN_FUNCTION(blsp_spi2), - APQ_PIN_FUNCTION(blsp_spi3), - APQ_PIN_FUNCTION(blsp_spi3_cs1), - APQ_PIN_FUNCTION(blsp_spi3_cs2), - APQ_PIN_FUNCTION(blsp_spi3_cs3), - APQ_PIN_FUNCTION(blsp_spi4), - APQ_PIN_FUNCTION(blsp_spi5), - APQ_PIN_FUNCTION(blsp_spi6), - APQ_PIN_FUNCTION(blsp_spi7), - APQ_PIN_FUNCTION(blsp_spi8), - APQ_PIN_FUNCTION(blsp_spi9), - APQ_PIN_FUNCTION(blsp_spi10), - APQ_PIN_FUNCTION(blsp_spi10_cs1), - APQ_PIN_FUNCTION(blsp_spi10_cs2), - APQ_PIN_FUNCTION(blsp_spi10_cs3), - APQ_PIN_FUNCTION(blsp_spi11), - APQ_PIN_FUNCTION(blsp_spi12), - APQ_PIN_FUNCTION(blsp_uart1), - APQ_PIN_FUNCTION(blsp_uart2), - APQ_PIN_FUNCTION(blsp_uart3), - APQ_PIN_FUNCTION(blsp_uart4), - APQ_PIN_FUNCTION(blsp_uart5), - APQ_PIN_FUNCTION(blsp_uart6), - APQ_PIN_FUNCTION(blsp_uart7), - APQ_PIN_FUNCTION(blsp_uart8), - APQ_PIN_FUNCTION(blsp_uart9), - APQ_PIN_FUNCTION(blsp_uart10), - APQ_PIN_FUNCTION(blsp_uart11), - APQ_PIN_FUNCTION(blsp_uart12), - APQ_PIN_FUNCTION(blsp_uim1), - APQ_PIN_FUNCTION(blsp_uim2), - APQ_PIN_FUNCTION(blsp_uim3), - APQ_PIN_FUNCTION(blsp_uim4), - APQ_PIN_FUNCTION(blsp_uim5), - APQ_PIN_FUNCTION(blsp_uim6), - APQ_PIN_FUNCTION(blsp_uim7), - APQ_PIN_FUNCTION(blsp_uim8), - APQ_PIN_FUNCTION(blsp_uim9), - APQ_PIN_FUNCTION(blsp_uim10), - APQ_PIN_FUNCTION(blsp_uim11), - APQ_PIN_FUNCTION(blsp_uim12), - APQ_PIN_FUNCTION(cam_mclk0), - APQ_PIN_FUNCTION(cam_mclk1), - APQ_PIN_FUNCTION(cam_mclk2), - APQ_PIN_FUNCTION(cam_mclk3), - APQ_PIN_FUNCTION(cci_async), - APQ_PIN_FUNCTION(cci_async_in0), - APQ_PIN_FUNCTION(cci_i2c0), - APQ_PIN_FUNCTION(cci_i2c1), - APQ_PIN_FUNCTION(cci_timer0), - APQ_PIN_FUNCTION(cci_timer1), - APQ_PIN_FUNCTION(cci_timer2), - APQ_PIN_FUNCTION(cci_timer3), - APQ_PIN_FUNCTION(cci_timer4), - APQ_PIN_FUNCTION(edp_hpd), - APQ_PIN_FUNCTION(gcc_gp1), - APQ_PIN_FUNCTION(gcc_gp2), - APQ_PIN_FUNCTION(gcc_gp3), - APQ_PIN_FUNCTION(gcc_obt), - APQ_PIN_FUNCTION(gcc_vtt), - APQ_PIN_FUNCTION(gp_mn), - APQ_PIN_FUNCTION(gp_pdm0), - APQ_PIN_FUNCTION(gp_pdm1), - APQ_PIN_FUNCTION(gp_pdm2), - APQ_PIN_FUNCTION(gp0_clk), - APQ_PIN_FUNCTION(gp1_clk), - APQ_PIN_FUNCTION(gpio), - APQ_PIN_FUNCTION(hdmi_cec), - APQ_PIN_FUNCTION(hdmi_ddc), - APQ_PIN_FUNCTION(hdmi_dtest), - APQ_PIN_FUNCTION(hdmi_hpd), - APQ_PIN_FUNCTION(hdmi_rcv), - APQ_PIN_FUNCTION(hsic), - APQ_PIN_FUNCTION(ldo_en), - APQ_PIN_FUNCTION(ldo_update), - APQ_PIN_FUNCTION(mdp_vsync), - APQ_PIN_FUNCTION(pci_e0), - APQ_PIN_FUNCTION(pci_e0_n), - APQ_PIN_FUNCTION(pci_e0_rst), - APQ_PIN_FUNCTION(pci_e1), - APQ_PIN_FUNCTION(pci_e1_rst), - APQ_PIN_FUNCTION(pci_e1_rst_n), - APQ_PIN_FUNCTION(pci_e1_clkreq_n), - APQ_PIN_FUNCTION(pri_mi2s), - APQ_PIN_FUNCTION(qua_mi2s), - APQ_PIN_FUNCTION(sata_act), - APQ_PIN_FUNCTION(sata_devsleep), - APQ_PIN_FUNCTION(sata_devsleep_n), - APQ_PIN_FUNCTION(sd_write), - APQ_PIN_FUNCTION(sdc_emmc_mode), - APQ_PIN_FUNCTION(sdc3), - APQ_PIN_FUNCTION(sdc4), - APQ_PIN_FUNCTION(sec_mi2s), - APQ_PIN_FUNCTION(slimbus), - APQ_PIN_FUNCTION(spdif_tx), - APQ_PIN_FUNCTION(spkr_i2s), - APQ_PIN_FUNCTION(spkr_i2s_ws), - APQ_PIN_FUNCTION(spss_geni), - APQ_PIN_FUNCTION(ter_mi2s), - APQ_PIN_FUNCTION(tsif1), - APQ_PIN_FUNCTION(tsif2), - APQ_PIN_FUNCTION(uim), - APQ_PIN_FUNCTION(uim_batt_alarm), + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(blsp_i2c6), + MSM_PIN_FUNCTION(blsp_i2c7), + MSM_PIN_FUNCTION(blsp_i2c8), + MSM_PIN_FUNCTION(blsp_i2c9), + MSM_PIN_FUNCTION(blsp_i2c10), + MSM_PIN_FUNCTION(blsp_i2c11), + MSM_PIN_FUNCTION(blsp_i2c12), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_spi1_cs1), + MSM_PIN_FUNCTION(blsp_spi1_cs2), + MSM_PIN_FUNCTION(blsp_spi1_cs3), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_spi3_cs1), + MSM_PIN_FUNCTION(blsp_spi3_cs2), + MSM_PIN_FUNCTION(blsp_spi3_cs3), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(blsp_spi6), + MSM_PIN_FUNCTION(blsp_spi7), + MSM_PIN_FUNCTION(blsp_spi8), + MSM_PIN_FUNCTION(blsp_spi9), + MSM_PIN_FUNCTION(blsp_spi10), + MSM_PIN_FUNCTION(blsp_spi10_cs1), + MSM_PIN_FUNCTION(blsp_spi10_cs2), + MSM_PIN_FUNCTION(blsp_spi10_cs3), + MSM_PIN_FUNCTION(blsp_spi11), + MSM_PIN_FUNCTION(blsp_spi12), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(blsp_uart3), + MSM_PIN_FUNCTION(blsp_uart4), + MSM_PIN_FUNCTION(blsp_uart5), + MSM_PIN_FUNCTION(blsp_uart6), + MSM_PIN_FUNCTION(blsp_uart7), + MSM_PIN_FUNCTION(blsp_uart8), + MSM_PIN_FUNCTION(blsp_uart9), + MSM_PIN_FUNCTION(blsp_uart10), + MSM_PIN_FUNCTION(blsp_uart11), + MSM_PIN_FUNCTION(blsp_uart12), + MSM_PIN_FUNCTION(blsp_uim1), + MSM_PIN_FUNCTION(blsp_uim2), + MSM_PIN_FUNCTION(blsp_uim3), + MSM_PIN_FUNCTION(blsp_uim4), + MSM_PIN_FUNCTION(blsp_uim5), + MSM_PIN_FUNCTION(blsp_uim6), + MSM_PIN_FUNCTION(blsp_uim7), + MSM_PIN_FUNCTION(blsp_uim8), + MSM_PIN_FUNCTION(blsp_uim9), + MSM_PIN_FUNCTION(blsp_uim10), + MSM_PIN_FUNCTION(blsp_uim11), + MSM_PIN_FUNCTION(blsp_uim12), + MSM_PIN_FUNCTION(cam_mclk0), + MSM_PIN_FUNCTION(cam_mclk1), + MSM_PIN_FUNCTION(cam_mclk2), + MSM_PIN_FUNCTION(cam_mclk3), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_async_in0), + MSM_PIN_FUNCTION(cci_i2c0), + MSM_PIN_FUNCTION(cci_i2c1), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(edp_hpd), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gcc_obt), + MSM_PIN_FUNCTION(gcc_vtt), + MSM_PIN_FUNCTION(gp_mn), + MSM_PIN_FUNCTION(gp_pdm0), + MSM_PIN_FUNCTION(gp_pdm1), + MSM_PIN_FUNCTION(gp_pdm2), + MSM_PIN_FUNCTION(gp0_clk), + MSM_PIN_FUNCTION(gp1_clk), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(hdmi_cec), + MSM_PIN_FUNCTION(hdmi_ddc), + MSM_PIN_FUNCTION(hdmi_dtest), + MSM_PIN_FUNCTION(hdmi_hpd), + MSM_PIN_FUNCTION(hdmi_rcv), + MSM_PIN_FUNCTION(hsic), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(pci_e0), + MSM_PIN_FUNCTION(pci_e0_n), + MSM_PIN_FUNCTION(pci_e0_rst), + MSM_PIN_FUNCTION(pci_e1), + MSM_PIN_FUNCTION(pci_e1_rst), + MSM_PIN_FUNCTION(pci_e1_rst_n), + MSM_PIN_FUNCTION(pci_e1_clkreq_n), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(qua_mi2s), + MSM_PIN_FUNCTION(sata_act), + MSM_PIN_FUNCTION(sata_devsleep), + MSM_PIN_FUNCTION(sata_devsleep_n), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sdc_emmc_mode), + MSM_PIN_FUNCTION(sdc3), + MSM_PIN_FUNCTION(sdc4), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(slimbus), + MSM_PIN_FUNCTION(spdif_tx), + MSM_PIN_FUNCTION(spkr_i2s), + MSM_PIN_FUNCTION(spkr_i2s_ws), + MSM_PIN_FUNCTION(spss_geni), + MSM_PIN_FUNCTION(ter_mi2s), + MSM_PIN_FUNCTION(tsif1), + MSM_PIN_FUNCTION(tsif2), + MSM_PIN_FUNCTION(uim), + MSM_PIN_FUNCTION(uim_batt_alarm), }; static const struct msm_pingroup apq8084_groups[] = { diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index adf7c8631f72..ea407e426bba 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -221,21 +221,21 @@ DECLARE_QCA_GPIO_PINS(99); gpio##id##_pins, \ ARRAY_SIZE(gpio##id##_pins)), \ .funcs = (int[]){ \ - qca_mux_gpio, /* gpio mode */ \ - qca_mux_##f1, \ - qca_mux_##f2, \ - qca_mux_##f3, \ - qca_mux_##f4, \ - qca_mux_##f5, \ - qca_mux_##f6, \ - qca_mux_##f7, \ - qca_mux_##f8, \ - qca_mux_##f9, \ - qca_mux_##f10, \ - qca_mux_##f11, \ - qca_mux_##f12, \ - qca_mux_##f13, \ - qca_mux_##f14 \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11, \ + msm_mux_##f12, \ + msm_mux_##f13, \ + msm_mux_##f14 \ }, \ .nfuncs = 15, \ .ctl_reg = 0x0 + 0x1000 * id, \ @@ -260,51 +260,51 @@ DECLARE_QCA_GPIO_PINS(99); enum ipq4019_functions { - qca_mux_gpio, - qca_mux_aud_pin, - qca_mux_audio_pwm, - qca_mux_blsp_i2c0, - qca_mux_blsp_i2c1, - qca_mux_blsp_spi0, - qca_mux_blsp_spi1, - qca_mux_blsp_uart0, - qca_mux_blsp_uart1, - qca_mux_chip_rst, - qca_mux_i2s_rx, - qca_mux_i2s_spdif_in, - qca_mux_i2s_spdif_out, - qca_mux_i2s_td, - qca_mux_i2s_tx, - qca_mux_jtag, - qca_mux_led0, - qca_mux_led1, - qca_mux_led2, - qca_mux_led3, - qca_mux_led4, - qca_mux_led5, - qca_mux_led6, - qca_mux_led7, - qca_mux_led8, - qca_mux_led9, - qca_mux_led10, - qca_mux_led11, - qca_mux_mdc, - qca_mux_mdio, - qca_mux_pcie, - qca_mux_pmu, - qca_mux_prng_rosc, - qca_mux_qpic, - qca_mux_rgmii, - qca_mux_rmii, - qca_mux_sdio, - qca_mux_smart0, - qca_mux_smart1, - qca_mux_smart2, - qca_mux_smart3, - qca_mux_tm, - qca_mux_wifi0, - qca_mux_wifi1, - qca_mux_NA, + msm_mux_gpio, + msm_mux_aud_pin, + msm_mux_audio_pwm, + msm_mux_blsp_i2c0, + msm_mux_blsp_i2c1, + msm_mux_blsp_spi0, + msm_mux_blsp_spi1, + msm_mux_blsp_uart0, + msm_mux_blsp_uart1, + msm_mux_chip_rst, + msm_mux_i2s_rx, + msm_mux_i2s_spdif_in, + msm_mux_i2s_spdif_out, + msm_mux_i2s_td, + msm_mux_i2s_tx, + msm_mux_jtag, + msm_mux_led0, + msm_mux_led1, + msm_mux_led2, + msm_mux_led3, + msm_mux_led4, + msm_mux_led5, + msm_mux_led6, + msm_mux_led7, + msm_mux_led8, + msm_mux_led9, + msm_mux_led10, + msm_mux_led11, + msm_mux_mdc, + msm_mux_mdio, + msm_mux_pcie, + msm_mux_pmu, + msm_mux_prng_rosc, + msm_mux_qpic, + msm_mux_rgmii, + msm_mux_rmii, + msm_mux_sdio, + msm_mux_smart0, + msm_mux_smart1, + msm_mux_smart2, + msm_mux_smart3, + msm_mux_tm, + msm_mux_wifi0, + msm_mux_wifi1, + msm_mux_NA, }; static const char * const gpio_groups[] = { @@ -470,50 +470,50 @@ static const char * const wifi1_groups[] = { }; static const struct pinfunction ipq4019_functions[] = { - QCA_PIN_FUNCTION(aud_pin), - QCA_PIN_FUNCTION(audio_pwm), - QCA_PIN_FUNCTION(blsp_i2c0), - QCA_PIN_FUNCTION(blsp_i2c1), - QCA_PIN_FUNCTION(blsp_spi0), - QCA_PIN_FUNCTION(blsp_spi1), - QCA_PIN_FUNCTION(blsp_uart0), - QCA_PIN_FUNCTION(blsp_uart1), - QCA_PIN_FUNCTION(chip_rst), - QCA_GPIO_PIN_FUNCTION(gpio), - QCA_PIN_FUNCTION(i2s_rx), - QCA_PIN_FUNCTION(i2s_spdif_in), - QCA_PIN_FUNCTION(i2s_spdif_out), - QCA_PIN_FUNCTION(i2s_td), - QCA_PIN_FUNCTION(i2s_tx), - QCA_PIN_FUNCTION(jtag), - QCA_PIN_FUNCTION(led0), - QCA_PIN_FUNCTION(led1), - QCA_PIN_FUNCTION(led2), - QCA_PIN_FUNCTION(led3), - QCA_PIN_FUNCTION(led4), - QCA_PIN_FUNCTION(led5), - QCA_PIN_FUNCTION(led6), - QCA_PIN_FUNCTION(led7), - QCA_PIN_FUNCTION(led8), - QCA_PIN_FUNCTION(led9), - QCA_PIN_FUNCTION(led10), - QCA_PIN_FUNCTION(led11), - QCA_PIN_FUNCTION(mdc), - QCA_PIN_FUNCTION(mdio), - QCA_PIN_FUNCTION(pcie), - QCA_PIN_FUNCTION(pmu), - QCA_PIN_FUNCTION(prng_rosc), - QCA_PIN_FUNCTION(qpic), - QCA_PIN_FUNCTION(rgmii), - QCA_PIN_FUNCTION(rmii), - QCA_PIN_FUNCTION(sdio), - QCA_PIN_FUNCTION(smart0), - QCA_PIN_FUNCTION(smart1), - QCA_PIN_FUNCTION(smart2), - QCA_PIN_FUNCTION(smart3), - QCA_PIN_FUNCTION(tm), - QCA_PIN_FUNCTION(wifi0), - QCA_PIN_FUNCTION(wifi1), + MSM_PIN_FUNCTION(aud_pin), + MSM_PIN_FUNCTION(audio_pwm), + MSM_PIN_FUNCTION(blsp_i2c0), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_spi0), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_uart0), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(chip_rst), + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(i2s_rx), + MSM_PIN_FUNCTION(i2s_spdif_in), + MSM_PIN_FUNCTION(i2s_spdif_out), + MSM_PIN_FUNCTION(i2s_td), + MSM_PIN_FUNCTION(i2s_tx), + MSM_PIN_FUNCTION(jtag), + MSM_PIN_FUNCTION(led0), + MSM_PIN_FUNCTION(led1), + MSM_PIN_FUNCTION(led2), + MSM_PIN_FUNCTION(led3), + MSM_PIN_FUNCTION(led4), + MSM_PIN_FUNCTION(led5), + MSM_PIN_FUNCTION(led6), + MSM_PIN_FUNCTION(led7), + MSM_PIN_FUNCTION(led8), + MSM_PIN_FUNCTION(led9), + MSM_PIN_FUNCTION(led10), + MSM_PIN_FUNCTION(led11), + MSM_PIN_FUNCTION(mdc), + MSM_PIN_FUNCTION(mdio), + MSM_PIN_FUNCTION(pcie), + MSM_PIN_FUNCTION(pmu), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qpic), + MSM_PIN_FUNCTION(rgmii), + MSM_PIN_FUNCTION(rmii), + MSM_PIN_FUNCTION(sdio), + MSM_PIN_FUNCTION(smart0), + MSM_PIN_FUNCTION(smart1), + MSM_PIN_FUNCTION(smart2), + MSM_PIN_FUNCTION(smart3), + MSM_PIN_FUNCTION(tm), + MSM_PIN_FUNCTION(wifi0), + MSM_PIN_FUNCTION(wifi1), }; static const struct msm_pingroup ipq4019_groups[] = { diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c index 0a50486337d3..02682eb82be1 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c @@ -166,17 +166,17 @@ static const unsigned int sdc3_data_pins[] = { 71 }; gpio##id##_pins, \ ARRAY_SIZE(gpio##id##_pins)), \ .funcs = (int[]){ \ - IPQ_MUX_gpio, \ - IPQ_MUX_##f1, \ - IPQ_MUX_##f2, \ - IPQ_MUX_##f3, \ - IPQ_MUX_##f4, \ - IPQ_MUX_##f5, \ - IPQ_MUX_##f6, \ - IPQ_MUX_##f7, \ - IPQ_MUX_##f8, \ - IPQ_MUX_##f9, \ - IPQ_MUX_##f10, \ + msm_mux_gpio, \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ }, \ .nfuncs = 11, \ .ctl_reg = 0x1000 + 0x10 * id, \ @@ -228,53 +228,53 @@ static const unsigned int sdc3_data_pins[] = { 71 }; } enum ipq8064_functions { - IPQ_MUX_gpio, - IPQ_MUX_mdio, - IPQ_MUX_mi2s, - IPQ_MUX_pdm, - IPQ_MUX_ssbi, - IPQ_MUX_spmi, - IPQ_MUX_audio_pcm, - IPQ_MUX_gsbi1, - IPQ_MUX_gsbi2, - IPQ_MUX_gsbi4, - IPQ_MUX_gsbi5, - IPQ_MUX_gsbi5_spi_cs1, - IPQ_MUX_gsbi5_spi_cs2, - IPQ_MUX_gsbi5_spi_cs3, - IPQ_MUX_gsbi6, - IPQ_MUX_gsbi7, - IPQ_MUX_nss_spi, - IPQ_MUX_sdc1, - IPQ_MUX_spdif, - IPQ_MUX_nand, - IPQ_MUX_tsif1, - IPQ_MUX_tsif2, - IPQ_MUX_usb_fs_n, - IPQ_MUX_usb_fs, - IPQ_MUX_usb2_hsic, - IPQ_MUX_rgmii2, - IPQ_MUX_sata, - IPQ_MUX_pcie1_rst, - IPQ_MUX_pcie1_prsnt, - IPQ_MUX_pcie1_pwrflt, - IPQ_MUX_pcie1_pwren_n, - IPQ_MUX_pcie1_pwren, - IPQ_MUX_pcie1_clk_req, - IPQ_MUX_pcie2_rst, - IPQ_MUX_pcie2_prsnt, - IPQ_MUX_pcie2_pwrflt, - IPQ_MUX_pcie2_pwren_n, - IPQ_MUX_pcie2_pwren, - IPQ_MUX_pcie2_clk_req, - IPQ_MUX_pcie3_rst, - IPQ_MUX_pcie3_prsnt, - IPQ_MUX_pcie3_pwrflt, - IPQ_MUX_pcie3_pwren_n, - IPQ_MUX_pcie3_pwren, - IPQ_MUX_pcie3_clk_req, - IPQ_MUX_ps_hold, - IPQ_MUX_NA, + msm_mux_gpio, + msm_mux_mdio, + msm_mux_mi2s, + msm_mux_pdm, + msm_mux_ssbi, + msm_mux_spmi, + msm_mux_audio_pcm, + msm_mux_gsbi1, + msm_mux_gsbi2, + msm_mux_gsbi4, + msm_mux_gsbi5, + msm_mux_gsbi5_spi_cs1, + msm_mux_gsbi5_spi_cs2, + msm_mux_gsbi5_spi_cs3, + msm_mux_gsbi6, + msm_mux_gsbi7, + msm_mux_nss_spi, + msm_mux_sdc1, + msm_mux_spdif, + msm_mux_nand, + msm_mux_tsif1, + msm_mux_tsif2, + msm_mux_usb_fs_n, + msm_mux_usb_fs, + msm_mux_usb2_hsic, + msm_mux_rgmii2, + msm_mux_sata, + msm_mux_pcie1_rst, + msm_mux_pcie1_prsnt, + msm_mux_pcie1_pwrflt, + msm_mux_pcie1_pwren_n, + msm_mux_pcie1_pwren, + msm_mux_pcie1_clk_req, + msm_mux_pcie2_rst, + msm_mux_pcie2_prsnt, + msm_mux_pcie2_pwrflt, + msm_mux_pcie2_pwren_n, + msm_mux_pcie2_pwren, + msm_mux_pcie2_clk_req, + msm_mux_pcie3_rst, + msm_mux_pcie3_prsnt, + msm_mux_pcie3_pwrflt, + msm_mux_pcie3_pwren_n, + msm_mux_pcie3_pwren, + msm_mux_pcie3_clk_req, + msm_mux_ps_hold, + msm_mux_NA, }; static const char * const gpio_groups[] = { @@ -480,52 +480,52 @@ static const char * const ps_hold_groups[] = { }; static const struct pinfunction ipq8064_functions[] = { - IPQ_GPIO_PIN_FUNCTION(gpio), - IPQ_PIN_FUNCTION(mdio), - IPQ_PIN_FUNCTION(ssbi), - IPQ_PIN_FUNCTION(spmi), - IPQ_PIN_FUNCTION(mi2s), - IPQ_PIN_FUNCTION(pdm), - IPQ_PIN_FUNCTION(audio_pcm), - IPQ_PIN_FUNCTION(gsbi1), - IPQ_PIN_FUNCTION(gsbi2), - IPQ_PIN_FUNCTION(gsbi4), - IPQ_PIN_FUNCTION(gsbi5), - IPQ_PIN_FUNCTION(gsbi5_spi_cs1), - IPQ_PIN_FUNCTION(gsbi5_spi_cs2), - IPQ_PIN_FUNCTION(gsbi5_spi_cs3), - IPQ_PIN_FUNCTION(gsbi6), - IPQ_PIN_FUNCTION(gsbi7), - IPQ_PIN_FUNCTION(nss_spi), - IPQ_PIN_FUNCTION(sdc1), - IPQ_PIN_FUNCTION(spdif), - IPQ_PIN_FUNCTION(nand), - IPQ_PIN_FUNCTION(tsif1), - IPQ_PIN_FUNCTION(tsif2), - IPQ_PIN_FUNCTION(usb_fs_n), - IPQ_PIN_FUNCTION(usb_fs), - IPQ_PIN_FUNCTION(usb2_hsic), - IPQ_PIN_FUNCTION(rgmii2), - IPQ_PIN_FUNCTION(sata), - IPQ_GPIO_PIN_FUNCTION(pcie1_rst), - IPQ_PIN_FUNCTION(pcie1_prsnt), - IPQ_PIN_FUNCTION(pcie1_pwren_n), - IPQ_PIN_FUNCTION(pcie1_pwren), - IPQ_PIN_FUNCTION(pcie1_pwrflt), - IPQ_PIN_FUNCTION(pcie1_clk_req), - IPQ_GPIO_PIN_FUNCTION(pcie2_rst), - IPQ_PIN_FUNCTION(pcie2_prsnt), - IPQ_PIN_FUNCTION(pcie2_pwren_n), - IPQ_PIN_FUNCTION(pcie2_pwren), - IPQ_PIN_FUNCTION(pcie2_pwrflt), - IPQ_PIN_FUNCTION(pcie2_clk_req), - IPQ_GPIO_PIN_FUNCTION(pcie3_rst), - IPQ_PIN_FUNCTION(pcie3_prsnt), - IPQ_PIN_FUNCTION(pcie3_pwren_n), - IPQ_PIN_FUNCTION(pcie3_pwren), - IPQ_PIN_FUNCTION(pcie3_pwrflt), - IPQ_PIN_FUNCTION(pcie3_clk_req), - IPQ_PIN_FUNCTION(ps_hold), + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(mdio), + MSM_PIN_FUNCTION(ssbi), + MSM_PIN_FUNCTION(spmi), + MSM_PIN_FUNCTION(mi2s), + MSM_PIN_FUNCTION(pdm), + MSM_PIN_FUNCTION(audio_pcm), + MSM_PIN_FUNCTION(gsbi1), + MSM_PIN_FUNCTION(gsbi2), + MSM_PIN_FUNCTION(gsbi4), + MSM_PIN_FUNCTION(gsbi5), + MSM_PIN_FUNCTION(gsbi5_spi_cs1), + MSM_PIN_FUNCTION(gsbi5_spi_cs2), + MSM_PIN_FUNCTION(gsbi5_spi_cs3), + MSM_PIN_FUNCTION(gsbi6), + MSM_PIN_FUNCTION(gsbi7), + MSM_PIN_FUNCTION(nss_spi), + MSM_PIN_FUNCTION(sdc1), + MSM_PIN_FUNCTION(spdif), + MSM_PIN_FUNCTION(nand), + MSM_PIN_FUNCTION(tsif1), + MSM_PIN_FUNCTION(tsif2), + MSM_PIN_FUNCTION(usb_fs_n), + MSM_PIN_FUNCTION(usb_fs), + MSM_PIN_FUNCTION(usb2_hsic), + MSM_PIN_FUNCTION(rgmii2), + MSM_PIN_FUNCTION(sata), + MSM_GPIO_PIN_FUNCTION(pcie1_rst), + MSM_PIN_FUNCTION(pcie1_prsnt), + MSM_PIN_FUNCTION(pcie1_pwren_n), + MSM_PIN_FUNCTION(pcie1_pwren), + MSM_PIN_FUNCTION(pcie1_pwrflt), + MSM_PIN_FUNCTION(pcie1_clk_req), + MSM_GPIO_PIN_FUNCTION(pcie2_rst), + MSM_PIN_FUNCTION(pcie2_prsnt), + MSM_PIN_FUNCTION(pcie2_pwren_n), + MSM_PIN_FUNCTION(pcie2_pwren), + MSM_PIN_FUNCTION(pcie2_pwrflt), + MSM_PIN_FUNCTION(pcie2_clk_req), + MSM_GPIO_PIN_FUNCTION(pcie3_rst), + MSM_PIN_FUNCTION(pcie3_prsnt), + MSM_PIN_FUNCTION(pcie3_pwren_n), + MSM_PIN_FUNCTION(pcie3_pwren), + MSM_PIN_FUNCTION(pcie3_pwrflt), + MSM_PIN_FUNCTION(pcie3_clk_req), + MSM_PIN_FUNCTION(ps_hold), }; static const struct msm_pingroup ipq8064_groups[] = { diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index b94ba1a4177e..342bf306e9be 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -14,21 +14,6 @@ struct platform_device; struct pinctrl_pin_desc; -#define APQ_PIN_FUNCTION(fname) \ - [APQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \ - fname##_groups, \ - ARRAY_SIZE(fname##_groups)) - -#define IPQ_PIN_FUNCTION(fname) \ - [IPQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \ - fname##_groups, \ - ARRAY_SIZE(fname##_groups)) - -#define IPQ_GPIO_PIN_FUNCTION(fname) \ - [IPQ_MUX_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \ - fname##_groups, \ - ARRAY_SIZE(fname##_groups)) - #define MSM_PIN_FUNCTION(fname) \ [msm_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ fname##_groups, \ @@ -39,16 +24,6 @@ struct pinctrl_pin_desc; fname##_groups, \ ARRAY_SIZE(fname##_groups)) -#define QCA_PIN_FUNCTION(fname) \ - [qca_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ - fname##_groups, \ - ARRAY_SIZE(fname##_groups)) - -#define QCA_GPIO_PIN_FUNCTION(fname) \ - [qca_mux_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \ - fname##_groups, \ - ARRAY_SIZE(fname##_groups)) - /** * struct msm_pingroup - Qualcomm pingroup definition * @grp: Generic data of the pin group (name and pins) From c0de88659b68402ed7e53fb998a058ef430c787b Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Mon, 17 Aug 2026 21:56:54 +0300 Subject: [PATCH 022/106] pinctrl: renesas: rzt2h: Fix used_irqs indexing in clear path struct rzt2h_pinctrl::used_irqs is supposed to be indexed based on the parent IRQ number. Do the translation using rzt2h_gpio_irq_map and clear it properly. Cc: stable@kernel.org Fixes: 829dde3369a9 ("pinctrl: renesas: rzt2h: Add GPIO IRQ chip to handle interrupts") Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260817185700.322370-2-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/renesas/pinctrl-rzt2h.c index eb70aee39f1a..a37f1e399446 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -1050,8 +1050,13 @@ static void rzt2h_gpio_irq_domain_free(struct irq_domain *domain, unsigned int v irq_hw_number_t hwirq = irqd_to_hwirq(d); u8 port = RZT2H_PIN_ID_TO_PORT(hwirq); u8 pin = RZT2H_PIN_ID_TO_PIN(hwirq); + u8 parent_irq; - if (test_and_clear_bit(hwirq - RZT2H_INTERRUPTS_START, pctrl->used_irqs)) + parent_irq = rzt2h_gpio_irq_map[hwirq]; + if (parent_irq < RZT2H_INTERRUPTS_START) + return; + + if (test_and_clear_bit(parent_irq - RZT2H_INTERRUPTS_START, pctrl->used_irqs)) rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, false); irq_domain_free_irqs_common(domain, virq, nr_irqs); From 2f006f5c617a56afe7683b607727349e0aea7814 Mon Sep 17 00:00:00 2001 From: Muzaffer Kadir Date: Mon, 7 Sep 2026 19:05:24 +0300 Subject: [PATCH 023/106] dt-bindings: pinctrl: qcom: Add MSM8952 pinctrl Add device tree bindings for the TLMM pin controller found on the Qualcomm MSM8952 platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Muzaffer Kadir Link: https://patch.msgid.link/20260907-msm8952-pinctrl-v5-1-9a2d8d72ffdb@mainlining.org Signed-off-by: Bartosz Golaszewski --- .../pinctrl/qcom,msm8952-pinctrl.yaml | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8952-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8952-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8952-pinctrl.yaml new file mode 100644 index 000000000000..d367bb078aff --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8952-pinctrl.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8952-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8952 TLMM pin controller + +maintainers: + - Muzaffer Kadir + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8952 SoC. + +properties: + compatible: + const: qcom,msm8952-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 66 + + gpio-line-names: + maxItems: 134 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8952-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8952-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8952-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-3])$" + - enum: [ qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, + qdsd_data3, sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, + sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, blsp_uart1, blsp_spi1, adsp_ext, blsp_i2c1, prng_rosc, qdss_cti_trig_out_b0, + qdss_cti_trig_out_a1, blsp_spi2, blsp_uart2, ldo_update, qdss_tracedata_b, + pbs1, pwr_modem_enabled_b, blsp_i2c3, gcc_gp2_clk_b, atest_combodac_to_gpio_native, + ldo_en, blsp_i2c2, gcc_gp1_clk_b, atest_gpsadc_dtest0_native, blsp_spi3, + blsp_uart3, sec_mi2s, pbs0, gcc_gp3_clk_b, blsp_spi4, blsp_uart4, pbs2, + pwr_nav_enabled_b, pwr_crypto_enabled_b, blsp_i2c4, blsp_spi5, blsp_uart5, + qdss_traceclk_a, atest_bbrx1, qdss_tracectl_b, qdss_cti_trig_in_b0, blsp_i2c6, + qdss_traceclk_b, atest_wlan0, m_voc, qdss_cti_trig_in_a0, atest_bbrx0, blsp_i2c5, + qdss_tracectl_a, atest_gpsadc_dtest1_native, qdss_tracedata_a, blsp_spi6, + blsp_uart6, atest_wlan1, mdp_vsync, pri_mi2s_mclk_a, sec_mi2s_mclk_a, + cam_mclk, cci_i2c, pwr_modem_enabled_a, cci_timer0, cci_timer1, pwr_nav_enabled_a, + pwr_crypto_enabled_a, cci_async, sd_write, qdss_cti_trig_out_a0, gcc_gp1_clk_a, + gcc_gp2_clk_a, gcc_gp3_clk_a, blsp6_spi, qdss_cti_trig_in_b1, uim_batt, + qdss_cti_trig_out_b1, uim1_data, uim1_clk, uim1_reset, uim1_present, uim2_data, + uim2_clk, uim2_reset, uim2_present, uim3_data, usb_fs, uim3_clk, uim3_reset, + uim3_present, atest_char3, dbg_out, bimc_dte0, sec_mi2s_mclk_b, pri_mi2s, + atest_char1, ebi_cdc, atest_char0, cdc_pdm0, pri_mi2s_mclk_b, lpass_slimbus, + lpass_slimbus0, lpass_slimbus1, wcss_bt, atest_char2, ebi_ch0, wcss_wlan2, + wcss_wlan1, wcss_wlan0, wcss_wlan, wcss_fm, ext_lpass, gcc_tlmm, dmic0_clk, + dmic0_data, qdss_cti_trig_in_a1, blsp_spi7, blsp_uart7, pri_mi2s_ws, wsa_io, + blsp_i2c7, blsp_spi8, blsp_uart8, blsp_i2c8, gcc_plltest, nav_pps_in_a, + pa_indicator, nav_pps_in_b, nav_pps, modem_tsync, nav_tsync, ssbi_wtr1, + gsm1_tx, gsm0_tx, atest_char, atest_tsens, bimc_dte1, + gp_mn, gp_pdm_0a, gp_pdm_0b, gp_pdm_1a, gp_pdm_1b, + gp_pdm_2a, gp_pdm_2b, gp0_clk, gp1_clk] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + msmgpio: pinctrl@1000000 { + compatible = "qcom,msm8952-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&msmgpio 0 0 134>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1-uart2-sleep-state { + pins = "gpio4", "gpio5"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + + spi1-default-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio2"; + function = "blsp_spi1"; + + drive-strength = <2>; + bias-disable; + }; + }; + }; From b53a6210af0fe559670e298349968beae2c7448b Mon Sep 17 00:00:00 2001 From: Muzaffer Kadir Date: Mon, 7 Sep 2026 19:05:25 +0300 Subject: [PATCH 024/106] pinctrl: qcom: Add MSM8952 tlmm pinctrl driver MSM8952 has same pin count and similar pinctrl functions mostly with msm8917, but some functions use different pins. Signed-off-by: Muzaffer Kadir Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260907-msm8952-pinctrl-v5-2-9a2d8d72ffdb@mainlining.org Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/Kconfig.msm | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-msm8952.c | 1257 ++++++++++++++++++++++++ 3 files changed, 1266 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8952.c diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index 9b95bf8ecb22..e45c701db627 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -243,6 +243,14 @@ config PINCTRL_MSM8917 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm MSM8917, MSM8937 platform. +config PINCTRL_MSM8952 + tristate "Qualcomm 8952 pin controller driver" + depends on ARM64 || COMPILE_TEST + default ARCH_QCOM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found on the Qualcomm MSM8952 platform. + config PINCTRL_MSM8953 tristate "Qualcomm 8953 pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index a29cbb55316b..a3daca77a448 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o obj-$(CONFIG_PINCTRL_MSM8909) += pinctrl-msm8909.o obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o obj-$(CONFIG_PINCTRL_MSM8917) += pinctrl-msm8917.o +obj-$(CONFIG_PINCTRL_MSM8952) += pinctrl-msm8952.o obj-$(CONFIG_PINCTRL_MSM8953) += pinctrl-msm8953.o obj-$(CONFIG_PINCTRL_MSM8976) += pinctrl-msm8976.o obj-$(CONFIG_PINCTRL_MSM8994) += pinctrl-msm8994.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm8952.c b/drivers/pinctrl/qcom/pinctrl-msm8952.c new file mode 100644 index 000000000000..6f83255cdc55 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8952.c @@ -0,0 +1,1257 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013, Sony Mobile Communications AB. + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2026 Muzaffer Kadir + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8952_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "SDC1_CLK"), PINCTRL_PIN(135, "SDC1_CMD"), + PINCTRL_PIN(136, "SDC1_DATA"), PINCTRL_PIN(137, "SDC1_RCLK"), + PINCTRL_PIN(138, "SDC2_CLK"), PINCTRL_PIN(139, "SDC2_CMD"), + PINCTRL_PIN(140, "SDC2_DATA"), PINCTRL_PIN(141, "QDSD_CLK"), + PINCTRL_PIN(142, "QDSD_CMD"), PINCTRL_PIN(143, "QDSD_DATA0"), + PINCTRL_PIN(144, "QDSD_DATA1"), PINCTRL_PIN(145, "QDSD_DATA2"), + PINCTRL_PIN(146, "QDSD_DATA3"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } + +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); + +static const unsigned int sdc1_clk_pins[] = { 134 }; +static const unsigned int sdc1_cmd_pins[] = { 135 }; +static const unsigned int sdc1_data_pins[] = { 136 }; +static const unsigned int sdc1_rclk_pins[] = { 137 }; +static const unsigned int sdc2_clk_pins[] = { 138 }; +static const unsigned int sdc2_cmd_pins[] = { 139 }; +static const unsigned int sdc2_data_pins[] = { 140 }; +static const unsigned int qdsd_clk_pins[] = { 141 }; +static const unsigned int qdsd_cmd_pins[] = { 142 }; +static const unsigned int qdsd_data0_pins[] = { 143 }; +static const unsigned int qdsd_data1_pins[] = { 144 }; +static const unsigned int qdsd_data2_pins[] = { 145 }; +static const unsigned int qdsd_data3_pins[] = { 146 }; + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, \ + f14) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ msm_mux_gpio, msm_mux_##f1, msm_mux_##f2, \ + msm_mux_##f3, msm_mux_##f4, msm_mux_##f5, \ + msm_mux_##f6, msm_mux_##f7, msm_mux_##f8, \ + msm_mux_##f9, msm_mux_##f10, msm_mux_##f11, \ + msm_mux_##f12, msm_mux_##f13, \ + msm_mux_##f14 }, \ + .nfuncs = 15, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x4 + 0x1000 * id, \ + .intr_cfg_reg = 0x8 + 0x1000 * id, \ + .intr_status_reg = 0xc + 0x1000 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum msm8952_functions { + msm_mux_blsp_uart1, + msm_mux_blsp_spi1, + msm_mux_adsp_ext, + msm_mux_gpio, + msm_mux_blsp_i2c1, + msm_mux_prng_rosc, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_blsp_spi2, + msm_mux_blsp_uart2, + msm_mux_ldo_update, + msm_mux_qdss_tracedata_b, + msm_mux_pbs1, + msm_mux_pwr_modem_enabled_b, + msm_mux_blsp_i2c3, + msm_mux_gcc_gp2_clk_b, + msm_mux_atest_combodac_to_gpio_native, + msm_mux_ldo_en, + msm_mux_blsp_i2c2, + msm_mux_gcc_gp1_clk_b, + msm_mux_atest_gpsadc_dtest0_native, + msm_mux_blsp_spi3, + msm_mux_blsp_uart3, + msm_mux_sec_mi2s, + msm_mux_pbs0, + msm_mux_gcc_gp3_clk_b, + msm_mux_blsp_spi4, + msm_mux_blsp_uart4, + msm_mux_pbs2, + msm_mux_pwr_nav_enabled_b, + msm_mux_pwr_crypto_enabled_b, + msm_mux_blsp_i2c4, + msm_mux_blsp_spi5, + msm_mux_blsp_uart5, + msm_mux_qdss_traceclk_a, + msm_mux_atest_bbrx1, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_blsp_i2c6, + msm_mux_qdss_traceclk_b, + msm_mux_atest_wlan0, + msm_mux_m_voc, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_atest_bbrx0, + msm_mux_blsp_i2c5, + msm_mux_qdss_tracectl_a, + msm_mux_atest_gpsadc_dtest1_native, + msm_mux_qdss_tracedata_a, + msm_mux_blsp_spi6, + msm_mux_blsp_uart6, + msm_mux_atest_wlan1, + msm_mux_mdp_vsync, + msm_mux_pri_mi2s_mclk_a, + msm_mux_sec_mi2s_mclk_a, + msm_mux_cam_mclk, + msm_mux_cci_i2c, + msm_mux_pwr_modem_enabled_a, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_pwr_nav_enabled_a, + msm_mux_pwr_crypto_enabled_a, + msm_mux_cci_async, + msm_mux_sd_write, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_gcc_gp1_clk_a, + msm_mux_gcc_gp2_clk_a, + msm_mux_gcc_gp3_clk_a, + msm_mux_blsp6_spi, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_uim_batt, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_uim1_data, + msm_mux_uim1_clk, + msm_mux_uim1_reset, + msm_mux_uim1_present, + msm_mux_uim2_data, + msm_mux_uim2_clk, + msm_mux_uim2_reset, + msm_mux_uim2_present, + msm_mux_uim3_data, + msm_mux_usb_fs, + msm_mux_uim3_clk, + msm_mux_uim3_reset, + msm_mux_uim3_present, + msm_mux_atest_char3, + msm_mux_dbg_out, + msm_mux_bimc_dte0, + msm_mux_sec_mi2s_mclk_b, + msm_mux_pri_mi2s, + msm_mux_atest_char1, + msm_mux_ebi_cdc, + msm_mux_atest_char0, + msm_mux_cdc_pdm0, + msm_mux_gp_mn, + msm_mux_gp_pdm_0a, + msm_mux_gp_pdm_0b, + msm_mux_gp_pdm_1a, + msm_mux_gp_pdm_1b, + msm_mux_gp_pdm_2a, + msm_mux_gp_pdm_2b, + msm_mux_gp0_clk, + msm_mux_gp1_clk, + msm_mux_pri_mi2s_mclk_b, + msm_mux_lpass_slimbus, + msm_mux_lpass_slimbus0, + msm_mux_lpass_slimbus1, + msm_mux_wcss_bt, + msm_mux_atest_char2, + msm_mux_ebi_ch0, + msm_mux_wcss_wlan2, + msm_mux_wcss_wlan1, + msm_mux_wcss_wlan0, + msm_mux_wcss_wlan, + msm_mux_wcss_fm, + msm_mux_ext_lpass, + msm_mux_gcc_tlmm, + msm_mux_dmic0_clk, + msm_mux_dmic0_data, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_blsp_spi7, + msm_mux_blsp_uart7, + msm_mux_pri_mi2s_ws, + msm_mux_wsa_io, + msm_mux_blsp_i2c7, + msm_mux_blsp_spi8, + msm_mux_blsp_uart8, + msm_mux_blsp_i2c8, + msm_mux_gcc_plltest, + msm_mux_nav_pps_in_a, + msm_mux_pa_indicator, + msm_mux_nav_pps_in_b, + msm_mux_nav_pps, + msm_mux_modem_tsync, + msm_mux_nav_tsync, + msm_mux_ssbi_wtr1, + msm_mux_gsm1_tx, + msm_mux_gsm0_tx, + msm_mux_atest_char, + msm_mux_atest_tsens, + msm_mux_bimc_dte1, + msm_mux_NA, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", +}; +static const char *const blsp_uart1_groups[] = { + "gpio0", + "gpio1", + "gpio2", + "gpio3", +}; +static const char *const blsp_spi1_groups[] = { + "gpio0", + "gpio1", + "gpio2", + "gpio3", +}; +static const char *const adsp_ext_groups[] = { "gpio1" }; +static const char *const qdss_cti_trig_out_b0_groups[] = { "gpio2" }; +static const char *const qdss_cti_trig_out_a1_groups[] = { "gpio3" }; +static const char *const blsp_spi2_groups[] = { + "gpio4", + "gpio5", + "gpio6", + "gpio7", +}; +static const char *const blsp_uart2_groups[] = { + "gpio4", + "gpio5", + "gpio6", + "gpio7", +}; +static const char *const ldo_update_groups[] = { "gpio4" }; +static const char *const qdss_tracedata_b_groups[] = { + "gpio8", "gpio9", "gpio12", "gpio13", "gpio23", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio66", + "gpio86", "gpio87", "gpio88", "gpio92", +}; +static const char *const blsp_i2c1_groups[] = { + "gpio2", + "gpio3", +}; +static const char *const prng_rosc_groups[] = { + "gpio2", +}; +static const char *const pbs1_groups[] = { "gpio9" }; +static const char *const pwr_modem_enabled_b_groups[] = { "gpio9" }; +static const char *const blsp_i2c3_groups[] = { + "gpio10", + "gpio11", +}; +static const char *const gcc_gp2_clk_b_groups[] = { "gpio10" }; +static const char *const atest_combodac_to_gpio_native_groups[] = { + "gpio4", "gpio12", "gpio13", "gpio20", "gpio21", "gpio28", "gpio29", + "gpio30", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", + "gpio45", "gpio46", "gpio47", "gpio48", "gpio67", "gpio115", +}; +static const char *const ldo_en_groups[] = { "gpio5" }; +static const char *const blsp_i2c2_groups[] = { + "gpio6", + "gpio7", +}; +static const char *const gcc_gp1_clk_b_groups[] = { "gpio6" }; +static const char *const atest_gpsadc_dtest0_native_groups[] = { "gpio7" }; +static const char *const gp_pdm_2a_groups[] = { "gpio7" }; +static const char *const blsp_spi3_groups[] = { + "gpio8", + "gpio9", + "gpio10", + "gpio11", +}; +static const char *const blsp_uart3_groups[] = { + "gpio8", + "gpio9", + "gpio10", + "gpio11", +}; +static const char *const sec_mi2s_groups[] = { + "gpio8", + "gpio9", + "gpio12", + "gpio13", +}; +static const char *const pbs0_groups[] = { "gpio8" }; +static const char *const gcc_gp3_clk_b_groups[] = { "gpio11" }; +static const char *const blsp_spi4_groups[] = { + "gpio12", + "gpio13", + "gpio14", + "gpio15", +}; +static const char *const blsp_uart4_groups[] = { + "gpio12", + "gpio13", + "gpio14", + "gpio15", +}; +static const char *const pbs2_groups[] = { "gpio12" }; +static const char *const pwr_nav_enabled_b_groups[] = { "gpio12" }; +static const char *const pwr_crypto_enabled_b_groups[] = { "gpio13" }; +static const char *const blsp_i2c4_groups[] = { + "gpio14", + "gpio15", +}; +static const char *const blsp_spi5_groups[] = { + "gpio16", + "gpio17", + "gpio18", + "gpio19", +}; +static const char *const blsp_uart5_groups[] = { + "gpio16", + "gpio17", + "gpio18", + "gpio19", +}; +static const char *const qdss_traceclk_a_groups[] = { "gpio16" }; +static const char *const atest_bbrx1_groups[] = { "gpio16" }; +static const char *const qdss_tracectl_b_groups[] = { "gpio20" }; +static const char *const gp_pdm_1b_groups[] = { "gpio20" }; +static const char *const qdss_cti_trig_in_b0_groups[] = { "gpio21" }; +static const char *const blsp_i2c6_groups[] = { + "gpio22", + "gpio23", +}; +static const char *const qdss_traceclk_b_groups[] = { "gpio22" }; +static const char *const atest_wlan0_groups[] = { "gpio22" }; +static const char *const m_voc_groups[] = { + "gpio17", + "gpio21", +}; +static const char *const qdss_cti_trig_in_a0_groups[] = { "gpio17" }; +static const char *const atest_bbrx0_groups[] = { "gpio17" }; +static const char *const blsp_i2c5_groups[] = { + "gpio18", + "gpio19", +}; +static const char *const qdss_tracectl_a_groups[] = { "gpio18" }; +static const char *const atest_gpsadc_dtest1_native_groups[] = { "gpio18" }; +static const char *const qdss_tracedata_a_groups[] = { + "gpio19", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", + "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", + "gpio37", "gpio38", "gpio39", "gpio40", +}; +static const char *const blsp_spi6_groups[] = { + "gpio20", + "gpio21", + "gpio22", + "gpio23", +}; +static const char *const blsp_uart6_groups[] = { + "gpio20", + "gpio21", + "gpio22", + "gpio23", +}; +static const char *const atest_wlan1_groups[] = { "gpio23" }; +static const char *const mdp_vsync_groups[] = { + "gpio24", + "gpio25", +}; +static const char *const pri_mi2s_mclk_a_groups[] = { "gpio25" }; +static const char *const sec_mi2s_mclk_a_groups[] = { "gpio25" }; +static const char *const cam_mclk_groups[] = { + "gpio26", + "gpio27", + "gpio28", +}; +static const char *const cci_i2c_groups[] = { + "gpio29", + "gpio30", + "gpio31", + "gpio32", +}; +static const char *const pwr_modem_enabled_a_groups[] = { "gpio29" }; +static const char *const cci_timer0_groups[] = { "gpio33" }; +static const char *const cci_timer1_groups[] = { "gpio34" }; +static const char *const pwr_nav_enabled_a_groups[] = { "gpio35" }; +static const char *const pwr_crypto_enabled_a_groups[] = { "gpio36" }; +static const char *const gp_pdm_2b_groups[] = { "gpio38" }; +static const char *const cci_async_groups[] = { "gpio39" }; +static const char *const gp_mn_groups[] = { "gpio39" }; +static const char *const sd_write_groups[] = { "gpio41" }; +static const char *const qdss_cti_trig_out_a0_groups[] = { "gpio41" }; +static const char *const gcc_gp1_clk_a_groups[] = { "gpio42" }; +static const char *const gcc_gp2_clk_a_groups[] = { "gpio43" }; +static const char *const gcc_gp3_clk_a_groups[] = { "gpio44" }; +static const char *const gp_pdm_1a_groups[] = { "gpio45" }; +static const char *const gp0_clk_groups[] = { "gpio46" }; +static const char *const gp1_clk_groups[] = { "gpio47" }; +static const char *const blsp6_spi_groups[] = { + "gpio47", + "gpio48", +}; +static const char *const gp_pdm_0b_groups[] = { "gpio48" }; +static const char *const qdss_cti_trig_in_b1_groups[] = { "gpio48" }; +static const char *const uim_batt_groups[] = { "gpio49" }; +static const char *const qdss_cti_trig_out_b1_groups[] = { "gpio50" }; +static const char *const uim1_data_groups[] = { "gpio51" }; +static const char *const uim1_clk_groups[] = { "gpio52" }; +static const char *const uim1_reset_groups[] = { "gpio53" }; +static const char *const uim1_present_groups[] = { "gpio54" }; +static const char *const uim2_data_groups[] = { "gpio55" }; +static const char *const uim2_clk_groups[] = { "gpio56" }; +static const char *const uim2_reset_groups[] = { "gpio57" }; +static const char *const uim2_present_groups[] = { "gpio58" }; +static const char *const uim3_data_groups[] = { "gpio59" }; +static const char *const usb_fs_groups[] = { + "gpio59", + "gpio60", +}; +static const char *const uim3_clk_groups[] = { "gpio60" }; +static const char *const uim3_reset_groups[] = { "gpio61" }; +static const char *const uim3_present_groups[] = { "gpio62" }; +static const char *const atest_char3_groups[] = { "gpio63" }; +static const char *const dbg_out_groups[] = { "gpio63" }; +static const char *const bimc_dte0_groups[] = { + "gpio63", + "gpio65", +}; +static const char *const sec_mi2s_mclk_b_groups[] = { "gpio66" }; +static const char *const gp_pdm_0a_groups[] = { "gpio66" }; +static const char *const pri_mi2s_groups[] = { + "gpio66", + "gpio88", + "gpio91", + "gpio93", +}; +static const char *const atest_char1_groups[] = { "gpio67" }; +static const char *const ebi_cdc_groups[] = { + "gpio67", "gpio69", "gpio118", "gpio119", "gpio120", "gpio123", +}; +static const char *const atest_char0_groups[] = { "gpio68" }; +static const char *const cdc_pdm0_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", +}; +static const char *const pri_mi2s_mclk_b_groups[] = { "gpio69" }; +static const char *const lpass_slimbus_groups[] = { "gpio70" }; +static const char *const lpass_slimbus0_groups[] = { "gpio71" }; +static const char *const lpass_slimbus1_groups[] = { "gpio72" }; +static const char *const wcss_bt_groups[] = { + "gpio75", + "gpio83", + "gpio84", +}; +static const char *const atest_char2_groups[] = { "gpio75" }; +static const char *const ebi_ch0_groups[] = { "gpio75" }; +static const char *const wcss_wlan2_groups[] = { "gpio76" }; +static const char *const wcss_wlan1_groups[] = { "gpio77" }; +static const char *const wcss_wlan0_groups[] = { "gpio78" }; +static const char *const wcss_wlan_groups[] = { + "gpio79", + "gpio80", +}; +static const char *const wcss_fm_groups[] = { + "gpio81", + "gpio82", +}; +static const char *const ext_lpass_groups[] = { "gpio81" }; +static const char *const gcc_tlmm_groups[] = { "gpio87" }; +static const char *const dmic0_clk_groups[] = { "gpio89" }; +static const char *const dmic0_data_groups[] = { "gpio90" }; +static const char *const qdss_cti_trig_in_a1_groups[] = { "gpio91" }; +static const char *const blsp_spi7_groups[] = { + "gpio92", + "gpio93", + "gpio94", + "gpio95", +}; +static const char *const blsp_uart7_groups[] = { + "gpio92", + "gpio93", + "gpio94", + "gpio95", +}; +static const char *const pri_mi2s_ws_groups[] = { "gpio92" }; +static const char *const wsa_io_groups[] = { + "gpio94", + "gpio95", +}; +static const char *const blsp_i2c7_groups[] = { + "gpio94", + "gpio95", +}; +static const char *const blsp_spi8_groups[] = { + "gpio96", + "gpio97", + "gpio98", + "gpio99", +}; +static const char *const blsp_uart8_groups[] = { + "gpio96", + "gpio97", + "gpio98", + "gpio99", +}; +static const char *const blsp_i2c8_groups[] = { + "gpio98", + "gpio99", +}; +static const char *const gcc_plltest_groups[] = { + "gpio98", + "gpio99", +}; +static const char *const nav_pps_in_a_groups[] = { "gpio111" }; +static const char *const pa_indicator_groups[] = { "gpio112" }; +static const char *const nav_pps_in_b_groups[] = { "gpio113" }; +static const char *const nav_pps_groups[] = { "gpio113" }; +static const char *const modem_tsync_groups[] = { "gpio113" }; +static const char *const nav_tsync_groups[] = { "gpio113" }; +static const char *const ssbi_wtr1_groups[] = { + "gpio114", + "gpio123", +}; +static const char *const gsm1_tx_groups[] = { "gpio115" }; +static const char *const gsm0_tx_groups[] = { "gpio117" }; +static const char *const atest_char_groups[] = { "gpio120" }; +static const char *const atest_tsens_groups[] = { "gpio120" }; +static const char *const bimc_dte1_groups[] = { + "gpio121", + "gpio122", +}; + +static const struct pinfunction msm8952_functions[] = { + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(adsp_ext), + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(pbs1), + MSM_PIN_FUNCTION(pwr_modem_enabled_b), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(gcc_gp2_clk_b), + MSM_PIN_FUNCTION(atest_combodac_to_gpio_native), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(gcc_gp1_clk_b), + MSM_PIN_FUNCTION(atest_gpsadc_dtest0_native), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_uart3), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(pbs0), + MSM_PIN_FUNCTION(gcc_gp3_clk_b), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_uart4), + MSM_PIN_FUNCTION(pbs2), + MSM_PIN_FUNCTION(pwr_nav_enabled_b), + MSM_PIN_FUNCTION(pwr_crypto_enabled_b), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(blsp_uart5), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(atest_bbrx1), + MSM_PIN_FUNCTION(qdss_tracectl_b), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(blsp_i2c6), + MSM_PIN_FUNCTION(qdss_traceclk_b), + MSM_PIN_FUNCTION(atest_wlan0), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(atest_bbrx0), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(atest_gpsadc_dtest1_native), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(blsp_spi6), + MSM_PIN_FUNCTION(blsp_uart6), + MSM_PIN_FUNCTION(atest_wlan1), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(pri_mi2s_mclk_a), + MSM_PIN_FUNCTION(sec_mi2s_mclk_a), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(pwr_modem_enabled_a), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(pwr_nav_enabled_a), + MSM_PIN_FUNCTION(pwr_crypto_enabled_a), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(gcc_gp1_clk_a), + MSM_PIN_FUNCTION(gcc_gp2_clk_a), + MSM_PIN_FUNCTION(gcc_gp3_clk_a), + MSM_PIN_FUNCTION(blsp6_spi), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim3_data), + MSM_PIN_FUNCTION(usb_fs), + MSM_PIN_FUNCTION(uim3_clk), + MSM_PIN_FUNCTION(uim3_reset), + MSM_PIN_FUNCTION(uim3_present), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(bimc_dte0), + MSM_PIN_FUNCTION(sec_mi2s_mclk_b), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(ebi_cdc), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(cdc_pdm0), + MSM_PIN_FUNCTION(gp_mn), + MSM_PIN_FUNCTION(gp_pdm_0a), + MSM_PIN_FUNCTION(gp_pdm_0b), + MSM_PIN_FUNCTION(gp_pdm_1a), + MSM_PIN_FUNCTION(gp_pdm_1b), + MSM_PIN_FUNCTION(gp_pdm_2a), + MSM_PIN_FUNCTION(gp_pdm_2b), + MSM_PIN_FUNCTION(gp0_clk), + MSM_PIN_FUNCTION(gp1_clk), + MSM_PIN_FUNCTION(pri_mi2s_mclk_b), + MSM_PIN_FUNCTION(lpass_slimbus), + MSM_PIN_FUNCTION(lpass_slimbus0), + MSM_PIN_FUNCTION(lpass_slimbus1), + MSM_PIN_FUNCTION(wcss_bt), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(ebi_ch0), + MSM_PIN_FUNCTION(wcss_wlan2), + MSM_PIN_FUNCTION(wcss_wlan1), + MSM_PIN_FUNCTION(wcss_wlan0), + MSM_PIN_FUNCTION(wcss_wlan), + MSM_PIN_FUNCTION(wcss_fm), + MSM_PIN_FUNCTION(ext_lpass), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_PIN_FUNCTION(dmic0_clk), + MSM_PIN_FUNCTION(dmic0_data), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(blsp_spi7), + MSM_PIN_FUNCTION(blsp_uart7), + MSM_PIN_FUNCTION(pri_mi2s_ws), + MSM_PIN_FUNCTION(wsa_io), + MSM_PIN_FUNCTION(blsp_i2c7), + MSM_PIN_FUNCTION(blsp_spi8), + MSM_PIN_FUNCTION(blsp_uart8), + MSM_PIN_FUNCTION(blsp_i2c8), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(nav_pps_in_a), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(nav_pps_in_b), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(modem_tsync), + MSM_PIN_FUNCTION(nav_tsync), + MSM_PIN_FUNCTION(ssbi_wtr1), + MSM_PIN_FUNCTION(gsm1_tx), + MSM_PIN_FUNCTION(gsm0_tx), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(bimc_dte1), +}; + +static const struct msm_pingroup msm8952_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, adsp_ext, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, prng_rosc, NA, NA, NA, NA, + NA, NA, NA, qdss_cti_trig_out_b0, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA, + NA, qdss_cti_trig_out_a1, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, ldo_update, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(5, blsp_spi2, blsp_uart2, ldo_en, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, gcc_gp1_clk_b, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, gp_pdm_2a, NA, + atest_gpsadc_dtest0_native, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, blsp_spi3, blsp_uart3, sec_mi2s, pbs0, NA, NA, NA, NA, NA, + NA, qdss_tracedata_b, NA, NA, NA), + PINGROUP(9, blsp_spi3, blsp_uart3, sec_mi2s, pbs1, pwr_modem_enabled_b, + NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA), + PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, gcc_gp2_clk_b, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, gcc_gp3_clk_b, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(12, blsp_spi4, blsp_uart4, sec_mi2s, pbs2, pwr_nav_enabled_b, + NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native), + PINGROUP(13, blsp_spi4, blsp_uart4, sec_mi2s, pwr_crypto_enabled_b, NA, + NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native), + PINGROUP(14, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA, NA), + PINGROUP(15, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA, NA), + PINGROUP(16, blsp_spi5, blsp_uart5, NA, NA, NA, NA, qdss_traceclk_a, NA, + atest_bbrx1, NA, NA, NA, NA, NA), + PINGROUP(17, blsp_spi5, blsp_uart5, m_voc, qdss_cti_trig_in_a0, NA, + atest_bbrx0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, blsp_spi5, blsp_uart5, blsp_i2c5, qdss_tracectl_a, NA, + atest_gpsadc_dtest1_native, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, qdss_tracedata_a, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, blsp_spi6, blsp_uart6, gp_pdm_1b, NA, NA, NA, NA, NA, + qdss_tracectl_b, NA, atest_combodac_to_gpio_native, NA, NA, + NA), + PINGROUP(21, blsp_spi6, blsp_uart6, m_voc, NA, NA, NA, NA, NA, + qdss_cti_trig_in_b0, NA, atest_combodac_to_gpio_native, NA, NA, + NA), + PINGROUP(22, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_traceclk_b, NA, + atest_wlan0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_tracedata_b, NA, + atest_wlan1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(25, mdp_vsync, pri_mi2s_mclk_a, sec_mi2s_mclk_a, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, cam_mclk, NA, NA, NA, NA, NA, qdss_tracedata_a, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(27, cam_mclk, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_a, NA, + NA, NA, NA, NA), + PINGROUP(28, cam_mclk, NA, NA, NA, NA, NA, qdss_tracedata_a, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA, NA), + PINGROUP(29, cci_i2c, pwr_modem_enabled_a, NA, NA, NA, NA, NA, + qdss_tracedata_a, NA, atest_combodac_to_gpio_native, NA, NA, + NA, NA), + PINGROUP(30, cci_i2c, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_a, NA, + atest_combodac_to_gpio_native, NA, NA, NA), + PINGROUP(31, cci_i2c, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_a, NA, + NA, NA, NA, NA), + PINGROUP(32, cci_i2c, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_a, NA, + NA, NA, NA, NA), + PINGROUP(33, cci_timer0, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_a, + NA, NA, NA, NA, NA), + PINGROUP(34, cci_timer1, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_a, + NA, NA, NA, NA, NA), + PINGROUP(35, pwr_nav_enabled_a, NA, NA, NA, NA, NA, NA, NA, + qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(36, pwr_crypto_enabled_a, NA, NA, NA, NA, NA, NA, NA, + qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(37, NA, NA, NA, NA, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(38, gp_pdm_2b, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA, NA), + PINGROUP(39, cci_async, gp_mn, NA, NA, NA, NA, qdss_tracedata_a, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA, NA), + PINGROUP(40, NA, NA, NA, NA, qdss_tracedata_a, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, sd_write, NA, NA, NA, NA, NA, NA, qdss_cti_trig_out_a0, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA), + PINGROUP(42, gcc_gp1_clk_a, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(43, gcc_gp2_clk_a, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(44, gcc_gp3_clk_a, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(45, gp_pdm_1a, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(46, gp0_clk, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(47, blsp6_spi, gp1_clk, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(48, blsp6_spi, gp_pdm_0b, qdss_cti_trig_in_b1, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(49, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(50, qdss_cti_trig_out_b1, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(51, uim1_data, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(52, uim1_clk, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(53, uim1_reset, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(54, uim1_present, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(55, uim2_data, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(56, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(57, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(58, uim2_present, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(59, uim3_data, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(60, uim3_clk, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(61, uim3_reset, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(62, uim3_present, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(63, atest_char3, dbg_out, bimc_dte0, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA, NA), + PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, bimc_dte0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(66, sec_mi2s_mclk_b, pri_mi2s, gp_pdm_0a, qdss_tracedata_b, NA, + NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, atest_char1, ebi_cdc, NA, atest_combodac_to_gpio_native, + NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, atest_char0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(69, cdc_pdm0, pri_mi2s_mclk_b, ebi_cdc, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA, NA), + PINGROUP(70, lpass_slimbus, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(71, lpass_slimbus0, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(72, lpass_slimbus1, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(73, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(74, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(75, wcss_bt, atest_char2, NA, ebi_ch0, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(76, wcss_wlan2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(77, wcss_wlan1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(78, wcss_wlan0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(79, wcss_wlan, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(80, wcss_wlan, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(81, wcss_fm, ext_lpass, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(82, wcss_fm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(83, wcss_bt, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(84, wcss_bt, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(87, qdss_tracedata_b, gcc_tlmm, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(88, pri_mi2s, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, + NA, NA, NA, NA), + PINGROUP(89, dmic0_clk, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(90, dmic0_data, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(91, pri_mi2s, NA, NA, NA, NA, NA, qdss_cti_trig_in_a1, NA, NA, + NA, NA, NA, NA, NA), + PINGROUP(92, blsp_spi7, blsp_uart7, pri_mi2s_ws, NA, NA, NA, NA, NA, + qdss_tracedata_b, NA, NA, NA, NA, NA), + PINGROUP(93, blsp_spi7, blsp_uart7, pri_mi2s, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA, NA), + PINGROUP(94, wsa_io, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA, NA, + NA, NA, NA, NA, NA, NA), + PINGROUP(95, wsa_io, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA, NA, + NA, NA, NA, NA, NA, NA), + PINGROUP(96, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(97, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(98, blsp_i2c8, blsp_spi8, blsp_uart8, gcc_plltest, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA), + PINGROUP(99, blsp_i2c8, blsp_spi8, blsp_uart8, gcc_plltest, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, NA, NA, nav_pps_in_a, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(112, NA, pa_indicator, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(113, NA, nav_pps_in_b, nav_pps, modem_tsync, nav_tsync, NA, NA, + NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, NA, ssbi_wtr1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(115, NA, gsm1_tx, NA, atest_combodac_to_gpio_native, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(116, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(117, gsm0_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(118, NA, ebi_cdc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(119, NA, ebi_cdc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(120, NA, atest_char, ebi_cdc, atest_tsens, NA, NA, NA, NA, NA, + NA, NA, NA, NA, NA), + PINGROUP(121, NA, NA, NA, bimc_dte1, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(122, NA, NA, NA, bimc_dte1, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(123, NA, ssbi_wtr1, ebi_cdc, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(124, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(125, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(126, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(127, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(128, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(129, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(131, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(132, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc1_clk, 0x10a000, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x10a000, 11, 3), + SDC_PINGROUP(sdc1_data, 0x10a000, 9, 0), + SDC_PINGROUP(sdc1_rclk, 0x10a000, 15, 0), + SDC_PINGROUP(sdc2_clk, 0x109000, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x109000, 11, 3), + SDC_PINGROUP(sdc2_data, 0x109000, 9, 0), + SDC_PINGROUP(qdsd_clk, 0x19c000, 3, 0), + SDC_PINGROUP(qdsd_cmd, 0x19c000, 8, 5), + SDC_PINGROUP(qdsd_data0, 0x19c000, 13, 10), + SDC_PINGROUP(qdsd_data1, 0x19c000, 18, 15), + SDC_PINGROUP(qdsd_data2, 0x19c000, 23, 20), + SDC_PINGROUP(qdsd_data3, 0x19c000, 28, 25), +}; + +static const struct msm_gpio_wakeirq_map msm8952_mpm_map[] = { + { 1, 4 }, { 5, 5 }, { 9, 6 }, { 12, 21 }, { 13, 10 }, { 17, 12 }, + { 21, 13 }, { 25, 20 }, { 28, 18 }, { 31, 16 }, { 34, 15 }, { 35, 11 }, + { 36, 9 }, { 37, 8 }, { 38, 3 }, { 42, 19 }, { 43, 22 }, { 44, 23 }, + { 45, 24 }, { 46, 25 }, { 48, 26 }, { 54, 14 }, { 58, 17 }, { 62, 53 }, + { 63, 30 }, { 65, 27 }, { 67, 50 }, { 70, 31 }, { 71, 32 }, { 72, 33 }, + { 73, 51 }, { 74, 52 }, { 81, 34 }, { 85, 35 }, { 90, 36 }, { 93, 28 }, + { 97, 29 }, +}; + +static const struct msm_pinctrl_soc_data msm8952_pinctrl = { + .pins = msm8952_pins, + .npins = ARRAY_SIZE(msm8952_pins), + .functions = msm8952_functions, + .nfunctions = ARRAY_SIZE(msm8952_functions), + .groups = msm8952_groups, + .ngroups = ARRAY_SIZE(msm8952_groups), + .ngpios = 134, + .wakeirq_map = msm8952_mpm_map, + .nwakeirq_map = ARRAY_SIZE(msm8952_mpm_map), +}; + +static int msm8952_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8952_pinctrl); +} + +static const struct of_device_id msm8952_pinctrl_of_match[] = { + { .compatible = "qcom,msm8952-pinctrl", }, + { }, +}; +MODULE_DEVICE_TABLE(of, msm8952_pinctrl_of_match); + +static struct platform_driver msm8952_pinctrl_driver = { + .driver = { + .name = "msm8952-pinctrl", + .of_match_table = msm8952_pinctrl_of_match, + }, + .probe = msm8952_pinctrl_probe, +}; + +static int __init msm8952_pinctrl_init(void) +{ + return platform_driver_register(&msm8952_pinctrl_driver); +} +arch_initcall(msm8952_pinctrl_init); + +static void __exit msm8952_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8952_pinctrl_driver); +} +module_exit(msm8952_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm msm8952 pinctrl driver"); +MODULE_LICENSE("GPL"); From 8d703ee95ade2d83e552025bcfb3344849311693 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Mon, 17 Aug 2026 21:56:58 +0300 Subject: [PATCH 025/106] pinctrl: renesas: rzt2h: Wire up struct gpio_chip::set_config Wire up struct gpio_chip::set_config to allow GPIO settings via pinctrl. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Reviewed-by: Bartosz Golaszewski Link: https://patch.msgid.link/20260817185700.322370-6-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/renesas/pinctrl-rzt2h.c index a37f1e399446..557708368e58 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -1118,6 +1118,7 @@ static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl) chip->direction_output = rzt2h_gpio_direction_output; chip->get = rzt2h_gpio_get; chip->set = rzt2h_gpio_set; + chip->set_config = gpiochip_generic_config; chip->label = dev_name(dev); if (of_property_present(np, "interrupt-controller")) { From 3f3fe195e7d908dc15ad7ab99f38e9225225b538 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Mon, 17 Aug 2026 21:56:59 +0300 Subject: [PATCH 026/106] pinctrl: renesas: rzt2h: Remove unused struct rzt2h_pinctrl::gpio_range The struct rzt2h_pinctrl::gpio_range field is unused and seems to be a vestige of calling pinctrl_add_gpio_range(). Remove it. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260817185700.322370-7-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/renesas/pinctrl-rzt2h.c index 557708368e58..d29ef107c2c1 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -94,7 +94,6 @@ struct rzt2h_pinctrl { void __iomem *base0, *base1; struct device *dev; struct gpio_chip gpio_chip; - struct pinctrl_gpio_range gpio_range; DECLARE_BITMAP(used_irqs, RZT2H_INTERRUPTS_NUM); raw_spinlock_t lock; /* lock read/write registers */ struct mutex mutex; /* serialize adding groups and functions */ @@ -1077,7 +1076,6 @@ static void rzt2h_gpio_init_irq_valid_mask(struct gpio_chip *gc, static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl) { - struct pinctrl_gpio_range *range = &pctrl->gpio_range; struct gpio_chip *chip = &pctrl->gpio_chip; struct device_node *np = pctrl->dev->of_node; struct irq_domain *parent_domain; @@ -1132,13 +1130,6 @@ static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl) girq->init_valid_mask = rzt2h_gpio_init_irq_valid_mask; } - range->id = 0; - range->pin_base = 0; - range->base = 0; - range->npins = chip->ngpio; - range->name = chip->label; - range->gc = chip; - ret = devm_gpiochip_add_data(dev, chip, pctrl); if (ret) return dev_err_probe(dev, ret, "gpiochip registration failed\n"); From 44c232e80adc26634e40b3dbeaa20711da9ecf0d Mon Sep 17 00:00:00 2001 From: Linkai Gong Date: Tue, 25 Aug 2026 11:04:28 +0800 Subject: [PATCH 027/106] pinctrl: amd: add timeout to irq-enable readback amd_gpio_irq_set_type() polls INTERRUPT_ENABLE with IRQs off and no timeout. Use readl_poll_timeout_atomic() and return -ETIMEDOUT. Fixes: b85bfa246efd ("pinctrl/amd: poll InterruptEnable bits in amd_gpio_irq_set_type") Signed-off-by: Linkai Gong Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-amd.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 15a398bb3be2..65728b590999 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -494,7 +495,7 @@ static void amd_gpio_irq_eoi(struct irq_data *d) static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) { int ret = 0; - u32 pin_reg, pin_reg_irq_en, mask; + u32 pin_reg, pin_reg_irq_en, mask, reg; unsigned long flags; struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct amd_gpio *gpio_dev = gpiochip_get_data(gc); @@ -568,8 +569,9 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) pin_reg_irq_en |= mask; pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); writel(pin_reg_irq_en, gpio_dev->base + hwirq * 4); - while ((readl(gpio_dev->base + hwirq * 4) & mask) != mask) - continue; + if (readl_poll_timeout_atomic(gpio_dev->base + hwirq * 4, reg, + (reg & mask) == mask, 1, 1000)) + ret = -ETIMEDOUT; writel(pin_reg, gpio_dev->base + hwirq * 4); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); From 407adb822b0813bc05a345c0adf804b912777ac5 Mon Sep 17 00:00:00 2001 From: Bhargav Joshi Date: Sat, 22 Aug 2026 22:08:53 +0530 Subject: [PATCH 028/106] dt-bindings: pinctrl: ti,pinctrl-palmas: Convert to DT schema Convert TI Palmas pin control text binding to DT schema. The legacy binding allowed any subnode name. Restrict them to standard prefixes to prevent the validator from accidentally evaluating standard integer properties (like phandle) as child nodes. Signed-off-by: Bhargav Joshi Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../bindings/pinctrl/pinctrl-palmas.txt | 105 ----------- .../bindings/pinctrl/ti,palmas-pinctrl.yaml | 170 ++++++++++++++++++ 2 files changed, 170 insertions(+), 105 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/ti,palmas-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt deleted file mode 100644 index c28d4eb83b76..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt +++ /dev/null @@ -1,105 +0,0 @@ -Palmas Pincontrol bindings - -The pins of Palmas device can be set on different option and provides -the configuration for Pull UP/DOWN, open drain etc. - -Required properties: -- compatible: It must be one of following: - - "ti,palmas-pinctrl" for Palma series of the pincontrol. - - "ti,tps65913-pinctrl" for Palma series device TPS65913. - - "ti,tps80036-pinctrl" for Palma series device TPS80036. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Palmas's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -list of pins. This configuration can include the mux function to select on -those pin(s), and various pin configuration parameters, such as pull-up, -open drain. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -Optional properties: -- ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode. - Selection primary or secondary function associated to I2C2_SCL_SCE, - I2C2_SDA_SDO pin/pad for DVFS1 interface -- ti,palmas-enable-dvfs2: Enable DVFS2. Configure pins for DVFS2 mode. - Selection primary or secondary function associated to GPADC_START - and SYSEN2 pin/pad for DVFS2 interface -- ti,palmas-override-powerhold: This is applicable for PMICs for which - GPIO7 is configured in POWERHOLD mode which has higher priority - over DEV_ON bit and keeps the PMIC supplies on even after the DEV_ON - bit is turned off. This property enables driver to over ride the - POWERHOLD value to GPIO7 so as to turn off the PMIC in power off - scenarios. So for GPIO7 if ti,palmas-override-powerhold is set - then the GPIO_7 field should never be muxed to anything else. - It should be set to POWERHOLD by default and only in case of - power off scenarios the driver will over ride the mux value. - -This binding uses the following generic properties as defined in -pinctrl-bindings.txt: - -Required: pins -Options: function, bias-disable, bias-pull-up, bias-pull-down, - drive-open-drain. - -Note that many of these properties are only valid for certain specific pins. -See the Palmas device datasheet for complete details regarding which pins -support which functionality. - -Valid values for pin names are: - gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, gpio9, - gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, vac, powergood, - nreswarm, pwrdown, gpadc_start, reset_in, nsleep, enable1, enable2, - int. - -Valid value of function names are: - gpio, led, pwm, regen, sysen, clk32kgaudio, id, vbus_det, chrg_det, - vac, vacok, powergood, usb_psel, msecure, pwrhold, int, nreswarm, - simrsto, simrsti, low_vbat, wireless_chrg1, rcm, pwrdown, gpadc_start, - reset_in, nsleep, enable. - -There are 4 special functions: opt0, opt1, opt2 and opt3. If any of these -functions is selected then directly pins register will be written with 0, 1, 2 -or 3 respectively if it is valid for that pins or list of pins. - -Example: - palmas: tps65913 { - .... - pinctrl { - compatible = "ti,tps65913-pinctrl"; - ti,palmas-enable-dvfs1; - pinctrl-names = "default"; - pinctrl-0 = <&palmas_pins_state>; - - palmas_pins_state: pinmux { - gpio0 { - pins = "gpio0"; - function = "id"; - bias-pull-up; - }; - - vac { - pins = "vac"; - function = "vacok"; - bias-pull-down; - }; - - gpio5 { - pins = "gpio5"; - function = "opt0"; - drive-open-drain = <1>; - }; - }; - }; - .... - }; diff --git a/Documentation/devicetree/bindings/pinctrl/ti,palmas-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ti,palmas-pinctrl.yaml new file mode 100644 index 000000000000..11c2d429633c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ti,palmas-pinctrl.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ti,palmas-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Palmas Pincontrol + +maintainers: + - Laxman Dewangan + +description: + The pins of Palmas device can be set on different option and provides + the configuration for Pull UP/DOWN, open drain etc. + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + enum: + - ti,palmas-pinctrl + - ti,tps65913-pinctrl + - ti,tps80036-pinctrl + + ti,palmas-enable-dvfs1: + type: boolean + description: + Enable DVFS1. Configure pins for DVFS1 mode. + Selection primary or secondary function associated to I2C2_SCL_SCE, + I2C2_SDA_SDO pin/pad for DVFS1 interface. + + ti,palmas-enable-dvfs2: + type: boolean + description: + Enable DVFS2. Configure pins for DVFS2 mode. + Selection primary or secondary function associated to GPADC_START + and SYSEN2 pin/pad for DVFS2 interface. + + ti,palmas-override-powerhold: + type: boolean + description: + This is applicable for PMICs for which GPIO7 is configured in POWERHOLD + mode which has higher priority over DEV_ON bit and keeps the PMIC + supplies on even after the DEV_ON bit is turned off. This property enables + driver to over ride the POWERHOLD value to GPIO7 so as to turn off the PMIC + in power off scenarios. So for GPIO7 if ti,palmas-override-powerhold is set + then the GPIO_7 field should never be muxed to anything else. + It should be set to POWERHOLD by default and only in case of + power off scenarios the driver will over ride the mux value. + +patternProperties: + '^(pinmux|pins?-[a-z0-9-]+)$': + type: object + additionalProperties: false + patternProperties: + '^(pin.*|gpio[0-9]+|vac|powergood|nreswarm|pwrdown|gpadc_start|reset_in|nsleep|enable[12]|int)$': + type: object + allOf: + - $ref: /schemas/pinctrl/pinmux-node.yaml + - $ref: /schemas/pinctrl/pincfg-node.yaml + unevaluatedProperties: false + properties: + pins: + items: + enum: + - gpio0 + - gpio1 + - gpio2 + - gpio3 + - gpio4 + - gpio5 + - gpio6 + - gpio7 + - gpio8 + - gpio9 + - gpio10 + - gpio11 + - gpio12 + - gpio13 + - gpio14 + - gpio15 + - vac + - powergood + - nreswarm + - pwrdown + - gpadc_start + - reset_in + - nsleep + - enable1 + - enable2 + - int + + function: + description: + Selects the mux function. There are 4 special functions opt0, + opt1, opt2 and opt3. If any of these functions is selected then + directly pins register will be written with 0, 1, 2 or 3 + respectively if it is valid for that pin or list of pins. + enum: + - gpio + - led + - pwm + - regen + - sysen + - clk32kgaudio + - id + - vbus_det + - chrg_det + - vac + - vacok + - powergood + - usb_psel + - msecure + - pwrhold + - int + - nreswarm + - simrsto + - simrsti + - low_vbat + - wireless_chrg1 + - rcm + - pwrdown + - gpadc_start + - reset_in + - nsleep + - enable + - opt0 + - opt1 + - opt2 + - opt3 + + required: + - pins + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + pmic { + pinctrl { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + pinctrl-names = "default"; + pinctrl-0 = <&palmas_pins_state>; + + pinmux { + gpio0 { + pins = "gpio0"; + function = "id"; + bias-pull-up; + }; + + vac { + pins = "vac"; + function = "vacok"; + bias-pull-down; + }; + + gpio5 { + pins = "gpio5"; + function = "opt0"; + drive-open-drain = <1>; + }; + }; + }; + }; From d6a27168cce7339c633bce88df00444489dbb5b7 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Mon, 31 Aug 2026 11:50:57 +0100 Subject: [PATCH 029/106] pinctrl: mpfs-mssio: fix whitespace in debugfs output The printout from mpfs_pinctrl_pinconf_dbg_show() is appended to information from the core, so a leading space is required or the world will end. Fixes: 488d704ed7b7 ("pinctrl: add polarfire soc mssio pinctrl driver") Signed-off-by: Conor Dooley Signed-off-by: Linus Walleij --- drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c b/drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c index ea1026a0d22c..502624221aca 100644 --- a/drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c +++ b/drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c @@ -612,7 +612,7 @@ static void mpfs_pinctrl_pinconf_dbg_show(struct pinctrl_dev *pctrl_dev, struct reg = mpfs_pinctrl_pin_to_iocfg_reg(pin); offset = mpfs_pinctrl_pin_to_iocfg_offset(pin); - seq_printf(seq, "pin: %u ", pin); + seq_printf(seq, " pin: %u ", pin); seq_printf(seq, "reg: %x offset: %u ", reg, offset); if (reg < 0 || offset < 0) From f3db268c44e0900d2e8330de2cbff744766213ff Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2026 10:41:05 +0200 Subject: [PATCH 030/106] dt-bindings: pinctrl: fsl: Replace tabs with spaces YAML files do not use tabs, even within the values in DTS. No functional change, although dt-style-check will warn about it ("[tab-in-yaml] tab character not allowed in DTS example"). Signed-off-by: Krzysztof Kozlowski Acked-by: Peng Fan Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml | 4 ++-- .../devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml | 8 ++++---- .../devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml | 4 ++-- .../devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml | 4 ++-- .../devicetree/bindings/pinctrl/fsl,imx9-pinctrl.yaml | 4 ++-- .../devicetree/bindings/pinctrl/fsl,imxrt1050.yaml | 4 ++-- .../devicetree/bindings/pinctrl/fsl,imxrt1170.yaml | 4 ++-- 7 files changed, 16 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml index 846e110062b2..0a69ed9880e4 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml @@ -179,7 +179,7 @@ examples: pinctrl_uart4: uart4grp { fsl,pins = - <0x288 0x658 0x000 0x3 0x0 0x140>, - <0x28c 0x65c 0x938 0x3 0x3 0x140>; + <0x288 0x658 0x000 0x3 0x0 0x140>, + <0x28c 0x65c 0x938 0x3 0x3 0x140>; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml index 7bd723ab1281..948160cfbc5f 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml @@ -95,8 +95,8 @@ examples: pinctrl_uart5: uart5grp { fsl,pins = - <0x0160 0x03D0 0x0714 0x1 0x0 0x7e>, - <0x0164 0x03D4 0x0000 0x1 0x0 0x76>; + <0x0160 0x03D0 0x0714 0x1 0x0 0x7e>, + <0x0164 0x03D4 0x0000 0x1 0x0 0x76>; }; }; - | @@ -107,7 +107,7 @@ examples: pinctrl_gpio_lpsr: gpio1-grp { fsl,pins = - <0x0008 0x0038 0x0000 0x0 0x0 0x59>, - <0x000C 0x003C 0x0000 0x0 0x0 0x59>; + <0x0008 0x0038 0x0000 0x0 0x0 0x59>, + <0x000C 0x003C 0x0000 0x0 0x0 0x59>; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml index 6068be11dfe2..2341633943c7 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml @@ -82,8 +82,8 @@ examples: pinctrl_uart2: uart2grp { fsl,pins = - <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>, - <0x240 0x4A8 0x000 0x0 0x0 0x140>; + <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>, + <0x240 0x4A8 0x000 0x0 0x0 0x140>; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml index 7dcf681271d3..dc86bf6e580f 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml @@ -74,8 +74,8 @@ examples: pinctrl_lpuart5: lpuart5grp { fsl,pins = - <0x0138 0x08F0 0x4 0x3 0x3>, - <0x013C 0x08EC 0x4 0x3 0x3>; + <0x0138 0x08F0 0x4 0x3 0x3>, + <0x013C 0x08EC 0x4 0x3 0x3>; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx9-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx9-pinctrl.yaml index 96e7b6995273..333b2e7fdaac 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx9-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx9-pinctrl.yaml @@ -78,8 +78,8 @@ examples: pinctrl_uart3: uart3grp { fsl,pins = - <0x48 0x1f8 0x41c 0x1 0x0 0x49>, - <0x4c 0x1fc 0x418 0x1 0x0 0x49>; + <0x48 0x1f8 0x41c 0x1 0x0 0x49>, + <0x4c 0x1fc 0x418 0x1 0x0 0x49>; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml index db5fe66ad873..854fbcd8e78a 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml @@ -73,7 +73,7 @@ examples: pinctrl_lpuart1: lpuart1grp { fsl,pins = - <0x0EC 0x2DC 0x000 0x2 0x0 0xf1>, - <0x0F0 0x2E0 0x000 0x2 0x0 0xf1>; + <0x0EC 0x2DC 0x000 0x2 0x0 0xf1>, + <0x0F0 0x2E0 0x000 0x2 0x0 0xf1>; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml index 2e880b3e537c..988db9507543 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml @@ -71,7 +71,7 @@ examples: reg = <0x400e8000 0x4000>; pinctrl_lpuart1: lpuart1grp { fsl,pins = - <0x16C 0x3B0 0x620 0x0 0x0 0xf1>, - <0x170 0x3B4 0x61C 0x0 0x0 0xf1>; + <0x16C 0x3B0 0x620 0x0 0x0 0xf1>, + <0x170 0x3B4 0x61C 0x0 0x0 0xf1>; }; }; From 7df755632142e59a5aec5f85f2654add49220102 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sun, 13 Sep 2026 22:56:50 +0300 Subject: [PATCH 031/106] pinctrl: renesas: rzt2h: Restore correct pin mode on IRQ free rzt2h_gpio_irq_domain_free() calls rzt2h_pinctrl_set_gpio_en() with false leaving the pin in interrupt function instead of returning it to GPIO mode. Pass true to rzt2h_pinctrl_set_gpio_en() to take the pin out of interrupt function after we're done using it as an IRQ. rzt2h_pinctrl_set_pfc_mode() switches the pin to Hi-Z, losing the previous PM value. Save the PM value before switching to Hi-Z, and restore it after the IRQ is freed. Cc: stable@kernel.org Fixes: 829dde3369a9 ("pinctrl: renesas: rzt2h: Add GPIO IRQ chip to handle interrupts") Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260913195654.3371385-2-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 43 +++++++++++++++++++++---- 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/renesas/pinctrl-rzt2h.c index d29ef107c2c1..9c1ac836ffa6 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -95,6 +95,7 @@ struct rzt2h_pinctrl { struct device *dev; struct gpio_chip gpio_chip; DECLARE_BITMAP(used_irqs, RZT2H_INTERRUPTS_NUM); + u8 saved_pm[RZT2H_INTERRUPTS_NUM]; raw_spinlock_t lock; /* lock read/write registers */ struct mutex mutex; /* serialize adding groups and functions */ bool safety_port_enabled; @@ -169,6 +170,26 @@ static int rzt2h_validate_pin(struct rzt2h_pinctrl *pctrl, unsigned int offset) return (pincfg & BIT(pin)) ? 0 : -EINVAL; } +static u8 rzt2h_pin_read_pm(struct rzt2h_pinctrl *pctrl, u8 port, u8 pin) +{ + u16 reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); + + return field_get(PM_PIN_MASK(pin), reg); +} + +static void rzt2h_pin_write_pm(struct rzt2h_pinctrl *pctrl, u8 port, u8 pin, + unsigned int pm) +{ + u16 reg; + + guard(raw_spinlock_irqsave)(&pctrl->lock); + + reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); + reg &= ~PM_PIN_MASK(pin); + reg |= pm << (pin * 2); + rzt2h_pinctrl_writew(pctrl, port, reg, PM(port)); +} + static void rzt2h_pinctrl_set_gpio_en(struct rzt2h_pinctrl *pctrl, u8 port, u8 pin, bool en) { @@ -1022,16 +1043,23 @@ static int rzt2h_gpio_child_to_parent_hwirq(struct gpio_chip *gc, struct rzt2h_pinctrl *pctrl = gpiochip_get_data(gc); u8 port = RZT2H_PIN_ID_TO_PORT(child); u8 pin = RZT2H_PIN_ID_TO_PIN(child); - u8 parent_irq; + u8 parent_irq, irq_idx; parent_irq = rzt2h_gpio_irq_map[child]; if (parent_irq < RZT2H_INTERRUPTS_START) return -EINVAL; - if (test_and_set_bit(parent_irq - RZT2H_INTERRUPTS_START, - pctrl->used_irqs)) + irq_idx = parent_irq - RZT2H_INTERRUPTS_START; + if (test_and_set_bit(irq_idx, pctrl->used_irqs)) return -EBUSY; + /* + * rzt2h_pinctrl_set_pfc_mode() sets PM to Hi-Z before switching to the + * interrupt function, losing the previous PM value. + * Save it so it can be restored when the IRQ is freed. + */ + pctrl->saved_pm[irq_idx] = rzt2h_pin_read_pm(pctrl, port, pin); + rzt2h_pinctrl_set_pfc_mode(pctrl, port, pin, PFC_FUNC_INTERRUPT); *parent = parent_irq; @@ -1049,14 +1077,17 @@ static void rzt2h_gpio_irq_domain_free(struct irq_domain *domain, unsigned int v irq_hw_number_t hwirq = irqd_to_hwirq(d); u8 port = RZT2H_PIN_ID_TO_PORT(hwirq); u8 pin = RZT2H_PIN_ID_TO_PIN(hwirq); - u8 parent_irq; + u8 parent_irq, irq_idx; parent_irq = rzt2h_gpio_irq_map[hwirq]; if (parent_irq < RZT2H_INTERRUPTS_START) return; - if (test_and_clear_bit(parent_irq - RZT2H_INTERRUPTS_START, pctrl->used_irqs)) - rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, false); + irq_idx = parent_irq - RZT2H_INTERRUPTS_START; + if (test_and_clear_bit(irq_idx, pctrl->used_irqs)) { + rzt2h_pin_write_pm(pctrl, port, pin, pctrl->saved_pm[irq_idx]); + rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, true); + } irq_domain_free_irqs_common(domain, virq, nr_irqs); } From d9980f93cef0f90a11f26296c68ed16b61a95ced Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sun, 13 Sep 2026 22:56:51 +0300 Subject: [PATCH 032/106] pinctrl: renesas: rzt2h: Setup IRQ in .irq_{request,release}_resources() When exporting a GPIO using the deprecated sysfs GPIO API, gpio_is_visible() calls gpiod_to_irq() to determine whether a GPIO is IRQ-capable, which ends up using struct gpio_irq_chip::child_to_parent_hwirq(). When using the GPIO character device, it is possible to request a line and to dynamically switch between using it as an IRQ or as a GPIO, by updating the edge detector. The current struct gpio_irq_chip::child_to_parent_hwirq() implementation makes the assumption that it will only be called with the intention of setting up the IRQ permanently, and that it will only be released when the IRQ domain is freed. Since we now know that this is not the case, take the following steps in order to properly handle that case. Implement struct irq_chip::irq_{request,release}_resources() based on the default GPIOCHIP_IRQ_RESOURCE_HELPERS implementations. Move the IRQ setup and release logic inside them. Keep the mapping logic inside ::child_to_parent_hwirq() to be able to provide a proper HW IRQ number, but do not actually setup the IRQ. Remove rzt2h_gpio_irq_domain_free() as its only purpose was to free the acquired IRQs. irq_domain_free_irqs_common() will still be set up as struct gpio_irq_chip::child_irq_domain_ops::free by gpiochip_hierarchy_setup_domain_ops(). Cc: stable@kernel.org Fixes: 829dde3369a9 ("pinctrl: renesas: rzt2h: Add GPIO IRQ chip to handle interrupts") Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260913195654.3371385-3-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 79 +++++++++++++++---------- 1 file changed, 49 insertions(+), 30 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/renesas/pinctrl-rzt2h.c index 9c1ac836ffa6..796120e70bc4 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -1020,32 +1020,17 @@ static int rzt2h_gpio_irq_set_wake(struct irq_data *d, unsigned int on) return 0; } -static const struct irq_chip rzt2h_gpio_irqchip = { - .name = "rzt2h-gpio", - .irq_disable = rzt2h_gpio_irq_disable, - .irq_enable = rzt2h_gpio_irq_enable, - .irq_mask = irq_chip_mask_parent, - .irq_unmask = irq_chip_unmask_parent, - .irq_set_type = irq_chip_set_type_parent, - .irq_set_wake = rzt2h_gpio_irq_set_wake, - .irq_eoi = irq_chip_eoi_parent, - .irq_set_affinity = irq_chip_set_affinity_parent, - .flags = IRQCHIP_IMMUTABLE, - GPIOCHIP_IRQ_RESOURCE_HELPERS, -}; - -static int rzt2h_gpio_child_to_parent_hwirq(struct gpio_chip *gc, - unsigned int child, - unsigned int child_type, - unsigned int *parent, - unsigned int *parent_type) +static int rzt2h_gpio_irq_request_resources(struct irq_data *d) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct rzt2h_pinctrl *pctrl = gpiochip_get_data(gc); - u8 port = RZT2H_PIN_ID_TO_PORT(child); - u8 pin = RZT2H_PIN_ID_TO_PIN(child); + irq_hw_number_t hwirq = irqd_to_hwirq(d); + u8 port = RZT2H_PIN_ID_TO_PORT(hwirq); + u8 pin = RZT2H_PIN_ID_TO_PIN(hwirq); u8 parent_irq, irq_idx; + int ret; - parent_irq = rzt2h_gpio_irq_map[child]; + parent_irq = rzt2h_gpio_irq_map[hwirq]; if (parent_irq < RZT2H_INTERRUPTS_START) return -EINVAL; @@ -1062,18 +1047,21 @@ static int rzt2h_gpio_child_to_parent_hwirq(struct gpio_chip *gc, rzt2h_pinctrl_set_pfc_mode(pctrl, port, pin, PFC_FUNC_INTERRUPT); - *parent = parent_irq; - *parent_type = child_type; + ret = gpiochip_lock_as_irq(gc, hwirq); + if (ret) { + clear_bit(irq_idx, pctrl->used_irqs); + rzt2h_pin_write_pm(pctrl, port, pin, pctrl->saved_pm[irq_idx]); + rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, true); + return ret; + } return 0; } -static void rzt2h_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, - unsigned int nr_irqs) +static void rzt2h_gpio_irq_release_resources(struct irq_data *d) { - struct irq_data *d = irq_domain_get_irq_data(domain, virq); struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct rzt2h_pinctrl *pctrl = container_of(gc, struct rzt2h_pinctrl, gpio_chip); + struct rzt2h_pinctrl *pctrl = gpiochip_get_data(gc); irq_hw_number_t hwirq = irqd_to_hwirq(d); u8 port = RZT2H_PIN_ID_TO_PORT(hwirq); u8 pin = RZT2H_PIN_ID_TO_PIN(hwirq); @@ -1089,7 +1077,39 @@ static void rzt2h_gpio_irq_domain_free(struct irq_domain *domain, unsigned int v rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, true); } - irq_domain_free_irqs_common(domain, virq, nr_irqs); + gpiochip_unlock_as_irq(gc, hwirq); +} + +static const struct irq_chip rzt2h_gpio_irqchip = { + .name = "rzt2h-gpio", + .irq_disable = rzt2h_gpio_irq_disable, + .irq_enable = rzt2h_gpio_irq_enable, + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_set_type = irq_chip_set_type_parent, + .irq_set_wake = rzt2h_gpio_irq_set_wake, + .irq_eoi = irq_chip_eoi_parent, + .irq_request_resources = rzt2h_gpio_irq_request_resources, + .irq_release_resources = rzt2h_gpio_irq_release_resources, + .irq_set_affinity = irq_chip_set_affinity_parent, + .flags = IRQCHIP_IMMUTABLE, +}; + +static int rzt2h_gpio_child_to_parent_hwirq(struct gpio_chip *gc, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) +{ + u8 parent_irq = rzt2h_gpio_irq_map[child]; + + if (parent_irq < RZT2H_INTERRUPTS_START) + return -EINVAL; + + *parent = parent_irq; + *parent_type = child_type; + + return 0; } static void rzt2h_gpio_init_irq_valid_mask(struct gpio_chip *gc, @@ -1157,7 +1177,6 @@ static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl) girq->parent_domain = parent_domain; girq->child_to_parent_hwirq = rzt2h_gpio_child_to_parent_hwirq; girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; - girq->child_irq_domain_ops.free = rzt2h_gpio_irq_domain_free; girq->init_valid_mask = rzt2h_gpio_init_irq_valid_mask; } From 55297a587c3748f320485a3b37fcccfe6f0440bb Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sun, 13 Sep 2026 22:56:52 +0300 Subject: [PATCH 033/106] pinctrl: renesas: rzt2h: Fix reading pin value in IRQ function rzt2h_gpio_get() only reports a level for pins in input or output mode and returns -EINVAL otherwise. When a pin is requested as an interrupt it is switched to IRQ function and its I/O mode is set to Hi-Z, so its value can no longer be read. gpiolib calls gpiod_get_value_cansleep() to determine the edge's direction when a line is watched with GPIO_V2_LINE_FLAG_EDGE_BOTH. Non-zero values are translated to a rising edge, zero to a falling edge. Since gpiod_get_value_cansleep() ends up calling rzt2h_gpio_get() which returns -EINVAL when the pin is in IRQ function, every edge is reported as rising. When using the IRQ function, the input buffers are enabled and the PINm registers reflect the live state of the input. Report the input level even when the pin is used as an IRQ. Cc: stable@kernel.org Fixes: 829dde3369a9 ("pinctrl: renesas: rzt2h: Add GPIO IRQ chip to handle interrupts") Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260913195654.3371385-4-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/renesas/pinctrl-rzt2h.c index 796120e70bc4..9d7e4cba85c9 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -170,6 +170,16 @@ static int rzt2h_validate_pin(struct rzt2h_pinctrl *pctrl, unsigned int offset) return (pincfg & BIT(pin)) ? 0 : -EINVAL; } +static bool rzt2h_pin_mode_is_peripheral(struct rzt2h_pinctrl *pctrl, u8 port, u8 bit) +{ + return rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit); +} + +static bool rzt2h_pin_read_input(struct rzt2h_pinctrl *pctrl, u8 port, u8 bit) +{ + return rzt2h_pinctrl_readb(pctrl, port, PIN(port)) & BIT(bit); +} + static u8 rzt2h_pin_read_pm(struct rzt2h_pinctrl *pctrl, u8 port, u8 pin) { u16 reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); @@ -847,6 +857,9 @@ static int rzt2h_gpio_get(struct gpio_chip *chip, unsigned int offset) u8 bit = RZT2H_PIN_ID_TO_PIN(offset); u16 reg; + if (rzt2h_pin_mode_is_peripheral(pctrl, port, bit)) + return rzt2h_pin_read_input(pctrl, port, bit); + reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); reg = (reg >> (bit * 2)) & PM_MASK; if (reg & PM_INPUT) From 20253c44c72785ad6d90d6fdc78c96e56a69f4b1 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sun, 13 Sep 2026 22:56:53 +0300 Subject: [PATCH 034/106] pinctrl: renesas: rzt2h: Reuse helpers The PMCm peripheral-mode test, the PINm input read, the PMm write, and the PMm read are open-coded in several places. Reuse the already existing helpers. Reviewed-by: Geert Uytterhoeven Signed-off-by: Cosmin Tanislav Link: https://patch.msgid.link/20260913195654.3371385-5-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 34 +++++++++---------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/renesas/pinctrl-rzt2h.c index 9d7e4cba85c9..80a581fdef37 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -223,7 +223,7 @@ static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl, reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port)); /* Check if pin is already configured to the desired function */ - if ((rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(pin)) && + if (rzt2h_pin_mode_is_peripheral(pctrl, port, pin) && field_get(PFC_PIN_MASK(pin), reg64) == func) return; @@ -777,15 +777,7 @@ static int rzt2h_gpio_request(struct gpio_chip *chip, unsigned int offset) static void rzt2h_gpio_set_direction(struct rzt2h_pinctrl *pctrl, u32 port, u8 bit, bool output) { - u16 reg; - - guard(raw_spinlock_irqsave)(&pctrl->lock); - - reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); - reg &= ~PM_PIN_MASK(bit); - - reg |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); - rzt2h_pinctrl_writew(pctrl, port, reg, PM(port)); + rzt2h_pin_write_pm(pctrl, port, bit, output ? PM_OUTPUT : PM_INPUT); } static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) @@ -794,8 +786,8 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) u8 port = RZT2H_PIN_ID_TO_PORT(offset); u8 bit = RZT2H_PIN_ID_TO_PIN(offset); u64 reg64; - u16 reg; int ret; + u8 pm; ret = rzt2h_validate_pin(pctrl, offset); if (ret) @@ -803,7 +795,7 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) guard(raw_spinlock_irqsave)(&pctrl->lock); - if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) { + if (rzt2h_pin_mode_is_peripheral(pctrl, port, bit)) { /* * When a GPIO is being requested as an IRQ, the pinctrl * framework expects to be able to read the GPIO's direction. @@ -821,11 +813,10 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) return -EINVAL; } - reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); - reg = (reg >> (bit * 2)) & PM_MASK; - if (reg & PM_OUTPUT) + pm = rzt2h_pin_read_pm(pctrl, port, bit); + if (pm & PM_OUTPUT) return GPIO_LINE_DIRECTION_OUT; - if (reg & PM_INPUT) + if (pm & PM_INPUT) return GPIO_LINE_DIRECTION_IN; return -EINVAL; @@ -855,16 +846,15 @@ static int rzt2h_gpio_get(struct gpio_chip *chip, unsigned int offset) struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); u8 port = RZT2H_PIN_ID_TO_PORT(offset); u8 bit = RZT2H_PIN_ID_TO_PIN(offset); - u16 reg; + u8 pm; if (rzt2h_pin_mode_is_peripheral(pctrl, port, bit)) return rzt2h_pin_read_input(pctrl, port, bit); - reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); - reg = (reg >> (bit * 2)) & PM_MASK; - if (reg & PM_INPUT) - return !!(rzt2h_pinctrl_readb(pctrl, port, PIN(port)) & BIT(bit)); - if (reg & PM_OUTPUT) + pm = rzt2h_pin_read_pm(pctrl, port, bit); + if (pm & PM_INPUT) + return rzt2h_pin_read_input(pctrl, port, bit); + if (pm & PM_OUTPUT) return !!(rzt2h_pinctrl_readb(pctrl, port, P(port)) & BIT(bit)); return -EINVAL; From 0cd4a7b3a4883970df3ae8814d9aabdecf65a81e Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sun, 13 Sep 2026 22:56:54 +0300 Subject: [PATCH 035/106] pinctrl: renesas: rzt2h: Add a helper for reading PFC Introduce a rzt2h_pin_read_pfc() helper and replace the open-coded implementation inside rzt2h_gpio_get_direction() to simplify the code. While at it, use field_get() with PFC_PIN_MASK to avoid the manual shift and mask. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260913195654.3371385-6-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/renesas/pinctrl-rzt2h.c index 80a581fdef37..4872a208e0c3 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -175,6 +175,13 @@ static bool rzt2h_pin_mode_is_peripheral(struct rzt2h_pinctrl *pctrl, u8 port, u return rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit); } +static u8 rzt2h_pin_read_pfc(struct rzt2h_pinctrl *pctrl, u8 port, u8 pin) +{ + u64 reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port)); + + return field_get(PFC_PIN_MASK(pin), reg64); +} + static bool rzt2h_pin_read_input(struct rzt2h_pinctrl *pctrl, u8 port, u8 bit) { return rzt2h_pinctrl_readb(pctrl, port, PIN(port)) & BIT(bit); @@ -785,7 +792,6 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); u8 port = RZT2H_PIN_ID_TO_PORT(offset); u8 bit = RZT2H_PIN_ID_TO_PIN(offset); - u64 reg64; int ret; u8 pm; @@ -805,9 +811,7 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) * called to enable the IRQ function. * Default to input direction for IRQ function. */ - reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port)); - reg64 = (reg64 >> (bit * 8)) & PFC_MASK; - if (reg64 == PFC_FUNC_INTERRUPT) + if (rzt2h_pin_read_pfc(pctrl, port, bit) == PFC_FUNC_INTERRUPT) return GPIO_LINE_DIRECTION_IN; return -EINVAL; From d29bfb93a19771b822dab6d7adbbbaf188cb1db5 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 15 Sep 2026 19:00:15 -0500 Subject: [PATCH 036/106] pinctrl: qcom: lpass-lpi: Include value in debugfs output As with other pinctrl providers, it's useful to be able to inspect the current GPIO state of the LPASS LPI pins during system integration and debugging. Extend the driver's debugfs logic to read the current value and include this in the printout. Signed-off-by: Bjorn Andersson Link: https://patch.msgid.link/20260915-pinctrl-lpass-debug-v1-1-bc49766c9f6f@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 5fd4a4eba654..9412fd36a4aa 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -421,6 +421,7 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s, struct pinctrl_pin_desc pindesc; unsigned int func; int is_out; + int value; int drive; int pull; u32 ctl_reg; @@ -443,7 +444,10 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s, drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg); pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); - seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func); + value = lpi_gpio_get(chip, offset); + + seq_printf(s, " %-8s: %-3s", pindesc.name, is_out ? "out" : "in"); + seq_printf(s, " %-4s func%d", str_high_low(value), func); seq_printf(s, " %dmA", lpi_regval_to_drive(drive)); seq_printf(s, " %s", pulls[pull]); } From 1c73cec7a7881eac8bc1b3e8e4fe6e43da5f1517 Mon Sep 17 00:00:00 2001 From: Hemanth Selam Date: Fri, 4 Sep 2026 18:02:56 +0530 Subject: [PATCH 037/106] pinctrl: fix typos in comments Fix typos in comments, reported by scripts/checkpatch.pl using the misspelling list in scripts/spelling.txt. Only touches comments, no code changes. Assisted-by: LLM Signed-off-by: Hemanth Selam Signed-off-by: Linus Walleij --- drivers/pinctrl/core.c | 4 ++-- drivers/pinctrl/pinconf.c | 2 +- drivers/pinctrl/pinctrl-st.c | 2 +- drivers/pinctrl/pinmux.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 1675dd36bd5c..ba6c71e6fc2c 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -147,7 +147,7 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name) { unsigned int i, pin; - /* The pin number can be retrived from the pin controller descriptor */ + /* The pin number can be retrieved from the pin controller descriptor */ for (i = 0; i < pctldev->desc->npins; i++) { struct pin_desc *desc; @@ -1747,7 +1747,7 @@ static int pinctrl_pins_show(struct seq_file *s, void *what) mutex_lock(&pctldev->mutex); - /* The pin number can be retrived from the pin controller descriptor */ + /* The pin number can be retrieved from the pin controller descriptor */ for (i = 0; i < pctldev->desc->npins; i++) { struct pin_desc *desc; diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index 81686844dfa5..ecc888b029d7 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -311,7 +311,7 @@ static int pinconf_pins_show(struct seq_file *s, void *what) mutex_lock(&pctldev->mutex); - /* The pin number can be retrived from the pin controller descriptor */ + /* The pin number can be retrieved from the pin controller descriptor */ for (i = 0; i < pctldev->desc->npins; i++) { struct pin_desc *desc; diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 8ce88e591f47..59ecc295fb8e 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1148,7 +1148,7 @@ static void st_parse_syscfgs(struct st_pinctrl *info, int bank, pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); - /* retime avaiable for all pins by default */ + /* retime available for all pins by default */ pc->rt_pin_mask = 0xff; of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); st_pctl_dt_setup_retime(info, bank, pc); diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index c705bc182266..574fc95b6712 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -636,7 +636,7 @@ static int pinmux_pins_show(struct seq_file *s, void *what) mutex_lock(&pctldev->mutex); - /* The pin number can be retrived from the pin controller descriptor */ + /* The pin number can be retrieved from the pin controller descriptor */ for (i = 0; i < pctldev->desc->npins; i++) { struct pin_desc *desc; bool is_hog = false; From 49a1b31c71a58a2384a8e5bc78fcd40f58e13ff9 Mon Sep 17 00:00:00 2001 From: Hemanth Selam Date: Fri, 4 Sep 2026 18:02:57 +0530 Subject: [PATCH 038/106] pinctrl: fix typo in log message Correct the misspelling in a message the user sees, reported by scripts/checkpatch.pl using the list in scripts/spelling.txt. Only the message text changes, no code changes. Assisted-by: LLM Signed-off-by: Hemanth Selam Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-equilibrium.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-equilibrium.c b/drivers/pinctrl/pinctrl-equilibrium.c index 349eb944b4ac..8e6cd35fc80c 100644 --- a/drivers/pinctrl/pinctrl-equilibrium.c +++ b/drivers/pinctrl/pinctrl-equilibrium.c @@ -618,7 +618,7 @@ static int funcs_utils(struct device *dev, struct pinfunction *funcs, if (of_property_read_string(np, "function", &fn_name)) { /* some groups may not have function, it's OK */ - dev_dbg(dev, "Group %s: not function binded!\n", + dev_dbg(dev, "Group %s: not function bound!\n", (char *)prop->value); continue; } From 01f20711d044f35a7a89ceec33df30e097147e8a Mon Sep 17 00:00:00 2001 From: Karl Mehltretter Date: Sat, 5 Sep 2026 10:02:35 +0200 Subject: [PATCH 039/106] pinctrl: stm32: Drop the nonexistent CONFIG_MACH_STM32MP25 from the STM32MP257 default Commit 619f8ca4a73d ("pinctrl: stm32: add stm32mp257 pinctrl support") made CONFIG_PINCTRL_STM32MP257 default to MACH_STM32MP25, following the MACH_* pattern of the arm32 entries above it, but no Kconfig symbol of that name exists and git log -S finds no Kconfig file that ever defined one: the STM32MP25 family is arm64 only, where CONFIG_ARCH_STM32 covers it. Commit dba0aff2b89b ("pinctrl: stm32: Allow compile as module for stm32mp257") added "|| (ARCH_STM32 && ARM64)" next to it, so the first half now evaluates to n and changes no configuration. Drop the first half. Fixes: 619f8ca4a73d ("pinctrl: stm32: add stm32mp257 pinctrl support") Assisted-by: LLM Signed-off-by: Karl Mehltretter Reviewed-by: Antonio Borneo Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig index d6a171523012..cc425bbfc996 100644 --- a/drivers/pinctrl/stm32/Kconfig +++ b/drivers/pinctrl/stm32/Kconfig @@ -55,7 +55,7 @@ config PINCTRL_STM32MP157 config PINCTRL_STM32MP257 tristate "STMicroelectronics STM32MP257 pin control" depends on OF && HAS_IOMEM - default MACH_STM32MP25 || (ARCH_STM32 && ARM64) + default ARCH_STM32 && ARM64 select PINCTRL_STM32 config PINCTRL_STM32_HDP From 8b6c66cfd1203d99dfe196b3e3f32dec7bec0e7b Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 10 Sep 2026 15:35:12 +0200 Subject: [PATCH 040/106] pinctrl: sunxi: rename SUNXI_PINCTRL_NEW_REG_LAYOUT After keeping the pinctrl IP mostly register compatible for almost a decade, in 2021 Allwinner introduced some changes to the register layout, which made us use a flag called SUNXI_PINCTRL_NEW_REG_LAYOUT. Now with their latest SoC (A733), Allwinner changed the pinctrl IP again, so "NEW" isn't really a fitting name anymore. Rename the symbol to SUNXI_PINCTRL_NCAT2_REG_LAYOUT, with "NCAT2" being a name often used in vendor source code to signify this "new" generation of SoCs. Just a rename of the symbol, no actual code changes. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c | 2 +- drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c | 2 +- drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c | 2 +- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 4 ++-- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c b/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c index 8efe35b77af4..37a60e5d1163 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c @@ -821,7 +821,7 @@ static const struct sunxi_pinctrl_desc d1_pinctrl_data = { static int d1_pinctrl_probe(struct platform_device *pdev) { return sunxi_pinctrl_init_with_flags(pdev, &d1_pinctrl_data, - SUNXI_PINCTRL_NEW_REG_LAYOUT); + SUNXI_PINCTRL_NCAT2_REG_LAYOUT); } static const struct of_device_id d1_pinctrl_match[] = { diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c index 462aa1c4a5fa..9e07fbb5be7c 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c @@ -35,7 +35,7 @@ static int a523_r_pinctrl_probe(struct platform_device *pdev) return sunxi_pinctrl_dt_table_init(pdev, a523_r_nr_bank_pins, a523_r_irq_bank_muxes, &a523_r_pinctrl_data, - SUNXI_PINCTRL_NEW_REG_LAYOUT); + SUNXI_PINCTRL_NCAT2_REG_LAYOUT); } static const struct of_device_id a523_r_pinctrl_match[] = { diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c index b6f78f1f30ac..801f62abc93d 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c @@ -34,7 +34,7 @@ static int a523_pinctrl_probe(struct platform_device *pdev) return sunxi_pinctrl_dt_table_init(pdev, a523_nr_bank_pins, a523_irq_bank_muxes, &a523_pinctrl_data, - SUNXI_PINCTRL_NEW_REG_LAYOUT | + SUNXI_PINCTRL_NCAT2_REG_LAYOUT | SUNXI_PINCTRL_ELEVEN_BANKS); } diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 25489beeb312..bc6948e3fb49 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -1107,7 +1107,7 @@ static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) muxval = (readl(pctl->membase + reg) & mask) >> shift; /* Change muxing to GPIO INPUT mode if at reset value */ - if (pctl->flags & SUNXI_PINCTRL_NEW_REG_LAYOUT) + if (pctl->flags & SUNXI_PINCTRL_NCAT2_REG_LAYOUT) disabled_mux = SUN4I_FUNC_DISABLED_NEW; else disabled_mux = SUN4I_FUNC_DISABLED_OLD; @@ -1589,7 +1589,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev, pctl->dev = &pdev->dev; pctl->desc = desc; pctl->flags = flags; - if (flags & SUNXI_PINCTRL_NEW_REG_LAYOUT) { + if (flags & SUNXI_PINCTRL_NCAT2_REG_LAYOUT) { pctl->bank_mem_size = D1_BANK_MEM_SIZE; pctl->pull_regs_offset = D1_PULL_REGS_OFFSET; pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 0daf7600e2fb..c519055e31b7 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -90,7 +90,7 @@ #define SUN4I_FUNC_DISABLED_NEW 15 #define SUNXI_PINCTRL_VARIANT_MASK GENMASK(7, 0) -#define SUNXI_PINCTRL_NEW_REG_LAYOUT BIT(8) +#define SUNXI_PINCTRL_NCAT2_REG_LAYOUT BIT(8) #define SUNXI_PINCTRL_PORTF_SWITCH BIT(9) #define SUNXI_PINCTRL_ELEVEN_BANKS BIT(10) From 149d4c5c98d5803ad33d169932378be7e68fedc8 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 10 Sep 2026 15:35:13 +0200 Subject: [PATCH 041/106] pinctrl: sunxi: only use PortK special handling on A523 The Allwinner A523 pinctrl IP requires an exception for addressing PortK, since the registers for this GPIO bank did not fit anymore in the existing MMIO frame. Since the A523 was also the first SoC to actually implement PortK, we just enabled this quirk unconditionally. Now the new Allwinner A733 changed the MMIO frame layout, so PortK can and must be handled without any special code. Mark the special casing for PortK with the ELEVEN_BANKS quirk flag we introduced, so that it will only be used on SoCs using the A523 pinctrl IP. Signed-off-by: Andre Przywara Reviewed-by: Chen-Yu Tsai Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index bc6948e3fb49..2524e0b3a2a5 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -67,7 +67,7 @@ static u32 sunxi_bank_offset(const struct sunxi_pinctrl *pctl, u32 pin) { u32 offset = 0; - if (pin >= PK_BASE) { + if (pin >= PK_BASE && (pctl->flags & SUNXI_PINCTRL_ELEVEN_BANKS)) { pin -= PK_BASE; offset = PIO_BANK_K_OFFSET; } From 8b367fc08be4d7fe7892db4351bf8bc51682ac1b Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 10 Sep 2026 15:35:14 +0200 Subject: [PATCH 042/106] pinctrl: sunxi: refactor IRQ register accessors So far on Allwinner SoCs the registers for controlling the IRQ capabilities of each bank are grouped separately, behind all the pinmux related register for all banks: 0x000 0x024 0x144 0x200 0x220 0x320 PortA PortB ... PortJ IRQ-A IRQ-B ... IRQ-J The newest SoCs now group the IRQ registers together with the other per-bank registers, so we need to change the accessor functions to account for that: 0x080 0x0c0 0x100 0x140 0x580 0x5c0 PortA IRQ-A PortB IRQ-B ... PortK IRQ-K In preparation for supporting those newer SoCs, pass in the pointer to "struct sunxi_pinctrl" instead of just its member "desc", so that we gain access to the flags, to later determine which of the layout variants we need to use. To simplify that, add a new sunxi_irq_base_reg() function that returns the respective IRQ register base address. Also split off the IRQ control register base offset (0x200) from each IRQ register's offset, so that the individual offsets can be added later separately, to that base address. No functional change at this point, just refactoring. Signed-off-by: Andre Przywara Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 21 +++++----- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 55 ++++++++++++++++----------- 2 files changed, 44 insertions(+), 32 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 2524e0b3a2a5..5f08c75549b4 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -762,9 +762,10 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, else val = 0xD; /* 3.3V */ - reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); + reg = readl(pctl->membase + sunxi_grp_config_reg(pctl, pin)); reg &= ~IO_BIAS_MASK; - writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); + writel(reg | val, pctl->membase + + sunxi_grp_config_reg(pctl, pin)); return 0; case BIAS_VOLTAGE_PIO_POW_MODE_CTL: val = uV > 1800000 && uV <= 2500000 ? BIT(bank) : 0; @@ -1140,7 +1141,7 @@ static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); - u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq); + u32 reg = sunxi_irq_cfg_reg(pctl, d->hwirq); u8 index = sunxi_irq_cfg_offset(d->hwirq); unsigned long flags; u32 regval; @@ -1187,7 +1188,7 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) static void sunxi_pinctrl_irq_ack(struct irq_data *d) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); - u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq); + u32 status_reg = sunxi_irq_status_reg(pctl, d->hwirq); u8 status_idx = sunxi_irq_status_offset(d->hwirq); /* Clear the IRQ */ @@ -1197,7 +1198,7 @@ static void sunxi_pinctrl_irq_ack(struct irq_data *d) static void sunxi_pinctrl_irq_mask(struct irq_data *d) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); - u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); + u32 reg = sunxi_irq_ctrl_reg(pctl, d->hwirq); u8 idx = sunxi_irq_ctrl_offset(d->hwirq); unsigned long flags; u32 val; @@ -1214,7 +1215,7 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d) static void sunxi_pinctrl_irq_unmask(struct irq_data *d) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); - u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); + u32 reg = sunxi_irq_ctrl_reg(pctl, d->hwirq); u8 idx = sunxi_irq_ctrl_offset(d->hwirq); unsigned long flags; u32 val; @@ -1318,7 +1319,7 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) chained_irq_enter(chip, desc); - reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); + reg = sunxi_irq_status_reg_from_bank(pctl, bank); val = readl(pctl->membase + reg); if (val) { @@ -1557,7 +1558,7 @@ static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl, writel(src | div << 4, pctl->membase + - sunxi_irq_debounce_reg_from_bank(pctl->desc, i)); + sunxi_irq_debounce_reg_from_bank(pctl, i)); } return 0; @@ -1745,10 +1746,10 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev, for (i = 0; i < pctl->desc->irq_banks; i++) { /* Mask and clear all IRQs before registering a handler */ writel(0, pctl->membase + - sunxi_irq_ctrl_reg_from_bank(pctl->desc, i)); + sunxi_irq_ctrl_reg_from_bank(pctl, i)); writel(0xffffffff, pctl->membase + - sunxi_irq_status_reg_from_bank(pctl->desc, i)); + sunxi_irq_status_reg_from_bank(pctl, i)); irq_set_chained_handler_and_data(pctl->irq[i], sunxi_pinctrl_irq_handler, diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index c519055e31b7..15aa6fe62dbb 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -57,20 +57,21 @@ #define IRQ_PER_BANK 32 -#define IRQ_CFG_REG 0x200 +#define IRQ_REGS_OFFSET 0x200 +#define IRQ_CFG_REG_OFFSET 0x00 #define IRQ_CFG_IRQ_PER_REG 8 #define IRQ_CFG_IRQ_BITS 4 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1) -#define IRQ_CTRL_REG 0x210 +#define IRQ_CTRL_REG_OFFSET 0x10 #define IRQ_CTRL_IRQ_PER_REG 32 #define IRQ_CTRL_IRQ_BITS 1 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1) -#define IRQ_STATUS_REG 0x214 +#define IRQ_STATUS_REG_OFFSET 0x14 #define IRQ_STATUS_IRQ_PER_REG 32 #define IRQ_STATUS_IRQ_BITS 1 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) -#define IRQ_DEBOUNCE_REG 0x218 +#define IRQ_DEBOUNCE_REG_OFFSET 0x18 #define IRQ_MEM_SIZE 0x20 @@ -226,7 +227,8 @@ struct sunxi_pinctrl { .irqnum = _irq, \ } -static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank) +static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, + u8 bank) { if (!desc->irq_bank_map) return bank; @@ -234,68 +236,77 @@ static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u return desc->irq_bank_map[bank]; } -static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc, +static inline u32 sunxi_irq_base_reg(const struct sunxi_pinctrl *pctl, u16 bank) +{ + return IRQ_REGS_OFFSET + + sunxi_irq_hw_bank_num(pctl->desc, bank) * IRQ_MEM_SIZE; +} + +static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl *pctl, u16 irq) { u8 bank = irq / IRQ_PER_BANK; u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04; - return IRQ_CFG_REG + - sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg; + return sunxi_irq_base_reg(pctl, bank) + IRQ_CFG_REG_OFFSET + reg; } static inline u32 sunxi_irq_cfg_offset(u16 irq) { u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG; + return irq_num * IRQ_CFG_IRQ_BITS; } -static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) +static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl *pctl, + u8 bank) { - return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; + return sunxi_irq_base_reg(pctl, bank) + IRQ_CTRL_REG_OFFSET; } -static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc, - u16 irq) +static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl *pctl, u16 irq) { u8 bank = irq / IRQ_PER_BANK; - return sunxi_irq_ctrl_reg_from_bank(desc, bank); + return sunxi_irq_ctrl_reg_from_bank(pctl, bank); } static inline u32 sunxi_irq_ctrl_offset(u16 irq) { u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG; + return irq_num * IRQ_CTRL_IRQ_BITS; } -static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) +static inline +u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl *pctl, u8 bank) { - return IRQ_DEBOUNCE_REG + - sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; + return sunxi_irq_base_reg(pctl, bank) + IRQ_DEBOUNCE_REG_OFFSET; } -static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) +static inline +u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl *pctl, u8 bank) { - return IRQ_STATUS_REG + - sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; + return sunxi_irq_base_reg(pctl, bank) + IRQ_STATUS_REG_OFFSET; } -static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc, +static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl *pctl, u16 irq) { u8 bank = irq / IRQ_PER_BANK; - return sunxi_irq_status_reg_from_bank(desc, bank); + return sunxi_irq_status_reg_from_bank(pctl, bank); } static inline u32 sunxi_irq_status_offset(u16 irq) { u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG; + return irq_num * IRQ_STATUS_IRQ_BITS; } -static inline u32 sunxi_grp_config_reg(u16 pin) +static inline u32 sunxi_grp_config_reg(const struct sunxi_pinctrl *pctl, + u16 pin) { u8 bank = pin / PINS_PER_BANK; From 3fa025dfe1e7be11ea9cd2174666d1f953a61226 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 10 Sep 2026 15:35:15 +0200 Subject: [PATCH 043/106] pinctrl: sunxi: support A733 generation MMIO register layout After Allwinner changed the layout of the pinctrl/GPIO IP MMIO register frame only a few years back, the new SoC generation (starting with the A733) changes the layout again: each port now uses 128 instead of 36 or 48 bytes, and the drive level registers move to make space for the new set/clear data registers. Also the PortA registers start at offset 0x80 instead of 0x0 as before, to make room for non-bank specific registers, like the pow_mod_sel registers, at the beginning of the MMIO frame. Finally the IRQ registers move into each bank's region. Add yet another quirk bit to mark this case, and set the existing register offset values to match the new layout. This also requires to add new members to struct sunxi_pinctrl, to accommodate the extra changes. The actual runtime code changes are fortunately minor. Signed-off-by: Andre Przywara Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 14 ++++++++++++-- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 14 ++++++++++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 5f08c75549b4..35aa3a8ea181 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -65,7 +65,7 @@ static struct irq_chip sunxi_pinctrl_level_irq_chip; */ static u32 sunxi_bank_offset(const struct sunxi_pinctrl *pctl, u32 pin) { - u32 offset = 0; + u32 offset = pctl->bank_offset; if (pin >= PK_BASE && (pctl->flags & SUNXI_PINCTRL_ELEVEN_BANKS)) { pin -= PK_BASE; @@ -102,7 +102,7 @@ static void sunxi_dlevel_reg(const struct sunxi_pinctrl *pctl, { u32 offset = pin % PINS_PER_BANK * pctl->dlevel_field_width; - *reg = sunxi_bank_offset(pctl, pin) + DLEVEL_REGS_OFFSET + + *reg = sunxi_bank_offset(pctl, pin) + pctl->drv_regs_offset + offset / BITS_PER_TYPE(u32) * sizeof(u32); *shift = offset % BITS_PER_TYPE(u32); *mask = (BIT(pctl->dlevel_field_width) - 1) << *shift; @@ -1592,15 +1592,25 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev, pctl->flags = flags; if (flags & SUNXI_PINCTRL_NCAT2_REG_LAYOUT) { pctl->bank_mem_size = D1_BANK_MEM_SIZE; + pctl->drv_regs_offset = DLEVEL_REGS_OFFSET; pctl->pull_regs_offset = D1_PULL_REGS_OFFSET; pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH; + } else if (flags & SUNXI_PINCTRL_NCAT3_REG_LAYOUT) { + pctl->bank_mem_size = A733_BANK_MEM_SIZE; + pctl->bank_offset = A733_BANK_OFFSET; + pctl->drv_regs_offset = A733_DLEVEL_REGS_OFFSET; + pctl->pull_regs_offset = A733_PULL_REGS_OFFSET; + pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH; } else { pctl->bank_mem_size = BANK_MEM_SIZE; + pctl->drv_regs_offset = DLEVEL_REGS_OFFSET; pctl->pull_regs_offset = PULL_REGS_OFFSET; pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH; } if (flags & SUNXI_PINCTRL_ELEVEN_BANKS) pctl->pow_mod_sel_offset = PIO_11B_POW_MOD_SEL_REG; + else if (flags & SUNXI_PINCTRL_NCAT3_REG_LAYOUT) + pctl->pow_mod_sel_offset = PIO_NCAT3_POW_MOD_SEL_REG; else pctl->pow_mod_sel_offset = PIO_POW_MOD_SEL_REG; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 15aa6fe62dbb..d09467ed437a 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -53,6 +53,12 @@ #define D1_DLEVEL_FIELD_WIDTH 4 #define D1_PULL_REGS_OFFSET 0x24 +#define A733_BANK_MEM_SIZE 0x80 +#define A733_BANK_OFFSET 0x80 +#define A733_DLEVEL_REGS_OFFSET 0x20 +#define A733_PULL_REGS_OFFSET 0x30 +#define A733_IRQ_REGS_OFFSET 0x40 + #define PINS_PER_BANK 32 #define IRQ_PER_BANK 32 @@ -94,7 +100,9 @@ #define SUNXI_PINCTRL_NCAT2_REG_LAYOUT BIT(8) #define SUNXI_PINCTRL_PORTF_SWITCH BIT(9) #define SUNXI_PINCTRL_ELEVEN_BANKS BIT(10) +#define SUNXI_PINCTRL_NCAT3_REG_LAYOUT BIT(11) +#define PIO_NCAT3_POW_MOD_SEL_REG 0x040 #define PIO_POW_MOD_SEL_REG 0x340 #define PIO_11B_POW_MOD_SEL_REG 0x380 #define PIO_POW_MOD_CTL_OFS 0x004 @@ -179,6 +187,8 @@ struct sunxi_pinctrl { struct pinctrl_dev *pctl_dev; unsigned long flags; u32 bank_mem_size; + u32 bank_offset; + u32 drv_regs_offset; u32 pull_regs_offset; u32 dlevel_field_width; u32 pow_mod_sel_offset; @@ -238,6 +248,10 @@ static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, static inline u32 sunxi_irq_base_reg(const struct sunxi_pinctrl *pctl, u16 bank) { + if (pctl->flags & SUNXI_PINCTRL_NCAT3_REG_LAYOUT) + return pctl->bank_offset + bank * pctl->bank_mem_size + + A733_IRQ_REGS_OFFSET; + return IRQ_REGS_OFFSET + sunxi_irq_hw_bank_num(pctl->desc, bank) * IRQ_MEM_SIZE; } From 5777ddfb5f361269e26a1989c9da774e3349c639 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 10 Sep 2026 15:35:16 +0200 Subject: [PATCH 044/106] dt-bindings: pinctrl: add compatible for Allwinner A733 The A733 contains a pin controller similar to previous SoCs, although with a change in the MMIO register frame layout. This SoC uses the new style of DT binding, where the pinmux values for each pin group are stored in the new "allwinner,pinmux" property in the DT node. Add the new compatible to the existing A523 binding, since they share a lot of features, including the number of banks and clocks. Signed-off-by: Andre Przywara Acked-by: Conor Dooley Signed-off-by: Linus Walleij --- .../bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml index f87b8274cc37..d7d0ba32ced4 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/allwinner,sun55i-a523-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A523 Pin Controller +title: Allwinner A523 & A733 Pin Controller maintainers: - Andre Przywara @@ -28,6 +28,8 @@ properties: enum: - allwinner,sun55i-a523-pinctrl - allwinner,sun55i-a523-r-pinctrl + - allwinner,sun60i-a733-pinctrl + - allwinner,sun60i-a733-r-pinctrl reg: maxItems: 1 @@ -126,6 +128,7 @@ allOf: compatible: enum: - allwinner,sun55i-a523-pinctrl + - allwinner,sun60i-a733-pinctrl then: properties: @@ -138,6 +141,7 @@ allOf: compatible: enum: - allwinner,sun55i-a523-r-pinctrl + - allwinner,sun60i-a733-r-pinctrl then: properties: From 31d68e10381cdcad09b7447eef68f8d03a6b3228 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 10 Sep 2026 15:35:17 +0200 Subject: [PATCH 045/106] pinctrl: sunxi: a523-r: add a733-r compatible string The secondary Allwinner A733 pincontroller ("-r") is interestingly not using the same new MMIO frame layout as the main controller, but is in fact very similar to the A523-r one: it has two banks, with 14 and 6 pins each. From the driver's perspective, this is all we care about, so we can re-use the a523-r pinctrl driver for the a733-r, too. The individual pinmux settings are different, so we must not use the a523-r compatible string as a fallback, but we can surely let the same driver care for both the a523-r and a733-r IP, as the pinmux values will be provided by the DT. Add the a733-r compatible string to the match list, without further distinguishing between the two. Should differences be discovered later, we can easily split this up then. Signed-off-by: Andre Przywara Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c index 9e07fbb5be7c..dfdcfa740ecc 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c @@ -40,6 +40,7 @@ static int a523_r_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id a523_r_pinctrl_match[] = { { .compatible = "allwinner,sun55i-a523-r-pinctrl", }, + { .compatible = "allwinner,sun60i-a733-r-pinctrl", }, {} }; From 0535bfbfa97bd3fe43749952756ef08917b31e48 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 10 Sep 2026 15:35:18 +0200 Subject: [PATCH 046/106] pinctrl: sunxi: add support for the Allwinner A733 The Allwinner A733 changes the layout of the pinctrl MMIO register frame, but stays otherwise rather close to the previous IP. The main PIO looks similar to the one in the A523, with ports B-K being implemented, each also with the same number of pins per port as on the A523. Use the DT based pinctrl driver to describe just the generic pinctrl properties, so advertise the number of pins per bank, interrupt capabilities and the new quirks. The actual function/mux assignment will be taken from the devicetree. Signed-off-by: Andre Przywara Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/Kconfig | 5 +++ drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c | 50 +++++++++++++++++++++ 3 files changed, 56 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index dc62eba96348..831bb1dc9373 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -141,4 +141,9 @@ config PINCTRL_SUN55I_A523_R default ARM64 && ARCH_SUNXI select PINCTRL_SUNXI +config PINCTRL_SUN60I_A733 + bool "Support for the Allwinner A733 PIO" + default ARM64 && ARCH_SUNXI + select PINCTRL_SUNXI + endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 951b3f1e4b4f..3658c9d06b49 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -29,5 +29,6 @@ obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o obj-$(CONFIG_PINCTRL_SUN50I_H616_R) += pinctrl-sun50i-h616-r.o obj-$(CONFIG_PINCTRL_SUN55I_A523) += pinctrl-sun55i-a523.o obj-$(CONFIG_PINCTRL_SUN55I_A523_R) += pinctrl-sun55i-a523-r.o +obj-$(CONFIG_PINCTRL_SUN60I_A733) += pinctrl-sun60i-a733.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c b/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c new file mode 100644 index 000000000000..ca82f08a3a65 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Allwinner A733 SoC pinctrl driver. + * + * Copyright (C) 2025 Arm Ltd. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const u8 a733_nr_bank_pins[SUNXI_PINCTRL_MAX_BANKS] = +/* PA PB PC PD PE PF PG PH PI PJ PK */ + { 0, 11, 17, 24, 16, 7, 15, 20, 17, 28, 26 }; + +static const u8 a733_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] = +/* PA PB PC PD PE PF PG PH PI PJ PK */ + { 0, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}; + +static struct sunxi_pinctrl_desc a733_pinctrl_data = { + .irq_banks = 10, + .irq_read_needs_mux = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, +}; + +static int a733_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_dt_table_init(pdev, a733_nr_bank_pins, + a733_irq_bank_muxes, + &a733_pinctrl_data, + SUNXI_PINCTRL_NCAT3_REG_LAYOUT); +} + +static const struct of_device_id a733_pinctrl_match[] = { + { .compatible = "allwinner,sun60i-a733-pinctrl", }, + {} +}; + +static struct platform_driver a733_pinctrl_driver = { + .probe = a733_pinctrl_probe, + .driver = { + .name = "sun60i-a733-pinctrl", + .of_match_table = a733_pinctrl_match, + }, +}; +builtin_platform_driver(a733_pinctrl_driver); From 400f2c68e261e160d915ea8016967dc6928bef5a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 13 Sep 2026 14:32:24 +0200 Subject: [PATCH 047/106] dt-bindings: pinctrl: Use consistent indentation in the example Correct indentation in the examples to consistent 2- or 4-spaces indentation to fix dt-check-style warnings ("example 0 [indent-consistent] indent mismatch ..."). Preferred is 4-spaces, but re-indenting entire example just for that is too much churn. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Gary Yang Reviewed-by: Michal Simek # ZynqMP Signed-off-by: Linus Walleij --- .../pinctrl/awinic,aw9523-pinctrl.yaml | 50 +++++++++---------- .../bindings/pinctrl/cix,sky1-pinctrl.yaml | 2 +- .../bindings/pinctrl/fsl,imx7d-pinctrl.yaml | 8 +-- .../bindings/pinctrl/intel,lgm-io.yaml | 14 +++--- .../pinctrl/mediatek,mt8183-pinctrl.yaml | 4 +- .../pinctrl/mediatek,mt8195-pinctrl.yaml | 2 +- .../bindings/pinctrl/qcom,hawi-tlmm.yaml | 4 +- .../bindings/pinctrl/qcom,kaanapali-tlmm.yaml | 4 +- .../bindings/pinctrl/qcom,maili-tlmm.yaml | 4 +- .../bindings/pinctrl/semtech,sx1501q.yaml | 4 +- .../bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml | 46 ++++++++--------- 11 files changed, 71 insertions(+), 71 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/awinic,aw9523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/awinic,aw9523-pinctrl.yaml index 98c310a3c63c..1c09c0fd4930 100644 --- a/Documentation/devicetree/bindings/pinctrl/awinic,aw9523-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/awinic,aw9523-pinctrl.yaml @@ -108,32 +108,32 @@ examples: #size-cells = <0>; aw9523: gpio-expander@58 { - compatible = "awinic,aw9523-pinctrl"; - reg = <0x58>; - interrupt-parent = <&tlmm>; - interrupts = <50 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 16>; - interrupt-controller; - #interrupt-cells = <2>; - reset-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; + compatible = "awinic,aw9523-pinctrl"; + reg = <0x58>; + interrupt-parent = <&tlmm>; + interrupts = <50 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 16>; + interrupt-controller; + #interrupt-cells = <2>; + reset-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; - keyboard-matrix-col-pins { - pins = "gpio8", "gpio9", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", "gpio15"; - function = "gpio"; - input-disable; - output-low; - }; + keyboard-matrix-col-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + input-disable; + output-low; + }; - keyboard-matrix-row-pins { - pins = "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6", "gpio7"; - function = "gpio"; - bias-pull-up; - drive-open-drain; - input-enable; - }; + keyboard-matrix-row-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + bias-pull-up; + drive-open-drain; + input-enable; + }; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml index 8ed53496c386..4ab1f00775cc 100644 --- a/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml @@ -86,6 +86,6 @@ examples: pinmux = ; bias-pull-up; drive-strength = <8>; - }; + }; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml index 948160cfbc5f..7275215918bb 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml @@ -106,8 +106,8 @@ examples: fsl,input-sel = <&iomuxc>; pinctrl_gpio_lpsr: gpio1-grp { - fsl,pins = - <0x0008 0x0038 0x0000 0x0 0x0 0x59>, - <0x000C 0x003C 0x0000 0x0 0x0 0x59>; - }; + fsl,pins = + <0x0008 0x0038 0x0000 0x0 0x0 0x59>, + <0x000C 0x003C 0x0000 0x0 0x0 0x59>; + }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml b/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml index 1144ca2896e3..96c405711f65 100644 --- a/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml +++ b/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml @@ -64,13 +64,13 @@ examples: reg = <0xe2880000 0x100000>; uart0-pins { - pins = <64>, /* UART_RX0 */ - <65>; /* UART_TX0 */ - function = "CONSOLE_UART0"; - pinmux = <1>, - <1>; - groups = "CONSOLE_UART0"; - }; + pins = <64>, /* UART_RX0 */ + <65>; /* UART_TX0 */ + function = "CONSOLE_UART0"; + pinmux = <1>, + <1>; + groups = "CONSOLE_UART0"; + }; }; ... diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml index 3db2438fadc7..4bcee7741fcd 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -221,8 +221,8 @@ examples: i2c0_pins_a: i2c0-pins { pins1 { - pinmux = , - ; + pinmux = , + ; mediatek,pull-up-adv = <3>; drive-strength-microamp = <1000>; }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml index 33cb71775db9..0bcafa78acb2 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml @@ -234,7 +234,7 @@ examples: - | #include #include - # + pio: pinctrl@10005000 { compatible = "mediatek,mt8195-pinctrl"; reg = <0x10005000 0x1000>, diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml index 3b3961789860..2b1354e212e5 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml @@ -113,8 +113,8 @@ examples: #interrupt-cells = <2>; qup-uart7-state { - pins = "gpio62", "gpio63"; - function = "qup1_se7"; + pins = "gpio62", "gpio63"; + function = "qup1_se7"; }; }; ... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,kaanapali-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,kaanapali-tlmm.yaml index 53534a07a1f0..ea7d4768483d 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,kaanapali-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,kaanapali-tlmm.yaml @@ -120,8 +120,8 @@ examples: #interrupt-cells = <2>; qup-uart7-state { - pins = "gpio62", "gpio63"; - function = "qup1_se7"; + pins = "gpio62", "gpio63"; + function = "qup1_se7"; }; }; ... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml index 64fe90b2391b..a0b56adb3388 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml @@ -113,8 +113,8 @@ examples: #interrupt-cells = <2>; qup-uart7-state { - pins = "gpio62", "gpio63"; - function = "qup1_se7"; + pins = "gpio62", "gpio63"; + function = "qup1_se7"; }; }; ... diff --git a/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml b/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml index 39d7dad3313b..f7a7551d7f50 100644 --- a/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml +++ b/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml @@ -244,8 +244,8 @@ examples: interrupt-controller; gpio1-cfg { - pins = "gpio1"; - bias-pull-up; + pins = "gpio1"; + bias-pull-up; }; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml index ce66fd15ff9c..300d38f87f2d 100644 --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml @@ -317,37 +317,37 @@ examples: #include zynqmp_firmware: zynqmp-firmware { pinctrl0: pinctrl { - compatible = "xlnx,zynqmp-pinctrl"; + compatible = "xlnx,zynqmp-pinctrl"; - pinctrl_uart1_default: uart1-default { - mux { - groups = "uart0_4_grp", "uart0_5_grp"; - function = "uart0"; - }; + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart0_4_grp", "uart0_5_grp"; + function = "uart0"; + }; - conf { - groups = "uart0_4_grp"; - slew-rate = ; - power-source = ; - }; + conf { + groups = "uart0_4_grp"; + slew-rate = ; + power-source = ; + }; - conf-rx { - pins = "MIO18"; - bias-pull-up; - }; + conf-rx { + pins = "MIO18"; + bias-pull-up; + }; - conf-tx { - pins = "MIO19"; - bias-disable; - input-schmitt-disable; - }; - }; + conf-tx { + pins = "MIO19"; + bias-disable; + input-schmitt-disable; + }; + }; }; }; uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; }; ... From 7dcf87d2dbbe8c9c1efb69fe9be728a3dfd51d3d Mon Sep 17 00:00:00 2001 From: Andrew Gaylard Date: Wed, 16 Sep 2026 12:49:19 +0200 Subject: [PATCH 048/106] pinctrl: fix PINCTRL_SPPCTL=m The PINCTRL_SPPCTL option is defined as a tristate in Kconfig, and the help text suggests that the user can build it as a module by setting to 'm'. However, it cannot currently be set to 'm', because SOC_SP7021, the only platform that supports it, is a bool option that uses 'select' on it. Also, the SP7021 requires this driver to be built in, in order to boot. Change the tristate to bool and fix the help text. Tested on linux-next-2026-09-14 on a LTPP3G2 board. This impossible tristate was detected by kconfirm, a static analysis tool for Kconfig, by Julian Braha . Fixes: aa74c44be19c ("pinctrl: Add driver for Sunplus SP7021") Signed-off-by: Andrew Gaylard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunplus/Kconfig | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/sunplus/Kconfig b/drivers/pinctrl/sunplus/Kconfig index 69f82590f6d2..aa9435d023d8 100644 --- a/drivers/pinctrl/sunplus/Kconfig +++ b/drivers/pinctrl/sunplus/Kconfig @@ -4,8 +4,8 @@ # config PINCTRL_SPPCTL - tristate "Sunplus SP7021 PinMux and GPIO driver" - depends on SOC_SP7021 + bool "Sunplus SP7021 PinMux and GPIO driver" + depends on SOC_SP7021 || COMPILE_TEST depends on OF && HAS_IOMEM select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS @@ -16,6 +16,4 @@ config PINCTRL_SPPCTL help Say Y here to support Sunplus SP7021 pinmux controller. This driver requires the pinctrl framework. - GPIO is provided by the same driver. - To compile this driver as a module, choose M here. - The module will be called sppinctrl. + This driver also provides GPIO. From 4d7c9430a26aea6a69521af3aa2d78dd5bc8d3ed Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Thu, 17 Sep 2026 14:10:13 -0700 Subject: [PATCH 049/106] pinctrl: qcom: tlmm-test: Add const to reg_names allocation type In preparation for converting the kmalloc family of allocators to the type-aware kmalloc_obj family, we need to make sure that the returned type from the allocation matches the type of the variable being assigned. (The kmalloc family returns "void *", which can be implicitly cast to any pointer type.) The assigned type is "const char **", but the converted allocation type would be "char **", which is the same type without the const qualifier. As there is no general way to safely add const qualifiers, take the size from the assignment target instead. No change in allocation size results. Build tested ARCH=x86_64 allmodconfig with GCC 16.2.0: drivers/pinctrl/qcom/tlmm-test.o Assisted-by: LLM coccinelle Signed-off-by: Kees Cook Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260917211009.i.312-kees@kernel.org Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/qcom/tlmm-test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/tlmm-test.c b/drivers/pinctrl/qcom/tlmm-test.c index 13c417731be7..8bff92dc0d0b 100644 --- a/drivers/pinctrl/qcom/tlmm-test.c +++ b/drivers/pinctrl/qcom/tlmm-test.c @@ -587,7 +587,7 @@ static int tlmm_reg_base(struct device_node *tlmm, struct resource *res) return count; } - reg_names = kcalloc(count, sizeof(char *), GFP_KERNEL); + reg_names = kcalloc(count, sizeof(*reg_names), GFP_KERNEL); if (!reg_names) return -ENOMEM; From c2d996d9c6dab31ae41d19507c2b7ef8dbc14602 Mon Sep 17 00:00:00 2001 From: Mehmet Fide Date: Thu, 24 Sep 2026 08:55:14 +0200 Subject: [PATCH 050/106] pinctrl: include linux/errno.h in consumer.h for ENOTSUPP The CONFIG_PINCTRL=n stubs of pinctrl_gpio_get_config() and pinctrl_gpio_set_config() return -ENOTSUPP, but the header only pulls in linux/err.h, which provides asm/errno.h and not the kernel-internal ENOTSUPP from linux/errno.h. A translation unit that includes pinctrl/consumer.h before anything else fails to build: include/linux/pinctrl/consumer.h:110:10: error: use of undeclared identifier 'ENOTSUPP' Include linux/errno.h explicitly. Fixes: b44aec87658e ("pinctrl: make the CONFIG_PINCTRL=n gpio config stubs return -ENOTSUPP") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202609240855.U59akHDO-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202609241240.61Hz5rix-lkp@intel.com/ Signed-off-by: Mehmet Fide Reviewed-by: Bartosz Golaszewski Signed-off-by: Linus Walleij --- include/linux/pinctrl/consumer.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h index 7be49d447426..81e7866bd2e3 100644 --- a/include/linux/pinctrl/consumer.h +++ b/include/linux/pinctrl/consumer.h @@ -12,6 +12,7 @@ #define __LINUX_PINCTRL_CONSUMER_H #include +#include #include #include From a854aa8e550502ef05c2836a4b426141d735bed1 Mon Sep 17 00:00:00 2001 From: Wentao Liang Date: Thu, 17 Sep 2026 13:48:11 +0000 Subject: [PATCH 051/106] pinctrl: nuvoton: Fix clock reference leak in ma35_get_bank_data() ma35_get_bank_data() obtains the bank clock with of_clk_get() and stores it in bank->clk, but returns clk_prepare_enable() directly. If that call fails, the reference taken by of_clk_get() is never dropped, and the driver has no other clk_put() for it. Drop the reference when clk_prepare_enable() fails. Fixes: f805e356313b ("pinctrl: nuvoton: Add ma35d1 pinctrl and GPIO driver") Signed-off-by: Wentao Liang Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-ma35.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvoton/pinctrl-ma35.c index dafa85c105a1..a79ebf4be2c3 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-ma35.c +++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c @@ -557,6 +557,8 @@ static int ma35_gpiolib_register(struct platform_device *pdev, struct ma35_pinct static int ma35_get_bank_data(struct ma35_pin_bank *bank) { + int ret; + bank->reg_base = fwnode_iomap(bank->fwnode, 0); if (!bank->reg_base) return -ENOMEM; @@ -569,7 +571,11 @@ static int ma35_get_bank_data(struct ma35_pin_bank *bank) if (IS_ERR(bank->clk)) return PTR_ERR(bank->clk); - return clk_prepare_enable(bank->clk); + ret = clk_prepare_enable(bank->clk); + if (ret) + clk_put(bank->clk); + + return ret; } static int ma35_pinctrl_get_soc_data(struct ma35_pinctrl *pctl, struct platform_device *pdev) From dfd8259507c53a3c7eb0dd11c1152c88e12aa316 Mon Sep 17 00:00:00 2001 From: Wentao Liang Date: Thu, 17 Sep 2026 13:50:56 +0000 Subject: [PATCH 052/106] pinctrl: stm32: Fix clock reference leak in stm32_pctl_probe() stm32_pctl_probe() obtains one clock per bank with of_clk_get_by_name(), but none of the error paths drop those references: the loop returns directly when a later clock lookup fails, and both the clk_bulk_prepare_enable() failure and the err_register path return without calling clk_bulk_put(). clk_bulk_disable_unprepare() only disables the clocks, it does not release them. Release the references on these paths; the success path keeps them as the driver needs them for suspend/resume. Fixes: 451bc9aea9a1 ("pinctrl: stm32: Add check for clk_enable()") Signed-off-by: Wentao Liang Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 6a99708a5a23..587dbf1512dc 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -1976,6 +1976,7 @@ int stm32_pctl_probe(struct platform_device *pdev) pctl->clks[i].clk = of_clk_get_by_name(np, NULL); if (IS_ERR(pctl->clks[i].clk)) { fwnode_handle_put(child); + clk_bulk_put(i, pctl->clks); return dev_err_probe(dev, PTR_ERR(pctl->clks[i].clk), "failed to get clk\n"); } @@ -1986,6 +1987,7 @@ int stm32_pctl_probe(struct platform_device *pdev) ret = clk_bulk_prepare_enable(banks, pctl->clks); if (ret) { dev_err(dev, "failed to prepare_enable clk (%d)\n", ret); + clk_bulk_put(banks, pctl->clks); return ret; } @@ -2010,6 +2012,7 @@ int stm32_pctl_probe(struct platform_device *pdev) } clk_bulk_disable_unprepare(banks, pctl->clks); + clk_bulk_put(banks, pctl->clks); return ret; } EXPORT_SYMBOL(stm32_pctl_probe); From 5678facf8979f62fb56d6554b81bf9cf3a9346fc Mon Sep 17 00:00:00 2001 From: Aryan Sinha Date: Thu, 17 Sep 2026 23:33:25 +0530 Subject: [PATCH 053/106] pinctrl: gemini: fix kernel-doc warnings struct gemini_pmx documents a virtbase member that does not exist and leaves pctl undocumented. struct gemini_pmx_func is missing num_groups. Drop the stale entry and add the two missing ones. No functional change. Signed-off-by: Aryan Sinha Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-gemini.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-gemini.c b/drivers/pinctrl/pinctrl-gemini.c index e9f61927858d..a029cab229bf 100644 --- a/drivers/pinctrl/pinctrl-gemini.c +++ b/drivers/pinctrl/pinctrl-gemini.c @@ -41,7 +41,7 @@ struct gemini_pin_conf { /** * struct gemini_pmx - state holder for the gemini pin controller * @dev: a pointer back to containing device - * @virtbase: the offset to the controller in virtual memory + * @pctl: the pin controller device * @map: regmap to access registers * @is_3512: whether the SoC/package is the 3512 variant * @is_3516: whether the SoC/package is the 3516 variant @@ -2031,6 +2031,7 @@ static const struct pinctrl_ops gemini_pctrl_ops = { * struct gemini_pmx_func - describes Gemini pinmux functions * @name: the name of this specific function * @groups: corresponding pin groups + * @num_groups: the number of pin groups */ struct gemini_pmx_func { const char *name; From cbb91e55a9d5227e53531ec5cc726411c9196a3d Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Thu, 17 Sep 2026 14:13:24 -0700 Subject: [PATCH 054/106] pinctrl: mediatek: Fix eint->base allocation type In preparation for making the devm_kmalloc family of allocators type aware, we need to make sure that the returned type from the allocation matches the type of the variable being assigned. (Before, the allocator would always return "void *", which can be implicitly cast to any pointer type.) This allocates the single-entry array that mtk-eint expects (nbase is set to 1). The assigned type is "void __iomem **", but the converted allocation type would be "void __iomem ***", as the size was taken from "pctl->eint->base" itself rather than from what it points at. Luckily "void __iomem **" and "void __iomem *" are the same size. Take the size from the pointed-at type to match the assignment. Build tested ARCH=x86_64 allmodconfig with GCC 16.2.0: drivers/pinctrl/mediatek/pinctrl-mtk-common.o Assisted-by: LLM coccinelle Signed-off-by: Kees Cook Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 1a977acd6883..857d39f3438d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -1032,7 +1032,8 @@ static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev) pctl->eint->nbase = 1; /* mtk-eint expects an array */ - pctl->eint->base = devm_kzalloc(pctl->dev, sizeof(pctl->eint->base), GFP_KERNEL); + pctl->eint->base = devm_kzalloc(pctl->dev, sizeof(*pctl->eint->base), + GFP_KERNEL); if (!pctl->eint->base) return -ENOMEM; From 07ba49a119bb38bfdc44d9db5280afd9c27714d0 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Thu, 17 Sep 2026 14:14:47 -0700 Subject: [PATCH 055/106] pinctrl: imx: Remove const from group_names allocation type In preparation for making the devm_kmalloc family of allocators type aware, we need to make sure that the returned type from the allocation matches the type of the variable being assigned. (Before, the allocator would always return "void *", which can be implicitly cast to any pointer type.) The assigned type is "const char **", but the converted allocation type would be "const char * const *", as the size was taken from "*func->groups", whose type "const char * const" is const qualified. As there is no general way to remove const qualifiers, take the size from the assignment target instead. No change in allocation size results. Build tested ARCH=x86_64 allmodconfig with GCC 16.2.0: drivers/pinctrl/freescale/pinctrl-imx.o Assisted-by: LLM coccinelle Signed-off-by: Kees Cook Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index f08ef52bf4f8..5a06be45f5c3 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -646,7 +646,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, } group_names = devm_kcalloc(ipctl->dev, func->ngroups, - sizeof(*func->groups), GFP_KERNEL); + sizeof(*group_names), GFP_KERNEL); if (!group_names) return -ENOMEM; i = 0; From 5dde08ea70b9941f739880db7c3eab49649ca34c Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:36 -0700 Subject: [PATCH 056/106] dt-bindings: pincfg-node: Add property 'input-debounce-ns' The StarFive JHB100 SoC hardware supports debounce time configuration with nanosecond granularity. The existing 'input-debounce' property uses microseconds, which is insufficient to accurately represent the hardware's finer timing steps. Add the property 'input-debounce-ns' to specify debounce time in nanoseconds as an alternative to the existing 'input-debounce' which uses microseconds. Make the new property unavailable when the existing property 'input-debounce' is selected to prevent conflicting definitions. Signed-off-by: Changhuang Liang Acked-by: Conor Dooley Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/pincfg-node.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml index 97dbce8a261f..17a6270dce31 100644 --- a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml @@ -104,6 +104,10 @@ properties: description: Takes the debounce time in usec as argument or 0 to disable debouncing + input-debounce-ns: + description: Takes the debounce time in nsec as argument or 0 to disable + debouncing + power-source: $ref: /schemas/types.yaml#/definitions/uint32 description: select between different power supplies @@ -214,6 +218,13 @@ allOf: input-schmitt-enable: false input-schmitt-microvolt: false + - if: + required: + - input-debounce + then: + properties: + input-debounce-ns: false + - if: required: - drive-strength From fead11de1f77acb4e2bf7c45b7ec6e24bc8cad6f Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:37 -0700 Subject: [PATCH 057/106] pinctrl: pinconf-generic: Add property 'input-debounce-ns' Add 'input-debounce-ns' to the generic parameters used for parsing DT files, along with the corresponding configuration parameter PIN_CONFIG_INPUT_DEBOUNCE_NS. This allows debounce time to be specified in nanoseconds as an alternative to the existing 'input-debounce' property which uses microseconds Signed-off-by: Changhuang Liang Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf-generic.c | 2 ++ include/linux/pinctrl/pinconf-generic.h | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 95c803c40a7d..36845517984e 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -43,6 +43,7 @@ static const struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA", true), PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH_UA, "output drive strength", "uA", true), PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec", true), + PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE_NS, "input debounce", "nsec", true), PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL, false), PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false), PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_UV, "input schmitt threshold", "uV", true), @@ -185,6 +186,7 @@ static const struct pinconf_generic_params dt_params[] = { { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, { "drive-strength-microamp", PIN_CONFIG_DRIVE_STRENGTH_UA, 0 }, { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, + { "input-debounce-ns", PIN_CONFIG_INPUT_DEBOUNCE_NS, 0 }, { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, { "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 }, diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index a5d4b2d8633a..1df63c732b99 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -71,6 +71,10 @@ struct pinctrl_map; * which means it will wait for signals to settle when reading inputs. The * argument gives the debounce time in usecs. Setting the * argument to zero turns debouncing off. + * @PIN_CONFIG_INPUT_DEBOUNCE_NS: this will configure the pin to debounce mode, + * which means it will wait for signals to settle when reading inputs. The + * argument gives the debounce time in nsecs. Setting the + * argument to zero turns debouncing off. * @PIN_CONFIG_INPUT_ENABLE: enable the pin's input. Note that this does not * affect the pin's ability to drive output. 1 enables input, 0 disables * input. @@ -143,6 +147,7 @@ enum pin_config_param { PIN_CONFIG_DRIVE_STRENGTH, PIN_CONFIG_DRIVE_STRENGTH_UA, PIN_CONFIG_INPUT_DEBOUNCE, + PIN_CONFIG_INPUT_DEBOUNCE_NS, PIN_CONFIG_INPUT_ENABLE, PIN_CONFIG_INPUT_SCHMITT, PIN_CONFIG_INPUT_SCHMITT_ENABLE, From 9d3dc8decb60fee944871e64cd3f8a26166fa7bb Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:38 -0700 Subject: [PATCH 058/106] dt-bindings: pinctrl: Add starfive,jhb100-sys0-pinctrl Add pinctrl bindings for StarFive JHB100 SoC System-0(sys0) pinctrl controller. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../pinctrl/starfive,jhb100-sys0-pinctrl.yaml | 164 ++++++++++++++++++ 1 file changed, 164 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml new file mode 100644 index 000000000000..a6f8d1b5c459 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml @@ -0,0 +1,164 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys0-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 System-0 Pin Controller + +description: | + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd. + + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1, + per2, per2pok, per3, adc0, adc1, emmc, and vga. + This document provides an overview of the "sys0" pinctrl domain. + + The "sys0" domain has a pin controller which provides + - function selection for GPIO pads. + - GPIO pad configuration. + - GPIO interrupt handling. + + In the SYS0 Pin Controller, there are 4 multi-function GPIO_PADs. Each of + them can be multiplexed to different hardware blocks through function + selection and each iopad has a maximum of up to 2 functions - 0 and 1. + Function 0 is the default function which is generally the GPIO function + (or occasionally, it can be a peripheral signal). + Function 1 is the alternate function or peripheral signal that can be + routed to the iopad. The function selection is carried out by writing + the function number to the iopad function select register. + + Each iopad is configurable with parameters such as input-enable, internal + pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input + debounce nanoseconds. + +maintainers: + - Changhuang Liang + +properties: + compatible: + items: + - const: starfive,jhb100-sys0-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + function selection, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate, input debounce and + drive-strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. + enum: [ auxpwrgood, gpio, hbled, pe2rst_out ] + + bias-disable: true + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-debounce-ns: + minimum: 0 + maximum: 10485680 + description: + Debounce time in nanoseconds. The hardware counts in 80 ns + stages with a 17-bit counter, so the maximum is 10485680 ns. + + input-disable: true + + input-enable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow + 1: fast + +required: + - compatible + - reg + - resets + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_sys0: pinctrl@13080000 { + compatible = "starfive,jhb100-sys0-pinctrl"; + reg = <0x0 0x13080000 0x0 0x800>; + resets = <&sys0crg 2>; + interrupts = <56>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_sys0 0 0 4>; + }; + }; From 9c4d0c8fc4c10eaecc651ecd3d2aa706f06a6637 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:39 -0700 Subject: [PATCH 059/106] pinctrl: starfive: Add StarFive JHB100 sys0 controller driver Add pinctrl driver for StarFive JHB100 SoC System-0(sys0) pinctrl controller. Simultaneously add a generic pinctrl driver framework for registering the pinctrl of other domains (sys1, sys2, and so on) in the JHB100 SoC. Co-developed-by: Lianfeng Ouyang Signed-off-by: Lianfeng Ouyang Signed-off-by: Alex Soo Signed-off-by: Changhuang Liang Signed-off-by: Linus Walleij --- MAINTAINERS | 8 + drivers/pinctrl/starfive/Kconfig | 19 + drivers/pinctrl/starfive/Makefile | 3 + .../starfive/pinctrl-starfive-jhb100-sys0.c | 121 ++ .../starfive/pinctrl-starfive-jhb100.c | 1446 +++++++++++++++++ .../starfive/pinctrl-starfive-jhb100.h | 153 ++ 6 files changed, 1750 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100.h diff --git a/MAINTAINERS b/MAINTAINERS index 3a19da74d00c..96c32bc7dd91 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26203,6 +26203,14 @@ S: Supported F: Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml F: drivers/irqchip/irq-starfive-jhb100-intc.c +STARFIVE JHB100 PINCTRL DRIVERS +M: Changhuang Liang +M: Lianfeng Ouyang +L: linux-gpio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pinctrl/starfive,jhb1*.yaml +F: drivers/pinctrl/starfive/pinctrl-starfive-jhb1* + STATIC BRANCH/CALL M: Peter Zijlstra M: Josh Poimboeuf diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index a9a7cb101684..b3cb513c23de 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -47,3 +47,22 @@ config PINCTRL_STARFIVE_JH7110_AON This also provides an interface to the GPIO pins not used by other peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. + +config PINCTRL_STARFIVE_JHB100 + bool + depends on OF + select GENERIC_PINCTRL + select GPIOLIB + select GPIOLIB_IRQCHIP + select OF_GPIO + +config PINCTRL_STARFIVE_JHB100_SYS0 + tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + select PINCTRL_STARFIVE_JHB100 + default ARCH_STARFIVE + help + Say yes here to support system-0 pin control on the StarFive JHB100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index ee0d32d085cb..c0d368f413bc 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -5,3 +5,6 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7100) += pinctrl-starfive-jh7100.o obj-$(CONFIG_PINCTRL_STARFIVE_JH7110) += pinctrl-starfive-jh7110.o obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_SYS) += pinctrl-starfive-jh7110-sys.o obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o + +obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o +obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c new file mode 100644 index 000000000000..ad6f889f7d1c --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JHB100 SoC System-0 domain + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include + +#include "pinctrl-starfive-jhb100.h" + +/* sys0 pad numbers */ +#define PADNUM_SYS0_GPIO_A2 2 +#define PADNUM_SYS0_GPIO_A3 3 + +static const struct jhb100_pin_layout_desc jhb100_sys0_pl_desc[] = { + { .pin_start = 0, .pin_cnt = 3, .name = "gpio", .gpio_func_sel = 0, }, + { .pin_start = 3, .pin_cnt = 1, .name = "bmcpcierp_pe2rst_out", .gpio_func_sel = 1, }, + { .pin_start = 4, .pin_cnt = 1, .name = "testen", .gpio_func_sel = -1, }, + { .pin_start = 5, .pin_cnt = 1, .name = "syspok_in", .gpio_func_sel = -1, }, + { .pin_start = 6, .pin_cnt = 1, .name = "sysrstn_in", .gpio_func_sel = -1, }, + { .pin_start = 7, .pin_cnt = 1, .name = "perstn0_in", .gpio_func_sel = -1, }, + { .pin_start = 8, .pin_cnt = 1, .name = "perstn1_in", .gpio_func_sel = -1, }, + { .pin_start = 9, .pin_cnt = 1, .name = "aprstn_out", .gpio_func_sel = -1, }, + { .pin_start = 10, .pin_cnt = 1, .name = "pcierp_wake", .gpio_func_sel = -1, }, + { 0xff }, +}; + +static const struct config_reg_layout_desc jhb100_sys0_pinctrl_crl_desc[] = { + { + .pin_start = 0, + .pin_cnt = 4, + .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 }, + .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 }, + .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 }, + .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 }, + .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 }, + .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 }, + .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 }, + }, + { + .pin_start = 4, + .pin_cnt = 5, + .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 0, .width = 1 }, + }, + { + .pin_start = 9, + .pin_cnt = 1, + .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 }, + .fields[PAD_CFG_SLEW_RATE] = { .shift = 2, .width = 1 }, + }, + { + .pin_start = 10, + .pin_cnt = 1, + .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 }, + .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 }, + .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 }, + .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 }, + .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 }, + .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 }, + }, + { 0xff }, +}; + +static const struct starfive_pinctrl_regs jhb100_sys0_pinctrl_regs = { + .func_sel = { .reg = 0x44, .width_per_pin = 2 }, + .config = 0x0c, + .output = 0x38, + .output_en = 0x3c, + .gpio_status = 0x40, + .irq_en = 0x48, + .irq_status = 0x4c, + .irq_clr = 0x50, + .irq_trigger = 0x54, + .irq_level = 0x58, + .irq_both_edge = 0x5c, + .irq_edge = 0x60, +}; + +static const struct jhb100_pinctrl_func_maps jhb100_func_maps_sys0[] = { + { .func = "auxpwrgood", .val = 1 }, + { .func = "gpio", .val = 0, + .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_SYS0_GPIO_A2) }, + { .func = "gpio", .val = 1, + .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_SYS0_GPIO_A3) }, + { .func = "hbled", .val = 1 }, + { .func = "pe2rst_out", .val = 0 }, +}; + +static const struct jhb100_pinctrl_domain_info jhb100_sys0_pinctrl_info = { + .name = "jhb100-sys0", + .pl_desc = jhb100_sys0_pl_desc, + .crl_desc = jhb100_sys0_pinctrl_crl_desc, + .regs = &jhb100_sys0_pinctrl_regs, + .fmaps = jhb100_func_maps_sys0, + .num_maps = ARRAY_SIZE(jhb100_func_maps_sys0), +}; + +static const struct of_device_id jhb100_sys0_pinctrl_of_match[] = { + { + .compatible = "starfive,jhb100-sys0-pinctrl", + .data = &jhb100_sys0_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jhb100_sys0_pinctrl_of_match); + +static struct platform_driver jhb100_sys0_pinctrl_driver = { + .probe = jhb100_pinctrl_probe, + .driver = { + .name = "starfive-jhb100-sys0-pinctrl", + .of_match_table = jhb100_sys0_pinctrl_of_match, + }, +}; +module_platform_driver(jhb100_sys0_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC System-0 domain"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.c new file mode 100644 index 000000000000..462a26697b88 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.c @@ -0,0 +1,1446 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JHB100 SoC + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "../core.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" +#include "../pinmux.h" +#include "pinctrl-starfive-jhb100.h" + +#define GPOEN_ENABLE 0 +#define GPOEN_DISABLE 1 + +#define JHB100_DEBOUNCE_WIDTH_STAGES_MAX GENMASK(16, 0) +#define JHB100_DEBOUNCE_WIDTH_STAGE_NS 80 + +/* mode select */ +#define JHB100_PUSH_PULL 0 +#define JHB100_OPEN_DRAIN 1 +#define JHB100_LEGACY_FAST_MODE_PLUS 2 +#define JHB100_LEGACY_FAST_MODE 3 + +/* i2c open-drain pull-up select */ +#define JHB100_I2C_OPEN_DRAIN_PU_600_OHMS 0 +#define JHB100_I2C_OPEN_DRAIN_PU_900_OHMS 1 +#define JHB100_I2C_OPEN_DRAIN_PU_1200_OHMS 2 +#define JHB100_I2C_OPEN_DRAIN_PU_2000_OHMS 3 + +/* + * On the StarFive JHB100 SoC, every 32 GPIOs correspond to one register address. The + * driver abstracts every 32 GPIOs into one GPIO bank to simplify code implementation. + */ +#define JHB100_NR_GPIOS_PER_BANK 32 +#define JHB100_BANK_OFFSET(n) ((n) * 4) +#define JHB100_GPIO_BANK(gpio) ((gpio) / JHB100_NR_GPIOS_PER_BANK) +#define JHB100_GPIO_MASK(gpio) BIT((gpio) % JHB100_NR_GPIOS_PER_BANK) +#define JHB100_GPIO_REG_OFFSET(gpio) JHB100_BANK_OFFSET(JHB100_GPIO_BANK(gpio)) + +static int jhb100_map_get_func_val(struct jhb100_pinctrl *sfp, const char *function, + unsigned int pin) +{ + const struct jhb100_pinctrl_func_maps *fmaps = sfp->info->fmaps; + size_t num = sfp->info->num_maps; + + for (int i = 0; i < num; i++) { + if (!strcmp(function, fmaps[i].func)) { + if (!fmaps[i].max_pin) + return fmaps[i].val; + + if (pin < fmaps[i].max_pin) + return fmaps[i].val; + + continue; + } + } + + return -EINVAL; +} + +static const struct config_reg_layout_desc *get_crl_desc_by_pin(struct jhb100_pinctrl *sfp, + unsigned int pin) +{ + const struct config_reg_layout_desc *crl_desc = sfp->info->crl_desc; + unsigned int i = 0; + + do { + if (pin >= crl_desc[i].pin_start && + pin < crl_desc[i].pin_start + crl_desc[i].pin_cnt) + return &crl_desc[i]; + } while (crl_desc[i++].pin_start != 0xff); + + return NULL; +} + +static const struct pinctrl_ops jhb100_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = pinctrl_generic_pins_function_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, +}; + +static void jhb100_set_function(struct jhb100_pinctrl *sfp, + unsigned int pin, u8 func) +{ + const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs; + unsigned int pins_per_reg, offset, shift; + void __iomem *func_sel_reg; + u32 func_sel_mask; + u32 func_sel_val; + + if (!pinctrl_regs->func_sel.reg || !pinctrl_regs->func_sel.width_per_pin) + return; + + pins_per_reg = 32 / pinctrl_regs->func_sel.width_per_pin; + offset = 4 * (pin / pins_per_reg); + shift = pinctrl_regs->func_sel.width_per_pin * (pin % pins_per_reg); + + func_sel_reg = sfp->base + pinctrl_regs->func_sel.reg + offset; + func_sel_mask = GENMASK(pinctrl_regs->func_sel.width_per_pin - 1, 0) << shift; + func_sel_val = func << shift; + + guard(raw_spinlock_irqsave)(&sfp->lock); + + func_sel_val |= readl_relaxed(func_sel_reg) & ~func_sel_mask; + writel_relaxed(func_sel_val, func_sel_reg); +} + +static int jhb100_set_one_pin_mux(struct jhb100_pinctrl *sfp, + unsigned int pin, + u8 func) +{ + jhb100_set_function(sfp, pin, func); + + return 0; +} + +static int jhb100_set_mux(struct pinctrl_dev *pctldev, + unsigned int fsel, unsigned int gsel) +{ + struct jhb100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + const struct group_desc *group; + unsigned int i; + const char **functions; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + functions = group->data; + + for (i = 0; i < group->grp.npins; i++) { + int function; + + function = jhb100_map_get_func_val(sfp, functions[i], group->grp.pins[i]); + if (function < 0) { + dev_err(pctldev->dev, "invalid function %s\n", functions[i]); + return function; + } + + jhb100_set_one_pin_mux(sfp, group->grp.pins[i], function); + } + + return 0; +} + +static int jhb100_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct jhb100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs; + const struct jhb100_pinctrl_domain_info *info = sfp->info; + unsigned int pins_per_reg, offset, shift; + u32 func_sel_mask, fs; + void __iomem *reg_gpio_func_sel; + s8 gpio_func_sel = sfp->gpio_func_sel_arr[pin]; + + if (!pinctrl_regs->func_sel.reg || !pinctrl_regs->func_sel.width_per_pin) + return -EINVAL; + + pins_per_reg = 32 / pinctrl_regs->func_sel.width_per_pin; + offset = 4 * (pin / pins_per_reg); + shift = pinctrl_regs->func_sel.width_per_pin * (pin % pins_per_reg); + + reg_gpio_func_sel = sfp->base + info->regs->func_sel.reg + offset; + func_sel_mask = GENMASK(info->regs->func_sel.width_per_pin - 1, 0) << shift; + + if (gpio_func_sel < 0) + return -EINVAL; + + guard(raw_spinlock_irqsave)(&sfp->lock); + + fs = readl_relaxed(reg_gpio_func_sel); + fs &= ~func_sel_mask; + fs |= (gpio_func_sel << shift); + writel_relaxed(fs, reg_gpio_func_sel); + + return 0; +} + +static void jhb100_padcfg_rmw(struct jhb100_pinctrl *sfp, + unsigned int pin, u32 mask, u32 value) +{ + void __iomem *reg; + unsigned int offset; + int padcfg_base; + + padcfg_base = sfp->info->regs->config; + + offset = 4 * pin; + + reg = sfp->base + padcfg_base + offset; + + value &= mask; + + guard(raw_spinlock_irqsave)(&sfp->lock); + + value |= readl_relaxed(reg) & ~mask; + writel_relaxed(value, reg); +} + +static int jhb100_gpio_direction_input(struct gpio_chip *gc, + unsigned int gpio) +{ + struct jhb100_pinctrl *sfp = gpiochip_get_data(gc); + const struct jhb100_pinctrl_domain_info *info = sfp->info; + const struct config_reg_layout_desc *crl_desc; + unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio); + void __iomem *reg_gpio_oen; + u32 doen = 0; + + crl_desc = get_crl_desc_by_pin(sfp, gpio); + if (!crl_desc) { + dev_err(sfp->dev, "pin %d can't not found reg layout descriptor\n", + gpio); + return -EINVAL; + } + + jhb100_padcfg_rmw(sfp, gpio, + RL_DESC_GENMASK(crl_desc, PAD_CFG_INPUT_ENABLE) | + RL_DESC_GENMASK(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT), + RL_DESC_GENMASK(crl_desc, PAD_CFG_INPUT_ENABLE) | + RL_DESC_GENMASK(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT)); + + reg_gpio_oen = sfp->base + info->regs->output_en + offset; + + guard(raw_spinlock_irqsave)(&sfp->lock); + doen = readl_relaxed(reg_gpio_oen) | JHB100_GPIO_MASK(gpio); + writel_relaxed(doen, reg_gpio_oen); + + return 0; +} + +static int jhb100_gpio_direction_output(struct gpio_chip *gc, unsigned int gpio) +{ + struct jhb100_pinctrl *sfp = gpiochip_get_data(gc); + const struct jhb100_pinctrl_domain_info *info = sfp->info; + const struct config_reg_layout_desc *crl_desc; + unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio); + void __iomem *reg_gpio_oen; + u32 doen = 0; + + crl_desc = get_crl_desc_by_pin(sfp, gpio); + if (!crl_desc) { + dev_err(sfp->dev, "pin %d can't not found reg layout descriptor\n", + gpio); + return -EINVAL; + } + + jhb100_padcfg_rmw(sfp, gpio, + RL_DESC_GENMASK(crl_desc, PAD_CFG_INPUT_ENABLE) | + RL_DESC_GENMASK(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT) | + RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) | + RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP), + 0); + + reg_gpio_oen = sfp->base + info->regs->output_en + offset; + + guard(raw_spinlock_irqsave)(&sfp->lock); + doen = readl_relaxed(reg_gpio_oen) & ~JHB100_GPIO_MASK(gpio); + writel_relaxed(doen, reg_gpio_oen); + + return 0; +} + +static int jhb100_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin, + bool input) +{ + struct jhb100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + + if (input) + return jhb100_gpio_direction_input(&sfp->gc, pin); + + return jhb100_gpio_direction_output(&sfp->gc, pin); +} + +static const struct pinmux_ops jhb100_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = jhb100_set_mux, + .gpio_request_enable = jhb100_gpio_request_enable, + .gpio_set_direction = jhb100_gpio_set_direction, +}; + +static const u8 jhb100_drive_strength_ma[4] = { 2, 4, 8, 12 }; + +static const u8 jhb100_drive_strength_ma_3bit[8] = { 2, 5, 8, 10, 14, 16, 18, 20 }; + +static u32 jhb100_padcfg_ds_to_mA(u32 padcfg) +{ + return jhb100_drive_strength_ma[padcfg]; +} + +static u32 jhb100_padcfg_ds_to_mA_3bit(u32 padcfg) +{ + return jhb100_drive_strength_ma_3bit[padcfg]; +} + +static u32 jhb100_padcfg_ds_to_uA(u32 padcfg) +{ + return (jhb100_drive_strength_ma[padcfg] * 1000); +} + +static u32 jhb100_padcfg_ds_to_uA_3bit(u32 padcfg) +{ + return (jhb100_drive_strength_ma_3bit[padcfg] * 1000); +} + +static u32 jhb100_padcfg_ds_from_mA(u32 v) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(jhb100_drive_strength_ma); i++) { + if (v <= jhb100_drive_strength_ma[i]) + break; + } + return i; +} + +static u32 jhb100_padcfg_ds_from_mA_3bit(u32 v) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(jhb100_drive_strength_ma_3bit); i++) { + if (v <= jhb100_drive_strength_ma_3bit[i]) + break; + } + return i; +} + +static u32 jhb100_padcfg_ds_from_uA(u32 v) +{ + /* Convert from uA to mA */ + v /= 1000; + + return jhb100_padcfg_ds_from_mA(v); +} + +static u32 jhb100_padcfg_ds_from_uA_3bit(u32 v) +{ + /* Convert from uA to mA */ + v /= 1000; + + return jhb100_padcfg_ds_from_mA_3bit(v); +} + +static u32 jhb100_padcfg_vsel_to_reg(u32 val) +{ + switch (val) { + case 3300: + case 1800: + return 0; + case 2500: + return 1; + default: + return 0; + } +} + +static int jhb100_pincfg_reg_to_vref(u32 val) +{ + const int vref_table[JHB100_PINVREF_NUM] = { 3300, 2500, 1800 }; + + return (val < JHB100_PINVREF_NUM) ? vref_table[val] : -ENOTSUPP; +} + +static u32 jhb100_pincfg_vref_to_reg(u32 val) +{ + switch (val) { + case 3300: + return JHB100_PINVREF_3_3V; + case 2500: + return JHB100_PINVREF_2_5V; + case 1800: + return JHB100_PINVREF_1_8V; + default: + return JHB100_PINVREF_3_3V; + } +} + +static int jhb100_pincfg_pin_vref_get(struct jhb100_pinctrl *sfp, unsigned int pin) +{ + const struct pinvref_reg *vref = &sfp->info->regs->vref; + u32 grp = 0, i; + int val; + + while (grp < vref->num_pv) { + for (i = 0; i < vref->pv_desc[grp].num_pins; i++) { + if (pin != vref->pv_desc[grp].pin_grp[i]) + continue; + + val = readl(sfp->base + vref->reg + grp * 4); + + return jhb100_pincfg_reg_to_vref(val); + } + + grp++; + } + + return -ENOTSUPP; +} + +static void jhb100_pincfg_pin_vref_set(struct jhb100_pinctrl *sfp, unsigned int pin, + u32 arg) +{ + const struct pinvref_reg *vref = &sfp->info->regs->vref; + u32 grp = 0, i; + + while (grp < vref->num_pv) { + for (i = 0; i < vref->pv_desc[grp].num_pins; i++) { + if (pin != vref->pv_desc[grp].pin_grp[i]) + continue; + + arg = jhb100_pincfg_vref_to_reg(arg); + + if (!(vref->pv_desc[grp].range & BIT(arg))) + return; + + guard(raw_spinlock_irqsave)(&sfp->lock); + writel(arg, sfp->base + vref->reg + grp * 4); + return; + } + + grp++; + } +} + +static int jhb100_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct jhb100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + int param = pinconf_to_config_param(*config); + const struct config_reg_layout_desc *crl_desc; + unsigned int padcfg_base, offset; + bool enabled = false; + u32 padcfg, arg; + int ret; + + padcfg_base = sfp->info->regs->config; + offset = 4 * pin; + + if (pin >= sfp->npins) + return -EINVAL; + + padcfg = readl_relaxed(sfp->base + padcfg_base + offset); + + crl_desc = get_crl_desc_by_pin(sfp, pin); + if (!crl_desc) { + dev_err(sfp->dev, "pin %d can't not found reg layout descriptor\n", pin); + return -EINVAL; + } + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + arg = 0; + + if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_DOWN) || + !RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_UP)) + return -ENOTSUPP; + + enabled = !(padcfg & (RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) | + RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP))); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = 1; + + if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_DOWN)) + return -ENOTSUPP; + + enabled = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN)) + >> RL_DESC_SHIFT(crl_desc, PAD_CFG_PULL_DOWN); + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_UP) && + !RL_DESC_SUPPORTED(crl_desc, PAD_CFG_OPEN_DRAIN_PULL_UP_SEL)) + return -ENOTSUPP; + + if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_UP)) { + arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP)) >> + RL_DESC_SHIFT(crl_desc, PAD_CFG_PULL_UP); + + enabled = arg ? true : false; + } + + if (!enabled && RL_DESC_SUPPORTED(crl_desc, PAD_CFG_OPEN_DRAIN_PULL_UP_SEL)) { + enabled = true; + + arg = (padcfg & + RL_DESC_GENMASK(crl_desc, PAD_CFG_OPEN_DRAIN_PULL_UP_SEL)) >> + RL_DESC_SHIFT(crl_desc, PAD_CFG_OPEN_DRAIN_PULL_UP_SEL); + + if (arg == JHB100_I2C_OPEN_DRAIN_PU_600_OHMS) + arg = 600; + else if (arg == JHB100_I2C_OPEN_DRAIN_PU_900_OHMS) + arg = 900; + else if (arg == JHB100_I2C_OPEN_DRAIN_PU_1200_OHMS) + arg = 1200; + else if (arg == JHB100_I2C_OPEN_DRAIN_PU_2000_OHMS) + arg = 2000; + else + return -ENOTSUPP; + } + + break; + case PIN_CONFIG_DRIVE_STRENGTH: + if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT)) { + enabled = true; + + arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT)) >> + RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT); + arg = jhb100_padcfg_ds_to_mA(arg); + } else if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT)) { + enabled = true; + + arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT)) >> + RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT); + arg = jhb100_padcfg_ds_to_mA_3bit(arg); + } else { + return -ENOTSUPP; + } + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT)) { + enabled = true; + + arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT)) >> + RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT); + arg = jhb100_padcfg_ds_to_uA(arg); + } else if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT)) { + enabled = true; + + arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT)) >> + RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT); + arg = jhb100_padcfg_ds_to_uA_3bit(arg); + } else { + return -ENOTSUPP; + } + break; + case PIN_CONFIG_INPUT_ENABLE: + if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_INPUT_ENABLE)) + return -ENOTSUPP; + + enabled = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_INPUT_ENABLE)) + >> RL_DESC_SHIFT(crl_desc, PAD_CFG_INPUT_ENABLE); + arg = enabled; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT)) + return -ENOTSUPP; + + enabled = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT)) + >> RL_DESC_SHIFT(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT); + arg = enabled; + break; + case PIN_CONFIG_SLEW_RATE: + if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_SLEW_RATE)) { + enabled = true; + + arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_SLEW_RATE)) >> + RL_DESC_SHIFT(crl_desc, PAD_CFG_SLEW_RATE); + } else if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_MODE_SELECT)) { + enabled = true; + + arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT)) >> + RL_DESC_SHIFT(crl_desc, PAD_CFG_MODE_SELECT); + + if (arg == JHB100_LEGACY_FAST_MODE_PLUS) + arg = 1; + else if (arg == JHB100_LEGACY_FAST_MODE) + arg = 0; + else + return -ENOTSUPP; + } else { + return -ENOTSUPP; + } + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_MODE_SELECT)) + return -ENOTSUPP; + + arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT)) >> + RL_DESC_SHIFT(crl_desc, PAD_CFG_MODE_SELECT); + + if (arg == JHB100_PUSH_PULL) + enabled = true; + + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_MODE_SELECT)) + return -ENOTSUPP; + + arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT)) >> + RL_DESC_SHIFT(crl_desc, PAD_CFG_MODE_SELECT); + + if (arg == JHB100_OPEN_DRAIN) + enabled = true; + + break; + case PIN_CONFIG_INPUT_DEBOUNCE_NS: + if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DEBOUNCE_WIDTH)) + return -ENOTSUPP; + + enabled = true; + + arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_DEBOUNCE_WIDTH)) >> + RL_DESC_SHIFT(crl_desc, PAD_CFG_DEBOUNCE_WIDTH); + + arg *= JHB100_DEBOUNCE_WIDTH_STAGE_NS; + + break; + case PIN_CONFIG_POWER_SOURCE: + if (!sfp->info->regs->vref.num_pv) + return -ENOTSUPP; + + ret = jhb100_pincfg_pin_vref_get(sfp, pin); + if (ret < 0) + return ret; + + arg = ret; + enabled = true; + + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return enabled ? 0 : -EINVAL; +} + +static int jhb100_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *configs, + unsigned int num_configs) +{ + struct jhb100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + const struct config_reg_layout_desc *crl_desc; + bool vref_set = false; + u32 value = 0; + u32 mask = 0; + u32 vref = 0; + int i; + + crl_desc = get_crl_desc_by_pin(sfp, pin); + if (!crl_desc) { + dev_err(sfp->dev, "pin %d can't not found reg layout descriptor\n", pin); + return -EINVAL; + } + + for (i = 0; i < num_configs; i++) { + int param = pinconf_to_config_param(configs[i]); + u32 arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_DOWN) || + !RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_UP)) + return -ENOTSUPP; + + mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) | + RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP); + value &= ~(RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) | + RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP)); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!arg || !RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_DOWN) || + !RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_UP)) + return -ENOTSUPP; + + mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) | + RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP); + value &= ~(RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) | + RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP)); + value |= RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN); + break; + case PIN_CONFIG_BIAS_PULL_UP: + if ((!arg || arg == 1) && RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_UP)) { + mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) | + RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP); + value &= ~(RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) | + RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP)); + value |= RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP); + } else if (arg && + RL_DESC_SUPPORTED(crl_desc, PAD_CFG_OPEN_DRAIN_PULL_UP_SEL)) { + mask |= RL_DESC_GENMASK(crl_desc, + PAD_CFG_OPEN_DRAIN_PULL_UP_SEL); + value &= ~RL_DESC_GENMASK(crl_desc, + PAD_CFG_OPEN_DRAIN_PULL_UP_SEL); + switch (arg) { + case 600: + value |= JHB100_I2C_OPEN_DRAIN_PU_600_OHMS << + RL_DESC_SHIFT(crl_desc, + PAD_CFG_OPEN_DRAIN_PULL_UP_SEL); + break; + case 900: + value |= JHB100_I2C_OPEN_DRAIN_PU_900_OHMS << + RL_DESC_SHIFT(crl_desc, + PAD_CFG_OPEN_DRAIN_PULL_UP_SEL); + break; + case 1200: + value |= JHB100_I2C_OPEN_DRAIN_PU_1200_OHMS << + RL_DESC_SHIFT(crl_desc, + PAD_CFG_OPEN_DRAIN_PULL_UP_SEL); + break; + case 2000: + value |= JHB100_I2C_OPEN_DRAIN_PU_2000_OHMS << + RL_DESC_SHIFT(crl_desc, + PAD_CFG_OPEN_DRAIN_PULL_UP_SEL); + break; + default: + return -ENOTSUPP; + } + } else { + return -ENOTSUPP; + } + break; + case PIN_CONFIG_DRIVE_STRENGTH: + if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT)) { + mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT); + value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT); + value |= jhb100_padcfg_ds_from_mA(arg) << + RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT); + } else if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT)) { + mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT); + value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT); + value |= jhb100_padcfg_ds_from_mA_3bit(arg) << + RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT); + } else { + return -ENOTSUPP; + } + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT)) { + mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT); + value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT); + value |= jhb100_padcfg_ds_from_uA(arg) << + RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT); + } else if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT)) { + mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT); + value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT); + value |= jhb100_padcfg_ds_from_uA_3bit(arg) << + RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT); + } else { + return -ENOTSUPP; + } + break; + case PIN_CONFIG_INPUT_ENABLE: + if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_INPUT_ENABLE)) + return -ENOTSUPP; + + mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_INPUT_ENABLE); + value = arg ? (value | RL_DESC_GENMASK(crl_desc, PAD_CFG_INPUT_ENABLE)) + : value; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT)) + return -ENOTSUPP; + + mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT); + value = arg ? + (value | RL_DESC_GENMASK(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT)) + : value; + break; + case PIN_CONFIG_SLEW_RATE: + if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_SLEW_RATE)) { + mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_SLEW_RATE); + value = arg ? + (value | RL_DESC_GENMASK(crl_desc, PAD_CFG_SLEW_RATE)) : + value; + } else if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_MODE_SELECT)) { + mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT); + value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT); + value |= arg ? + JHB100_LEGACY_FAST_MODE_PLUS << + RL_DESC_SHIFT(crl_desc, PAD_CFG_MODE_SELECT) : + JHB100_LEGACY_FAST_MODE << + RL_DESC_SHIFT(crl_desc, PAD_CFG_MODE_SELECT); + } else { + return -ENOTSUPP; + } + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_MODE_SELECT)) + return -ENOTSUPP; + + mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT); + value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT); + value |= JHB100_PUSH_PULL << + RL_DESC_SHIFT(crl_desc, PAD_CFG_MODE_SELECT); + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_MODE_SELECT)) + return -ENOTSUPP; + + mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT); + value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT); + value |= JHB100_OPEN_DRAIN << + RL_DESC_SHIFT(crl_desc, PAD_CFG_MODE_SELECT); + break; + case PIN_CONFIG_INPUT_DEBOUNCE_NS: { + u32 debounce_stage; + + if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DEBOUNCE_WIDTH)) + return -ENOTSUPP; + + mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_DEBOUNCE_WIDTH); + value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_DEBOUNCE_WIDTH); + + debounce_stage = arg ? arg / JHB100_DEBOUNCE_WIDTH_STAGE_NS : 0; + debounce_stage = umin(debounce_stage, JHB100_DEBOUNCE_WIDTH_STAGES_MAX); + + value |= (debounce_stage << + RL_DESC_SHIFT(crl_desc, PAD_CFG_DEBOUNCE_WIDTH)); + + break; + }; + case PIN_CONFIG_POWER_SOURCE: + if (!sfp->info->regs->vref.num_pv && + !RL_DESC_SUPPORTED(crl_desc, PAD_CFG_VSEL)) + return -ENOTSUPP; + + if (sfp->info->regs->vref.num_pv) { + vref_set = true; + vref = arg; + } + + if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_VSEL)) { + mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_VSEL); + value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_VSEL); + + value |= jhb100_padcfg_vsel_to_reg(arg) << + RL_DESC_SHIFT(crl_desc, PAD_CFG_VSEL); + } + break; + default: + return -ENOTSUPP; + } + } + + jhb100_padcfg_rmw(sfp, pin, mask, value); + + if (vref_set) + jhb100_pincfg_pin_vref_set(sfp, pin, vref); + + return 0; +} + +static int jhb100_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int gsel, + unsigned long *config) +{ + const struct group_desc *group; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + return jhb100_pinconf_get(pctldev, group->grp.pins[0], config); +} + +static int jhb100_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int gsel, + unsigned long *configs, + unsigned int num_configs) +{ + const struct group_desc *group; + int ret; + u32 i; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + for (i = 0; i < group->grp.npins; i++) { + ret = jhb100_pinconf_set(pctldev, group->grp.pins[i], configs, num_configs); + if (ret) { + dev_err(pctldev->dev, "failed to set config for pin %d\n", + group->grp.pins[i]); + return ret; + } + } + + return 0; +} + +static const struct pinconf_ops jhb100_pinconf_ops = { + .pin_config_get = jhb100_pinconf_get, + .pin_config_set = jhb100_pinconf_set, + .pin_config_group_get = jhb100_pinconf_group_get, + .pin_config_group_set = jhb100_pinconf_group_set, + .is_generic = true, +}; + +static int jhb100_gpio_get_direction(struct gpio_chip *gc, + unsigned int gpio) +{ + struct jhb100_pinctrl *sfp = gpiochip_get_data(gc); + const struct jhb100_pinctrl_domain_info *info = sfp->info; + unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio); + u32 doen; + void __iomem *reg_gpio_oen; + + reg_gpio_oen = sfp->base + info->regs->output_en + offset; + + doen = !!(readl_relaxed(reg_gpio_oen) & JHB100_GPIO_MASK(gpio)); + + return doen == GPOEN_ENABLE ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; +} + +static int jhb100_gpio_get(struct gpio_chip *gc, unsigned int gpio) +{ + struct jhb100_pinctrl *sfp = gpiochip_get_data(gc); + const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs; + void __iomem *reg_gpio_status; + + reg_gpio_status = sfp->base + pinctrl_regs->gpio_status + + JHB100_GPIO_REG_OFFSET(gpio); + + return !!(readl_relaxed(reg_gpio_status) & JHB100_GPIO_MASK(gpio)); +} + +static int jhb100_gpio_set(struct gpio_chip *gc, unsigned int gpio, int value) +{ + struct jhb100_pinctrl *sfp = gpiochip_get_data(gc); + const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs; + void __iomem *reg_gpio_out; + u32 dout; + + reg_gpio_out = sfp->base + pinctrl_regs->output + JHB100_GPIO_REG_OFFSET(gpio); + + guard(raw_spinlock_irqsave)(&sfp->lock); + + dout = readl_relaxed(reg_gpio_out); + + if (value) + dout |= JHB100_GPIO_MASK(gpio); + else + dout &= ~JHB100_GPIO_MASK(gpio); + + writel_relaxed(dout, reg_gpio_out); + + return 0; +} + +static int jhb100_pinctrl_gpio_direction_output(struct gpio_chip *gc, + unsigned int gpio, int value) +{ + int ret; + + ret = jhb100_gpio_set(gc, gpio, value); + if (ret) + return ret; + + return pinctrl_gpio_direction_output(gc, gpio); +} + +static void jhb100_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct jhb100_pinctrl *sfp = gpiochip_get_data(gc); + const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs; + irq_hw_number_t gpio = irqd_to_hwirq(d); + unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio); + void __iomem *ic; + u32 value; + u32 mask; + + ic = sfp->base + pinctrl_regs->irq_clr + offset; + mask = JHB100_GPIO_MASK(gpio); + + guard(raw_spinlock_irqsave)(&sfp->lock); + + value = readl_relaxed(ic) & ~mask; + writel_relaxed(value | mask, ic); + value = readl_relaxed(ic) & ~mask; + writel_relaxed(value, ic); +} + +static void jhb100_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct jhb100_pinctrl *sfp = gpiochip_get_data(gc); + const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs; + irq_hw_number_t gpio = irqd_to_hwirq(d); + unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio); + void __iomem *ien; + u32 value; + u32 mask; + + ien = sfp->base + pinctrl_regs->irq_en + offset; + mask = JHB100_GPIO_MASK(gpio); + + guard(raw_spinlock_irqsave)(&sfp->lock); + + value = readl_relaxed(ien) & ~mask; + writel_relaxed(value, ien); + + gpiochip_disable_irq(gc, d->hwirq); +} + +static void jhb100_irq_mask_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct jhb100_pinctrl *sfp = gpiochip_get_data(gc); + const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs; + irq_hw_number_t gpio = irqd_to_hwirq(d); + unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio); + void __iomem *ien; + void __iomem *ic; + u32 value; + u32 mask; + + ien = sfp->base + pinctrl_regs->irq_en + offset; + ic = sfp->base + pinctrl_regs->irq_clr + offset; + mask = JHB100_GPIO_MASK(gpio); + + guard(raw_spinlock_irqsave)(&sfp->lock); + + value = readl_relaxed(ien) & ~mask; + writel_relaxed(value, ien); + + value = readl_relaxed(ic) & ~mask; + writel_relaxed(value | mask, ic); + value = readl_relaxed(ic) & ~mask; + writel_relaxed(value, ic); +} + +static void jhb100_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct jhb100_pinctrl *sfp = gpiochip_get_data(gc); + const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs; + irq_hw_number_t gpio = irqd_to_hwirq(d); + unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio); + void __iomem *ien; + u32 value; + u32 mask; + + ien = sfp->base + pinctrl_regs->irq_en + offset; + mask = JHB100_GPIO_MASK(gpio); + + gpiochip_enable_irq(gc, d->hwirq); + + guard(raw_spinlock_irqsave)(&sfp->lock); + + value = readl_relaxed(ien) | mask; + writel_relaxed(value, ien); +} + +static int jhb100_irq_set_type(struct irq_data *d, unsigned int trigger) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct jhb100_pinctrl *sfp = gpiochip_get_data(gc); + const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs; + irq_hw_number_t gpio = irqd_to_hwirq(d); + unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio); + void __iomem *base; + u32 irq_type, edge_both, polarity, mask; + + base = sfp->base + offset; + mask = JHB100_GPIO_MASK(gpio); + + switch (trigger) { + case IRQ_TYPE_EDGE_RISING: + irq_type = mask; /* 1: edge triggered */ + edge_both = 0; /* 0: single edge */ + polarity = mask; /* 1: rising edge */ + break; + case IRQ_TYPE_EDGE_FALLING: + irq_type = mask; /* 1: edge triggered */ + edge_both = 0; /* 0: single edge */ + polarity = 0; /* 0: falling edge */ + break; + case IRQ_TYPE_EDGE_BOTH: + irq_type = mask; /* 1: edge triggered */ + edge_both = mask; /* 1: both edges */ + polarity = 0; /* 0: ignored */ + break; + case IRQ_TYPE_LEVEL_HIGH: + irq_type = 0; /* 0: level triggered */ + edge_both = 0; /* 0: ignored */ + polarity = mask; /* 1: high level */ + break; + case IRQ_TYPE_LEVEL_LOW: + irq_type = 0; /* 0: level triggered */ + edge_both = 0; /* 0: ignored */ + polarity = 0; /* 0: low level */ + break; + default: + return -EINVAL; + } + + if (trigger & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(d, handle_edge_irq); + else + irq_set_handler_locked(d, handle_level_irq); + + guard(raw_spinlock_irqsave)(&sfp->lock); + + irq_type |= readl_relaxed(base + pinctrl_regs->irq_trigger) & ~mask; + writel_relaxed(irq_type, base + pinctrl_regs->irq_trigger); + + edge_both |= readl_relaxed(base + pinctrl_regs->irq_both_edge) & ~mask; + writel_relaxed(edge_both, base + pinctrl_regs->irq_both_edge); + + if (irq_type & mask) { /* edge polarity */ + polarity |= readl_relaxed(base + pinctrl_regs->irq_edge) & ~mask; + writel_relaxed(polarity, base + pinctrl_regs->irq_edge); + } else { /* level polarity */ + polarity |= readl_relaxed(base + pinctrl_regs->irq_level) & ~mask; + writel_relaxed(polarity, base + pinctrl_regs->irq_level); + } + + return 0; +} + +static int jhb100_irq_set_wake(struct irq_data *d, unsigned int enable) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct jhb100_pinctrl *sfp = gpiochip_get_data(gc); + int ret; + + if (enable) + ret = enable_irq_wake(sfp->irq); + else + ret = disable_irq_wake(sfp->irq); + if (ret) + dev_err(sfp->dev, "failed to %s wake-up interrupt\n", + enable ? "enable" : "disable"); + + return ret; +} + +static void jhb100_irq_print_chip(struct irq_data *d, struct seq_file *p) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + seq_puts(p, gc->label); +} + +static const struct irq_chip jhb100_irq_chip = { + .irq_ack = jhb100_irq_ack, + .irq_mask = jhb100_irq_mask, + .irq_mask_ack = jhb100_irq_mask_ack, + .irq_unmask = jhb100_irq_unmask, + .irq_set_type = jhb100_irq_set_type, + .irq_set_wake = jhb100_irq_set_wake, + .irq_print_chip = jhb100_irq_print_chip, + .flags = IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_IMMUTABLE | + IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | + IRQCHIP_MASK_ON_SUSPEND, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static irqreturn_t jhb100_gpio_irq_handler(int irq, void *dev_id) +{ + struct jhb100_pinctrl *sfp = dev_id; + struct gpio_chip *gc = &sfp->gc; + struct gpio_irq_chip *girq = &gc->irq; + const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs; + irqreturn_t ret = IRQ_NONE; + unsigned int bit; + unsigned long is; + + for (unsigned int i = 0; i < sfp->num_banks; i++) { + is = readl_relaxed(sfp->base + pinctrl_regs->irq_status + + JHB100_BANK_OFFSET(i)); + if (!is) + continue; + + for_each_set_bit(bit, &is, JHB100_NR_GPIOS_PER_BANK) { + unsigned int gpio = i * JHB100_NR_GPIOS_PER_BANK + bit; + + if (gpio >= gc->ngpio) + break; + + generic_handle_domain_irq(girq->domain, gpio); + } + + ret = IRQ_HANDLED; + } + + return ret; +} + +static +struct pinctrl_pin_desc *devm_create_pins_from_pld(struct device *dev, + const struct jhb100_pin_layout_desc *desc, + const char *prefix, + unsigned int *total_pins, + unsigned int *total_gpios, + s8 **gpio_func_sel_arr) +{ + struct pinctrl_pin_desc *pins = NULL; + unsigned int i, j, ngpios = 0, npins = 0, pin_index = 0; + unsigned int same_name_found = 0; + s8 *arr; + + if (!dev || !desc || !prefix) { + dev_err(dev, "Invalid parameters: desc=%p, prefix=%s\n", + desc, prefix); + return ERR_PTR(-EINVAL); + } + + for (i = 0; desc[i].pin_start != 0xff; i++) { + if (!desc[i].pin_cnt) { + dev_err(dev, "Invalid pin cnt\n"); + return ERR_PTR(-EINVAL); + } + + npins += desc[i].pin_cnt; + } + + if (npins == 0) { + dev_err(dev, "No pins defined\n"); + return ERR_PTR(-EINVAL); + } + + dev_dbg(dev, "Total pins to create: %d\n", npins); + + pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return ERR_PTR(-ENOMEM); + + arr = devm_kzalloc(dev, npins, GFP_KERNEL); + if (!arr) + return ERR_PTR(-ENOMEM); + + for (i = 0; desc[i].pin_start != 0xff; i++) { + same_name_found = 0; + + for (j = 0; j < i; j++) { + if (!strcmp(desc[j].name, desc[i].name)) { + same_name_found = 1; + break; + } + } + + for (j = 0; j < desc[i].pin_cnt; j++) { + char *name = NULL; + int pin_num = desc[i].pin_start + j; + + pins[pin_index].number = pin_num; + if (same_name_found) { + name = devm_kasprintf(dev, GFP_KERNEL, "%s_%s_%d", + prefix, desc[i].name, + desc[i].pin_start + j); + } else { + if (desc[i].pin_cnt > 1) + name = devm_kasprintf(dev, GFP_KERNEL, "%s_%s_%d", + prefix, desc[i].name, j); + else + name = devm_kasprintf(dev, GFP_KERNEL, "%s_%s", + prefix, desc[i].name); + } + + if (!name) { + dev_err(dev, "Failed to allocate pin name for pin %d\n", + pin_num); + return ERR_PTR(-ENOMEM); + } + + if (!strcmp(desc[i].name, "gpio") || desc[i].gpio_func_sel != -1) + ngpios++; + + pins[pin_index].name = name; + arr[pin_index] = desc[i].gpio_func_sel; + pin_index++; + } + } + + *total_pins = npins; + *total_gpios = ngpios; + *gpio_func_sel_arr = arr; + + return pins; +} + +static void jhb100_reset_control_assert(void *data) +{ + reset_control_assert(data); +} + +int jhb100_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct gpio_irq_chip *girq; + struct gpio_chip *gc; + const struct jhb100_pinctrl_domain_info *info; + struct jhb100_pinctrl *sfp; + struct pinctrl_desc *jhb100_pinctrl_desc; + const struct starfive_pinctrl_regs *pinctrl_regs; + struct reset_control *rst; + struct clk *clk; + int ret; + + info = device_get_match_data(&pdev->dev); + if (!info) + return -ENODEV; + + pinctrl_regs = info->regs; + + sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL); + if (!sfp) + return -ENOMEM; + + sfp->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sfp->base)) + return PTR_ERR(sfp->base); + + clk = devm_clk_get_optional_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "could not get & enable clock\n"); + + rst = devm_reset_control_array_get_optional_shared(dev); + if (IS_ERR(rst)) + return dev_err_probe(dev, PTR_ERR(rst), "could not get reset control\n"); + + ret = reset_control_deassert(rst); + if (ret) + return dev_err_probe(dev, ret, "could not deassert reset\n"); + + ret = devm_add_action_or_reset(dev, jhb100_reset_control_assert, rst); + if (ret) + return ret; + + sfp->irq = platform_get_irq(pdev, 0); + if (sfp->irq < 0) + return sfp->irq; + + sfp->pins = devm_create_pins_from_pld(dev, info->pl_desc, info->name, + &sfp->npins, &sfp->ngpios, + &sfp->gpio_func_sel_arr); + if (IS_ERR(sfp->pins)) + return PTR_ERR(sfp->pins); + + jhb100_pinctrl_desc = devm_kzalloc(&pdev->dev, + sizeof(*jhb100_pinctrl_desc), + GFP_KERNEL); + if (!jhb100_pinctrl_desc) + return -ENOMEM; + + jhb100_pinctrl_desc->name = dev_name(dev); + jhb100_pinctrl_desc->pctlops = &jhb100_pinctrl_ops; + jhb100_pinctrl_desc->pmxops = &jhb100_pinmux_ops; + jhb100_pinctrl_desc->confops = &jhb100_pinconf_ops; + jhb100_pinctrl_desc->owner = THIS_MODULE; + jhb100_pinctrl_desc->pins = sfp->pins; + jhb100_pinctrl_desc->npins = sfp->npins; + + sfp->info = info; + sfp->dev = dev; + platform_set_drvdata(pdev, sfp); + + raw_spin_lock_init(&sfp->lock); + + ret = devm_pinctrl_register_and_init(dev, jhb100_pinctrl_desc, + sfp, &sfp->pctl); + if (ret) + return dev_err_probe(dev, ret, + "could not register pinctrl driver\n"); + + ret = pinctrl_enable(sfp->pctl); + if (ret) + return ret; + + sfp->num_banks = DIV_ROUND_UP(sfp->ngpios, JHB100_NR_GPIOS_PER_BANK); + if (sfp->num_banks > JHB100_MAX_BANKS) + return dev_err_probe(dev, -EINVAL, + "%u GPIOs need %u banks, max %d\n", + sfp->ngpios, sfp->num_banks, JHB100_MAX_BANKS); + + for (unsigned int i = 0; i < sfp->num_banks; i++) { + /* mask all GPIO interrupts */ + writel_relaxed(0U, sfp->base + pinctrl_regs->irq_en + JHB100_BANK_OFFSET(i)); + /* clear all interrupts */ + writel_relaxed(~0U, sfp->base + pinctrl_regs->irq_clr + JHB100_BANK_OFFSET(i)); + writel_relaxed(0U, sfp->base + pinctrl_regs->irq_clr + JHB100_BANK_OFFSET(i)); + } + + gc = &sfp->gc; + gc->label = dev_name(dev); + gc->parent = dev; + gc->owner = THIS_MODULE; + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; + gc->get_direction = jhb100_gpio_get_direction; + gc->direction_input = pinctrl_gpio_direction_input; + gc->direction_output = jhb100_pinctrl_gpio_direction_output; + gc->get = jhb100_gpio_get; + gc->set = jhb100_gpio_set; + gc->set_config = gpiochip_generic_config; + gc->base = -1; + gc->ngpio = sfp->ngpios; + + girq = &gc->irq; + girq->handler = handle_simple_irq; + + gpio_irq_chip_set_chip(girq, &jhb100_irq_chip); + + ret = devm_gpiochip_add_data(dev, gc, sfp); + if (ret) + return dev_err_probe(dev, ret, "could not register gpiochip\n"); + + ret = devm_request_irq(dev, sfp->irq, jhb100_gpio_irq_handler, 0, + gc->label, sfp); + if (ret < 0) + return ret; + + dev_info(dev, "StarFive JHB100 GPIO chip registered %d GPIOs\n", + sfp->ngpios); + + return 0; +} +EXPORT_SYMBOL_GPL(jhb100_pinctrl_probe); + +MODULE_DESCRIPTION("Pinctrl driver for the StarFive JHB100 SoC"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.h b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.h new file mode 100644 index 000000000000..baac5978ba7e --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Pinctrl / GPIO driver for StarFive JHB100 SoC + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#ifndef __PINCTRL_STARFIVE_JHB100_H__ +#define __PINCTRL_STARFIVE_JHB100_H__ + +#include +#include +#include + +/* power-source value */ +enum jhb100_pinvref { + JHB100_PINVREF_3_3V, + JHB100_PINVREF_2_5V, + JHB100_PINVREF_1_8V, + JHB100_PINVREF_NUM +}; + +#define JHB100_MAX_BANKS 2 + +struct jhb100_pin_layout_desc { + unsigned int pin_start; + unsigned int pin_cnt; + const char *name; + s8 gpio_func_sel; +}; + +struct jhb100_pinctrl { + struct device *dev; + struct gpio_chip gc; + unsigned int num_banks; + struct pinctrl_gpio_range gpios; + raw_spinlock_t lock; + const char *iodomain_name; + void __iomem *base; + struct pinctrl_dev *pctl; + /* register read/write mutex */ + struct mutex mutex; + const struct jhb100_pinctrl_domain_info *info; + int irq; + struct irq_domain *irq_domain; + const struct pinctrl_pin_desc *pins; + unsigned int npins; + unsigned int ngpios; + s8 *gpio_func_sel_arr; +}; + +struct pinvref_desc { + unsigned int range; + u32 pin_grp[32]; + u32 num_pins; +}; + +struct pinvref_reg { + unsigned int reg; + const struct pinvref_desc *pv_desc; + u32 num_pv; +}; + +struct gpio_irq_reg { + unsigned int reg; + unsigned int width_per_pin; +}; + +struct starfive_pinctrl_regs { + struct pinvref_reg vref; + struct gpio_irq_reg func_sel; + unsigned int config; + unsigned int output; + unsigned int output_en; + unsigned int gpio_status; + unsigned int irq_en; + unsigned int irq_status; + unsigned int irq_clr; + unsigned int irq_trigger; + unsigned int irq_level; + unsigned int irq_both_edge; + unsigned int irq_edge; +}; + +struct reg_layout_field { + unsigned char shift; + unsigned char width; +}; + +enum jhb100_pad_cfg_field { + PAD_CFG_DEBOUNCE_WIDTH, + PAD_CFG_DRIVE_STRENGTH_2BIT, + PAD_CFG_DRIVE_STRENGTH_3BIT, + PAD_CFG_INPUT_ENABLE, + PAD_CFG_VSEL, + PAD_CFG_MODE_SELECT, + PAD_CFG_OPEN_DRAIN_PULL_UP_SEL, + PAD_CFG_PULL_DOWN, + PAD_CFG_PULL_UP, + PAD_CFG_SCHMITT_TRIGGER_SELECT, + PAD_CFG_SLEW_RATE, + PAD_CFG_COUNT +}; + +#define RL_DESC_SUPPORTED(crl_desc, field_enum) ({ \ + typeof(crl_desc) _desc = (crl_desc); \ + (_desc && (_desc)->fields[(field_enum)].width > 0); \ +}) + +#define RL_DESC_SHIFT(crl_desc, field_enum) ({ \ + typeof(crl_desc) __desc = (crl_desc); \ + (__desc)->fields[(field_enum)].shift; \ +}) + +#define RL_DESC_GENMASK(crl_desc, field_enum) ({ \ + typeof(crl_desc) __desc = (crl_desc); \ + RL_DESC_SUPPORTED(__desc, field_enum) ? \ + GENMASK( \ + (__desc)->fields[(field_enum)].shift + (__desc)->fields[(field_enum)].width - 1, \ + (__desc)->fields[(field_enum)].shift \ + ) : 0; \ +}) + +struct config_reg_layout_desc { + unsigned int pin_start; + unsigned int pin_cnt; + + struct reg_layout_field fields[PAD_CFG_COUNT]; +}; + +#define JHB100_FUNC_MAPS_MAX_PIN(n) ((n) + 1) + +struct jhb100_pinctrl_func_maps { + char *func; + unsigned char val; + u32 max_pin; +}; + +struct jhb100_pinctrl_domain_info { + const char *name; + const struct pinctrl_pin_desc *pins; + const struct jhb100_pin_layout_desc *pl_desc; + const struct jhb100_pinctrl_func_maps *fmaps; + u32 num_maps; + const struct config_reg_layout_desc *crl_desc; + const struct starfive_pinctrl_regs *regs; +}; + +int jhb100_pinctrl_probe(struct platform_device *pdev); + +#endif /* __PINCTRL_STARFIVE_JHB100_H__ */ From 6701c1c00891af014e43941b62e9e6699d18322d Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:40 -0700 Subject: [PATCH 060/106] dt-bindings: pinctrl: Add starfive,jhb100-sys0h-pinctrl Add pinctrl bindings for StarFive JHB100 SoC System-0 host(sys0h) pinctrl controller. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../starfive,jhb100-sys0h-pinctrl.yaml | 162 ++++++++++++++++++ 1 file changed, 162 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml new file mode 100644 index 000000000000..bfbd36928d7c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 System-0 Host Pin Controller + +description: | + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd. + + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1, + per2, per2pok, per3, adc0, adc1, emmc, and vga. + This document provides an overview of the "sys0h" pinctrl domain. + + The "sys0h" domain has a pin controller which provides + - function selection for GPIO pads. + - GPIO pad configuration. + - GPIO interrupt handling. + + In the SYS0H Pin Controller, there are 12 multi-function GPIO_PADs. Each of + them can be multiplexed to different hardware blocks through function + selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3. + Function 0 is the default function which is generally the GPIO function + (or occasionally, it can be a peripheral signal). + Functions 1, 2, and 3 are the alternate functions or peripheral signals that + can be routed to the iopad. The function selection can be carried out by + writing the function number to the iopad function select register. + + Each iopad is configurable with parameters such as input-enable, internal + pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input + debounce nanoseconds. + +maintainers: + - Changhuang Liang + +properties: + compatible: + items: + - const: starfive,jhb100-sys0h-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + function selection, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate, input debounce nanoseconds and + drive-strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. + enum: [ espi, espi_reset, espi0_vw, espi1_vw, gpio, scap_trigger ] + + bias-disable: true + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-debounce-ns: + minimum: 0 + maximum: 10485680 + description: + Debounce time in nanoseconds. The hardware counts in 80 ns + stages with a 17-bit counter, so the maximum is 10485680 ns. + input-disable: true + + input-enable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow + 1: fast +required: + - compatible + - reg + - resets + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_sys0h: pinctrl@13080800 { + compatible = "starfive,jhb100-sys0h-pinctrl"; + reg = <0x0 0x13080800 0x0 0x800>; + resets = <&sys0crg 3>; + interrupts = <57>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_sys0h 0 0 12>; + }; + }; From 6e4fa8e9f1eb57c88e3f7feaf540f03c6b23febc Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:41 -0700 Subject: [PATCH 061/106] pinctrl: starfive: Add StarFive JHB100 sys0h controller driver Add pinctrl driver for StarFive JHB100 SoC System-0 Host(sys0h) pinctrl controller. Co-developed-by: Lianfeng Ouyang Signed-off-by: Lianfeng Ouyang Signed-off-by: Alex Soo Signed-off-by: Changhuang Liang Signed-off-by: Linus Walleij --- drivers/pinctrl/starfive/Kconfig | 11 +++ drivers/pinctrl/starfive/Makefile | 1 + .../starfive/pinctrl-starfive-jhb100-sys0h.c | 99 +++++++++++++++++++ 3 files changed, 111 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0h.c diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index b3cb513c23de..992238f5b49d 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -66,3 +66,14 @@ config PINCTRL_STARFIVE_JHB100_SYS0 This also provides an interface to the GPIO pins not used by other peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. + +config PINCTRL_STARFIVE_JHB100_SYS0H + tristate "StarFive JHB100 SoC System-0 Host pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + select PINCTRL_STARFIVE_JHB100 + default ARCH_STARFIVE + help + Say yes here to support System-0 Host pin control on the StarFive JHB100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index c0d368f413bc..b26156a6d0eb 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o +obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0h.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0h.c new file mode 100644 index 000000000000..fb486ac60072 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0h.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JHB100 SoC System-0 host domain + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include + +#include "pinctrl-starfive-jhb100.h" + +/* sys0h pad numbers */ +#define PADNUM_SYS0H_GPIO_A10 6 +#define PADNUM_SYS0H_GPIO_A11 7 +#define PADNUM_SYS0H_GPIO_A15 11 + +static const struct jhb100_pin_layout_desc jhb100_sys0h_pl_desc[] = { + { .pin_start = 0, .pin_cnt = 7, .name = "gpio", .gpio_func_sel = 0 }, + { .pin_start = 7, .pin_cnt = 1, .name = "espi0_reset", .gpio_func_sel = 1 }, + { .pin_start = 8, .pin_cnt = 4, .name = "gpio", .gpio_func_sel = 0 }, + { 0xff }, +}; + +static const struct config_reg_layout_desc jhb100_sys0h_pinctrl_rl_desc[] = { + { + .pin_start = 0, + .pin_cnt = 12, + .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 }, + .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 }, + .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 }, + .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 }, + .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 }, + .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 }, + .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 }, + }, + { 0xff }, +}; + +static const struct starfive_pinctrl_regs jhb100_sys0h_pinctrl_regs = { + .func_sel = { .reg = 0x40, .width_per_pin = 2 }, + .config = 0x04, + .output = 0x34, + .output_en = 0x38, + .gpio_status = 0x3c, + .irq_en = 0x44, + .irq_status = 0x48, + .irq_clr = 0x4c, + .irq_trigger = 0x50, + .irq_level = 0x54, + .irq_both_edge = 0x58, + .irq_edge = 0x5c, +}; + +static const struct jhb100_pinctrl_func_maps jhb100_func_maps_sys0h[] = { + { .func = "espi", .val = 1 }, + { .func = "espi_reset", .val = 0 }, + { .func = "espi0_vw", .val = 1 }, + { .func = "espi1_vw", .val = 2 }, + { .func = "gpio", .val = 0, + .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_SYS0H_GPIO_A10) }, + { .func = "gpio", .val = 1, + .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_SYS0H_GPIO_A11) }, + { .func = "gpio", .val = 0, + .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_SYS0H_GPIO_A15) }, + { .func = "scap_trigger", .val = 3 }, +}; + +static const struct jhb100_pinctrl_domain_info jhb100_sys0h_pinctrl_info = { + .name = "jhb100-sys0h", + .pl_desc = jhb100_sys0h_pl_desc, + .crl_desc = jhb100_sys0h_pinctrl_rl_desc, + .regs = &jhb100_sys0h_pinctrl_regs, + .fmaps = jhb100_func_maps_sys0h, + .num_maps = ARRAY_SIZE(jhb100_func_maps_sys0h), +}; + +static const struct of_device_id jhb100_sys0h_pinctrl_of_match[] = { + { + .compatible = "starfive,jhb100-sys0h-pinctrl", + .data = &jhb100_sys0h_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jhb100_sys0h_pinctrl_of_match); + +static struct platform_driver jhb100_sys0h_pinctrl_driver = { + .probe = jhb100_pinctrl_probe, + .driver = { + .name = "starfive-jhb100-sys0h-pinctrl", + .of_match_table = jhb100_sys0h_pinctrl_of_match, + }, +}; +module_platform_driver(jhb100_sys0h_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC System-0 host domain"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL"); From bf8241062c79140366ab36a3a4fa099f45fa6ed4 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:42 -0700 Subject: [PATCH 062/106] dt-bindings: pinctrl: Add starfive,jhb100-sys1-pinctrl Add pinctrl bindings for StarFive JHB100 SoC System-1(sys1) pinctrl controller. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../pinctrl/starfive,jhb100-sys1-pinctrl.yaml | 164 ++++++++++++++++++ 1 file changed, 164 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys1-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys1-pinctrl.yaml new file mode 100644 index 000000000000..55e111117ea0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys1-pinctrl.yaml @@ -0,0 +1,164 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 System-1 Pin Controller + +description: | + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd. + + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1, + per2, per2pok, per3, adc0, adc1, emmc, and vga. + This document provides an overview of the "sys1" pinctrl domain. + + The "sys1" domain has a pin controller which provides + - function selection for GPIO pads. + - GPIO pad configuration. + - GPIO interrupt handling. + + In the SYS1 Pin Controller, there are 8 multi-function GPIO_PADs. Each of + them can be multiplexed to different hardware blocks through function + selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3. + Function 0 is the default function which is generally the GPIO function + (or occasionally, it can be a peripheral signal). + Function 1, 2, and 3 are the alternate functions or peripheral signals that + can be routed to the iopad. The function selection can be carried out by + writing the function number to the iopad function select register. + + Each iopad is configurable with parameters such as input-enable, internal + pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input + debounce nanoseconds. + +maintainers: + - Changhuang Liang + +properties: + compatible: + items: + - const: starfive,jhb100-sys1-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + function selection, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate, input debounce nanoseconds + and drive-strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. + enum: [ espi, espi_reset, gpio, host0_port80, host1_port80 ] + + bias-disable: true + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-debounce-ns: + minimum: 0 + maximum: 10485680 + description: + Debounce time in nanoseconds. The hardware counts in 80 ns + stages with a 17-bit counter, so the maximum is 10485680 ns. + + input-disable: true + + input-enable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow + 1: fast + +required: + - compatible + - reg + - resets + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_sys1: pinctrl@13081000 { + compatible = "starfive,jhb100-sys1-pinctrl"; + reg = <0x0 0x13081000 0x0 0x1000>; + resets = <&sys1crg 2>; + interrupts = <58>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_sys1 0 0 8>; + }; + }; From 1d5c13990916ca70711deb6390788ff86900fbc1 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:43 -0700 Subject: [PATCH 063/106] pinctrl: starfive: Add StarFive JHB100 sys1 controller driver Add pinctrl driver for StarFive JHB100 SoC System-1(sys1) pinctrl controller. Co-developed-by: Lianfeng Ouyang Signed-off-by: Lianfeng Ouyang Signed-off-by: Alex Soo Signed-off-by: Changhuang Liang Signed-off-by: Linus Walleij --- drivers/pinctrl/starfive/Kconfig | 11 +++ drivers/pinctrl/starfive/Makefile | 1 + .../starfive/pinctrl-starfive-jhb100-sys1.c | 94 +++++++++++++++++++ 3 files changed, 106 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys1.c diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index 992238f5b49d..895b9cb0cb2a 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -77,3 +77,14 @@ config PINCTRL_STARFIVE_JHB100_SYS0H This also provides an interface to the GPIO pins not used by other peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. + +config PINCTRL_STARFIVE_JHB100_SYS1 + tristate "StarFive JHB100 SoC System-1 pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + select PINCTRL_STARFIVE_JHB100 + default ARCH_STARFIVE + help + Say yes here to support System-1 pin control on the StarFive JHB100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index b26156a6d0eb..8d96cf80d377 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o +obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys1.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys1.c new file mode 100644 index 000000000000..2185c3d15bc2 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys1.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JHB100 SoC System-1 domain + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include + +#include "pinctrl-starfive-jhb100.h" + +/* sys1 pad numbers */ +#define PADNUM_SYS1_GPIO_A22 6 +#define PADNUM_SYS1_GPIO_A23 7 + +static const struct jhb100_pin_layout_desc jhb100_sys1_pl_desc[] = { + { .pin_start = 0, .pin_cnt = 7, .name = "gpio", .gpio_func_sel = 0 }, + { .pin_start = 7, .pin_cnt = 1, .name = "espi1_reset", .gpio_func_sel = 1 }, + { 0xff }, +}; + +static const struct config_reg_layout_desc jhb100_sys1_pinctrl_rl_desc[] = { + { + .pin_start = 0, + .pin_cnt = 8, + .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 }, + .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 }, + .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 }, + .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 }, + .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 }, + .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 }, + .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 }, + }, + { 0xff }, +}; + +static const struct starfive_pinctrl_regs jhb100_sys1_pinctrl_regs = { + .func_sel = { .reg = 0x30, .width_per_pin = 2 }, + .config = 0x04, + .output = 0x24, + .output_en = 0x28, + .gpio_status = 0x2c, + .irq_en = 0x34, + .irq_status = 0x38, + .irq_clr = 0x3c, + .irq_trigger = 0x40, + .irq_level = 0x44, + .irq_both_edge = 0x48, + .irq_edge = 0x4c, +}; + +static const struct jhb100_pinctrl_func_maps jhb100_func_maps_sys1[] = { + { .func = "espi", .val = 1 }, + { .func = "espi_reset", .val = 0 }, + { .func = "gpio", .val = 0, + .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_SYS1_GPIO_A22) }, + { .func = "gpio", .val = 1, + .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_SYS1_GPIO_A23) }, + { .func = "host0_port80", .val = 2 }, + { .func = "host1_port80", .val = 3 }, +}; + +static const struct jhb100_pinctrl_domain_info jhb100_sys1_pinctrl_info = { + .name = "jhb100-sys1", + .pl_desc = jhb100_sys1_pl_desc, + .crl_desc = jhb100_sys1_pinctrl_rl_desc, + .regs = &jhb100_sys1_pinctrl_regs, + .fmaps = jhb100_func_maps_sys1, + .num_maps = ARRAY_SIZE(jhb100_func_maps_sys1), +}; + +static const struct of_device_id jhb100_sys1_pinctrl_of_match[] = { + { + .compatible = "starfive,jhb100-sys1-pinctrl", + .data = &jhb100_sys1_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jhb100_sys1_pinctrl_of_match); + +static struct platform_driver jhb100_sys1_pinctrl_driver = { + .probe = jhb100_pinctrl_probe, + .driver = { + .name = "starfive-jhb100-sys1-pinctrl", + .of_match_table = jhb100_sys1_pinctrl_of_match, + }, +}; +module_platform_driver(jhb100_sys1_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC System-1 domain"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL"); From 941cc8022c219cea601fa85b6b2f0f49605ea722 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:44 -0700 Subject: [PATCH 064/106] dt-bindings: pinctrl: Add starfive,jhb100-sys2-pinctrl Add pinctrl bindings for StarFive JHB100 SoC System-2(sys2) pinctrl controller. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../pinctrl/starfive,jhb100-sys2-pinctrl.yaml | 165 ++++++++++++++++++ 1 file changed, 165 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml new file mode 100644 index 000000000000..e2d18e0d4916 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys2-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 System-2 Pin Controller + +description: | + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd. + + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1, + per2, per2pok, per3, adc0, adc1, emmc, and vga. + This document provides an overview of the "sys2" pinctrl domain. + + The "sys2" domain has a pin controller which provides + - function selection for GPIO pads. + - GPIO pad configuration. + - GPIO interrupt handling. + + In the SYS2 Pin Controller, there are 37 multi-function GPIO_PADs. Each of + them can be multiplexed to different hardware blocks through function + selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3. + Function 0 is the default function which is the GPIO function. + Function 1, 2, and 3 are the alternate functions or peripheral signals that + can be routed to the iopad. The function selection can be carried out by + writing the function number to the iopad function select register. + + Each iopad is configurable with parameters such as input-enable, internal + pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input + debounce nanoseconds, power source. + +maintainers: + - Changhuang Liang + +properties: + compatible: + items: + - const: starfive,jhb100-sys2-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + function selection, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate, input debounce nanoseconds, + power-source and drive-strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. + enum: [ gpio, host0_port80, host1_port80, jtag, smbalert, uart ] + + bias-disable: true + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-debounce-ns: + minimum: 0 + maximum: 10485680 + description: + Debounce time in nanoseconds. The hardware counts in 80 ns + stages with a 17-bit counter, so the maximum is 10485680 ns. + + input-disable: true + + input-enable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + power-source: + enum: [ 1800, 3300 ] + description: I/O voltage in millivolt. + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow + 1: fast + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_sys2: pinctrl@13082000 { + compatible = "starfive,jhb100-sys2-pinctrl"; + reg = <0x0 0x13082000 0x0 0x1000>; + interrupts = <59>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_sys2 0 0 37>; + }; + }; From 594deb7f74f4444e251073d5577736fa433c78fa Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:45 -0700 Subject: [PATCH 065/106] pinctrl: starfive: Add StarFive JHB100 sys2 controller driver Add pinctrl driver for StarFive JHB100 SoC System-2(sys2) pinctrl controller. Co-developed-by: Lianfeng Ouyang Signed-off-by: Lianfeng Ouyang Signed-off-by: Alex Soo Signed-off-by: Changhuang Liang Signed-off-by: Linus Walleij --- drivers/pinctrl/starfive/Kconfig | 11 ++ drivers/pinctrl/starfive/Makefile | 1 + .../starfive/pinctrl-starfive-jhb100-sys2.c | 140 ++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys2.c diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index 895b9cb0cb2a..1d7e661455a8 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -88,3 +88,14 @@ config PINCTRL_STARFIVE_JHB100_SYS1 This also provides an interface to the GPIO pins not used by other peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. + +config PINCTRL_STARFIVE_JHB100_SYS2 + tristate "StarFive JHB100 SoC System-2 pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + select PINCTRL_STARFIVE_JHB100 + default ARCH_STARFIVE + help + Say yes here to support System-2 pin control on the StarFive JHB100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index 8d96cf80d377..b817ad93b91d 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o +obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS2) += pinctrl-starfive-jhb100-sys2.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys2.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys2.c new file mode 100644 index 000000000000..2744744882e8 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys2.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JHB100 SoC System-2 domain + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include + +#include "pinctrl-starfive-jhb100.h" + +/* sys2 pad numbers */ +#define PADNUM_SYS2_GPIO_A36 12 +#define PADNUM_SYS2_GPIO_A37 13 +#define PADNUM_SYS2_GPIO_A38 14 +#define PADNUM_SYS2_GPIO_A39 15 +#define PADNUM_SYS2_GPIO_A40 16 +#define PADNUM_SYS2_GPIO_A41 17 +#define PADNUM_SYS2_GPIO_A42 18 +#define PADNUM_SYS2_GPIO_A43 19 + +static const struct jhb100_pin_layout_desc jhb100_sys2_pl_desc[] = { + { .pin_start = 0, .pin_cnt = 37, .name = "gpio", .gpio_func_sel = 0 }, + { .pin_start = 37, .pin_cnt = 1, .name = "jtag_tck", .gpio_func_sel = -1 }, + { .pin_start = 38, .pin_cnt = 1, .name = "jtag_tresetn", .gpio_func_sel = -1 }, + { .pin_start = 39, .pin_cnt = 1, .name = "jtag_tmc", .gpio_func_sel = -1 }, + { .pin_start = 40, .pin_cnt = 1, .name = "jtag_tdi", .gpio_func_sel = -1 }, + { .pin_start = 41, .pin_cnt = 1, .name = "jtag_tdo", .gpio_func_sel = -1 }, + { .pin_start = 42, .pin_cnt = 1, .name = "jtag_hpd", .gpio_func_sel = -1 }, + { 0xff }, +}; + +static const struct config_reg_layout_desc jhb100_sys2_pinctrl_rl_desc[] = { + { + .pin_start = 0, + .pin_cnt = 37, + .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 }, + .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 }, + .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 }, + .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 }, + .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 }, + .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 }, + .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 }, + }, + { + .pin_start = 37, + .pin_cnt = 6, + .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 }, + .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 }, + .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 }, + .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 }, + .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 }, + .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 }, + }, + { 0xff }, +}; + +static const struct pinvref_desc pinvref_desc_sys2[] = { + { + /* gpiow */ + .pin_grp = { + PADNUM_SYS2_GPIO_A36, + PADNUM_SYS2_GPIO_A37, + PADNUM_SYS2_GPIO_A38, + PADNUM_SYS2_GPIO_A39 + }, + .num_pins = 4, + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V) + }, + { + /* gpiow-inner */ + .pin_grp = { + PADNUM_SYS2_GPIO_A40, + PADNUM_SYS2_GPIO_A41, + PADNUM_SYS2_GPIO_A42, + PADNUM_SYS2_GPIO_A43 + }, + .num_pins = 4, + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V) + }, +}; + +static const struct starfive_pinctrl_regs jhb100_sys2_pinctrl_regs = { + .vref = { .reg = 0x000, .pv_desc = pinvref_desc_sys2, + .num_pv = ARRAY_SIZE(pinvref_desc_sys2) }, + .func_sel = { .reg = 0x0d4, .width_per_pin = 2 }, + .config = 0x010, + .output = 0x0bc, + .output_en = 0x0c4, + .gpio_status = 0x0cc, + .irq_en = 0x0e0, + .irq_status = 0x0e8, + .irq_clr = 0x0f0, + .irq_trigger = 0x0f8, + .irq_level = 0x100, + .irq_both_edge = 0x108, + .irq_edge = 0x110, +}; + +static const struct jhb100_pinctrl_func_maps jhb100_func_maps_sys2[] = { + { .func = "gpio", .val = 0 }, + { .func = "host0_port80", .val = 2 }, + { .func = "host1_port80", .val = 3 }, + { .func = "jtag", .val = 2 }, + { .func = "smbalert", .val = 2 }, + { .func = "uart", .val = 1 }, +}; + +static const struct jhb100_pinctrl_domain_info jhb100_sys2_pinctrl_info = { + .name = "jhb100-sys2", + .pl_desc = jhb100_sys2_pl_desc, + .crl_desc = jhb100_sys2_pinctrl_rl_desc, + .regs = &jhb100_sys2_pinctrl_regs, + .fmaps = jhb100_func_maps_sys2, + .num_maps = ARRAY_SIZE(jhb100_func_maps_sys2), +}; + +static const struct of_device_id jhb100_sys2_pinctrl_of_match[] = { + { + .compatible = "starfive,jhb100-sys2-pinctrl", + .data = &jhb100_sys2_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jhb100_sys2_pinctrl_of_match); + +static struct platform_driver jhb100_sys2_pinctrl_driver = { + .probe = jhb100_pinctrl_probe, + .driver = { + .name = "starfive-jhb100-sys2-pinctrl", + .of_match_table = jhb100_sys2_pinctrl_of_match, + }, +}; +module_platform_driver(jhb100_sys2_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC System-2 domain"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL"); From 402323de0c04a40ac14216fa4422256a3f02e8e8 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:46 -0700 Subject: [PATCH 066/106] dt-bindings: pinctrl: Add starfive,jhb100-per0-pinctrl Add pinctrl bindings for StarFive JHB100 SoC Peripheral-0(per0) pinctrl controller. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../pinctrl/starfive,jhb100-per0-pinctrl.yaml | 179 ++++++++++++++++++ 1 file changed, 179 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml new file mode 100644 index 000000000000..0e7e7f231e2b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml @@ -0,0 +1,179 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per0-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 Peripheral-0 Pin Controller + +description: | + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd. + + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1, + per2, per2pok, per3, adc0, adc1, emmc, and vga. + This document provides an overview of the "per0" pinctrl domain. + + The "per0" domain has a pin controller which provides + - function selection for GPIO pads. + - GPIO pad configuration. + - GPIO interrupt handling. + + In the Peripheral-0 Pin Controller, there are 60 multi-function GPIO_PADs. + Each of them can be multiplexed to several hardware blocks through function + selection. Each iopad has a maximum of up to 3 functions - 0, 1, and 2. + Function 0 is the default function which is generally the GPIO function. + Function 1 and 2 are the alternate function or signal of an iopad. The + function 1 and function 2 are other optional functions or peripheral + signals that can be routed to an iopad. The function selection can be carried + out by writing the function number to the iopad function select register. + + Each iopad is configurable with parameters such as input-enable, internal + pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input + debounce nanoseconds, power source and drive type (open-drain or push-pull). + +maintainers: + - Changhuang Liang + +properties: + compatible: + items: + - const: starfive,jhb100-per0-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + function selection, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate, input debounce nanoseconds, + drive-open-drain, drive-push-pull, power-source and drive-strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. + enum: [ gmac_mdio, gpio, i2c, i3c, smbalert, wdt ] + + bias-disable: true + + bias-pull-down: + type: boolean + + bias-pull-up: + oneOf: + - type: boolean + - enum: [ 600, 900, 1200, 2000 ] + description: Pull up RSEL type resistance values (in ohms) + description: + For normal pull up type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull up type a resistance value (in ohms) can be added. + + drive-open-drain: true + + drive-push-pull: true + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-debounce-ns: + minimum: 0 + maximum: 10485680 + description: + Debounce time in nanoseconds. The hardware counts in 80 ns + stages with a 17-bit counter, so the maximum is 10485680 ns. + + input-disable: true + + input-enable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + power-source: + enum: [ 1800, 3300 ] + description: I/O voltage in millivolt. + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow + 1: fast + +required: + - compatible + - reg + - resets + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_per0: pinctrl@11a0a000 { + compatible = "starfive,jhb100-per0-pinctrl"; + reg = <0x0 0x11a0a000 0x0 0x1000>; + resets = <&per0crg 0>; + interrupts = <60>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_per0 0 0 60>; + }; + }; From 14abdf1eae71a73e23a51162bb0f956275ccb384 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:47 -0700 Subject: [PATCH 067/106] pinctrl: starfive: Add StarFive JHB100 per0 controller driver Add pinctrl driver for StarFive JHB100 SoC Peripheral-0(per0) pinctrl controller. Co-developed-by: Lianfeng Ouyang Signed-off-by: Lianfeng Ouyang Signed-off-by: Alex Soo Signed-off-by: Changhuang Liang Signed-off-by: Linus Walleij --- drivers/pinctrl/starfive/Kconfig | 11 ++ drivers/pinctrl/starfive/Makefile | 1 + .../starfive/pinctrl-starfive-jhb100-per0.c | 182 ++++++++++++++++++ 3 files changed, 194 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per0.c diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index 1d7e661455a8..07f9cb3d6eae 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -56,6 +56,17 @@ config PINCTRL_STARFIVE_JHB100 select GPIOLIB_IRQCHIP select OF_GPIO +config PINCTRL_STARFIVE_JHB100_PER0 + tristate "StarFive JHB100 SoC Peripheral-0 pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + select PINCTRL_STARFIVE_JHB100 + default ARCH_STARFIVE + help + Say yes here to support Peripheral-0 pin control on the StarFive JHB100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. + config PINCTRL_STARFIVE_JHB100_SYS0 tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver" depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index b817ad93b91d..f2bb0c35a2a0 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_SYS) += pinctrl-starfive-jh7110-sys.o obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o +obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per0.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per0.c new file mode 100644 index 000000000000..679954b19808 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per0.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-0 domain + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include + +#include "pinctrl-starfive-jhb100.h" + +/* per0 pad numbers */ +#define PADNUM_PER0_GPIO_B8 8 +#define PADNUM_PER0_GPIO_B9 9 +#define PADNUM_PER0_GPIO_B10 10 +#define PADNUM_PER0_GPIO_B11 11 +#define PADNUM_PER0_GPIO_B12 12 +#define PADNUM_PER0_GPIO_B13 13 +#define PADNUM_PER0_GPIO_B14 14 +#define PADNUM_PER0_GPIO_B15 15 +#define PADNUM_PER0_GPIO_B16 16 +#define PADNUM_PER0_GPIO_B17 17 +#define PADNUM_PER0_GPIO_B18 18 +#define PADNUM_PER0_GPIO_B19 19 +#define PADNUM_PER0_GPIO_B20 20 +#define PADNUM_PER0_GPIO_B21 21 +#define PADNUM_PER0_GPIO_B22 22 +#define PADNUM_PER0_GPIO_B23 23 +#define PADNUM_PER0_GPIO_B32 32 +#define PADNUM_PER0_GPIO_B33 33 +#define PADNUM_PER0_GPIO_B34 34 +#define PADNUM_PER0_GPIO_B35 35 +#define PADNUM_PER0_GPIO_B36 36 +#define PADNUM_PER0_GPIO_B37 37 +#define PADNUM_PER0_GPIO_B38 38 +#define PADNUM_PER0_GPIO_B39 39 +#define PADNUM_PER0_GPIO_B40 40 +#define PADNUM_PER0_GPIO_B41 41 +#define PADNUM_PER0_GPIO_B42 42 +#define PADNUM_PER0_GPIO_B43 43 +#define PADNUM_PER0_GPIO_B59 59 + +static const struct jhb100_pin_layout_desc jhb100_per0_pl_desc[] = { + { .pin_start = 0, .pin_cnt = 60, .name = "gpio", .gpio_func_sel = 0 }, + { 0xff }, +}; + +static const struct config_reg_layout_desc jhb100_per0_pinctrl_rl_desc[] = { + { + .pin_start = 0, + .pin_cnt = 60, + .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 0, .width = 1 }, + .fields[PAD_CFG_MODE_SELECT] = { .shift = 1, .width = 2 }, + .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 }, + .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 }, + .fields[PAD_CFG_OPEN_DRAIN_PULL_UP_SEL] = { .shift = 5, .width = 2 }, + .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 7, .width = 1 }, + .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 }, + }, + { 0xff }, +}; + +static const struct pinvref_desc pinvref_desc_per0[] = { + { + /* gpioe-i3c0 */ + .pin_grp = { + PADNUM_PER0_GPIO_B8, + PADNUM_PER0_GPIO_B9, + PADNUM_PER0_GPIO_B10, + PADNUM_PER0_GPIO_B11, + PADNUM_PER0_GPIO_B32, + PADNUM_PER0_GPIO_B33 + }, + .num_pins = 6, + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V) + }, + { + /* gpioe-i3c1 */ + .pin_grp = { + PADNUM_PER0_GPIO_B12, + PADNUM_PER0_GPIO_B13, + PADNUM_PER0_GPIO_B14, + PADNUM_PER0_GPIO_B15, + PADNUM_PER0_GPIO_B34, + PADNUM_PER0_GPIO_B35 + }, + .num_pins = 6, + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V) + }, + { + /* gpioe-i3c2 */ + .pin_grp = { + PADNUM_PER0_GPIO_B16, + PADNUM_PER0_GPIO_B17, + PADNUM_PER0_GPIO_B18, + PADNUM_PER0_GPIO_B19, + PADNUM_PER0_GPIO_B20, + PADNUM_PER0_GPIO_B21, + PADNUM_PER0_GPIO_B22, + PADNUM_PER0_GPIO_B23 + }, + .num_pins = 8, + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V) + }, + { + /* gpioe-i3c4 */ + .pin_grp = { + PADNUM_PER0_GPIO_B36, + PADNUM_PER0_GPIO_B37, + PADNUM_PER0_GPIO_B38, + PADNUM_PER0_GPIO_B39, + PADNUM_PER0_GPIO_B40, + PADNUM_PER0_GPIO_B41, + PADNUM_PER0_GPIO_B42, + PADNUM_PER0_GPIO_B43 + }, + .num_pins = 8, + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V) + }, +}; + +static const struct starfive_pinctrl_regs jhb100_per0_pinctrl_regs = { + .vref = { .reg = 0x004, .pv_desc = pinvref_desc_per0, + .num_pv = ARRAY_SIZE(pinvref_desc_per0) }, + .func_sel = { .reg = 0x11c, .width_per_pin = 2 }, + .config = 0x014, + .output = 0x104, + .output_en = 0x10c, + .gpio_status = 0x114, + .irq_en = 0x12c, + .irq_status = 0x134, + .irq_clr = 0x13c, + .irq_trigger = 0x144, + .irq_level = 0x14c, + .irq_both_edge = 0x154, + .irq_edge = 0x15c, +}; + +static const struct jhb100_pinctrl_func_maps jhb100_func_maps_per0[] = { + { .func = "gmac_mdio", .val = 2 }, + { .func = "gpio", .val = 0 }, + { .func = "i2c", .val = 1 }, + { .func = "i3c", .val = 2, + .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER0_GPIO_B23) }, + { .func = "i3c", .val = 1, + .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER0_GPIO_B59) }, + { .func = "smbalert", .val = 1 }, + { .func = "wdt", .val = 2 }, +}; + +static const struct jhb100_pinctrl_domain_info jhb100_per0_pinctrl_info = { + .name = "jhb100-per0", + .pl_desc = jhb100_per0_pl_desc, + .crl_desc = jhb100_per0_pinctrl_rl_desc, + .regs = &jhb100_per0_pinctrl_regs, + .fmaps = jhb100_func_maps_per0, + .num_maps = ARRAY_SIZE(jhb100_func_maps_per0), +}; + +static const struct of_device_id jhb100_per0_pinctrl_of_match[] = { + { + .compatible = "starfive,jhb100-per0-pinctrl", + .data = &jhb100_per0_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jhb100_per0_pinctrl_of_match); + +static struct platform_driver jhb100_per0_pinctrl_driver = { + .probe = jhb100_pinctrl_probe, + .driver = { + .name = "starfive-jhb100-per0-pinctrl", + .of_match_table = jhb100_per0_pinctrl_of_match, + }, +}; +module_platform_driver(jhb100_per0_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-0 domain"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL"); From d6001140c2e8ebcaeec8ed97e12ea8385aa369b1 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:48 -0700 Subject: [PATCH 068/106] dt-bindings: pinctrl: Add starfive,jhb100-per1-pinctrl Add pinctrl bindings for StarFive JHB100 SoC Peripheral-1(per1) pinctrl controller. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../pinctrl/starfive,jhb100-per1-pinctrl.yaml | 178 ++++++++++++++++++ 1 file changed, 178 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml new file mode 100644 index 000000000000..932dcc8ace85 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 Peripheral-1 Pin Controller + +description: | + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd. + + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1, + per2, per2pok, per3, adc0, adc1, emmc, and vga. + This document provides an overview of the "per1" pinctrl domain. + + The "per1" domain has a pin controller which provides + - function selection for GPIO pads. + - GPIO pad configuration. + - GPIO interrupt handling. + + In the Peripheral-1 Pin Controller, there are 36 multi-function GPIO_PADs. + Each of them can be multiplexed to several peripherals through function + selection. Each iopad has a maximum of up to 3 functions - 0, 1, and 2. + Function 0 is the default function which is generally the GPIO function. + Function 1 and 2 are the alternate functions or peripheral signals that + can be routed to the iopad. The function selection can be carried out by + writing the function number to the iopad function select register. + + Each iopad is configurable with parameters such as input-enable, internal + pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input + debounce nanoseconds, power source and drive type (open-drain or push-pull). + +maintainers: + - Changhuang Liang + +properties: + compatible: + items: + - const: starfive,jhb100-per1-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + function selection, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate, input debounce nanoseconds, + drive-open-drain, drive-push-pull, power-source and drive-strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. + enum: [ gpio, i2c, sfc, sgpio, spi ] + + bias-disable: true + + bias-pull-down: + type: boolean + + bias-pull-up: + oneOf: + - type: boolean + - enum: [ 600, 900, 1200, 2000 ] + description: Pull up RSEL type resistance values (in ohms) + description: + For normal pull up type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull up type a resistance value (in ohms) can be added. + + drive-open-drain: true + + drive-push-pull: true + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-debounce-ns: + minimum: 0 + maximum: 10485680 + description: + Debounce time in nanoseconds. The hardware counts in 80 ns + stages with a 17-bit counter, so the maximum is 10485680 ns. + + input-disable: true + + input-enable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + power-source: + enum: [ 1800, 3300 ] + description: I/O voltage in millivolt. + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow + 1: fast + +required: + - compatible + - reg + - resets + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_per1: pinctrl@11b42000 { + compatible = "starfive,jhb100-per1-pinctrl"; + reg = <0x0 0x11b42000 0x0 0x800>; + resets = <&per1crg 0>; + interrupts = <61>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_per1 0 0 36>; + }; + }; From 2539dfb77e559320e213c301c388c2c2925aa3ed Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:49 -0700 Subject: [PATCH 069/106] pinctrl: starfive: Add StarFive JHB100 per1 controller driver Add pinctrl driver for StarFive JHB100 SoC Peripheral-1(per1) pinctrl controller. Co-developed-by: Lianfeng Ouyang Signed-off-by: Lianfeng Ouyang Signed-off-by: Alex Soo Signed-off-by: Changhuang Liang Signed-off-by: Linus Walleij --- drivers/pinctrl/starfive/Kconfig | 11 + drivers/pinctrl/starfive/Makefile | 1 + .../starfive/pinctrl-starfive-jhb100-per1.c | 193 ++++++++++++++++++ 3 files changed, 205 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index 07f9cb3d6eae..823062be6d9f 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -67,6 +67,17 @@ config PINCTRL_STARFIVE_JHB100_PER0 peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. +config PINCTRL_STARFIVE_JHB100_PER1 + tristate "StarFive JHB100 SoC Peripheral-1 pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + select PINCTRL_STARFIVE_JHB100 + default ARCH_STARFIVE + help + Say yes here to support Peripheral-1 pin control on the StarFive JHB100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. + config PINCTRL_STARFIVE_JHB100_SYS0 tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver" depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index f2bb0c35a2a0..6beef7e313ef 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o +obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c new file mode 100644 index 000000000000..45fc231e2c86 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-1 domain + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include + +#include "pinctrl-starfive-jhb100.h" + +/* per1 pad numbers */ +#define PADNUM_PER1_GPIO_C0 0 +#define PADNUM_PER1_GPIO_C1 1 +#define PADNUM_PER1_GPIO_C2 2 +#define PADNUM_PER1_GPIO_C3 3 +#define PADNUM_PER1_GPIO_C4 4 +#define PADNUM_PER1_GPIO_C5 5 +#define PADNUM_PER1_GPIO_C6 6 +#define PADNUM_PER1_GPIO_C7 7 +#define PADNUM_PER1_GPIO_C8 8 +#define PADNUM_PER1_GPIO_C9 9 +#define PADNUM_PER1_GPIO_C10 10 +#define PADNUM_PER1_GPIO_C11 11 +#define PADNUM_PER1_GPIO_C12 12 +#define PADNUM_PER1_GPIO_C13 13 +#define PADNUM_PER1_GPIO_C14 14 +#define PADNUM_PER1_GPIO_C15 15 +#define PADNUM_PER1_GPIO_C16 16 +#define PADNUM_PER1_GPIO_C17 17 +#define PADNUM_PER1_GPIO_C18 18 +#define PADNUM_PER1_GPIO_C19 19 +#define PADNUM_PER1_GPIO_C20 20 +#define PADNUM_PER1_GPIO_C21 21 +#define PADNUM_PER1_GPIO_C22 22 +#define PADNUM_PER1_GPIO_C23 23 +#define PADNUM_PER1_GPIO_C24 24 +#define PADNUM_PER1_GPIO_C25 25 +#define PADNUM_PER1_GPIO_C26 26 +#define PADNUM_PER1_GPIO_C27 27 +#define PADNUM_PER1_GPIO_C31 31 +#define PADNUM_PER1_GPIO_C35 35 + +static const struct jhb100_pin_layout_desc jhb100_per1_pl_desc[] = { + { .pin_start = 0, .pin_cnt = 36, .name = "gpio", .gpio_func_sel = 0 }, + { 0xff }, +}; + +static const struct config_reg_layout_desc jhb100_per1_pinctr_rldesc[] = { + { + .pin_start = 0, + .pin_cnt = 32, + .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 }, + .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 }, + .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 }, + .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 }, + .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 }, + .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 }, + .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 }, + }, + { + .pin_start = 32, + .pin_cnt = 4, + .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 0, .width = 1 }, + .fields[PAD_CFG_MODE_SELECT] = { .shift = 1, .width = 2 }, + .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 }, + .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 }, + .fields[PAD_CFG_OPEN_DRAIN_PULL_UP_SEL] = { .shift = 5, .width = 2 }, + .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 7, .width = 1 }, + .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 }, + }, + { 0xff }, +}; + +static const struct pinvref_desc pinvref_desc_per1[] = { + { + /* gpioe-spi */ + .pin_grp = { + PADNUM_PER1_GPIO_C0, + PADNUM_PER1_GPIO_C1, + PADNUM_PER1_GPIO_C2, + PADNUM_PER1_GPIO_C3, + PADNUM_PER1_GPIO_C4 + }, + .num_pins = 5, + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V) + }, + { + /* gpioe-qspi0 */ + .pin_grp = { + PADNUM_PER1_GPIO_C5, + PADNUM_PER1_GPIO_C6, + PADNUM_PER1_GPIO_C7, + PADNUM_PER1_GPIO_C8, + PADNUM_PER1_GPIO_C9, + PADNUM_PER1_GPIO_C10, + PADNUM_PER1_GPIO_C11 + }, + .num_pins = 7, + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V) + }, + { + /* gpioe-qspi1 */ + .pin_grp = { + PADNUM_PER1_GPIO_C12, + PADNUM_PER1_GPIO_C13, + PADNUM_PER1_GPIO_C14, + PADNUM_PER1_GPIO_C15, + PADNUM_PER1_GPIO_C16, + PADNUM_PER1_GPIO_C17, + PADNUM_PER1_GPIO_C18, + PADNUM_PER1_GPIO_C19 + }, + .num_pins = 8, + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V) + }, + { + /* gpioe-qspi2 */ + .pin_grp = { + PADNUM_PER1_GPIO_C20, + PADNUM_PER1_GPIO_C21, + PADNUM_PER1_GPIO_C22, + PADNUM_PER1_GPIO_C23, + PADNUM_PER1_GPIO_C24, + PADNUM_PER1_GPIO_C25, + PADNUM_PER1_GPIO_C26, + PADNUM_PER1_GPIO_C27 + }, + .num_pins = 8, + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V) + }, +}; + +static const struct starfive_pinctrl_regs jhb100_per1_pinctrl_regs = { + .vref = { .reg = 0x00, .pv_desc = pinvref_desc_per1, + .num_pv = ARRAY_SIZE(pinvref_desc_per1) }, + .func_sel = { .reg = 0xbc, .width_per_pin = 2 }, + .config = 0x14, + .output = 0xa4, + .output_en = 0xac, + .gpio_status = 0xb4, + .irq_en = 0xc8, + .irq_status = 0xd0, + .irq_clr = 0xd8, + .irq_trigger = 0xe0, + .irq_level = 0xe8, + .irq_both_edge = 0xf0, + .irq_edge = 0xf8, +}; + +static const struct jhb100_pinctrl_func_maps jhb100_func_maps_per1[] = { + { .func = "gpio", .val = 0 }, + { .func = "i2c", .val = 1 }, + { .func = "sfc", .val = 1 }, + { .func = "sgpio", .val = 1, + .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER1_GPIO_C31) }, + { .func = "sgpio", .val = 2, + .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER1_GPIO_C35) }, + { .func = "spi", .val = 1 }, +}; + +static const struct jhb100_pinctrl_domain_info jhb100_per1_pinctrl_info = { + .name = "jhb100-per1", + .pl_desc = jhb100_per1_pl_desc, + .crl_desc = jhb100_per1_pinctr_rldesc, + .regs = &jhb100_per1_pinctrl_regs, + .fmaps = jhb100_func_maps_per1, + .num_maps = ARRAY_SIZE(jhb100_func_maps_per1), +}; + +static const struct of_device_id jhb100_per1_pinctrl_of_match[] = { + { + .compatible = "starfive,jhb100-per1-pinctrl", + .data = &jhb100_per1_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jhb100_per1_pinctrl_of_match); + +static struct platform_driver jhb100_per1_pinctrl_driver = { + .probe = jhb100_pinctrl_probe, + .driver = { + .name = "starfive-jhb100-per1-pinctrl", + .of_match_table = jhb100_per1_pinctrl_of_match, + }, +}; +module_platform_driver(jhb100_per1_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-1 domain"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL"); From b598855cc302ef9f619180f3c90271878e662ad0 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:50 -0700 Subject: [PATCH 070/106] dt-bindings: pinctrl: Add starfive,jhb100-per2-pinctrl Add pinctrl bindings for StarFive JHB100 SoC Peripheral-2(per2) pinctrl controller. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../pinctrl/starfive,jhb100-per2-pinctrl.yaml | 168 ++++++++++++++++++ 1 file changed, 168 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml new file mode 100644 index 000000000000..18ee37a2bb1f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml @@ -0,0 +1,168 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per2-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 Peripheral-2 Pin Controller + +description: | + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd. + + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1, + per2, per2pok, per3, adc0, adc1, emmc, and vga. + This document provides an overview of the "per2" pinctrl domain. + + The "per2" domain has a pin controller which provides + - function selection for GPIO pads. + - GPIO pad configuration. + - GPIO interrupt handling. + + In the Peripheral-2 Pin Controller, there are 31 multi-function GPIO_PADs. + Each of them can be multiplexed to several peripherals through function + selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3. + Function 0 is the default function which is generally the GPIO function. + Function 1, 2, and 3 are the alternate functions or peripheral signals + that can be routed to an iopad. The function selection can be carried + out by writing the function number to the iopad function select register. + + Each iopad is configurable with parameters such as input-enable, internal + pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input + debounce nanoseconds, power source. + +maintainers: + - Changhuang Liang + +properties: + compatible: + items: + - const: starfive,jhb100-per2-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + function selection, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate, input debounce nanoseconds, + power-source and drive-strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. + enum: [ fan_tach, gmac_rgmii, gmac_rmii, gpio, host0_port80, + host1_port80 ] + + bias-disable: true + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-debounce-ns: + minimum: 0 + maximum: 10485680 + description: + Debounce time in nanoseconds. The hardware counts in 80 ns + stages with a 17-bit counter, so the maximum is 10485680 ns. + + input-disable: true + + input-enable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + power-source: + enum: [ 1800, 2500, 3300 ] + description: I/O voltage in millivolt. + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow + 1: fast + +required: + - compatible + - reg + - resets + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_per2: pinctrl@11bc2000 { + compatible = "starfive,jhb100-per2-pinctrl"; + reg = <0x0 0x11bc2000 0x0 0x400>; + resets = <&per2crg 0>; + interrupts = <62>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_per2 0 0 31>; + }; + }; From 260a7f2d171521a46c61fa5c583f45b7dbbe3722 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:51 -0700 Subject: [PATCH 071/106] pinctrl: starfive: Add StarFive JHB100 per2 controller driver Add pinctrl driver for StarFive JHB100 SoC Peripheral-2(per2) pinctrl controller. Co-developed-by: Lianfeng Ouyang Signed-off-by: Lianfeng Ouyang Signed-off-by: Alex Soo Signed-off-by: Changhuang Liang Signed-off-by: Linus Walleij --- drivers/pinctrl/starfive/Kconfig | 11 ++ drivers/pinctrl/starfive/Makefile | 1 + .../starfive/pinctrl-starfive-jhb100-per2.c | 136 ++++++++++++++++++ 3 files changed, 148 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2.c diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index 823062be6d9f..0c55d712c2e8 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -78,6 +78,17 @@ config PINCTRL_STARFIVE_JHB100_PER1 peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. +config PINCTRL_STARFIVE_JHB100_PER2 + tristate "StarFive JHB100 SoC Peripheral-2 pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + select PINCTRL_STARFIVE_JHB100 + default ARCH_STARFIVE + help + Say yes here to support Peripheral-2 pin control on the StarFive JHB100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. + config PINCTRL_STARFIVE_JHB100_SYS0 tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver" depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index 6beef7e313ef..33213bd1919f 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o +obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2) += pinctrl-starfive-jhb100-per2.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2.c new file mode 100644 index 000000000000..282266a127c7 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-2 domain + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include + +#include "pinctrl-starfive-jhb100.h" + +/* per2 pad numbers */ +#define PADNUM_PER2_GPIO_D19 19 +#define PADNUM_PER2_GPIO_D20 20 +#define PADNUM_PER2_GPIO_D21 21 +#define PADNUM_PER2_GPIO_D22 22 +#define PADNUM_PER2_GPIO_D23 23 +#define PADNUM_PER2_GPIO_D24 24 +#define PADNUM_PER2_GPIO_D25 25 +#define PADNUM_PER2_GPIO_D26 26 +#define PADNUM_PER2_GPIO_D27 27 +#define PADNUM_PER2_GPIO_D28 28 +#define PADNUM_PER2_GPIO_D29 29 +#define PADNUM_PER2_GPIO_D30 30 + +static const struct jhb100_pin_layout_desc jhb100_per2_pl_desc[] = { + { .pin_start = 0, .pin_cnt = 15, .name = "gpio", .gpio_func_sel = 0 }, + { .pin_start = 15, .pin_cnt = 1, .name = "gpio", .gpio_func_sel = -1 }, + { .pin_start = 16, .pin_cnt = 15, .name = "gpio", .gpio_func_sel = 0 }, + { 0xff }, +}; + +static const struct config_reg_layout_desc jhb100_per2_pinctrl_rl_desc[] = { + { + .pin_start = 0, + .pin_cnt = 19, + .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 }, + .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 }, + .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 }, + .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 }, + .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 }, + .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 }, + .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 }, + }, + { + .pin_start = 19, + .pin_cnt = 12, + .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 0, .width = 1 }, + .fields[PAD_CFG_SLEW_RATE] = { .shift = 1, .width = 1 }, + .fields[PAD_CFG_VSEL] = { .shift = 2, .width = 2 }, + .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 }, + }, + { 0xff }, +}; + +static const struct pinvref_desc pinvref_desc_per2[] = { + { + /* gpionw */ + .pin_grp = { + PADNUM_PER2_GPIO_D19, + PADNUM_PER2_GPIO_D20, + PADNUM_PER2_GPIO_D21, + PADNUM_PER2_GPIO_D22, + PADNUM_PER2_GPIO_D23, + PADNUM_PER2_GPIO_D24, + PADNUM_PER2_GPIO_D25, + PADNUM_PER2_GPIO_D26, + PADNUM_PER2_GPIO_D27, + PADNUM_PER2_GPIO_D28, + PADNUM_PER2_GPIO_D29, + PADNUM_PER2_GPIO_D30 + }, + .num_pins = 12, + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_2_5V) | + BIT(JHB100_PINVREF_3_3V) + }, +}; + +static const struct starfive_pinctrl_regs jhb100_per2_pinctrl_regs = { + .vref = { .reg = 0x00, .pv_desc = pinvref_desc_per2, + .num_pv = ARRAY_SIZE(pinvref_desc_per2) }, + .func_sel = { .reg = 0x8c, .width_per_pin = 2 }, + .config = 0x04, + .output = 0x80, + .output_en = 0x84, + .gpio_status = 0x88, + .irq_en = 0x94, + .irq_status = 0x98, + .irq_clr = 0x9c, + .irq_trigger = 0xa0, + .irq_level = 0xa4, + .irq_both_edge = 0xa8, + .irq_edge = 0xac, +}; + +static const struct jhb100_pinctrl_func_maps jhb100_func_maps_per2[] = { + { .func = "fan_tach", .val = 1 }, + { .func = "gmac_rgmii", .val = 1 }, + { .func = "gmac_rmii", .val = 2 }, + { .func = "gpio", .val = 0 }, + { .func = "host0_port80", .val = 2 }, + { .func = "host1_port80", .val = 3 }, +}; + +static const struct jhb100_pinctrl_domain_info jhb100_per2_pinctrl_info = { + .name = "jhb100-per2", + .pl_desc = jhb100_per2_pl_desc, + .crl_desc = jhb100_per2_pinctrl_rl_desc, + .regs = &jhb100_per2_pinctrl_regs, + .fmaps = jhb100_func_maps_per2, + .num_maps = ARRAY_SIZE(jhb100_func_maps_per2), +}; + +static const struct of_device_id jhb100_per2_pinctrl_of_match[] = { + { + .compatible = "starfive,jhb100-per2-pinctrl", + .data = &jhb100_per2_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jhb100_per2_pinctrl_of_match); + +static struct platform_driver jhb100_per2_pinctrl_driver = { + .probe = jhb100_pinctrl_probe, + .driver = { + .name = "starfive-jhb100-per2-pinctrl", + .of_match_table = jhb100_per2_pinctrl_of_match, + }, +}; +module_platform_driver(jhb100_per2_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-2 domain"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL"); From c9ed9daba98a5c1f1fd658b8c38b4dfb160f83cf Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:52 -0700 Subject: [PATCH 072/106] dt-bindings: pinctrl: Add starfive,jhb100-per2pok-pinctrl Add pinctrl bindings for StarFive JHB100 SoC Peripheral-2 Power OK (per2pok) pinctrl controller. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../starfive,jhb100-per2pok-pinctrl.yaml | 162 ++++++++++++++++++ 1 file changed, 162 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml new file mode 100644 index 000000000000..28a4d7f30cc9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 Peripheral-2 Power OK Pin Controller + +description: | + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd. + + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1, + per2, per2pok, per3, adc0, adc1, emmc, and vga. + This document provides an overview of the "per2pok" pinctrl domain. + + The "per2pok" domain has a pin controller which provides + - function selection for GPIO pads. + - GPIO interrupt handling. + + In the Peripheral-2 Power OK Pin Controller, there are 18 multi-function + GPIO_PADs. Each can be multiplexed to several peripherals through function + selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3. + Function 0 is the default function or generally the GPIO function. + Function 1, 2, and 3 are alternate functions or peripheral signals that can + be routed to an iopad. The function selection can be carried out by writing + the function number to the iopad function select register. + + Each iopad is configurable with parameters such as input-enable, internal + pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input + debounce nanoseconds. + +maintainers: + - Changhuang Liang + +properties: + compatible: + items: + - const: starfive,jhb100-per2pok-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + function selection, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate, input debounce nanoseconds + and drive-strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. + enum: [ can, gpio, host0_port80, host1_port80, passthru, pwm ] + + bias-disable: true + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-debounce-ns: + minimum: 0 + maximum: 10485680 + description: + Debounce time in nanoseconds. The hardware counts in 80 ns + stages with a 17-bit counter, so the maximum is 10485680 ns. + + input-disable: true + + input-enable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow + 1: fast + +required: + - compatible + - reg + - resets + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_per2pok: pinctrl@11bc2400 { + compatible = "starfive,jhb100-per2pok-pinctrl"; + reg = <0x0 0x11bc2400 0x0 0x400>; + resets = <&per2crg 1>; + interrupts = <63>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_per2pok 0 0 18>; + }; + }; From c12e9b3e390065f0c2b31bf95bb46fdcac93c01c Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:53 -0700 Subject: [PATCH 073/106] pinctrl: starfive: Add StarFive JHB100 per2pok controller driver Add pinctrl driver for StarFive JHB100 SoC Peripheral-2 Power OK (per2pok) pinctrl controller. Co-developed-by: Lianfeng Ouyang Signed-off-by: Lianfeng Ouyang Signed-off-by: Alex Soo Signed-off-by: Changhuang Liang Signed-off-by: Linus Walleij --- drivers/pinctrl/starfive/Kconfig | 11 +++ drivers/pinctrl/starfive/Makefile | 1 + .../pinctrl-starfive-jhb100-per2pok.c | 99 +++++++++++++++++++ 3 files changed, 111 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2pok.c diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index 0c55d712c2e8..426be481a3fb 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -89,6 +89,17 @@ config PINCTRL_STARFIVE_JHB100_PER2 peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. +config PINCTRL_STARFIVE_JHB100_PER2POK + tristate "StarFive JHB100 SoC Peripheral-2 Power OK pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + select PINCTRL_STARFIVE_JHB100 + default ARCH_STARFIVE + help + Say yes here to support Peripheral-2 Power OK pin control on the StarFive JHB100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. + config PINCTRL_STARFIVE_JHB100_SYS0 tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver" depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index 33213bd1919f..213002da9cdd 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2) += pinctrl-starfive-jhb100-per2.o +obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2POK) += pinctrl-starfive-jhb100-per2pok.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2pok.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2pok.c new file mode 100644 index 000000000000..6bb3b47e65f0 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2pok.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-2 Power OK domain + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include + +#include "pinctrl-starfive-jhb100.h" + +/* per2pok pad numbers */ +#define PADNUM_PER2POK_GPIO_D36 5 +#define PADNUM_PER2POK_GPIO_D40 9 +#define PADNUM_PER2POK_GPIO_D48 17 + +static const struct jhb100_pin_layout_desc jhb100_per2pok_pl_desc[] = { + { .pin_start = 0, .pin_cnt = 10, .name = "gpio", .gpio_func_sel = 0 }, + { .pin_start = 10, .pin_cnt = 8, .name = "pwm_channel", .gpio_func_sel = 1 }, + { 0xff }, +}; + +static const struct config_reg_layout_desc jhb100_per2pok_pinctrl_rl_desc[] = { + { + .pin_start = 0, + .pin_cnt = 18, + .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 }, + .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 }, + .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 }, + .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 }, + .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 }, + .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 }, + .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 }, + }, + { 0xff }, +}; + +static const struct starfive_pinctrl_regs jhb100_per2pok_pinctrl_regs = { + .func_sel = { .reg = 0x58, .width_per_pin = 2 }, + .config = 0x04, + .output = 0x4c, + .output_en = 0x50, + .gpio_status = 0x54, + .irq_en = 0x60, + .irq_status = 0x64, + .irq_clr = 0x68, + .irq_trigger = 0x6c, + .irq_level = 0x70, + .irq_both_edge = 0x74, + .irq_edge = 0x78, +}; + +static const struct jhb100_pinctrl_func_maps jhb100_func_maps_per2pok[] = { + { .func = "can", .val = 1 }, + { .func = "gpio", .val = 0, + .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER2POK_GPIO_D40) }, + { .func = "gpio", .val = 1, + .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER2POK_GPIO_D48) }, + { .func = "host0_port80", .val = 2 }, + { .func = "host1_port80", .val = 3 }, + { .func = "passthru", .val = 2, + .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER2POK_GPIO_D36) }, + { .func = "passthru", .val = 1, + .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER2POK_GPIO_D40) }, + { .func = "pwm", .val = 0 }, +}; + +static const struct jhb100_pinctrl_domain_info jhb100_per2pok_pinctrl_info = { + .name = "jhb100-per2pok", + .pl_desc = jhb100_per2pok_pl_desc, + .crl_desc = jhb100_per2pok_pinctrl_rl_desc, + .regs = &jhb100_per2pok_pinctrl_regs, + .fmaps = jhb100_func_maps_per2pok, + .num_maps = ARRAY_SIZE(jhb100_func_maps_per2pok), +}; + +static const struct of_device_id jhb100_per2pok_pinctrl_of_match[] = { + { + .compatible = "starfive,jhb100-per2pok-pinctrl", + .data = &jhb100_per2pok_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jhb100_per2pok_pinctrl_of_match); + +static struct platform_driver jhb100_per2pok_pinctrl_driver = { + .probe = jhb100_pinctrl_probe, + .driver = { + .name = "starfive-jhb100-per2pok-pinctrl", + .of_match_table = jhb100_per2pok_pinctrl_of_match, + }, +}; +module_platform_driver(jhb100_per2pok_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-2 Power OK domain"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL"); From 340588f9b94c9015ade9c64bfa5eab5b44f3172e Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:54 -0700 Subject: [PATCH 074/106] dt-bindings: pinctrl: Add starfive,jhb100-per3-pinctrl Add pinctrl bindings for StarFive JHB100 SoC Peripheral-3(per3) pinctrl controller. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../pinctrl/starfive,jhb100-per3-pinctrl.yaml | 166 ++++++++++++++++++ 1 file changed, 166 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml new file mode 100644 index 000000000000..92093315ef15 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per3-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 Peripheral-3 Pin Controller + +description: | + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd. + + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1, + per2, per2pok, per3, adc0, adc1, emmc, and vga. + This document provides an overview of the "per3" pinctrl domain. + + The "per3" domain has a pin controller which provides + - function selection for GPIO pads. + - GPIO interrupt handling. + + In the Peripheral-3 Pin Controller, there are 11 multi-function GPIO_PADs. + Each of them can be multiplexed to several peripherals through function + selection. Each iopad has a maximum of up to 2 functions - 0 and 1. + Function 0 is the default function which is generally the GPIO function. + Function 1 is the alternate function or peripheral signal that can be + routed to an iopad. The function selection can be carried out by writing + the function number to the iopad function select register. + + Each iopad is configurable with parameters such as input-enable, internal + pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input + debounce nanoseconds, power source. + +maintainers: + - Changhuang Liang + +properties: + compatible: + items: + - const: starfive,jhb100-per3-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + function selection, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate, input debounce nanoseconds, + power-source and drive-strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. + enum: [ gmac_mdio, gmac_rmii, gpio ] + + bias-disable: true + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-debounce-ns: + minimum: 0 + maximum: 10485680 + description: + Debounce time in nanoseconds. The hardware counts in 80 ns + stages with a 17-bit counter, so the maximum is 10485680 ns. + + input-disable: true + + input-enable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + power-source: + enum: [ 1800, 2500, 3300 ] + description: I/O voltage in millivolt. + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow + 1: fast + +required: + - compatible + - reg + - resets + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_per3: pinctrl@11c42000 { + compatible = "starfive,jhb100-per3-pinctrl"; + reg = <0x0 0x11c42000 0x0 0x1000>; + resets = <&per3crg 6>; + interrupts = <64>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_per3 0 0 11>; + }; + }; From 1bb38968b936eec9d25ed904f137555951b323c3 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Thu, 10 Sep 2026 03:03:55 -0700 Subject: [PATCH 075/106] pinctrl: starfive: Add StarFive JHB100 per3 controller driver Add pinctrl driver for StarFive JHB100 SoC Peripheral-3(per3) pinctrl controller. Co-developed-by: Lianfeng Ouyang Signed-off-by: Lianfeng Ouyang Signed-off-by: Alex Soo Signed-off-by: Changhuang Liang Signed-off-by: Linus Walleij --- drivers/pinctrl/starfive/Kconfig | 11 ++ drivers/pinctrl/starfive/Makefile | 1 + .../starfive/pinctrl-starfive-jhb100-per3.c | 129 ++++++++++++++++++ 3 files changed, 141 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per3.c diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index 426be481a3fb..11bd429b45b7 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -100,6 +100,17 @@ config PINCTRL_STARFIVE_JHB100_PER2POK peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. +config PINCTRL_STARFIVE_JHB100_PER3 + tristate "StarFive JHB100 SoC Peripheral-3 pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + select PINCTRL_STARFIVE_JHB100 + default ARCH_STARFIVE + help + Say yes here to support Peripheral-3 pin control on the StarFive JHB100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. + config PINCTRL_STARFIVE_JHB100_SYS0 tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver" depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index 213002da9cdd..351fce524fec 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2) += pinctrl-starfive-jhb100-per2.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2POK) += pinctrl-starfive-jhb100-per2pok.o +obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER3) += pinctrl-starfive-jhb100-per3.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per3.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per3.c new file mode 100644 index 000000000000..24158d90f75d --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per3.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-3 domain + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include + +#include "pinctrl-starfive-jhb100.h" + +/* per3 pad numbers */ +#define PADNUM_PER3_GPIO_E0 0 +#define PADNUM_PER3_GPIO_E1 1 +#define PADNUM_PER3_GPIO_E2 2 +#define PADNUM_PER3_GPIO_E3 3 +#define PADNUM_PER3_GPIO_E4 4 +#define PADNUM_PER3_GPIO_E5 5 +#define PADNUM_PER3_GPIO_E6 6 +#define PADNUM_PER3_GPIO_E7 7 +#define PADNUM_PER3_GPIO_E8 8 +#define PADNUM_PER3_GPIO_E9 9 +#define PADNUM_PER3_GPIO_E10 10 + +static const struct jhb100_pin_layout_desc jhb100_per3_pl_desc[] = { + { .pin_start = 0, .pin_cnt = 11, .name = "gpio", .gpio_func_sel = 0 }, + { 0xff }, +}; + +static const struct config_reg_layout_desc jhb100_per3_pinctrl_rl_desc[] = { + { + .pin_start = 0, + .pin_cnt = 2, + .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 }, + .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 }, + .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 }, + .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 }, + .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 }, + .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 }, + .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 }, + }, + { + .pin_start = 2, + .pin_cnt = 9, + .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 0, .width = 1 }, + .fields[PAD_CFG_SLEW_RATE] = { .shift = 1, .width = 1 }, + .fields[PAD_CFG_VSEL] = { .shift = 2, .width = 2 }, + .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 }, + }, + { 0xff }, +}; + +static const struct pinvref_desc pinvref_desc_per3[] = { + { + /* gpios */ + .pin_grp = { + PADNUM_PER3_GPIO_E0, + PADNUM_PER3_GPIO_E1, + PADNUM_PER3_GPIO_E2, + PADNUM_PER3_GPIO_E3, + PADNUM_PER3_GPIO_E4, + PADNUM_PER3_GPIO_E5, + PADNUM_PER3_GPIO_E6, + PADNUM_PER3_GPIO_E7, + PADNUM_PER3_GPIO_E8, + PADNUM_PER3_GPIO_E9, + PADNUM_PER3_GPIO_E10 + }, + .num_pins = 11, + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_2_5V) | + BIT(JHB100_PINVREF_3_3V) + }, +}; + +static const struct starfive_pinctrl_regs jhb100_per3_pinctrl_regs = { + .vref = { .reg = 0x00, .pv_desc = pinvref_desc_per3, + .num_pv = ARRAY_SIZE(pinvref_desc_per3) }, + .func_sel = { .reg = 0x3c, .width_per_pin = 2 }, + .config = 0x04, + .output = 0x30, + .output_en = 0x34, + .gpio_status = 0x38, + .irq_en = 0x40, + .irq_status = 0x44, + .irq_clr = 0x48, + .irq_trigger = 0x4c, + .irq_level = 0x50, + .irq_both_edge = 0x54, + .irq_edge = 0x58, +}; + +static const struct jhb100_pinctrl_func_maps jhb100_func_maps_per3[] = { + { .func = "gmac_mdio", .val = 1 }, + { .func = "gmac_rmii", .val = 1 }, + { .func = "gpio", .val = 0 }, +}; + +static const struct jhb100_pinctrl_domain_info jhb100_per3_pinctrl_info = { + .name = "jhb100-per3", + .pl_desc = jhb100_per3_pl_desc, + .crl_desc = jhb100_per3_pinctrl_rl_desc, + .regs = &jhb100_per3_pinctrl_regs, + .fmaps = jhb100_func_maps_per3, + .num_maps = ARRAY_SIZE(jhb100_func_maps_per3), +}; + +static const struct of_device_id jhb100_per3_pinctrl_of_match[] = { + { + .compatible = "starfive,jhb100-per3-pinctrl", + .data = &jhb100_per3_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jhb100_per3_pinctrl_of_match); + +static struct platform_driver jhb100_per3_pinctrl_driver = { + .probe = jhb100_pinctrl_probe, + .driver = { + .name = "starfive-jhb100-per3-pinctrl", + .of_match_table = jhb100_per3_pinctrl_of_match, + }, +}; +module_platform_driver(jhb100_per3_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-3 domain"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL"); From 49d304b41cd45f0f825a9e6e6750eec3d7f332aa Mon Sep 17 00:00:00 2001 From: Basavaraj Natikar Date: Mon, 21 Sep 2026 10:57:43 +0530 Subject: [PATCH 076/106] pinctrl: amd: Centralize per-pin register access Add a helper to translate a pin into its per-pin register address and use it at every per-pin access, so a second GPIO bank added later can be addressed from a single place. No functional change. Signed-off-by: Basavaraj Natikar Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-amd.c | 85 ++++++++++++++++++----------------- 1 file changed, 44 insertions(+), 41 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 65728b590999..543733c2aae0 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -40,6 +40,11 @@ static struct amd_gpio *pinctrl_dev; #endif +static inline void __iomem *amd_gpio_pin_reg(struct amd_gpio *gpio_dev, unsigned int pin) +{ + return gpio_dev->base + pin * 4; +} + static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) { unsigned long flags; @@ -47,7 +52,7 @@ static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) struct amd_gpio *gpio_dev = gpiochip_get_data(gc); raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + offset * 4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) @@ -63,9 +68,9 @@ static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) struct amd_gpio *gpio_dev = gpiochip_get_data(gc); raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + offset * 4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset)); pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); - writel(pin_reg, gpio_dev->base + offset * 4); + writel(pin_reg, amd_gpio_pin_reg(gpio_dev, offset)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); return 0; @@ -79,13 +84,13 @@ static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, struct amd_gpio *gpio_dev = gpiochip_get_data(gc); raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + offset * 4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset)); pin_reg |= BIT(OUTPUT_ENABLE_OFF); if (value) pin_reg |= BIT(OUTPUT_VALUE_OFF); else pin_reg &= ~BIT(OUTPUT_VALUE_OFF); - writel(pin_reg, gpio_dev->base + offset * 4); + writel(pin_reg, amd_gpio_pin_reg(gpio_dev, offset)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); return 0; @@ -98,7 +103,7 @@ static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) struct amd_gpio *gpio_dev = gpiochip_get_data(gc); raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + offset * 4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); return !!(pin_reg & BIT(PIN_STS_OFF)); @@ -112,12 +117,12 @@ static int amd_gpio_set_value(struct gpio_chip *gc, unsigned int offset, struct amd_gpio *gpio_dev = gpiochip_get_data(gc); raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + offset * 4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset)); if (value) pin_reg |= BIT(OUTPUT_VALUE_OFF); else pin_reg &= ~BIT(OUTPUT_VALUE_OFF); - writel(pin_reg, gpio_dev->base + offset * 4); + writel(pin_reg, amd_gpio_pin_reg(gpio_dev, offset)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); return 0; @@ -137,7 +142,7 @@ static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset, debounce = 0; } - pin_reg = readl(gpio_dev->base + offset * 4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset)); if (debounce) { pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; @@ -186,7 +191,7 @@ static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset, pin_reg &= ~DB_TMR_OUT_MASK; pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); } - writel(pin_reg, gpio_dev->base + offset * 4); + writel(pin_reg, amd_gpio_pin_reg(gpio_dev, offset)); return ret; } @@ -248,7 +253,7 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) for (; i < pin_num; i++) { seq_printf(s, "#%d\t", i); raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + i * 4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, i)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { @@ -387,10 +392,10 @@ static void amd_gpio_irq_enable(struct irq_data *d) gpiochip_enable_irq(gc, hwirq); raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + hwirq * 4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq)); pin_reg |= BIT(INTERRUPT_ENABLE_OFF); pin_reg |= BIT(INTERRUPT_MASK_OFF); - writel(pin_reg, gpio_dev->base + hwirq * 4); + writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } @@ -403,10 +408,10 @@ static void amd_gpio_irq_disable(struct irq_data *d) irq_hw_number_t hwirq = irqd_to_hwirq(d); raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + hwirq * 4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq)); pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); pin_reg &= ~BIT(INTERRUPT_MASK_OFF); - writel(pin_reg, gpio_dev->base + hwirq * 4); + writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); gpiochip_disable_irq(gc, hwirq); @@ -421,9 +426,9 @@ static void amd_gpio_irq_mask(struct irq_data *d) irq_hw_number_t hwirq = irqd_to_hwirq(d); raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + hwirq * 4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq)); pin_reg &= ~BIT(INTERRUPT_MASK_OFF); - writel(pin_reg, gpio_dev->base + hwirq * 4); + writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } @@ -436,9 +441,9 @@ static void amd_gpio_irq_unmask(struct irq_data *d) irq_hw_number_t hwirq = irqd_to_hwirq(d); raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + hwirq * 4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq)); pin_reg |= BIT(INTERRUPT_MASK_OFF); - writel(pin_reg, gpio_dev->base + hwirq * 4); + writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } @@ -456,14 +461,14 @@ static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) hwirq, str_enable_disable(on)); raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + hwirq * 4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq)); if (on) pin_reg |= wake_mask; else pin_reg &= ~wake_mask; - writel(pin_reg, gpio_dev->base + hwirq * 4); + writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); if (on) @@ -502,7 +507,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) irq_hw_number_t hwirq = irqd_to_hwirq(d); raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + hwirq * 4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq)); switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_RISING: @@ -568,11 +573,11 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) pin_reg_irq_en = pin_reg; pin_reg_irq_en |= mask; pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); - writel(pin_reg_irq_en, gpio_dev->base + hwirq * 4); - if (readl_poll_timeout_atomic(gpio_dev->base + hwirq * 4, reg, + writel(pin_reg_irq_en, amd_gpio_pin_reg(gpio_dev, hwirq)); + if (readl_poll_timeout_atomic(amd_gpio_pin_reg(gpio_dev, hwirq), reg, (reg & mask) == mask, 1, 1000)) ret = -ETIMEDOUT; - writel(pin_reg, gpio_dev->base + hwirq * 4); + writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); return ret; @@ -615,7 +620,6 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id) struct gpio_chip *gc = &gpio_dev->gc; unsigned int i, irqnr; unsigned long flags; - u32 __iomem *regs; bool ret = false; u32 regval; u64 status, mask; @@ -629,15 +633,14 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id) /* Bit 0-45 contain the relevant status bits */ status &= (1ULL << 46) - 1; - regs = gpio_dev->base; - for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { + for (mask = 1, irqnr = 0; status; mask <<= 1, irqnr += 4) { if (!(status & mask)) continue; status &= ~mask; /* Each status bit covers four pins */ for (i = 0; i < 4; i++) { - regval = readl(regs + i); + regval = readl(amd_gpio_pin_reg(gpio_dev, irqnr + i)); if (regval & PIN_IRQ_PENDING) pm_pr_dbg("GPIO %d is active: 0x%x", @@ -660,7 +663,7 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id) * avoid a system hang caused by an interrupt storm. */ raw_spin_lock_irqsave(&gpio_dev->lock, flags); - regval = readl(regs + i); + regval = readl(amd_gpio_pin_reg(gpio_dev, irqnr + i)); if (!gpiochip_line_is_irq(gc, irqnr + i)) { regval &= ~BIT(INTERRUPT_MASK_OFF); dev_dbg(&gpio_dev->pdev->dev, @@ -669,7 +672,7 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id) } else { ret = true; } - writel(regval, regs + i); + writel(regval, amd_gpio_pin_reg(gpio_dev, irqnr + i)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } } @@ -745,7 +748,7 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev, enum pin_config_param param = pinconf_to_config_param(*config); raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + pin*4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, pin)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); switch (param) { case PIN_CONFIG_INPUT_DEBOUNCE: @@ -790,7 +793,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, for (i = 0; i < num_configs; i++) { param = pinconf_to_config_param(configs[i]); arg = pinconf_to_config_argument(configs[i]); - pin_reg = readl(gpio_dev->base + pin*4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, pin)); switch (param) { case PIN_CONFIG_INPUT_DEBOUNCE: @@ -820,7 +823,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, ret = -ENOTSUPP; } - writel(pin_reg, gpio_dev->base + pin*4); + writel(pin_reg, amd_gpio_pin_reg(gpio_dev, pin)); } out_unlock: raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); @@ -897,9 +900,9 @@ static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + pin * 4); + pin_reg = readl(amd_gpio_pin_reg(gpio_dev, pin)); pin_reg &= ~mask; - writel(pin_reg, gpio_dev->base + pin * 4); + writel(pin_reg, amd_gpio_pin_reg(gpio_dev, pin)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } @@ -919,7 +922,7 @@ static void amd_gpio_check_pending(void) int pin = desc->pins[i].number; u32 tmp; - tmp = readl(gpio_dev->base + pin * 4); + tmp = readl(amd_gpio_pin_reg(gpio_dev, pin)); if (tmp & PIN_IRQ_PENDING) pm_pr_dbg("%s: GPIO %d is active: 0x%x.\n", __func__, pin, tmp); } @@ -977,12 +980,12 @@ static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend continue; raw_spin_lock_irqsave(&gpio_dev->lock, flags); - gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING; + gpio_dev->saved_regs[i] = readl(amd_gpio_pin_reg(gpio_dev, pin)) & ~PIN_IRQ_PENDING; /* mask any interrupts not intended to be a wake source */ if (!(gpio_dev->saved_regs[i] & wake_mask)) { writel(gpio_dev->saved_regs[i] & ~BIT(INTERRUPT_MASK_OFF), - gpio_dev->base + pin * 4); + amd_gpio_pin_reg(gpio_dev, pin)); pm_pr_dbg("Disabling GPIO #%d interrupt for %s.\n", pin, is_suspend ? "suspend" : "hibernate"); } @@ -1031,8 +1034,8 @@ static int amd_gpio_resume(struct device *dev) continue; raw_spin_lock_irqsave(&gpio_dev->lock, flags); - gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; - writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4); + gpio_dev->saved_regs[i] |= readl(amd_gpio_pin_reg(gpio_dev, pin)) & PIN_IRQ_PENDING; + writel(gpio_dev->saved_regs[i], amd_gpio_pin_reg(gpio_dev, pin)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } From 319955f5f8fd22e7f8934a4a62e0ddcc4a8cd6ed Mon Sep 17 00:00:00 2001 From: Basavaraj Natikar Date: Mon, 21 Sep 2026 10:57:44 +0530 Subject: [PATCH 077/106] pinctrl: amd: Factor out optional named resource lookup The optional iomux resource is looked up by name. A following patch needs the same lookup for another optional resource, along with a minimum size check. Factor it out into a helper that also rejects a resource smaller than a caller-supplied size. No functional change for iomux. Signed-off-by: Basavaraj Natikar Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-amd.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 543733c2aae0..18fce75fe86c 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -1137,28 +1137,31 @@ static struct pinctrl_desc amd_pinctrl_desc = { .owner = THIS_MODULE, }; -static void amd_get_iomux_res(struct amd_gpio *gpio_dev) +static void __iomem *amd_get_named_res(struct device *dev, struct platform_device *pdev, + const char *name, resource_size_t minsz) { - struct pinctrl_desc *desc = &amd_pinctrl_desc; - struct device *dev = &gpio_dev->pdev->dev; + struct resource *res; + void __iomem *base; int index; - index = device_property_match_string(dev, "pinctrl-resource-names", "iomux"); + index = device_property_match_string(dev, "pinctrl-resource-names", name); if (index < 0) { - dev_dbg(dev, "iomux not supported\n"); - goto out_no_pinmux; + dev_dbg(dev, "%s not supported\n", name); + return NULL; } - gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index); - if (IS_ERR(gpio_dev->iomux_base)) { - dev_dbg(dev, "iomux not supported %d io resource\n", index); - goto out_no_pinmux; + base = devm_platform_get_and_ioremap_resource(pdev, index, &res); + if (IS_ERR(base)) { + dev_dbg(dev, "%s not supported %d io resource\n", name, index); + return NULL; } - return; + if (resource_size(res) < minsz) { + dev_err(dev, "%s resource too small\n", name); + return NULL; + } -out_no_pinmux: - desc->pmxops = NULL; + return base; } static int amd_gpio_probe(struct platform_device *pdev) @@ -1213,7 +1216,9 @@ static int amd_gpio_probe(struct platform_device *pdev) gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); amd_pinctrl_desc.name = dev_name(&pdev->dev); - amd_get_iomux_res(gpio_dev); + gpio_dev->iomux_base = amd_get_named_res(&pdev->dev, pdev, "iomux", 0); + if (!gpio_dev->iomux_base) + amd_pinctrl_desc.pmxops = NULL; gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, gpio_dev); if (IS_ERR(gpio_dev->pctrl)) { From 46aa97128fc49eb5e4d1125c087c0d2b576c40ab Mon Sep 17 00:00:00 2001 From: Basavaraj Natikar Date: Mon, 21 Sep 2026 10:57:45 +0530 Subject: [PATCH 078/106] pinctrl: amd: Add support for the Remote GPIO (RGPIO) bank Some AMD platforms expose a second GPIO bank, Remote GPIO (RGPIO), covering pins 256-271 through a separate register region advertised by name. Add support for these pins, including their interrupts, when the region is advertised and the main bank spans the expected number of registers, so they are usable like the main bank pins. The RGPIO pins stay inactive on platforms that do not expose the region. Co-developed-by: Matt DeVillier Signed-off-by: Matt DeVillier Co-developed-by: Guruvendra Punugupati Signed-off-by: Guruvendra Punugupati Signed-off-by: Basavaraj Natikar Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-amd.c | 121 ++++++++++++++++++++++- drivers/pinctrl/pinctrl-amd.h | 174 ++++++++++++++++++++++++++++++++++ 2 files changed, 292 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 18fce75fe86c..e8b9a8e57149 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -42,6 +42,8 @@ static struct amd_gpio *pinctrl_dev; static inline void __iomem *amd_gpio_pin_reg(struct amd_gpio *gpio_dev, unsigned int pin) { + if (gpio_dev->base_rgpio && pin >= AMD_GPIO_RGPIO_PIN_BASE) + return gpio_dev->base_rgpio + (pin - AMD_GPIO_RGPIO_PIN_BASE) * 4; return gpio_dev->base + pin * 4; } @@ -244,6 +246,10 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) i = 192; pin_num = AMD_GPIO_PINS_BANK3 + i; break; + case 4: + i = AMD_GPIO_RGPIO_PIN_BASE; + pin_num = AMD_GPIO_PINS_BANK4 + i; + break; default: /* Illegal bank number, ignore */ continue; @@ -676,6 +682,58 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } } + + /* + * Unlike WAKE_INT_STATUS_REG0/1, where each status bit covers four + * pins, the RGPIO status register uses one bit per pin. As with the + * main bank status registers, a bit is cleared by acknowledging the + * pending interrupt on its pin below (clearing PIN_IRQ_PENDING); no + * separate write to the RGPIO status register is required. + */ + if (gpio_dev->base_rgpio) { + u32 status_rgpio; + + raw_spin_lock_irqsave(&gpio_dev->lock, flags); + status_rgpio = readl(gpio_dev->base_rgpio + WAKE_INT_STATUS_REG_RGPIO); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); + + status_rgpio &= GENMASK(AMD_GPIO_PINS_BANK4 - 1, 0); + + for (i = 0; i < AMD_GPIO_PINS_BANK4; i++) { + unsigned int pin = AMD_GPIO_RGPIO_PIN_BASE + i; + + if (!(status_rgpio & BIT(i))) + continue; + + regval = readl(amd_gpio_pin_reg(gpio_dev, pin)); + + if (regval & PIN_IRQ_PENDING) + pm_pr_dbg("GPIO %d is active: 0x%x", pin, regval); + + /* caused wake on resume context for shared IRQ */ + if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) + return true; + + if (!(regval & PIN_IRQ_PENDING) || + !(regval & BIT(INTERRUPT_MASK_OFF))) + continue; + generic_handle_domain_irq_safe(gc->irq.domain, pin); + + raw_spin_lock_irqsave(&gpio_dev->lock, flags); + regval = readl(amd_gpio_pin_reg(gpio_dev, pin)); + if (!gpiochip_line_is_irq(gc, pin)) { + regval &= ~BIT(INTERRUPT_MASK_OFF); + dev_dbg(&gpio_dev->pdev->dev, + "Disabling spurious GPIO IRQ %d\n", + pin); + } else { + ret = true; + } + writel(regval, amd_gpio_pin_reg(gpio_dev, pin)); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); + } + } + /* did not cause wake on resume context for shared IRQ */ if (irq < 0) return false; @@ -747,6 +805,9 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev, struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param = pinconf_to_config_param(*config); + if (pin >= AMD_GPIO_RGPIO_PIN_BASE && !gpio_dev->base_rgpio) + return -EOPNOTSUPP; + raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(amd_gpio_pin_reg(gpio_dev, pin)); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); @@ -789,6 +850,9 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, enum pin_config_param param; struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); + if (pin >= AMD_GPIO_RGPIO_PIN_BASE && !gpio_dev->base_rgpio) + return -EOPNOTSUPP; + raw_spin_lock_irqsave(&gpio_dev->lock, flags); for (i = 0; i < num_configs; i++) { param = pinconf_to_config_param(configs[i]); @@ -898,6 +962,9 @@ static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) if (!pd) continue; + if (pin >= AMD_GPIO_RGPIO_PIN_BASE && !gpio_dev->base_rgpio) + continue; + raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(amd_gpio_pin_reg(gpio_dev, pin)); @@ -922,6 +989,9 @@ static void amd_gpio_check_pending(void) int pin = desc->pins[i].number; u32 tmp; + if (pin >= AMD_GPIO_RGPIO_PIN_BASE && !gpio_dev->base_rgpio) + continue; + tmp = readl(amd_gpio_pin_reg(gpio_dev, pin)); if (tmp & PIN_IRQ_PENDING) pm_pr_dbg("%s: GPIO %d is active: 0x%x.\n", __func__, pin, tmp); @@ -1068,7 +1138,8 @@ static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector, { struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); - if (!gpio_dev->iomux_base) { + if (!gpio_dev->iomux_base && + pmx_functions[selector].index < AMD_GPIO_RGPIO_PIN_BASE) { dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector); return -EINVAL; } @@ -1084,6 +1155,34 @@ static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsi struct device *dev = &gpio_dev->pdev->dev; struct pin_desc *pd; int ind, index; + unsigned int pin = gpio_dev->groups[group].pins[0]; + + if (pin >= AMD_GPIO_RGPIO_PIN_BASE) { + if (!gpio_dev->base_rgpio) + return -EINVAL; + + for (index = 0; index < NSELECTS; index++) + if (!strcmp(gpio_dev->groups[group].name, + pmx_functions[function].groups[index])) + break; + if (index >= NSELECTS) + return -EINVAL; + + writeb(index, gpio_dev->base_rgpio + AMD_GPIO_RGPIO_MUX_OFFSET + + (pin - AMD_GPIO_RGPIO_PIN_BASE)); + + if (index != (readb(gpio_dev->base_rgpio + AMD_GPIO_RGPIO_MUX_OFFSET + + (pin - AMD_GPIO_RGPIO_PIN_BASE)) & FUNCTION_MASK)) { + dev_err(dev, "RGPIO_GPIO %u mux not present or supported\n", pin); + return -EINVAL; + } + + for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) { + pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]); + pd->mux_owner = gpio_dev->groups[group].name; + } + return 0; + } if (!gpio_dev->iomux_base) return -EINVAL; @@ -1184,6 +1283,19 @@ static int amd_gpio_probe(struct platform_device *pdev) return PTR_ERR(gpio_dev->base); } + gpio_dev->base_rgpio = amd_get_named_res(&pdev->dev, pdev, "rgpio", + WAKE_INT_STATUS_REG_RGPIO + sizeof(u32)); + /* + * RGPIO pins are numbered from AMD_GPIO_RGPIO_PIN_BASE, so the main + * bank must span exactly that many register slots for the RGPIO pin + * numbering to line up. Disable RGPIO if the main bank is a different + * size. + */ + if (gpio_dev->base_rgpio && resource_size(res) / 4 != AMD_GPIO_RGPIO_PIN_BASE) { + dev_err(&pdev->dev, "unexpected GPIO bank size, disabling RGPIO\n"); + gpio_dev->base_rgpio = NULL; + } + gpio_dev->irq = platform_get_irq(pdev, 0); if (gpio_dev->irq < 0) return gpio_dev->irq; @@ -1210,14 +1322,17 @@ static int amd_gpio_probe(struct platform_device *pdev) gpio_dev->gc.owner = THIS_MODULE; gpio_dev->gc.parent = &pdev->dev; gpio_dev->gc.ngpio = resource_size(res) / 4; - gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; + if (gpio_dev->base_rgpio) { + gpio_dev->gc.ngpio += AMD_GPIO_PINS_BANK4; + gpio_dev->hwbank_num++; + } gpio_dev->groups = kerncz_groups; gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); amd_pinctrl_desc.name = dev_name(&pdev->dev); gpio_dev->iomux_base = amd_get_named_res(&pdev->dev, pdev, "iomux", 0); - if (!gpio_dev->iomux_base) + if (!gpio_dev->iomux_base && !gpio_dev->base_rgpio) amd_pinctrl_desc.pmxops = NULL; gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, gpio_dev); diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index 3a1e5bffaf6e..c602c4b648bd 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -15,6 +15,18 @@ #define AMD_GPIO_PINS_BANK1 64 #define AMD_GPIO_PINS_BANK2 56 #define AMD_GPIO_PINS_BANK3 32 +#define AMD_GPIO_PINS_BANK4 16 + +/* + * Remote GPIO (RGPIO) is a second GPIO bank on some AMD platforms. Firmware + * advertises its register region as an optional resource named "rgpio" (via + * the pinctrl-resource-names _DSD property). Relative to that region's base, + * RGPIO pin AMD_GPIO_RGPIO_PIN_BASE + n uses a per-pin control register at + * n * 4, a pinmux selector byte at AMD_GPIO_RGPIO_MUX_OFFSET + n, and one + * interrupt status bit (bit n) in WAKE_INT_STATUS_REG_RGPIO. + */ +#define AMD_GPIO_RGPIO_PIN_BASE 256 +#define AMD_GPIO_RGPIO_MUX_OFFSET 0xC0 #define WAKE_INT_MASTER_REG 0xfc #define INTERNAL_GPIO0_DEBOUNCE (1 << 15) @@ -22,6 +34,7 @@ #define WAKE_INT_STATUS_REG0 0x2f8 #define WAKE_INT_STATUS_REG1 0x2fc +#define WAKE_INT_STATUS_REG_RGPIO 0x0F4 #define DB_TMR_OUT_OFF 0 #define DB_TMR_OUT_UNIT_OFF 4 @@ -94,6 +107,7 @@ struct amd_function { struct amd_gpio { raw_spinlock_t lock; void __iomem *base; + void __iomem *base_rgpio; void __iomem *iomux_base; const struct pingroup *groups; @@ -292,6 +306,22 @@ static const struct pinctrl_pin_desc kerncz_pins[] = { PINCTRL_PIN(181, "GPIO_181"), PINCTRL_PIN(182, "GPIO_182"), PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(256, "GPIO_256"), + PINCTRL_PIN(257, "GPIO_257"), + PINCTRL_PIN(258, "GPIO_258"), + PINCTRL_PIN(259, "GPIO_259"), + PINCTRL_PIN(260, "GPIO_260"), + PINCTRL_PIN(261, "GPIO_261"), + PINCTRL_PIN(262, "GPIO_262"), + PINCTRL_PIN(263, "GPIO_263"), + PINCTRL_PIN(264, "GPIO_264"), + PINCTRL_PIN(265, "GPIO_265"), + PINCTRL_PIN(266, "GPIO_266"), + PINCTRL_PIN(267, "GPIO_267"), + PINCTRL_PIN(268, "GPIO_268"), + PINCTRL_PIN(269, "GPIO_269"), + PINCTRL_PIN(270, "GPIO_270"), + PINCTRL_PIN(271, "GPIO_271"), }; #define AMD_PINS(...) (const unsigned int []){__VA_ARGS__} @@ -873,6 +903,70 @@ enum amd_functions { IMX_F1_GPIO144, IMX_F2_GPIO144, IMX_F3_GPIO144, + IMX_F0_GPIO256, + IMX_F1_GPIO256, + IMX_F2_GPIO256, + IMX_F3_GPIO256, + IMX_F0_GPIO257, + IMX_F1_GPIO257, + IMX_F2_GPIO257, + IMX_F3_GPIO257, + IMX_F0_GPIO258, + IMX_F1_GPIO258, + IMX_F2_GPIO258, + IMX_F3_GPIO258, + IMX_F0_GPIO259, + IMX_F1_GPIO259, + IMX_F2_GPIO259, + IMX_F3_GPIO259, + IMX_F0_GPIO260, + IMX_F1_GPIO260, + IMX_F2_GPIO260, + IMX_F3_GPIO260, + IMX_F0_GPIO261, + IMX_F1_GPIO261, + IMX_F2_GPIO261, + IMX_F3_GPIO261, + IMX_F0_GPIO262, + IMX_F1_GPIO262, + IMX_F2_GPIO262, + IMX_F3_GPIO262, + IMX_F0_GPIO263, + IMX_F1_GPIO263, + IMX_F2_GPIO263, + IMX_F3_GPIO263, + IMX_F0_GPIO264, + IMX_F1_GPIO264, + IMX_F2_GPIO264, + IMX_F3_GPIO264, + IMX_F0_GPIO265, + IMX_F1_GPIO265, + IMX_F2_GPIO265, + IMX_F3_GPIO265, + IMX_F0_GPIO266, + IMX_F1_GPIO266, + IMX_F2_GPIO266, + IMX_F3_GPIO266, + IMX_F0_GPIO267, + IMX_F1_GPIO267, + IMX_F2_GPIO267, + IMX_F3_GPIO267, + IMX_F0_GPIO268, + IMX_F1_GPIO268, + IMX_F2_GPIO268, + IMX_F3_GPIO268, + IMX_F0_GPIO269, + IMX_F1_GPIO269, + IMX_F2_GPIO269, + IMX_F3_GPIO269, + IMX_F0_GPIO270, + IMX_F1_GPIO270, + IMX_F2_GPIO270, + IMX_F3_GPIO270, + IMX_F0_GPIO271, + IMX_F1_GPIO271, + IMX_F2_GPIO271, + IMX_F3_GPIO271, }; #define AMD_PINCTRL_FUNC_GRP(_number, _func) \ @@ -1456,6 +1550,70 @@ static const struct pingroup kerncz_groups[] = { AMD_PINCTRL_FUNC_GRP(144, 1), AMD_PINCTRL_FUNC_GRP(144, 2), AMD_PINCTRL_FUNC_GRP(144, 3), + AMD_PINCTRL_FUNC_GRP(256, 0), + AMD_PINCTRL_FUNC_GRP(256, 1), + AMD_PINCTRL_FUNC_GRP(256, 2), + AMD_PINCTRL_FUNC_GRP(256, 3), + AMD_PINCTRL_FUNC_GRP(257, 0), + AMD_PINCTRL_FUNC_GRP(257, 1), + AMD_PINCTRL_FUNC_GRP(257, 2), + AMD_PINCTRL_FUNC_GRP(257, 3), + AMD_PINCTRL_FUNC_GRP(258, 0), + AMD_PINCTRL_FUNC_GRP(258, 1), + AMD_PINCTRL_FUNC_GRP(258, 2), + AMD_PINCTRL_FUNC_GRP(258, 3), + AMD_PINCTRL_FUNC_GRP(259, 0), + AMD_PINCTRL_FUNC_GRP(259, 1), + AMD_PINCTRL_FUNC_GRP(259, 2), + AMD_PINCTRL_FUNC_GRP(259, 3), + AMD_PINCTRL_FUNC_GRP(260, 0), + AMD_PINCTRL_FUNC_GRP(260, 1), + AMD_PINCTRL_FUNC_GRP(260, 2), + AMD_PINCTRL_FUNC_GRP(260, 3), + AMD_PINCTRL_FUNC_GRP(261, 0), + AMD_PINCTRL_FUNC_GRP(261, 1), + AMD_PINCTRL_FUNC_GRP(261, 2), + AMD_PINCTRL_FUNC_GRP(261, 3), + AMD_PINCTRL_FUNC_GRP(262, 0), + AMD_PINCTRL_FUNC_GRP(262, 1), + AMD_PINCTRL_FUNC_GRP(262, 2), + AMD_PINCTRL_FUNC_GRP(262, 3), + AMD_PINCTRL_FUNC_GRP(263, 0), + AMD_PINCTRL_FUNC_GRP(263, 1), + AMD_PINCTRL_FUNC_GRP(263, 2), + AMD_PINCTRL_FUNC_GRP(263, 3), + AMD_PINCTRL_FUNC_GRP(264, 0), + AMD_PINCTRL_FUNC_GRP(264, 1), + AMD_PINCTRL_FUNC_GRP(264, 2), + AMD_PINCTRL_FUNC_GRP(264, 3), + AMD_PINCTRL_FUNC_GRP(265, 0), + AMD_PINCTRL_FUNC_GRP(265, 1), + AMD_PINCTRL_FUNC_GRP(265, 2), + AMD_PINCTRL_FUNC_GRP(265, 3), + AMD_PINCTRL_FUNC_GRP(266, 0), + AMD_PINCTRL_FUNC_GRP(266, 1), + AMD_PINCTRL_FUNC_GRP(266, 2), + AMD_PINCTRL_FUNC_GRP(266, 3), + AMD_PINCTRL_FUNC_GRP(267, 0), + AMD_PINCTRL_FUNC_GRP(267, 1), + AMD_PINCTRL_FUNC_GRP(267, 2), + AMD_PINCTRL_FUNC_GRP(267, 3), + AMD_PINCTRL_FUNC_GRP(268, 0), + AMD_PINCTRL_FUNC_GRP(268, 1), + AMD_PINCTRL_FUNC_GRP(268, 2), + AMD_PINCTRL_FUNC_GRP(268, 3), + AMD_PINCTRL_FUNC_GRP(269, 0), + AMD_PINCTRL_FUNC_GRP(269, 1), + AMD_PINCTRL_FUNC_GRP(269, 2), + AMD_PINCTRL_FUNC_GRP(269, 3), + AMD_PINCTRL_FUNC_GRP(270, 0), + AMD_PINCTRL_FUNC_GRP(270, 1), + AMD_PINCTRL_FUNC_GRP(270, 2), + AMD_PINCTRL_FUNC_GRP(270, 3), + AMD_PINCTRL_FUNC_GRP(271, 0), + AMD_PINCTRL_FUNC_GRP(271, 1), + AMD_PINCTRL_FUNC_GRP(271, 2), + AMD_PINCTRL_FUNC_GRP(271, 3), PINCTRL_PINGROUP("i2c0", AMD_PINS(145, 146), 2), PINCTRL_PINGROUP("i2c1", AMD_PINS(147, 148), 2), @@ -1620,6 +1778,22 @@ static const struct amd_function pmx_functions[] = { AMD_PMUX_FUNC(142), AMD_PMUX_FUNC(143), AMD_PMUX_FUNC(144), + AMD_PMUX_FUNC(256), + AMD_PMUX_FUNC(257), + AMD_PMUX_FUNC(258), + AMD_PMUX_FUNC(259), + AMD_PMUX_FUNC(260), + AMD_PMUX_FUNC(261), + AMD_PMUX_FUNC(262), + AMD_PMUX_FUNC(263), + AMD_PMUX_FUNC(264), + AMD_PMUX_FUNC(265), + AMD_PMUX_FUNC(266), + AMD_PMUX_FUNC(267), + AMD_PMUX_FUNC(268), + AMD_PMUX_FUNC(269), + AMD_PMUX_FUNC(270), + AMD_PMUX_FUNC(271), }; #endif From c7c5e0641485e10b587c60d1cf485a38fb1334dc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 21 Sep 2026 11:41:46 +0200 Subject: [PATCH 079/106] pinctrl: axp209: Drop check for disabled devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since commit 6b5c350648b8 ("mfd: mfd-core: Honour Device Tree's request to disable a child-device") the mfd core checks for disabled devices, so there is no use in doing that again in the mfd child driver. Drop the check. Signed-off-by: Uwe Kleine-König Reviewed-by: Chen-Yu Tsai Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-axp209.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c index 2bd8487484a8..5539ce642b39 100644 --- a/drivers/pinctrl/pinctrl-axp209.c +++ b/drivers/pinctrl/pinctrl-axp209.c @@ -442,9 +442,6 @@ static int axp20x_pctl_probe(struct platform_device *pdev) struct pinctrl_desc *pctrl_desc; int ret; - if (!of_device_is_available(pdev->dev.of_node)) - return -ENODEV; - if (!axp20x) { dev_err(&pdev->dev, "Parent drvdata not set\n"); return -EINVAL; From c1fb14e022c00ec6147cebce8bca8db027a40faf Mon Sep 17 00:00:00 2001 From: Long Zhao Date: Mon, 21 Sep 2026 12:23:23 +0800 Subject: [PATCH 080/106] dt-bindings: pinctrl: add Ambarella CV75 pinctrl Document the CV75 pin controller binding using generic function and groups properties for pinmux configuration. Reviewed-by: Linus Walleij Reviewed-by: Krzysztof Kozlowski Signed-off-by: Long Zhao Signed-off-by: Linus Walleij --- .../pinctrl/ambarella,cv75-pinctrl.yaml | 237 ++++++++++++++++++ 1 file changed, 237 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml new file mode 100644 index 000000000000..ee464a0f80d9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml @@ -0,0 +1,237 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ambarella,cv75-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ambarella CV75 Pin Controller + +maintainers: + - Long Zhao + +description: + The Ambarella CV75 pin controller configures pin multiplexing, bias and + drive strength for the main GPIO banks. Pin groups and their mux settings + are defined by the pin controller driver and selected by function and group + names. + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + const: ambarella,cv75-pinctrl + + reg: + maxItems: 1 + description: IOMUX registers + + ambarella,drive-strength-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: RCT syscon containing the drive-strength registers. + + ambarella,pull-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: Secure scratchpad syscon containing the pull registers. + +patternProperties: + "^[a-z0-9-]+-pins$": + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + additionalProperties: false + + properties: + function: + enum: + - can0 + - can1 + - dmic0 + - enet0 + - hsync0 + - hsync1 + - i2c0 + - i2c1 + - i2c2 + - i2c3 + - i2cs + - i2s0 + - i2s1 + - ir + - pwm0 + - pwm1 + - pwm2 + - pwm3 + - pwm4 + - pwm5 + - pwm6 + - pwm7 + - pwm8 + - pwm9 + - pwm10 + - pwm11 + - sdmmc0 + - sdmmc1 + - snand + - spi0 + - spi1 + - spi2 + - spi3 + - spi_slave + - spinor + - uart0 + - uart1 + - uart2 + - uart3 + - uart4 + - vin_master_sync + - vsync0 + - vsync1 + - vsync2 + - vsync3 + - wdt + + groups: + items: + enum: + - can0 + - can1 + - dmic0 + - enet_2nd_ref_clk_a + - enet_2nd_ref_clk_b + - enet_ext_osc_clk + - enet0_ptp_pps_o + - hsync0 + - hsync1 + - i2c0_a + - i2c0_b + - i2c1_a + - i2c1_b + - i2c2 + - i2c3_a + - i2c3_b + - i2c3_c + - i2cs_a + - i2cs_b + - i2cs_c + - i2cs_d + - i2s0 + - i2s1 + - ir + - pwm0 + - pwm1 + - pwm2 + - pwm3 + - pwm4_a + - pwm4_b + - pwm5_a + - pwm5_b + - pwm6_a + - pwm6_b + - pwm7_a + - pwm7_b + - pwm8_a + - pwm8_b + - pwm9_a + - pwm9_b + - pwm10_a + - pwm10_b + - pwm11_a + - pwm11_b + - rgmii0 + - rmii0 + - sdmmc0_1bit + - sdmmc0_4bit + - sdmmc0_cd + - sdmmc0_hs_sel + - sdmmc0_reset + - sdmmc0_wp + - sdmmc1_1bit + - sdmmc1_4bit + - sdmmc1_cd + - sdmmc1_hs_sel + - sdmmc1_reset + - sdmmc1_wp + - snand + - spi0 + - spi1 + - spi2 + - spi3_a + - spi3_b + - spi3_c + - spi_slave_a + - spi_slave_b + - spi_slave_c + - spi_slave_d + - spi_slave_e + - spinor + - uart0 + - uart1 + - uart1_flow + - uart2_a + - uart2_b + - uart2_c + - uart2_flow_a + - uart2_flow_b + - uart3_a + - uart3_b + - uart3_flow_a + - uart3_flow_b + - uart4_a + - uart4_b + - uart4_flow_a + - uart4_flow_b + - vin_master_sync_a + - vin_master_sync_b + - vin_master_sync_c + - vin_master_sync_d + - vin_master_sync_e + - vsync0 + - vsync1 + - vsync2 + - vsync3 + - wdt_a + - wdt_b + - wdt_c + - wdt_d + - wdt_e + - wdt_f + minItems: 1 + maxItems: 6 + uniqueItems: true + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + + drive-strength: + enum: [3, 4, 5, 6, 7, 8, 9, 12] + + required: + - function + - groups + +required: + - compatible + - reg + - ambarella,drive-strength-syscon + - ambarella,pull-syscon + +unevaluatedProperties: false + +examples: + - | + pinctrl: pinctrl@e4010000 { + compatible = "ambarella,cv75-pinctrl"; + reg = <0xe4010000 0x1000>; + ambarella,drive-strength-syscon = <&rct>; + ambarella,pull-syscon = <&scratchpad>; + + uart0-pins { + function = "uart0"; + groups = "uart0"; + bias-disable; + drive-strength = <8>; + }; + }; From b40e9d140c24650184697882056ce00c091f6b72 Mon Sep 17 00:00:00 2001 From: Long Zhao Date: Mon, 21 Sep 2026 12:23:34 +0800 Subject: [PATCH 081/106] pinctrl: ambarella: add CV75 pin controller Add an Ambarella pinmux-only pinctrl driver with CV75 function/group tables. GPIO is handled by the PL061 driver. Signed-off-by: Long Zhao Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 17 + drivers/pinctrl/Makefile | 2 + drivers/pinctrl/pinctrl-ambarella-cv75.c | 587 +++++++++++++++++++++++ drivers/pinctrl/pinctrl-ambarella.c | 533 ++++++++++++++++++++ drivers/pinctrl/pinctrl-ambarella.h | 40 ++ 5 files changed, 1179 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-ambarella-cv75.c create mode 100644 drivers/pinctrl/pinctrl-ambarella.c create mode 100644 drivers/pinctrl/pinctrl-ambarella.h diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index e1ab3a916086..78c252ccd73f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -37,6 +37,23 @@ config DEBUG_PINCTRL help Say Y here to add some extra checks and diagnostics to PINCTRL calls. +config PINCTRL_AMB + bool "Ambarella pin controller support" + depends on ARCH_AMBARELLA || COMPILE_TEST + depends on HAS_IOMEM + default y if ARCH_AMBARELLA + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GPIOLIB + select GPIO_PL061 + select MFD_SYSCON + select PINCONF + select PINMUX + help + Say Y here to enable the Ambarella pinmux/pinconf controller. + GPIO is provided by the PL061 driver. + config PINCTRL_AMD bool "AMD GPIO pin control" depends on HAS_IOMEM diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index a35d71135abf..ce0825f4fc1b 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -10,6 +10,8 @@ obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o obj-$(CONFIG_GENERIC_PINCTRL) += pinctrl-generic.o obj-$(CONFIG_OF) += devicetree.o +obj-$(CONFIG_PINCTRL_AMB) += pinctrl-ambarella.o +obj-$(CONFIG_PINCTRL_AMB) += pinctrl-ambarella-cv75.o obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o obj-$(CONFIG_PINCTRL_AMDISP) += pinctrl-amdisp.o obj-$(CONFIG_PINCTRL_APPLE_GPIO) += pinctrl-apple-gpio.o diff --git a/drivers/pinctrl/pinctrl-ambarella-cv75.c b/drivers/pinctrl/pinctrl-ambarella-cv75.c new file mode 100644 index 000000000000..eb25fd94ece8 --- /dev/null +++ b/drivers/pinctrl/pinctrl-ambarella-cv75.c @@ -0,0 +1,587 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Ambarella CV75 pinctrl data + * + * Copyright (C) 2026, Ambarella, Inc. + */ + +#include +#include +#include + +#include + +#include "pinctrl-ambarella.h" + +#define CV75_EXPAND(...) __VA_ARGS__ +#define CV75_GROUP_PINS_ALTS(_name, _pin_list, _alt_list) \ + static const unsigned int cv75_##_name##_pins[] = { CV75_EXPAND _pin_list }; \ + static const u8 cv75_##_name##_alts[] = { CV75_EXPAND _alt_list }; \ + static const struct pingroup cv75_##_name##_grp = \ + PINCTRL_PINGROUP(#_name, cv75_##_name##_pins, \ + ARRAY_SIZE(cv75_##_name##_pins)); \ + static_assert(ARRAY_SIZE(cv75_##_name##_pins) == \ + ARRAY_SIZE(cv75_##_name##_alts)) + +#define CV75_GROUP(_name) \ +{ \ + .grp = &cv75_##_name##_grp, \ + .alts = cv75_##_name##_alts, \ +} + +#define CV75_FUNCTION(_name) \ + PINCTRL_PINFUNCTION(#_name, cv75_##_name##_groups, ARRAY_SIZE(cv75_##_name##_groups)) + +/* UART */ +CV75_GROUP_PINS_ALTS(uart0, (44, 45), (1, 1)); +CV75_GROUP_PINS_ALTS(uart1, (46, 47), (1, 1)); +CV75_GROUP_PINS_ALTS(uart1_flow, (48, 49), (1, 1)); +CV75_GROUP_PINS_ALTS(uart2_a, (46, 47), (2, 2)); +CV75_GROUP_PINS_ALTS(uart2_b, (50, 51), (2, 2)); +CV75_GROUP_PINS_ALTS(uart2_c, (66, 68), (2, 2)); +CV75_GROUP_PINS_ALTS(uart2_flow_a, (48, 49), (2, 2)); +CV75_GROUP_PINS_ALTS(uart2_flow_b, (65, 67), (3, 3)); +CV75_GROUP_PINS_ALTS(uart3_a, (70, 72), (3, 3)); +CV75_GROUP_PINS_ALTS(uart3_b, (80, 79), (3, 3)); +CV75_GROUP_PINS_ALTS(uart3_flow_a, (71, 69), (3, 3)); +CV75_GROUP_PINS_ALTS(uart3_flow_b, (81, 82), (3, 3)); +CV75_GROUP_PINS_ALTS(uart4_a, (29, 30), (3, 3)); +CV75_GROUP_PINS_ALTS(uart4_b, (76, 77), (3, 3)); +CV75_GROUP_PINS_ALTS(uart4_flow_a, (28, 31), (3, 3)); +CV75_GROUP_PINS_ALTS(uart4_flow_b, (74, 75), (3, 3)); + +/* Flash */ +CV75_GROUP_PINS_ALTS(snand, (79, 80, 81, 82, 83, 84), (1, 1, 1, 1, 1, 1)); +CV75_GROUP_PINS_ALTS(spinor, (79, 80, 81, 82, 83, 84, 85), + (2, 2, 2, 2, 2, 2, 2)); + +/* SD/MMC */ +CV75_GROUP_PINS_ALTS(sdmmc0_cd, (6), (1)); +CV75_GROUP_PINS_ALTS(sdmmc0_wp, (7), (1)); +CV75_GROUP_PINS_ALTS(sdmmc0_reset, (8), (1)); +CV75_GROUP_PINS_ALTS(sdmmc0_hs_sel, (93), (1)); +CV75_GROUP_PINS_ALTS(sdmmc0_1bit, (0, 4, 5), (1, 1, 1)); +CV75_GROUP_PINS_ALTS(sdmmc0_4bit, (0, 1, 2, 3, 4, 5), (1, 1, 1, 1, 1, 1)); +CV75_GROUP_PINS_ALTS(sdmmc1_cd, (15), (1)); +CV75_GROUP_PINS_ALTS(sdmmc1_wp, (16), (1)); +CV75_GROUP_PINS_ALTS(sdmmc1_reset, (17), (1)); +CV75_GROUP_PINS_ALTS(sdmmc1_hs_sel, (94), (1)); +CV75_GROUP_PINS_ALTS(sdmmc1_1bit, (9, 13, 14), (1, 1, 1)); +CV75_GROUP_PINS_ALTS(sdmmc1_4bit, (9, 10, 11, 12, 13, 14), (1, 1, 1, 1, 1, 1)); + +/* Ethernet */ +CV75_GROUP_PINS_ALTS(enet_ext_osc_clk, (77), (1)); +CV75_GROUP_PINS_ALTS(enet_2nd_ref_clk_a, (78), (1)); +CV75_GROUP_PINS_ALTS(enet_2nd_ref_clk_b, (76), (2)); +CV75_GROUP_PINS_ALTS(enet0_ptp_pps_o, (74), (1)); +CV75_GROUP_PINS_ALTS(rgmii0, (62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 75, 76), + (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)); +CV75_GROUP_PINS_ALTS(rmii0, (62, 63, 64, 67, 68, 71, 72, 73, 75), + (1, 1, 1, 1, 1, 1, 1, 1, 2)); + +/* I2C */ +CV75_GROUP_PINS_ALTS(i2c0_a, (67, 68), (2, 2)); +CV75_GROUP_PINS_ALTS(i2c0_b, (86, 87), (1, 1)); +CV75_GROUP_PINS_ALTS(i2c1_a, (22, 23), (2, 2)); +CV75_GROUP_PINS_ALTS(i2c1_b, (69, 70), (2, 2)); +CV75_GROUP_PINS_ALTS(i2c2, (88, 89), (1, 1)); +CV75_GROUP_PINS_ALTS(i2c3_a, (24, 25), (2, 2)); +CV75_GROUP_PINS_ALTS(i2c3_b, (48, 49), (3, 3)); +CV75_GROUP_PINS_ALTS(i2c3_c, (58, 59), (3, 3)); +CV75_GROUP_PINS_ALTS(i2cs_a, (19, 21), (2, 2)); +CV75_GROUP_PINS_ALTS(i2cs_b, (60, 61), (3, 3)); +CV75_GROUP_PINS_ALTS(i2cs_c, (71, 72), (2, 2)); +CV75_GROUP_PINS_ALTS(i2cs_d, (86, 87), (2, 2)); + +/* CAN, IR, WDT */ +CV75_GROUP_PINS_ALTS(can0, (50, 51), (1, 1)); +CV75_GROUP_PINS_ALTS(can1, (52, 53), (1, 1)); +CV75_GROUP_PINS_ALTS(ir, (18), (1)); +CV75_GROUP_PINS_ALTS(wdt_a, (20), (2)); +CV75_GROUP_PINS_ALTS(wdt_b, (27), (3)); +CV75_GROUP_PINS_ALTS(wdt_c, (39), (2)); +CV75_GROUP_PINS_ALTS(wdt_d, (83), (3)); +CV75_GROUP_PINS_ALTS(wdt_e, (85), (4)); +CV75_GROUP_PINS_ALTS(wdt_f, (90), (1)); + +/* I2S */ +CV75_GROUP_PINS_ALTS(i2s0, (54, 55, 56, 57), (1, 1, 1, 1)); +CV75_GROUP_PINS_ALTS(i2s1, (58, 59, 60, 61), (1, 1, 1, 1)); +CV75_GROUP_PINS_ALTS(dmic0, (54, 55), (2, 2)); + +/* PWM */ +CV75_GROUP_PINS_ALTS(pwm0, (40), (1)); +CV75_GROUP_PINS_ALTS(pwm1, (41), (1)); +CV75_GROUP_PINS_ALTS(pwm2, (42), (1)); +CV75_GROUP_PINS_ALTS(pwm3, (43), (1)); +CV75_GROUP_PINS_ALTS(pwm4_a, (19), (3)); +CV75_GROUP_PINS_ALTS(pwm4_b, (32), (4)); +CV75_GROUP_PINS_ALTS(pwm5_a, (20), (3)); +CV75_GROUP_PINS_ALTS(pwm5_b, (33), (4)); +CV75_GROUP_PINS_ALTS(pwm6_a, (21), (3)); +CV75_GROUP_PINS_ALTS(pwm6_b, (34), (4)); +CV75_GROUP_PINS_ALTS(pwm7_a, (22), (3)); +CV75_GROUP_PINS_ALTS(pwm7_b, (35), (4)); +CV75_GROUP_PINS_ALTS(pwm8_a, (23), (3)); +CV75_GROUP_PINS_ALTS(pwm8_b, (36), (4)); +CV75_GROUP_PINS_ALTS(pwm9_a, (24), (3)); +CV75_GROUP_PINS_ALTS(pwm9_b, (37), (4)); +CV75_GROUP_PINS_ALTS(pwm10_a, (25), (3)); +CV75_GROUP_PINS_ALTS(pwm10_b, (38), (4)); +CV75_GROUP_PINS_ALTS(pwm11_a, (26), (3)); +CV75_GROUP_PINS_ALTS(pwm11_b, (39), (4)); + +/* SPI */ +CV75_GROUP_PINS_ALTS(spi0, (19, 20, 21), (1, 1, 1)); +CV75_GROUP_PINS_ALTS(spi1, (24, 25, 26), (1, 1, 1)); +CV75_GROUP_PINS_ALTS(spi2, (28, 29, 30), (1, 1, 1)); +CV75_GROUP_PINS_ALTS(spi3_a, (32, 33, 34), (5, 5, 5)); +CV75_GROUP_PINS_ALTS(spi3_b, (40, 41, 43), (2, 2, 2)); +CV75_GROUP_PINS_ALTS(spi3_c, (58, 59, 60), (2, 2, 2)); +CV75_GROUP_PINS_ALTS(spi_slave_a, (24, 25, 26, 27), (4, 4, 4, 4)); +CV75_GROUP_PINS_ALTS(spi_slave_b, (28, 29, 30, 31), (2, 2, 2, 2)); +CV75_GROUP_PINS_ALTS(spi_slave_c, (36, 37, 38, 39), (5, 5, 5, 5)); +CV75_GROUP_PINS_ALTS(spi_slave_d, (50, 51, 52, 53), (3, 3, 3, 3)); +CV75_GROUP_PINS_ALTS(spi_slave_e, (81, 82, 83, 84), (4, 4, 4, 4)); + +/* VIN master sync */ +CV75_GROUP_PINS_ALTS(vin_master_sync_a, (91, 92), (1, 1)); +CV75_GROUP_PINS_ALTS(vin_master_sync_b, (91, 92), (2, 2)); +CV75_GROUP_PINS_ALTS(vin_master_sync_c, (40, 41), (3, 3)); +CV75_GROUP_PINS_ALTS(vin_master_sync_d, (46, 47), (3, 3)); +CV75_GROUP_PINS_ALTS(vin_master_sync_e, (79, 80), (4, 4)); +CV75_GROUP_PINS_ALTS(vsync0, (32), (1)); +CV75_GROUP_PINS_ALTS(vsync1, (33), (1)); +CV75_GROUP_PINS_ALTS(vsync2, (34), (1)); +CV75_GROUP_PINS_ALTS(vsync3, (35), (1)); +CV75_GROUP_PINS_ALTS(hsync0, (36), (1)); +CV75_GROUP_PINS_ALTS(hsync1, (37), (1)); + +static const struct amb_pinmux_group cv75_pin_groups[] = { + /* UART */ + CV75_GROUP(uart0), + CV75_GROUP(uart1), + CV75_GROUP(uart1_flow), + CV75_GROUP(uart2_a), + CV75_GROUP(uart2_b), + CV75_GROUP(uart2_c), + CV75_GROUP(uart2_flow_a), + CV75_GROUP(uart2_flow_b), + CV75_GROUP(uart3_a), + CV75_GROUP(uart3_b), + CV75_GROUP(uart3_flow_a), + CV75_GROUP(uart3_flow_b), + CV75_GROUP(uart4_a), + CV75_GROUP(uart4_b), + CV75_GROUP(uart4_flow_a), + CV75_GROUP(uart4_flow_b), + /* Flash */ + CV75_GROUP(snand), + CV75_GROUP(spinor), + /* SD/MMC */ + CV75_GROUP(sdmmc0_cd), + CV75_GROUP(sdmmc0_wp), + CV75_GROUP(sdmmc0_reset), + CV75_GROUP(sdmmc0_hs_sel), + CV75_GROUP(sdmmc0_1bit), + CV75_GROUP(sdmmc0_4bit), + CV75_GROUP(sdmmc1_cd), + CV75_GROUP(sdmmc1_wp), + CV75_GROUP(sdmmc1_reset), + CV75_GROUP(sdmmc1_hs_sel), + CV75_GROUP(sdmmc1_1bit), + CV75_GROUP(sdmmc1_4bit), + /* Ethernet */ + CV75_GROUP(enet_ext_osc_clk), + CV75_GROUP(enet_2nd_ref_clk_a), + CV75_GROUP(enet_2nd_ref_clk_b), + CV75_GROUP(enet0_ptp_pps_o), + CV75_GROUP(rgmii0), + CV75_GROUP(rmii0), + /* I2C */ + CV75_GROUP(i2c0_a), + CV75_GROUP(i2c0_b), + CV75_GROUP(i2c1_a), + CV75_GROUP(i2c1_b), + CV75_GROUP(i2c2), + CV75_GROUP(i2c3_a), + CV75_GROUP(i2c3_b), + CV75_GROUP(i2c3_c), + CV75_GROUP(i2cs_a), + CV75_GROUP(i2cs_b), + CV75_GROUP(i2cs_c), + CV75_GROUP(i2cs_d), + /* CAN, IR, WDT */ + CV75_GROUP(can0), + CV75_GROUP(can1), + CV75_GROUP(ir), + CV75_GROUP(wdt_a), + CV75_GROUP(wdt_b), + CV75_GROUP(wdt_c), + CV75_GROUP(wdt_d), + CV75_GROUP(wdt_e), + CV75_GROUP(wdt_f), + /* I2S */ + CV75_GROUP(i2s0), + CV75_GROUP(i2s1), + CV75_GROUP(dmic0), + /* PWM */ + CV75_GROUP(pwm0), + CV75_GROUP(pwm1), + CV75_GROUP(pwm2), + CV75_GROUP(pwm3), + CV75_GROUP(pwm4_a), + CV75_GROUP(pwm4_b), + CV75_GROUP(pwm5_a), + CV75_GROUP(pwm5_b), + CV75_GROUP(pwm6_a), + CV75_GROUP(pwm6_b), + CV75_GROUP(pwm7_a), + CV75_GROUP(pwm7_b), + CV75_GROUP(pwm8_a), + CV75_GROUP(pwm8_b), + CV75_GROUP(pwm9_a), + CV75_GROUP(pwm9_b), + CV75_GROUP(pwm10_a), + CV75_GROUP(pwm10_b), + CV75_GROUP(pwm11_a), + CV75_GROUP(pwm11_b), + /* SPI */ + CV75_GROUP(spi0), + CV75_GROUP(spi1), + CV75_GROUP(spi2), + CV75_GROUP(spi3_a), + CV75_GROUP(spi3_b), + CV75_GROUP(spi3_c), + CV75_GROUP(spi_slave_a), + CV75_GROUP(spi_slave_b), + CV75_GROUP(spi_slave_c), + CV75_GROUP(spi_slave_d), + CV75_GROUP(spi_slave_e), + /* VIN master sync */ + CV75_GROUP(vin_master_sync_a), + CV75_GROUP(vin_master_sync_b), + CV75_GROUP(vin_master_sync_c), + CV75_GROUP(vin_master_sync_d), + CV75_GROUP(vin_master_sync_e), + CV75_GROUP(vsync0), + CV75_GROUP(vsync1), + CV75_GROUP(vsync2), + CV75_GROUP(vsync3), + CV75_GROUP(hsync0), + CV75_GROUP(hsync1), +}; + +static const char * const cv75_uart0_groups[] = { + "uart0", +}; + +static const char * const cv75_uart1_groups[] = { + "uart1", + "uart1_flow", +}; + +static const char * const cv75_uart2_groups[] = { + "uart2_a", + "uart2_b", + "uart2_c", + "uart2_flow_a", + "uart2_flow_b", +}; + +static const char * const cv75_uart3_groups[] = { + "uart3_a", + "uart3_b", + "uart3_flow_a", + "uart3_flow_b", +}; + +static const char * const cv75_uart4_groups[] = { + "uart4_a", + "uart4_b", + "uart4_flow_a", + "uart4_flow_b", +}; + +static const char * const cv75_snand_groups[] = { + "snand", +}; + +static const char * const cv75_spinor_groups[] = { + "spinor", +}; + +static const char * const cv75_sdmmc0_groups[] = { + "sdmmc0_cd", + "sdmmc0_wp", + "sdmmc0_reset", + "sdmmc0_hs_sel", + "sdmmc0_1bit", + "sdmmc0_4bit", +}; + +static const char * const cv75_sdmmc1_groups[] = { + "sdmmc1_cd", + "sdmmc1_wp", + "sdmmc1_reset", + "sdmmc1_hs_sel", + "sdmmc1_1bit", + "sdmmc1_4bit", +}; + +static const char * const cv75_enet0_groups[] = { + "enet_ext_osc_clk", + "enet_2nd_ref_clk_a", + "enet_2nd_ref_clk_b", + "enet0_ptp_pps_o", + "rgmii0", + "rmii0", +}; + +static const char * const cv75_i2c0_groups[] = { + "i2c0_a", + "i2c0_b", +}; + +static const char * const cv75_i2c1_groups[] = { + "i2c1_a", + "i2c1_b", +}; + +static const char * const cv75_i2c2_groups[] = { + "i2c2", +}; + +static const char * const cv75_i2c3_groups[] = { + "i2c3_a", + "i2c3_b", + "i2c3_c", +}; + +static const char * const cv75_i2cs_groups[] = { + "i2cs_a", + "i2cs_b", + "i2cs_c", + "i2cs_d", +}; + +static const char * const cv75_can0_groups[] = { + "can0", +}; + +static const char * const cv75_can1_groups[] = { + "can1", +}; + +static const char * const cv75_ir_groups[] = { + "ir", +}; + +static const char * const cv75_wdt_groups[] = { + "wdt_a", + "wdt_b", + "wdt_c", + "wdt_d", + "wdt_e", + "wdt_f", +}; + +static const char * const cv75_i2s0_groups[] = { + "i2s0", +}; + +static const char * const cv75_i2s1_groups[] = { + "i2s1", +}; + +static const char * const cv75_dmic0_groups[] = { + "dmic0", +}; + +static const char * const cv75_pwm0_groups[] = { + "pwm0", +}; + +static const char * const cv75_pwm1_groups[] = { + "pwm1", +}; + +static const char * const cv75_pwm2_groups[] = { + "pwm2", +}; + +static const char * const cv75_pwm3_groups[] = { + "pwm3", +}; + +static const char * const cv75_pwm4_groups[] = { + "pwm4_a", + "pwm4_b", +}; + +static const char * const cv75_pwm5_groups[] = { + "pwm5_a", + "pwm5_b", +}; + +static const char * const cv75_pwm6_groups[] = { + "pwm6_a", + "pwm6_b", +}; + +static const char * const cv75_pwm7_groups[] = { + "pwm7_a", + "pwm7_b", +}; + +static const char * const cv75_pwm8_groups[] = { + "pwm8_a", + "pwm8_b", +}; + +static const char * const cv75_pwm9_groups[] = { + "pwm9_a", + "pwm9_b", +}; + +static const char * const cv75_pwm10_groups[] = { + "pwm10_a", + "pwm10_b", +}; + +static const char * const cv75_pwm11_groups[] = { + "pwm11_a", + "pwm11_b", +}; + +static const char * const cv75_spi0_groups[] = { + "spi0", +}; + +static const char * const cv75_spi1_groups[] = { + "spi1", +}; + +static const char * const cv75_spi2_groups[] = { + "spi2", +}; + +static const char * const cv75_spi3_groups[] = { + "spi3_a", + "spi3_b", + "spi3_c", +}; + +static const char * const cv75_spi_slave_groups[] = { + "spi_slave_a", + "spi_slave_b", + "spi_slave_c", + "spi_slave_d", + "spi_slave_e", +}; + +static const char * const cv75_vin_master_sync_groups[] = { + "vin_master_sync_a", + "vin_master_sync_b", + "vin_master_sync_c", + "vin_master_sync_d", + "vin_master_sync_e", +}; + +static const char * const cv75_vsync0_groups[] = { + "vsync0", +}; + +static const char * const cv75_vsync1_groups[] = { + "vsync1", +}; + +static const char * const cv75_vsync2_groups[] = { + "vsync2", +}; + +static const char * const cv75_vsync3_groups[] = { + "vsync3", +}; + +static const char * const cv75_hsync0_groups[] = { + "hsync0", +}; + +static const char * const cv75_hsync1_groups[] = { + "hsync1", +}; + +static const struct pinfunction cv75_pin_functions[] = { + CV75_FUNCTION(uart0), + CV75_FUNCTION(uart1), + CV75_FUNCTION(uart2), + CV75_FUNCTION(uart3), + CV75_FUNCTION(uart4), + CV75_FUNCTION(snand), + CV75_FUNCTION(spinor), + CV75_FUNCTION(sdmmc0), + CV75_FUNCTION(sdmmc1), + CV75_FUNCTION(enet0), + CV75_FUNCTION(i2c0), + CV75_FUNCTION(i2c1), + CV75_FUNCTION(i2c2), + CV75_FUNCTION(i2c3), + CV75_FUNCTION(i2cs), + CV75_FUNCTION(can0), + CV75_FUNCTION(can1), + CV75_FUNCTION(ir), + CV75_FUNCTION(wdt), + CV75_FUNCTION(i2s0), + CV75_FUNCTION(i2s1), + CV75_FUNCTION(dmic0), + CV75_FUNCTION(pwm0), + CV75_FUNCTION(pwm1), + CV75_FUNCTION(pwm2), + CV75_FUNCTION(pwm3), + CV75_FUNCTION(pwm4), + CV75_FUNCTION(pwm5), + CV75_FUNCTION(pwm6), + CV75_FUNCTION(pwm7), + CV75_FUNCTION(pwm8), + CV75_FUNCTION(pwm9), + CV75_FUNCTION(pwm10), + CV75_FUNCTION(pwm11), + CV75_FUNCTION(spi0), + CV75_FUNCTION(spi1), + CV75_FUNCTION(spi2), + CV75_FUNCTION(spi3), + CV75_FUNCTION(spi_slave), + CV75_FUNCTION(vin_master_sync), + CV75_FUNCTION(vsync0), + CV75_FUNCTION(vsync1), + CV75_FUNCTION(vsync2), + CV75_FUNCTION(vsync3), + CV75_FUNCTION(hsync0), + CV75_FUNCTION(hsync1), +}; + +const struct amb_pinctrl_data ambarella_cv75_pinctrl_data = { + .groups = cv75_pin_groups, + .functions = cv75_pin_functions, + .ngroups = ARRAY_SIZE(cv75_pin_groups), + .nfunctions = ARRAY_SIZE(cv75_pin_functions), + .nr_banks = 3, + .npins = 96, + .ds0 = { + 0x314, 0x320, 0x32c, + }, + .ds1 = { + 0x318, 0x324, 0x330, + }, + .ds2 = { + 0x31c, 0x328, 0x334, + }, + .pull_en = { + 0x60, 0x64, 0x68, + }, + .pull_dir = { + 0x7c, 0x80, 0x84, + }, + .have_ds2 = true, +}; diff --git a/drivers/pinctrl/pinctrl-ambarella.c b/drivers/pinctrl/pinctrl-ambarella.c new file mode 100644 index 000000000000..83afef6a123f --- /dev/null +++ b/drivers/pinctrl/pinctrl-ambarella.c @@ -0,0 +1,533 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl driver for Ambarella SoCs + * + * Copyright (C) 2012-2026, Ambarella, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "core.h" +#include "pinmux.h" +#include "pinctrl-ambarella.h" + +#define IOMUX_REG(bank, n) (((bank) * 0xc) + ((n) * 4)) +#define IOMUX_CTRL_SET 0xf0 + +#define PINID_TO_BANK(p) ((p) >> 5) +#define PINID_TO_OFFSET(p) ((p) & 0x1f) + +struct amb_pinctrl { + struct pinctrl_desc desc; + void __iomem *iomux_base; + struct regmap *ds_regmap; + struct regmap *pull_regmap; + const struct amb_pinctrl_data *data; + struct device *dev; + struct pinctrl_dev *pctl; + spinlock_t lock; +}; + +static const int amb_ds1_ma[] = { 2, 4, 8, 12 }; +static const int amb_ds2_ma[] = { 3, 4, 6, 8, 9, 12 }; + +static const struct pinctrl_ops amb_pctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +static void amb_iomux_commit(struct amb_pinctrl *ipc) +{ + writel(0x1, ipc->iomux_base + IOMUX_CTRL_SET); + writel(0x0, ipc->iomux_base + IOMUX_CTRL_SET); +} + +static void amb_pinmux_set_altfunc(struct amb_pinctrl *ipc, u32 bank, + u32 offset, u32 altfunc) +{ + if (bank >= ipc->data->nr_banks) + return; + + for (unsigned int i = 0; i < 3; i++) { + unsigned long data; + + data = readl_relaxed(ipc->iomux_base + IOMUX_REG(bank, i)); + __assign_bit(offset, &data, altfunc & BIT(i)); + writel_relaxed(data, ipc->iomux_base + IOMUX_REG(bank, i)); + } +} + +static int amb_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int selector, unsigned int group) +{ + struct amb_pinctrl *ipc = pinctrl_dev_get_drvdata(pctldev); + struct group_desc *grp; + const u8 *alts; + unsigned long flags; + + (void)selector; + + grp = pinctrl_generic_get_group(pctldev, group); + if (!grp || !grp->data) + return -EINVAL; + + alts = grp->data; + + spin_lock_irqsave(&ipc->lock, flags); + for (unsigned int i = 0; i < grp->grp.npins; i++) { + unsigned int pin = grp->grp.pins[i]; + + amb_pinmux_set_altfunc(ipc, PINID_TO_BANK(pin), + PINID_TO_OFFSET(pin), alts[i]); + } + amb_iomux_commit(ipc); + spin_unlock_irqrestore(&ipc->lock, flags); + + return 0; +} + +static int amb_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct amb_pinctrl *ipc = pinctrl_dev_get_drvdata(pctldev); + unsigned long flags; + + if (!range || !range->gc) + return -EINVAL; + + if (pin >= ipc->data->npins) + return -EINVAL; + + spin_lock_irqsave(&ipc->lock, flags); + amb_pinmux_set_altfunc(ipc, PINID_TO_BANK(pin), PINID_TO_OFFSET(pin), 0); + amb_iomux_commit(ipc); + spin_unlock_irqrestore(&ipc->lock, flags); + + return 0; +} + +static const struct pinmux_ops amb_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = amb_pinmux_set_mux, + .gpio_request_enable = amb_pinmux_gpio_request_enable, + .strict = true, +}; + +static int amb_drive_strength_to_reg_ds1(u32 strength) +{ + for (unsigned int i = 0; i < ARRAY_SIZE(amb_ds1_ma); i++) { + if (amb_ds1_ma[i] == strength) + return i; + } + + return -EINVAL; +} + +static int amb_drive_strength_to_reg_ds2(u32 strength) +{ + /* Hardware steps are 3, 4, 6, 8, 9, 12 mA; 5 and 7 are accepted aliases */ + if (strength == 5) + strength = 4; + else if (strength == 7) + strength = 8; + + for (unsigned int i = 0; i < ARRAY_SIZE(amb_ds2_ma); i++) { + if (amb_ds2_ma[i] == strength) + return i; + } + + return -EINVAL; +} + +static int amb_drive_strength_to_reg(const struct amb_pinctrl *ipc, u32 strength) +{ + if (ipc->data->have_ds2) + return amb_drive_strength_to_reg_ds2(strength); + + return amb_drive_strength_to_reg_ds1(strength); +} + +static int amb_reg_to_drive_strength(const struct amb_pinctrl *ipc, u32 ds) +{ + if (ipc->data->have_ds2) { + if (ds >= ARRAY_SIZE(amb_ds2_ma)) + return -EINVAL; + return amb_ds2_ma[ds]; + } + + if (ds >= ARRAY_SIZE(amb_ds1_ma)) + return -EINVAL; + + return amb_ds1_ma[ds]; +} + +static int amb_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct amb_pinctrl *ipc = pinctrl_dev_get_drvdata(pctldev); + u32 bank = PINID_TO_BANK(pin); + u32 offset = PINID_TO_OFFSET(pin); + unsigned int mask = BIT(offset); + int ret; + + if (bank >= ipc->data->nr_banks) + return -EINVAL; + + for (unsigned int i = 0; i < num_configs; i++) { + enum pin_config_param param = pinconf_to_config_param(configs[i]); + u32 arg = pinconf_to_config_argument(configs[i]); + int ds; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret = regmap_assign_bits(ipc->pull_regmap, ipc->data->pull_en[bank], + mask, false); + if (ret) + return ret; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_UP: + ret = regmap_assign_bits(ipc->pull_regmap, ipc->data->pull_dir[bank], + mask, param == PIN_CONFIG_BIAS_PULL_UP); + if (ret) + return ret; + ret = regmap_assign_bits(ipc->pull_regmap, ipc->data->pull_en[bank], + mask, true); + if (ret) + return ret; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + ds = amb_drive_strength_to_reg(ipc, arg); + if (ds < 0) + return ds; + if (ipc->data->have_ds2) { + ret = regmap_assign_bits(ipc->ds_regmap, ipc->data->ds0[bank], + mask, ds & BIT(0)); + if (ret) + return ret; + ret = regmap_assign_bits(ipc->ds_regmap, ipc->data->ds1[bank], + mask, ds & BIT(1)); + if (ret) + return ret; + ret = regmap_assign_bits(ipc->ds_regmap, ipc->data->ds2[bank], + mask, ds & BIT(2)); + if (ret) + return ret; + } else { + ret = regmap_assign_bits(ipc->ds_regmap, ipc->data->ds0[bank], + mask, ds & BIT(1)); + if (ret) + return ret; + ret = regmap_assign_bits(ipc->ds_regmap, ipc->data->ds1[bank], + mask, ds & BIT(0)); + if (ret) + return ret; + } + break; + default: + return -ENOTSUPP; + } + } + + return 0; +} + +static int amb_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + const unsigned int *pins; + unsigned int npins; + int ret; + + ret = pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins); + if (ret) + return ret; + + for (unsigned int i = 0; i < npins; i++) { + ret = amb_pinconf_set(pctldev, pins[i], configs, num_configs); + if (ret) + return ret; + } + + return 0; +} + +static int amb_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct amb_pinctrl *ipc = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + u32 bank = PINID_TO_BANK(pin); + u32 offset = PINID_TO_OFFSET(pin); + u32 pull_en, pull_dir, ds0, ds1, ds2, ds; + bool en, dir, b0, b1, b2; + int ret, strength; + + if (bank >= ipc->data->nr_banks) + return -EINVAL; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_UP: + ret = regmap_read(ipc->pull_regmap, ipc->data->pull_en[bank], + &pull_en); + if (ret) + return ret; + + ret = regmap_read(ipc->pull_regmap, ipc->data->pull_dir[bank], + &pull_dir); + if (ret) + return ret; + + en = !!(pull_en & BIT(offset)); + dir = !!(pull_dir & BIT(offset)); + + if (param == PIN_CONFIG_BIAS_DISABLE) { + if (en) + return -EINVAL; + *config = pinconf_to_config_packed(param, 0); + return 0; + } + + if (!en) + return -EINVAL; + if (param == PIN_CONFIG_BIAS_PULL_UP && !dir) + return -EINVAL; + if (param == PIN_CONFIG_BIAS_PULL_DOWN && dir) + return -EINVAL; + + *config = pinconf_to_config_packed(param, 1); + return 0; + + case PIN_CONFIG_DRIVE_STRENGTH: + ret = regmap_read(ipc->ds_regmap, ipc->data->ds0[bank], &ds0); + if (ret) + return ret; + + ret = regmap_read(ipc->ds_regmap, ipc->data->ds1[bank], &ds1); + if (ret) + return ret; + + b0 = !!(ds0 & BIT(offset)); + b1 = !!(ds1 & BIT(offset)); + if (ipc->data->have_ds2) { + ret = regmap_read(ipc->ds_regmap, ipc->data->ds2[bank], + &ds2); + if (ret) + return ret; + + b2 = !!(ds2 & BIT(offset)); + ds = (b2 << 2) | (b1 << 1) | b0; + } else { + ds = (b0 << 1) | b1; + } + + strength = amb_reg_to_drive_strength(ipc, ds); + if (strength < 0) + return strength; + + *config = pinconf_to_config_packed(param, strength); + return 0; + + default: + return -ENOTSUPP; + } +} + +static const struct pinconf_ops amb_pinconf_ops = { + .is_generic = true, + .pin_config_get = amb_pinconf_get, + .pin_config_set = amb_pinconf_set, + .pin_config_group_set = amb_pinconf_group_set, +}; + +static int amb_pinctrl_add_groups(struct amb_pinctrl *ipc) +{ + const struct amb_pinctrl_data *data = ipc->data; + + for (unsigned int i = 0; i < data->ngroups; i++) { + const struct amb_pinmux_group *g = &data->groups[i]; + int ret; + + if (!g->grp || !g->grp->name || !g->grp->pins || + !g->grp->npins || !g->alts) + return -EINVAL; + + for (unsigned int j = 0; j < g->grp->npins; j++) { + if (g->grp->pins[j] >= data->npins) + return -EINVAL; + } + + ret = pinctrl_generic_add_group(ipc->pctl, g->grp->name, + g->grp->pins, g->grp->npins, + (void *)g->alts); + if (ret < 0) + return ret; + } + + return 0; +} + +static int amb_pinctrl_add_functions(struct amb_pinctrl *ipc) +{ + const struct amb_pinctrl_data *data = ipc->data; + + for (unsigned int i = 0; i < data->nfunctions; i++) { + int ret; + + ret = pinmux_generic_add_pinfunction(ipc->pctl, + &data->functions[i], NULL); + if (ret < 0) + return ret; + } + + return 0; +} + +static int amb_pinctrl_register(struct amb_pinctrl *ipc) +{ + struct pinctrl_pin_desc *pindesc; + char **names; + int ret; + + pindesc = devm_kcalloc(ipc->dev, ipc->data->npins, sizeof(*pindesc), + GFP_KERNEL); + if (!pindesc) + return -ENOMEM; + + names = devm_kasprintf_strarray(ipc->dev, "io", ipc->data->npins); + if (!names) + return -ENOMEM; + + for (unsigned int pin = 0; pin < ipc->data->npins; pin++) { + pindesc[pin].number = pin; + pindesc[pin].name = names[pin]; + } + + ipc->desc.name = dev_name(ipc->dev); + ipc->desc.pins = pindesc; + ipc->desc.npins = ipc->data->npins; + ipc->desc.pctlops = &amb_pctrl_ops; + ipc->desc.pmxops = &amb_pinmux_ops; + ipc->desc.confops = &amb_pinconf_ops; + ipc->desc.owner = THIS_MODULE; + + ret = devm_pinctrl_register_and_init(ipc->dev, &ipc->desc, ipc, &ipc->pctl); + if (ret) + return ret; + + ret = amb_pinctrl_add_groups(ipc); + if (ret) + return ret; + + ret = amb_pinctrl_add_functions(ipc); + if (ret) + return ret; + + return pinctrl_enable(ipc->pctl); +} + +static int amb_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct amb_pinctrl *ipc; + int ret; + + ipc = devm_kzalloc(dev, sizeof(*ipc), GFP_KERNEL); + if (!ipc) + return -ENOMEM; + + ipc->dev = dev; + ipc->data = device_get_match_data(dev); + if (!ipc->data) + return dev_err_probe(dev, -ENODATA, "missing SoC data\n"); + + if (!ipc->data->nr_banks || ipc->data->nr_banks > AMBA_MAX_BANKS || + !ipc->data->npins || + !ipc->data->groups || !ipc->data->ngroups || + !ipc->data->functions || !ipc->data->nfunctions) + return dev_err_probe(dev, -EINVAL, "invalid SoC data\n"); + + ipc->iomux_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ipc->iomux_base)) + return PTR_ERR(ipc->iomux_base); + + ipc->ds_regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), + "ambarella,drive-strength-syscon"); + if (IS_ERR(ipc->ds_regmap)) + return dev_err_probe(dev, PTR_ERR(ipc->ds_regmap), + "missing drive-strength syscon\n"); + + ipc->pull_regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), + "ambarella,pull-syscon"); + if (IS_ERR(ipc->pull_regmap)) + return dev_err_probe(dev, PTR_ERR(ipc->pull_regmap), + "missing pull syscon\n"); + + spin_lock_init(&ipc->lock); + + ret = amb_pinctrl_register(ipc); + if (ret) + return dev_err_probe(dev, ret, "failed to register pinctrl\n"); + + platform_set_drvdata(pdev, ipc); + + return 0; +} + +static const struct of_device_id amb_pinctrl_dt_match[] = { + { + .compatible = "ambarella,cv75-pinctrl", + .data = &ambarella_cv75_pinctrl_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, amb_pinctrl_dt_match); + +static struct platform_driver amb_pinctrl_driver = { + .probe = amb_pinctrl_probe, + .driver = { + .name = "ambarella-pinctrl", + .of_match_table = amb_pinctrl_dt_match, + }, +}; + +static int __init amb_pinctrl_drv_register(void) +{ + return platform_driver_register(&amb_pinctrl_driver); +} +arch_initcall(amb_pinctrl_drv_register); + +MODULE_AUTHOR("Cao Rongrong "); +MODULE_DESCRIPTION("Ambarella SoC pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-ambarella.h b/drivers/pinctrl/pinctrl-ambarella.h new file mode 100644 index 000000000000..37e9c420662c --- /dev/null +++ b/drivers/pinctrl/pinctrl-ambarella.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Ambarella pinctrl SoC data + * + * Copyright (C) 2012-2026, Ambarella, Inc. + */ + +#ifndef _PINCTRL_AMBARELLA_H +#define _PINCTRL_AMBARELLA_H + +#include + +#define AMBA_MAX_BANKS 8 + +struct pingroup; +struct pinfunction; + +struct amb_pinmux_group { + const struct pingroup *grp; + const u8 *alts; +}; + +struct amb_pinctrl_data { + const struct amb_pinmux_group *groups; + const struct pinfunction *functions; + unsigned int ngroups; + unsigned int nfunctions; + unsigned int nr_banks; + unsigned int npins; + unsigned int ds0[AMBA_MAX_BANKS]; + unsigned int ds1[AMBA_MAX_BANKS]; + unsigned int ds2[AMBA_MAX_BANKS]; + unsigned int pull_en[AMBA_MAX_BANKS]; + unsigned int pull_dir[AMBA_MAX_BANKS]; + bool have_ds2; +}; + +extern const struct amb_pinctrl_data ambarella_cv75_pinctrl_data; + +#endif /* _PINCTRL_AMBARELLA_H */ From 707855c21198c6a0b73efa053ac4fe733cbe1985 Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Wed, 16 Sep 2026 12:04:35 +0900 Subject: [PATCH 082/106] pinctrl: pinctrl-generic-mux: Fix provider resource leak on re-parse The pinctrl core re-parses a consumer's pinctrl on every probe attempt (pinctrl_bind_pins() runs before the driver's probe(), and again on each deferred-probe retry or re-bind), so .dt_node_to_map() must be side-effect free and safe to call repeatedly. mux_pinmux_dt_node_to_map() instead allocated provider-side resources on every call - the mux_pin_function, the group name table and a mux_state reference, plus a group name and a pinctrl_generic_add_group() registration via pinctrl_generic_to_map(). All of these are allocated with devm_*() against the provider device, so they live for the provider's lifetime and are only released when the provider itself is unbound. The .dt_free_map() path never touches them; it frees the per-consumer pinctrl_map only. Every re-parse therefore adds another set of provider-side allocations that are never reclaimed, so a consumer that repeatedly defers probe or is re-bound leaks memory and mux_state references on the provider without bound. The groups and functions of a board-level mux are static and fully described by the device tree, so build them once at probe time in the new mux_pinctrl_probe_dt(). mux_pinmux_dt_node_to_map() then only looks up the already registered group and builds the per-consumer mux map, which the core frees via .dt_free_map. As the mux has no pin electrical configuration, no config map is emitted. Reported-by: Sashiko Closes: https://sashiko.dev/#/patchset/20260824022020.2812810-1-chancel.liu%40oss.nxp.com Fixes: 34acc5a8adfb ("pinctrl: add generic board-level pinctrl driver using mux framework") Signed-off-by: Chancel Liu Assisted-by: LLM Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-generic-mux.c | 76 ++++++++++++++++++++------- 1 file changed, 56 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/pinctrl-generic-mux.c b/drivers/pinctrl/pinctrl-generic-mux.c index 202b72351efb..de85b4e75eb8 100644 --- a/drivers/pinctrl/pinctrl-generic-mux.c +++ b/drivers/pinctrl/pinctrl-generic-mux.c @@ -10,13 +10,11 @@ #include #include #include -#include #include #include #include #include "core.h" -#include "pinconf.h" #include "pinmux.h" #include "pinctrl-utils.h" @@ -38,39 +36,73 @@ mux_pinmux_dt_node_to_map(struct pinctrl_dev *pctldev, struct pinctrl_map **maps, unsigned int *num_maps) { unsigned int num_reserved_maps = 0; - struct mux_pin_function *function; - const char **group_names; int ret; - function = devm_kzalloc(pctldev->dev, sizeof(*function), GFP_KERNEL); - if (!function) - return -ENOMEM; + *maps = NULL; + *num_maps = 0; - group_names = devm_kcalloc(pctldev->dev, 1, sizeof(*group_names), GFP_KERNEL); - if (!group_names) - return -ENOMEM; - - function->mux_state = devm_mux_state_get_from_np(pctldev->dev, NULL, np_config); - if (IS_ERR(function->mux_state)) - return PTR_ERR(function->mux_state); - - ret = pinctrl_generic_to_map(pctldev, np_config, np_config, maps, - num_maps, &num_reserved_maps, group_names, - 0, &np_config->name, NULL, 0); + if (pinctrl_get_group_selector(pctldev, np_config->name) < 0) + return -ENODEV; + ret = pinctrl_utils_reserve_map(pctldev, maps, &num_reserved_maps, + num_maps, 1); if (ret) return ret; - ret = pinmux_generic_add_function(pctldev, np_config->name, group_names, - 1, function); + ret = pinctrl_utils_add_map_mux(pctldev, maps, &num_reserved_maps, + num_maps, np_config->name, + np_config->name); if (ret < 0) { pinctrl_utils_free_map(pctldev, *maps, *num_maps); + *maps = NULL; + *num_maps = 0; return ret; } return 0; } +static int mux_pinctrl_probe_dt(struct pinctrl_dev *pctldev, + struct device_node *np) +{ + struct device *dev = pctldev->dev; + + for_each_available_child_of_node_scoped(np, grp) { + struct mux_pin_function *function; + const char **group_names; + int ret; + + function = devm_kzalloc(dev, sizeof(*function), GFP_KERNEL); + if (!function) + return -ENOMEM; + + group_names = devm_kcalloc(dev, 1, sizeof(*group_names), GFP_KERNEL); + if (!group_names) + return -ENOMEM; + + group_names[0] = grp->name; + + function->mux_state = devm_mux_state_get_from_np(dev, NULL, grp); + if (IS_ERR(function->mux_state)) + return dev_err_probe(dev, PTR_ERR(function->mux_state), + "failed to get mux-state for %pOFn\n", + grp); + + ret = pinctrl_generic_add_group(pctldev, grp->name, NULL, 0, NULL); + if (ret < 0) + return dev_err_probe(dev, ret, + "failed to add group %pOFn\n", grp); + + ret = pinmux_generic_add_function(pctldev, grp->name, group_names, + 1, function); + if (ret < 0) + return dev_err_probe(dev, ret, + "failed to add function %pOFn\n", grp); + } + + return 0; +} + static const struct pinctrl_ops mux_pinctrl_ops = { .get_groups_count = pinctrl_generic_get_group_count, .get_group_name = pinctrl_generic_get_group_name, @@ -157,6 +189,10 @@ static int mux_pinctrl_probe(struct platform_device *pdev) if (ret) return dev_err_probe(dev, ret, "Failed to register pinctrl.\n"); + ret = mux_pinctrl_probe_dt(mpctl->pctl, dev->of_node); + if (ret) + return ret; + ret = pinctrl_enable(mpctl->pctl); if (ret) return dev_err_probe(dev, ret, "Failed to enable pinctrl.\n"); From d1c4db1ad4f3093535c1271088d11f7f3176eea4 Mon Sep 17 00:00:00 2001 From: Andrew Gaylard Date: Thu, 24 Sep 2026 18:03:44 +0200 Subject: [PATCH 083/106] pinctrl: sunplus: fix kernel-doc parameter descriptions in sppctl.c Add missing parameter descriptions to kernel-doc comments for sppctl_func_set(), sppctl_gmx_set(), sppctl_first_get(), sppctl_master_get(), and sppctl_fully_pinmux_conv(), fixing all W=1 kernel-doc warnings in this file. Improve the phrasing of some the other comments in this file, while we're at it. The warnings for sppctl_func_set() (@val) and sppctl_gmx_set() (@pctl) were newly introduced by commit 7dcf87d2dbbe ("pinctrl: fix PINCTRL_SPPCTL=m"); the rest were pre-existing. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202609240204.VHoUp5qw-lkp@intel.com/ Signed-off-by: Andrew Gaylard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunplus/sppctl.c | 45 ++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/sunplus/sppctl.c b/drivers/pinctrl/sunplus/sppctl.c index 67e036d66245..8a3fb9b56597 100644 --- a/drivers/pinctrl/sunplus/sppctl.c +++ b/drivers/pinctrl/sunplus/sppctl.c @@ -149,27 +149,30 @@ static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_ /** * sppctl_func_set() - Set pin of fully-pinmux function. + * @pctl: SP7021 pinctrl driver data + * @func: function number of the pinmux pin + * @val: value to write to the control-field * - * Mask-fields and control-fields of fully-pinmux function of SP7021 are - * arranged as shown below: + * Mask-fields and control-fields of the fully-pinmux function of + * SP7021 are arranged like this: * * func# | register | mask-field | control-field * -------+----------+--------------+--------------- * 0 | base[0] | (22 : 16) | ( 6 : 0) * 1 | base[0] | (30 : 24) | (14 : 8) * 2 | base[1] | (22 : 16) | ( 6 : 0) - * 3 | baeg[1] | (30 : 24) | (14 : 8) + * 3 | base[1] | (30 : 24) | (14 : 8) * : | : | : | : * - * where mask-fields are used to protect control-fields from write-in - * accidentally. Set the corresponding bits in the mask-field before - * you write a value into a control-field. + * where each mask-field protects its control-field from accidental + * writes. Set the corresponding bits in the mask-field when writing a + * value into a control-field. * * Control-fields are used to set where the function pin is going to * be routed to. * - * Note that mask-fields and control-fields of even number of 'func' - * are located at bits (22:16) and (6:0), while odd number of 'func's + * Note that mask-fields and control-fields of even number 'func's + * are located at bits (22:16) and (6:0), while odd number 'func's * are located at bits (30:24) and (14:8). */ static void sppctl_func_set(struct sppctl_pdata *pctl, u8 func, u8 val) @@ -206,9 +209,14 @@ static void sppctl_func_set(struct sppctl_pdata *pctl, u8 func, u8 val) /** * sppctl_gmx_set() - Set pin of group-pinmux. + * @pctl: SP7021 pinctrl driver data + * @reg_off: register offset from the base register + * @bit_off: bit offset within the register + * @bit_sz: size of the control-field in bits + * @val: value to write to the control-field * - * Mask-fields and control-fields of group-pinmux function of SP7021 are - * arranged as shown below: + * Mask-fields and control-fields of the group-pinmux function of + * SP7021 are arranged like this: * * register | mask-fields | control-fields * ----------+--------------+---------------- @@ -217,9 +225,9 @@ static void sppctl_func_set(struct sppctl_pdata *pctl, u8 func, u8 val) * base[2] | (31 : 24) | (15 : 0) * : | : | : * - * where mask-fields are used to protect control-fields from write-in - * accidentally. Set the corresponding bits in the mask-field before - * you write a value into a control-field. + * where each mask-field protects its control-field from accidental + * writes. Set the corresponding bits in the mask-field when writing a + * value into a control-field. * * Control-fields are used to set where the function pin is going to * be routed to. A control-field consists of one or more bits. @@ -242,6 +250,8 @@ static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 /** * sppctl_first_get() - get bit of FIRST register. + * @chip: GPIO chip data + * @offset: pin offset within the GPIO chip * * There are 4 FIRST registers. Each has 32 control-bits. * Totally, there are 4 * 32 = 128 control-bits. @@ -271,6 +281,8 @@ static int sppctl_first_get(struct gpio_chip *chip, unsigned int offset) /** * sppctl_master_get() - get bit of MASTER register. + * @chip: GPIO chip data + * @offset: pin offset within the GPIO chip * * There are 8 MASTER registers. Each has 16 mask-bits and 16 control-bits. * Upper 16-bit of MASTER registers are mask-bits while lower 16-bit are @@ -285,9 +297,9 @@ static int sppctl_first_get(struct gpio_chip *chip, unsigned int offset) * : | : | : * master[7] | (127 : 112) | (127 : 112) * - * where mask-bits are used to protect control-bits from write-in - * accidentally. Set the corresponding mask-bit before you write - * a value into a control-bit. + * where each mask-field protects its control-field from accidental + * writes. Set the corresponding bits in the mask-field when writing a + * value into a control-field. * * Each control-bit sets type of a GPIO pin when FIRST bit is 1. * 0: a IOP pin @@ -679,6 +691,7 @@ static int sppctl_get_function_groups(struct pinctrl_dev *pctldev, unsigned int /** * sppctl_fully_pinmux_conv - Convert GPIO# to fully-pinmux control-field setting + * @offset: GPIO pin number to convert * * Each fully-pinmux function can be mapped to any of GPIO 8 ~ 71 by * settings its control-field. Refer to following table: From d0833b246581567f8d513e1c7bb52e65690e69d6 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Thu, 17 Sep 2026 14:14:53 -0700 Subject: [PATCH 084/106] pinctrl: s32cc: Remove const from groups allocation type In preparation for making the devm_kmalloc family of allocators type aware, we need to make sure that the returned type from the allocation matches the type of the variable being assigned. (Before, the allocator would always return "void *", which can be implicitly cast to any pointer type.) The assigned type is "const char **", but the converted allocation type would be "const char * const *", as the size was taken from "*func->groups", whose type "const char * const" is const qualified. As there is no general way to remove const qualifiers, take the size from the assignment target instead. No change in allocation size results. Build tested ARCH=arm64 allmodconfig with GCC aarch64-linux-gnu 16.1.0: drivers/pinctrl/nxp/pinctrl-s32cc.o Assisted-by: LLM coccinelle Signed-off-by: Kees Cook Reviewed-by: Ghennadi Procopciuc Signed-off-by: Linus Walleij --- drivers/pinctrl/nxp/pinctrl-s32cc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c index 4b40770a38b7..9c4ebae22674 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -825,7 +825,7 @@ static int s32_pinctrl_parse_functions(struct device_node *np, "No groups defined in %pOF\n", np); groups = devm_kcalloc(info->dev, func->ngroups, - sizeof(*func->groups), GFP_KERNEL); + sizeof(*groups), GFP_KERNEL); if (!groups) return -ENOMEM; From 0b056aef31602cd10d2b35adc4746781b4fb8609 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Sat, 26 Sep 2026 18:04:14 +0800 Subject: [PATCH 085/106] pinctrl: mediatek: mt7629: fix the 2.4 GHz Wi-Fi pin mode array The wf0_2g group contains nine pins but only eight mux values. mtk_pinmux_set_mux() indexes the mode array once for each pin, reading past its end when configuring pin 78 (WF0_2G_HB6). This can select an unrelated mux value or fail with -EINVAL, preventing the Wi-Fi device from probing. Add the missing mode 1 entry for WF0_2G_HB6. Fixes: b44677375fee ("pinctrl: mediatek: add pinctrl support for MT7629 SoC") Signed-off-by: Chuanhong Guo Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mt7629.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/drivers/pinctrl/mediatek/pinctrl-mt7629.c index 385d66b8e3fb..29a4c171e8b6 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c @@ -294,7 +294,7 @@ static int mt7629_pwm_1_funcs[] = { 2, }; /* WF 2G */ static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, }; -static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; +static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, }; /* WF 5G */ static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, }; From 337cdfc8779eb93d2f4a877c2dcf4d56b1afed8c Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 1 Oct 2026 14:37:30 +0200 Subject: [PATCH 086/106] MAINTAINERS: add git tree for the Qualcomm pin control entry I stage Qualcomm pin control changes in my own tree before sending them upstream to Linus Walleij. Add a git URL to the MAINTAINERS entry. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Linus Walleij --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 96c32bc7dd91..56e5e38dd4f2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22601,6 +22601,7 @@ QUALCOMM PINCTRL DRIVERS M: Bartosz Golaszewski L: linux-arm-msm@vger.kernel.org S: Supported +T: git git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git F: Documentation/devicetree/bindings/pinctrl/qcom,*.yaml F: drivers/pinctrl/qcom/ From 3fb206b9b2bbe6fef175a47bee6dc588993700ac Mon Sep 17 00:00:00 2001 From: Yureka Lilian Date: Sat, 26 Sep 2026 16:51:45 +0200 Subject: [PATCH 087/106] dt-bindings: pinctrl: apple,pinctrl: Add t8140 compatible The pinctrl_ap GPIO controller on the MacBook Neo crashes upon reading REG_GPIOx for certain pins. These pins, which are also listed in Apple's device tree, are described by the gpio-reserved-ranges property. Signed-off-by: Yureka Lilian Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/apple,pinctrl.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index f08d2c4f5784..21cd666a8903 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -17,6 +17,7 @@ description: | properties: compatible: oneOf: + - const: apple,t8140-pinctrl - items: - enum: - apple,t6020-pinctrl @@ -51,6 +52,8 @@ properties: gpio-ranges: maxItems: 1 + gpio-reserved-ranges: true + apple,npins: $ref: /schemas/types.yaml#/definitions/uint32 description: The number of pins in this GPIO controller. @@ -89,6 +92,15 @@ patternProperties: allOf: - $ref: pinctrl.yaml# + - if: + not: + properties: + compatible: + contains: + const: apple,t8140-pinctrl + then: + properties: + gpio-reserved-ranges: false required: - compatible From ee8e9a7bea33f240184b45efced1e523fbbc6767 Mon Sep 17 00:00:00 2001 From: Yureka Lilian Date: Sat, 26 Sep 2026 16:51:46 +0200 Subject: [PATCH 088/106] pinctrl: apple: Add t8140-pinctrl support Ensure the regmap does not attempt to read REG_GPIOx of any of the pins marked with gpio-reserved-ranges. For this purpose, move the regmap_init just before the first regmap_read, at which point the valid_mask has been populated from the gpio-reserved-ranges device tree property. With this, make the driver accept the new t8140 base compatible as with this modifications the driver can now be loaded on this SoC without crashing. Signed-off-by: Yureka Lilian Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-apple-gpio.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index 6305b96aaa73..6b26a23d283c 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -66,6 +66,13 @@ struct apple_gpio_pinctrl { #define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22) #define REG_IRQ(g, x) (0x800 + 0x40 * (g) + 4 * ((x) >> 5)) +static bool apple_gpio_readable_register(struct device *dev, unsigned int reg) +{ + struct apple_gpio_pinctrl *pctl = dev_get_drvdata(dev); + + return gpiochip_line_is_valid(&pctl->gpio_chip, reg / 4); +} + static const struct regmap_config regmap_config = { .reg_bits = 32, .val_bits = 32, @@ -75,6 +82,7 @@ static const struct regmap_config regmap_config = { .num_reg_defaults_raw = 512, .use_relaxed_mmio = true, .use_raw_spinlock = true, + .readable_reg = apple_gpio_readable_register, }; /* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */ @@ -90,6 +98,13 @@ static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl, int ret; u32 val; + if (!pctl->map) { + pctl->map = devm_regmap_init_mmio(pctl->dev, pctl->base, ®map_config); + if (IS_ERR(pctl->map)) + return dev_err_probe(pctl->dev, PTR_ERR(pctl->map), + "Failed to create regmap\n"); + } + ret = regmap_read(pctl->map, REG_GPIO(pin), &val); if (ret) return 0; @@ -475,11 +490,6 @@ static int apple_gpio_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(pctl->base)) return PTR_ERR(pctl->base); - pctl->map = devm_regmap_init_mmio(&pdev->dev, pctl->base, ®map_config); - if (IS_ERR(pctl->map)) - return dev_err_probe(&pdev->dev, PTR_ERR(pctl->map), - "Failed to create regmap\n"); - for (i = 0; i < npins; i++) { pins[i].number = i; pins[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "PIN%u", i); @@ -522,6 +532,7 @@ static int apple_gpio_pinctrl_probe(struct platform_device *pdev) } static const struct of_device_id apple_gpio_pinctrl_of_match[] = { + { .compatible = "apple,t8140-pinctrl", }, { .compatible = "apple,t8103-pinctrl", }, { .compatible = "apple,pinctrl", }, { } From 06a4459733daf58d983e59bc2a72aa5ff39fa6d9 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 2 Oct 2026 14:46:20 +0200 Subject: [PATCH 089/106] pinctrl: ambarella: add CONFIG_OF dependency On randconfig builds without CONFIG_OF, this driver fails to link: x86_64-linux-ld: vmlinux.o: in function `pinconf_generic_dt_node_to_map_all': pinctrl-ambarella.c:(.text+0x54cdf0): undefined reference to `pinconf_generic_dt_node_to_map' Enforce OF as a dependency as we do for other such drivers. Fixes: b40e9d140c24 ("pinctrl: ambarella: add CV75 pin controller") Signed-off-by: Arnd Bergmann Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 78c252ccd73f..26b07ae84672 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -41,6 +41,7 @@ config PINCTRL_AMB bool "Ambarella pin controller support" depends on ARCH_AMBARELLA || COMPILE_TEST depends on HAS_IOMEM + depends on OF default y if ARCH_AMBARELLA select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS From b89f7dd31aa319b2e9a8c50ee7d4755031fecce6 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 2 Oct 2026 14:47:15 +0200 Subject: [PATCH 090/106] pinctrl: starfive: fix missing CONFIG_OF dependencies The common driver portion requires CONFIG_OF, but the drivers selecting it do not, so we get random warnings: WARNING: unmet direct dependencies detected for PINCTRL_STARFIVE_JHB100 Depends on [n]: PINCTRL [=y] && OF [=n] Selected by [y]: - PINCTRL_STARFIVE_JHB100_PER1 [=y] && PINCTRL [=y] && (ARCH_STARFIVE || COMPILE_TEST [=y]) - PINCTRL_STARFIVE_JHB100_PER2POK [=y] && PINCTRL [=y] && (ARCH_STARFIVE || COMPILE_TEST [=y]) - PINCTRL_STARFIVE_JHB100_SYS1 [=y] && PINCTRL [=y] && (ARCH_STARFIVE || COMPILE_TEST [=y]) Selected by [m]: - PINCTRL_STARFIVE_JHB100_PER0 [=m] && PINCTRL [=y] && (ARCH_STARFIVE || COMPILE_TEST [=y]) - PINCTRL_STARFIVE_JHB100_SYS0 [=m] && PINCTRL [=y] && (ARCH_STARFIVE || COMPILE_TEST [=y]) Apparently the problem is selecting CONFIG_OF_GPIO, which is a mistake the newly added driver copied from others. This was recently cleaned up with commit e785c990adcc ("pinctrl: Kconfig: drop unneeded dependencies on OF_GPIO"). Do the same here for consistency and to avoid the warning. Fixes: 9c4d0c8fc4c1 ("pinctrl: starfive: Add StarFive JHB100 sys0 controller driver") Signed-off-by: Arnd Bergmann Reviewed-by: Changhuang Liang Signed-off-by: Linus Walleij --- drivers/pinctrl/starfive/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index 11bd429b45b7..7ff506a15dd8 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -50,11 +50,9 @@ config PINCTRL_STARFIVE_JH7110_AON config PINCTRL_STARFIVE_JHB100 bool - depends on OF select GENERIC_PINCTRL select GPIOLIB select GPIOLIB_IRQCHIP - select OF_GPIO config PINCTRL_STARFIVE_JHB100_PER0 tristate "StarFive JHB100 SoC Peripheral-0 pinctrl and GPIO driver" From 39b717b20c09028ee293b949a96325c0aa89a1a0 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 2 Oct 2026 17:42:04 +0300 Subject: [PATCH 091/106] pinctrl: ambarella: fix NULL vs IS_ERR() bug in amb_pinctrl_register() The devm_kasprintf_strarray() function never returns NULL, it returns error pointers on error or a valid pointer on success. Fix the error checking to match. Fixes: b40e9d140c24 ("pinctrl: ambarella: add CV75 pin controller") Signed-off-by: Dan Carpenter Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ambarella.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ambarella.c b/drivers/pinctrl/pinctrl-ambarella.c index 83afef6a123f..5ed1010c5ce5 100644 --- a/drivers/pinctrl/pinctrl-ambarella.c +++ b/drivers/pinctrl/pinctrl-ambarella.c @@ -426,8 +426,8 @@ static int amb_pinctrl_register(struct amb_pinctrl *ipc) return -ENOMEM; names = devm_kasprintf_strarray(ipc->dev, "io", ipc->data->npins); - if (!names) - return -ENOMEM; + if (IS_ERR(names)) + return PTR_ERR(names); for (unsigned int pin = 0; pin < ipc->data->npins; pin++) { pindesc[pin].number = pin; From b40fd714e5f90ad309148a64ea8ab4104ba3a6cb Mon Sep 17 00:00:00 2001 From: Alex Tran Date: Thu, 17 Sep 2026 15:55:55 -0700 Subject: [PATCH 092/106] pinctrl: scmi: Replace pinmux ops get function info with generics During probe, populate the pinctrl device with function info so that the generic callbacks can be used to fetch function count, name, and groups. Remove locally stored functions since caching them in this driver is no longer needed. Signed-off-by: Alex Tran Acked-by: Sudeep Holla Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-scmi.c | 151 +++++++++++++-------------------- 1 file changed, 61 insertions(+), 90 deletions(-) diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c index 1bb36ca477b7..1d85a16f300d 100644 --- a/drivers/pinctrl/pinctrl-scmi.c +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -24,6 +24,7 @@ #include "pinctrl-utils.h" #include "core.h" #include "pinconf.h" +#include "pinmux.h" #define DRV_NAME "scmi-pinctrl" @@ -37,8 +38,6 @@ struct scmi_pinctrl { struct scmi_protocol_handle *ph; struct pinctrl_dev *pctldev; struct pinctrl_desc pctl_desc; - struct pinfunction *functions; - unsigned int nr_functions; }; static int pinctrl_scmi_get_groups_count(struct pinctrl_dev *pctldev) @@ -84,86 +83,6 @@ static const struct pinctrl_ops pinctrl_scmi_pinctrl_ops = { #endif }; -static int pinctrl_scmi_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pinctrl_ops->count_get(pmx->ph, FUNCTION_TYPE); -} - -static const char *pinctrl_scmi_get_function_name(struct pinctrl_dev *pctldev, - unsigned int selector) -{ - int ret; - const char *name; - struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - - ret = pinctrl_ops->name_get(pmx->ph, selector, FUNCTION_TYPE, &name); - if (ret) { - dev_err(pmx->dev, "get name failed with err %d", ret); - return NULL; - } - - return name; -} - -static int pinctrl_scmi_get_function_groups(struct pinctrl_dev *pctldev, - unsigned int selector, - const char * const **p_groups, - unsigned int * const p_num_groups) -{ - struct pinfunction *func; - const unsigned int *group_ids; - unsigned int num_groups; - const char **groups; - int ret, i; - struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - - if (!p_groups || !p_num_groups) - return -EINVAL; - - if (selector >= pmx->nr_functions) - return -EINVAL; - - func = &pmx->functions[selector]; - if (func->ngroups) - goto done; - - ret = pinctrl_ops->function_groups_get(pmx->ph, selector, &num_groups, - &group_ids); - if (ret) { - dev_err(pmx->dev, "Unable to get function groups, err %d", ret); - return ret; - } - if (!num_groups) - return -EINVAL; - - groups = kcalloc(num_groups, sizeof(*groups), GFP_KERNEL); - if (!groups) - return -ENOMEM; - - for (i = 0; i < num_groups; i++) { - groups[i] = pinctrl_scmi_get_group_name(pctldev, group_ids[i]); - if (!groups[i]) { - ret = -EINVAL; - goto err_free; - } - } - - func->ngroups = num_groups; - func->groups = groups; -done: - *p_groups = func->groups; - *p_num_groups = func->ngroups; - - return 0; - -err_free: - kfree(groups); - - return ret; -} - static int pinctrl_scmi_func_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, unsigned int group) { @@ -190,9 +109,9 @@ static int pinctrl_scmi_free(struct pinctrl_dev *pctldev, unsigned int offset) static const struct pinmux_ops pinctrl_scmi_pinmux_ops = { .request = pinctrl_scmi_request, .free = pinctrl_scmi_free, - .get_functions_count = pinctrl_scmi_get_functions_count, - .get_function_name = pinctrl_scmi_get_function_name, - .get_function_groups = pinctrl_scmi_get_function_groups, + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, .set_mux = pinctrl_scmi_func_set_mux, }; @@ -487,6 +406,60 @@ static const struct pinconf_ops pinctrl_scmi_pinconf_ops = { .pin_config_config_dbg_show = pinconf_generic_dump_config, }; +static int pinctrl_scmi_get_functions(struct scmi_pinctrl *pmx) +{ + unsigned int nr_funcs, nr_groups, i, j; + const unsigned int *group_ids; + const char *fname; + const char **gnames; + int ret; + + nr_funcs = pinctrl_ops->count_get(pmx->ph, FUNCTION_TYPE); + + for (i = 0; i < nr_funcs; i++) { + ret = pinctrl_ops->name_get(pmx->ph, i, FUNCTION_TYPE, + &fname); + if (ret) + return ret; + + ret = pinctrl_ops->function_groups_get(pmx->ph, i, + &nr_groups, + &group_ids); + if (ret) + return ret; + + if (!nr_groups) + dev_warn(pmx->dev, + "Function %s contains no groups\n", + fname); + + gnames = devm_kmalloc_array(pmx->dev, nr_groups, + sizeof(*gnames), GFP_KERNEL); + if (!gnames) + return -ENOMEM; + + for (j = 0; j < nr_groups; j++) { + ret = pinctrl_ops->name_get(pmx->ph, group_ids[j], + GROUP_TYPE, &gnames[j]); + if (ret) + return ret; + } + + ret = pinmux_generic_add_function(pmx->pctldev, fname, gnames, + nr_groups, NULL); + if (ret < 0) + return ret; + if (ret != i) { + dev_err(pmx->dev, + "Duplicate function name: %s index: %u selector: %d\n", + fname, i, ret); + return -EINVAL; + } + } + + return 0; +} + static int pinctrl_scmi_get_pins(struct scmi_pinctrl *pmx, struct pinctrl_desc *desc) { @@ -571,11 +544,9 @@ static int scmi_pinctrl_probe(struct scmi_device *sdev) if (ret) return dev_err_probe(dev, ret, "Failed to register pinctrl\n"); - pmx->nr_functions = pinctrl_scmi_get_functions_count(pmx->pctldev); - pmx->functions = devm_kcalloc(dev, pmx->nr_functions, - sizeof(*pmx->functions), GFP_KERNEL); - if (!pmx->functions) - return -ENOMEM; + ret = pinctrl_scmi_get_functions(pmx); + if (ret) + return dev_err_probe(dev, ret, "Failed to register functions\n"); return pinctrl_enable(pmx->pctldev); } From 5218b9ab39c96303862b5ad02bce6cbe066a4349 Mon Sep 17 00:00:00 2001 From: Alex Tran Date: Thu, 17 Sep 2026 15:55:56 -0700 Subject: [PATCH 093/106] pinctrl: scmi: Replace pinctrl ops get group info with generics During probe, populate the pinctrl device with group info so that the generic callbacks can be used to fetch group count, name, and pins. Signed-off-by: Alex Tran Acked-by: Sudeep Holla Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-scmi.c | 81 +++++++++++++++++++--------------- 1 file changed, 45 insertions(+), 36 deletions(-) diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c index 1d85a16f300d..c93d61dfa282 100644 --- a/drivers/pinctrl/pinctrl-scmi.c +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -40,43 +40,10 @@ struct scmi_pinctrl { struct pinctrl_desc pctl_desc; }; -static int pinctrl_scmi_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pinctrl_ops->count_get(pmx->ph, GROUP_TYPE); -} - -static const char *pinctrl_scmi_get_group_name(struct pinctrl_dev *pctldev, - unsigned int selector) -{ - int ret; - const char *name; - struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - - ret = pinctrl_ops->name_get(pmx->ph, selector, GROUP_TYPE, &name); - if (ret) { - dev_err(pmx->dev, "get name failed with err %d", ret); - return NULL; - } - - return name; -} - -static int pinctrl_scmi_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int selector, - const unsigned int **pins, - unsigned int *num_pins) -{ - struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pinctrl_ops->group_pins_get(pmx->ph, selector, pins, num_pins); -} - static const struct pinctrl_ops pinctrl_scmi_pinctrl_ops = { - .get_groups_count = pinctrl_scmi_get_groups_count, - .get_group_name = pinctrl_scmi_get_group_name, - .get_group_pins = pinctrl_scmi_get_group_pins, + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, #ifdef CONFIG_OF .dt_node_to_map = pinconf_generic_dt_node_to_map_all, .dt_free_map = pinconf_generic_dt_free_map, @@ -460,6 +427,44 @@ static int pinctrl_scmi_get_functions(struct scmi_pinctrl *pmx) return 0; } +static int pinctrl_scmi_get_groups(struct scmi_pinctrl *pmx) +{ + unsigned int nr_groups, nr_pins, i; + const unsigned int *pins; + const char *gname; + int ret; + + nr_groups = pinctrl_ops->count_get(pmx->ph, GROUP_TYPE); + + for (i = 0; i < nr_groups; i++) { + ret = pinctrl_ops->name_get(pmx->ph, i, GROUP_TYPE, &gname); + if (ret) + return ret; + + ret = pinctrl_ops->group_pins_get(pmx->ph, i, &pins, + &nr_pins); + if (ret) + return ret; + + if (!nr_pins) + dev_warn(pmx->dev, + "Group %s contains no pins\n", gname); + + ret = pinctrl_generic_add_group(pmx->pctldev, gname, pins, + nr_pins, NULL); + if (ret < 0) + return ret; + if (ret != i) { + dev_err(pmx->dev, + "Duplicate group name: %s index: %u selector: %d\n", + gname, i, ret); + return -EINVAL; + } + } + + return 0; +} + static int pinctrl_scmi_get_pins(struct scmi_pinctrl *pmx, struct pinctrl_desc *desc) { @@ -544,6 +549,10 @@ static int scmi_pinctrl_probe(struct scmi_device *sdev) if (ret) return dev_err_probe(dev, ret, "Failed to register pinctrl\n"); + ret = pinctrl_scmi_get_groups(pmx); + if (ret) + return dev_err_probe(dev, ret, "Failed to register groups\n"); + ret = pinctrl_scmi_get_functions(pmx); if (ret) return dev_err_probe(dev, ret, "Failed to register functions\n"); From c4e625828ac1b9dba1c055c6d631b447e44b0ab5 Mon Sep 17 00:00:00 2001 From: Alex Tran Date: Thu, 17 Sep 2026 15:55:57 -0700 Subject: [PATCH 094/106] pinctrl: kconfig: Select generic pinctrl helpers for scmi pinctrl Select the corresponding pinctrl and pinmux generic Kconfig symbols when PINCTRL_SCMI is enabled. Signed-off-by: Alex Tran Acked-by: Sudeep Holla Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 26b07ae84672..dc7138302c55 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -553,6 +553,8 @@ config PINCTRL_SCMI tristate "Pinctrl driver using SCMI protocol interface" depends on ARM_SCMI_PROTOCOL || COMPILE_TEST select PINMUX + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF help This driver provides support for pinctrl which is controlled From e873c665e503ebfb6dafaf9346c3956695686226 Mon Sep 17 00:00:00 2001 From: Jiale Yao Date: Sat, 3 Oct 2026 16:31:54 +0800 Subject: [PATCH 095/106] pinctrl: sprd: free maps on DT map failure sprd_dt_node_to_map() reserves map storage before adding mux and configuration entries. If a later operation fails, the error path only frees the temporary configurations and leaves the map allocation reachable through the output pointer. Free the partially built map on failure. The caller ignores the output parameters when the mapping callback returns an error, so they do not need to be reset after freeing the map. Fixes: 41d32cfce1ae ("pinctrl: sprd: Add Spreadtrum pin control driver") Signed-off-by: Jiale Yao Reviewed-by: Baolin Wang Signed-off-by: Linus Walleij --- drivers/pinctrl/sprd/pinctrl-sprd.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c index 16cf9d15f247..a565d4fd4233 100644 --- a/drivers/pinctrl/sprd/pinctrl-sprd.c +++ b/drivers/pinctrl/sprd/pinctrl-sprd.c @@ -326,6 +326,9 @@ static int sprd_dt_node_to_map(struct pinctrl_dev *pctldev, out: kfree(configs); + if (ret < 0) + pinctrl_utils_free_map(pctldev, *map, *num_maps); + return ret; } From efd9330bb69732868a0ecc83df0a00553096bc8f Mon Sep 17 00:00:00 2001 From: Jiale Yao Date: Sat, 3 Oct 2026 16:31:56 +0800 Subject: [PATCH 096/106] pinctrl: tegra: xusb: free maps on DT map failure tegra_xusb_padctl_parse_subnode() can append mappings before a later child or configuration operation fails. The top-level callback currently returns the error while retaining all mappings allocated for earlier children. Free the accumulated map on failure. The caller ignores the output parameters when the mapping callback returns an error, so they do not need to be reset after freeing the map. Signed-off-by: Jiale Yao Signed-off-by: Linus Walleij --- drivers/pinctrl/tegra/pinctrl-tegra-xusb.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c index c6a51bb21215..fb70f8aee56b 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c @@ -248,10 +248,14 @@ static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl, &reserved_maps, num_maps); if (err < 0) - return err; + goto err_free_map; } return 0; + +err_free_map: + pinctrl_utils_free_map(pinctrl, *maps, *num_maps); + return err; } static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = { From 26f6997b9bb2dcb4fc657fdcfc7f549fe43e78a2 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Fri, 25 Sep 2026 18:52:43 +0000 Subject: [PATCH 097/106] dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Pull pinctrl node changes from MT6795 document mediatek,pinctrl-mt6795.yaml has different node name patterns which match bindings of other MediaTek pin controllers, ref for pinmux-node.yaml which has a description of the pinmux property, as well as some additional descriptions for some pin configuration properties. Pull those changes into mediatek,mt6779-pinctrl.yaml and adjust the example DTS to match in preparation to combine the MT6795 document into it. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Linus Walleij --- .../pinctrl/mediatek,mt6779-pinctrl.yaml | 36 ++++++++++++++----- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index f4bab7a132d3..0dcbca5ca8f9 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -111,12 +111,12 @@ allOf: - "#interrupt-cells" patternProperties: - '-[0-9]*$': + '-pins$': type: object additionalProperties: false patternProperties: - '-pins*$': + '^pins': type: object description: A pinctrl node should contain at least one subnodes representing the @@ -124,7 +124,9 @@ patternProperties: pins it needs, and how they should be configured, with regard to muxer configuration, pullups, drive strength, input enable/disable and input schmitt. - $ref: /schemas/pinctrl/pincfg-node.yaml + allOf: + - $ref: pinmux-node.yaml + - $ref: pincfg-node.yaml properties: pinmux: @@ -135,9 +137,25 @@ patternProperties: bias-disable: true - bias-pull-up: true + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: Pull up PUPD/R0/R1 type define value. + description: | + For normal pull up type, it is not necessary to specify R1R0 + values; When pull up type is PUPD/R0/R1, adding R1R0 defines + will set different resistance values. - bias-pull-down: true + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: Pull down PUPD/R0/R1 type define value. + description: | + For normal pull down type, it is not necessary to specify R1R0 + values; When pull down type is PUPD/R0/R1, adding R1R0 defines + will set different resistance values. input-enable: true @@ -221,8 +239,8 @@ examples: #interrupt-cells = <2>; interrupts = ; - mmc0_pins_default: mmc0-0 { - cmd-dat-pins { + mmc0_pins_default: mmc0-pins { + pins-cmd-dat { pinmux = , , , @@ -235,11 +253,11 @@ examples: input-enable; mediatek,pull-up-adv = <1>; }; - clk-pins { + pins-clk { pinmux = ; mediatek,pull-down-adv = <2>; }; - rst-pins { + pins-rst { pinmux = ; mediatek,pull-up-adv = <0>; }; From 7617cd520387f230b7c2301e82671a0aeb8455a2 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Fri, 25 Sep 2026 18:52:57 +0000 Subject: [PATCH 098/106] dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Improve pinctrl subnode and property descriptions Change "subnodes" to "subnode" in subnode description for better grammatical accuracy, wrap all descriptions at 80 characters, and remove literal style indicators from descriptions that don't need their new lines preserved. Signed-off-by: Yassine Oudjana Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring Signed-off-by: Linus Walleij --- .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index 0dcbca5ca8f9..4dc9504e24ad 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -119,11 +119,11 @@ patternProperties: '^pins': type: object description: - A pinctrl node should contain at least one subnodes representing the + A pinctrl node should contain at least one subnode representing the pinctrl groups available on the machine. Each subnode will list the - pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and input - schmitt. + pins it needs, and how they should be configured, with regard to + muxer configuration, pullups, drive strength, input enable/disable + and input schmitt. allOf: - $ref: pinmux-node.yaml - $ref: pincfg-node.yaml @@ -133,7 +133,8 @@ patternProperties: description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are - defined as macros in dt-bindings/pinctrl/-pinfunc.h directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h + directly. bias-disable: true @@ -142,7 +143,7 @@ patternProperties: - type: boolean - enum: [100, 101, 102, 103] description: Pull up PUPD/R0/R1 type define value. - description: | + description: For normal pull up type, it is not necessary to specify R1R0 values; When pull up type is PUPD/R0/R1, adding R1R0 defines will set different resistance values. @@ -152,7 +153,7 @@ patternProperties: - type: boolean - enum: [100, 101, 102, 103] description: Pull down PUPD/R0/R1 type define value. - description: | + description: For normal pull down type, it is not necessary to specify R1R0 values; When pull down type is PUPD/R0/R1, adding R1R0 defines will set different resistance values. From 2035f19379581a9014adb4482bef732a7fe85f1d Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Fri, 25 Sep 2026 18:53:10 +0000 Subject: [PATCH 099/106] dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Add MT6795 Combine MT6795 pin controller document into MT6779 one. In the process, amend the example with comments and additional pinctrl nodes from the MT6795 example, replace the current interrupts property description with the one from the MT6795 document since it makes more sense and define its items using conditionals as they now vary between variants. Also use conditionals to define valid values for the drive-strength property as well as items of the interrupts property for each variant since they are different on MT6795. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../pinctrl/mediatek,mt6779-pinctrl.yaml | 72 +++++- .../pinctrl/mediatek,mt6795-pinctrl.yaml | 236 ------------------ 2 files changed, 70 insertions(+), 238 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index 4dc9504e24ad..4df697103041 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -8,6 +8,7 @@ title: MediaTek MT6779 Pin Controller maintainers: - Andy Teng + - AngeloGioacchino Del Regno - Sean Wang description: @@ -18,6 +19,7 @@ properties: compatible: enum: - mediatek,mt6779-pinctrl + - mediatek,mt6795-pinctrl - mediatek,mt6797-pinctrl reg: @@ -81,6 +83,45 @@ allOf: - const: iocfg_lt - const: iocfg_tl - const: eint + + patternProperties: + '-pins$': + patternProperties: + '^pins': + properties: + drive-strength: + enum: [2, 4, 8, 12, 16] + + - if: + properties: + compatible: + contains: + const: mediatek,mt6795-pinctrl + then: + properties: + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: base + - const: eint + + interrupts: + minItems: 1 + items: + - description: EINT interrupt + - description: EINT event_b interrupt + + patternProperties: + '-pins$': + patternProperties: + '^pins': + properties: + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + - if: properties: compatible: @@ -99,6 +140,15 @@ allOf: - const: iocfgb - const: iocfgr - const: iocfgt + + patternProperties: + '-pins$': + patternProperties: + '^pins': + properties: + drive-strength: + enum: [2, 4, 8, 12, 16] + - if: properties: reg-names: @@ -170,10 +220,14 @@ patternProperties: input-schmitt-disable: true - drive-strength: - enum: [2, 4, 8, 12, 16] + drive-strength: true slew-rate: + description: | + Set the slew rate. Valid arguments are described as below: + 0: Normal slew rate + 1: Slower slew + $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] mediatek,pull-up-adv: @@ -263,5 +317,19 @@ examples: mediatek,pull-up-adv = <0>; }; }; + + /* GPIO0 set as multifunction GPIO0 */ + gpio-pins { + pins { + pinmux = ; + }; + }; + + /* GPIO52 set as multifunction SDA0 */ + i2c0-pins { + pins { + pinmux = ; + }; + }; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml deleted file mode 100644 index 9a937f414cc9..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml +++ /dev/null @@ -1,236 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: MediaTek MT6795 Pin Controller - -maintainers: - - AngeloGioacchino Del Regno - - Sean Wang - -description: - The MediaTek's MT6795 Pin controller is used to control SoC pins. - -properties: - compatible: - const: mediatek,mt6795-pinctrl - - gpio-controller: true - - '#gpio-cells': - description: - Number of cells in GPIO specifier. Since the generic GPIO binding is used, - the amount of cells must be specified as 2. See the below mentioned gpio - binding representation for description of particular cells. - const: 2 - - gpio-ranges: - description: GPIO valid number range. - maxItems: 1 - - reg: - description: - Physical address base for GPIO base and eint registers. - minItems: 2 - - reg-names: - items: - - const: base - - const: eint - - interrupt-controller: true - - '#interrupt-cells': - const: 2 - - interrupts: - description: Interrupt outputs to the system interrupt controller (sysirq). - minItems: 1 - items: - - description: EINT interrupt - - description: EINT event_b interrupt - -# PIN CONFIGURATION NODES -patternProperties: - '-pins$': - type: object - additionalProperties: false - patternProperties: - '^pins': - type: object - additionalProperties: false - description: | - A pinctrl node should contain at least one subnodes representing the - pinctrl groups available on the machine. Each subnode will list the - pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and input - schmitt. - An example of using macro: - pincontroller { - /* GPIO0 set as multifunction GPIO0 */ - gpio-pins { - pins { - pinmux = ; - } - }; - /* GPIO45 set as multifunction SDA0 */ - i2c0-pins { - pins { - pinmux = ; - } - }; - }; - $ref: pinmux-node.yaml - - properties: - pinmux: - description: - Integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and are - defined as macros in dt-bindings/pinctrl/-pinfunc.h directly. - - drive-strength: - enum: [2, 4, 6, 8, 10, 12, 14, 16] - - bias-pull-down: - oneOf: - - type: boolean - - enum: [100, 101, 102, 103] - description: mt6795 pull down PUPD/R0/R1 type define value. - description: - For normal pull down type, it is not necessary to specify R1R0 - values; When pull down type is PUPD/R0/R1, adding R1R0 defines - will set different resistance values. - - bias-pull-up: - oneOf: - - type: boolean - - enum: [100, 101, 102, 103] - description: mt6795 pull up PUPD/R0/R1 type define value. - description: - For normal pull up type, it is not necessary to specify R1R0 - values; When pull up type is PUPD/R0/R1, adding R1R0 defines will - set different resistance values. - - bias-disable: true - - output-high: true - - output-low: true - - input-enable: true - - input-disable: true - - input-schmitt-enable: true - - input-schmitt-disable: true - - mediatek,pull-up-adv: - description: | - Pull up settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as - below: - 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. - 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. - 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. - 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3] - - mediatek,pull-down-adv: - description: | - Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as - below: - 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. - 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. - 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. - 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3] - - slew-rate: - description: | - Set the slew rate. Valid arguments are described as below: - 0: Normal slew rate - 1: Slower slew - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - required: - - pinmux - -allOf: - - $ref: pinctrl.yaml# - -required: - - compatible - - reg - - reg-names - - interrupts - - interrupt-controller - - '#interrupt-cells' - - gpio-controller - - '#gpio-cells' - - gpio-ranges - -additionalProperties: false - -examples: - - | - #include - #include - #include - - soc { - #address-cells = <2>; - #size-cells = <2>; - - pio: pinctrl@10005000 { - compatible = "mediatek,mt6795-pinctrl"; - reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; - reg-names = "base", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 196>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <2>; - - i2c0-pins { - pins-sda-scl { - pinmux = , - ; - }; - }; - - mmc0-pins { - pins-cmd-dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - bias-pull-up = ; - }; - - pins-clk { - pinmux = ; - bias-pull-down = ; - }; - - pins-rst { - pinmux = ; - bias-pull-up = ; - }; - }; - }; - }; From a2be6087ed05fe3562c2d23c88621e818d71b767 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Fri, 25 Sep 2026 18:53:23 +0000 Subject: [PATCH 100/106] dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Document MT6765 pin controller The MT6765 pin controller has had a driver for a while, but DT bindings were never documented for it. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Linus Walleij --- .../pinctrl/mediatek,mt6779-pinctrl.yaml | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index 4df697103041..94117008ebf9 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -18,6 +18,7 @@ description: properties: compatible: enum: + - mediatek,mt6765-pinctrl - mediatek,mt6779-pinctrl - mediatek,mt6795-pinctrl - mediatek,mt6797-pinctrl @@ -61,6 +62,41 @@ required: allOf: - $ref: pinctrl.yaml# + - if: + properties: + compatible: + contains: + const: mediatek,mt6765-pinctrl + then: + properties: + reg: + minItems: 9 + maxItems: 9 + + reg-names: + items: + - const: iocfg0 + - const: iocfg1 + - const: iocfg2 + - const: iocfg3 + - const: iocfg4 + - const: iocfg5 + - const: iocfg6 + - const: iocfg7 + - const: eint + + interrupts: + items: + - description: EINT interrupt + + patternProperties: + '-pins$': + patternProperties: + '^pins': + properties: + drive-strength: + enum: [1, 2, 4, 16] + - if: properties: compatible: From c0610dccfc3f2eee8187020ee796d1f591ecad83 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Fri, 25 Sep 2026 18:53:39 +0000 Subject: [PATCH 101/106] dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Add bindings for MT6735 pin controller Add DT bindings for the MT6735 pin controller. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../pinctrl/mediatek,mt6779-pinctrl.yaml | 39 + MAINTAINERS | 7 + .../pinctrl/mediatek,mt6735-pinfunc.h | 1148 +++++++++++++++++ 3 files changed, 1194 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mediatek,mt6735-pinfunc.h diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index 94117008ebf9..5b61da80da8b 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -10,6 +10,7 @@ maintainers: - Andy Teng - AngeloGioacchino Del Regno - Sean Wang + - Yassine Oudjana description: The MediaTek pin controller on MT6779 is used to control pin functions, pull @@ -18,6 +19,8 @@ description: properties: compatible: enum: + - mediatek,mt6735-pinctrl + - mediatek,mt6735m-pinctrl - mediatek,mt6765-pinctrl - mediatek,mt6779-pinctrl - mediatek,mt6795-pinctrl @@ -62,6 +65,42 @@ required: allOf: - $ref: pinctrl.yaml# + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt6735-pinctrl + - mediatek,mt6735m-pinctrl + then: + properties: + reg: + minItems: 8 + maxItems: 8 + + reg-names: + items: + - const: gpio + - const: iocfg0 + - const: iocfg1 + - const: iocfg2 + - const: iocfg3 + - const: iocfg4 + - const: iocfg5 + - const: eint + + interrupts: + items: + - description: EINT interrupt + + patternProperties: + '-pins$': + patternProperties: + '^pins': + properties: + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + - if: properties: compatible: diff --git a/MAINTAINERS b/MAINTAINERS index 56e5e38dd4f2..92069eaad2cb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21559,6 +21559,13 @@ F: drivers/pinctrl/mediatek/pinctrl-rt2880.c F: drivers/pinctrl/mediatek/pinctrl-rt305x.c F: drivers/pinctrl/mediatek/pinctrl-rt3883.c +PIN CONTROLLER - MEDIATEK MT6735 +M: Yassine Oudjana +L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +F: include/dt-bindings/pinctrl/mediatek,mt6735-pinfunc.h + PIN CONTROLLER - MICROCHIP AT91 M: Ludovic Desroches L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/include/dt-bindings/pinctrl/mediatek,mt6735-pinfunc.h b/include/dt-bindings/pinctrl/mediatek,mt6735-pinfunc.h new file mode 100644 index 000000000000..bc7c9fc4548d --- /dev/null +++ b/include/dt-bindings/pinctrl/mediatek,mt6735-pinfunc.h @@ -0,0 +1,1148 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Yassine Oudjana + */ + +#ifndef _DT_BINDINGS_PINCTRL_MEDIATEK_MT6735_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_MEDIATEK_MT6735_PINFUNC_H + +#include "mt65xx.h" + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_IDDIG (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_DPI_D4 (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_CLKM4 (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_PWM3 (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_KCOL2 (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_C2K_ARM_EINT0 (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_PWM2 (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_DPI_D5 (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_MD_EINT0 (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_TDD_TDO (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_PTA_RXD (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_C2K_ARM_EINT1 (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_CLKM0 (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_DPI_D6 (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_MD_EINT0 (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_USB_DRVVBUS (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_PTA_TXD (MTK_PIN_NO(2) | 6) +#define PINMUX_GPIO2__FUNC_C2K_ARM_EINT2 (MTK_PIN_NO(2) | 7) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_CLKM1 (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_DPI_D7 (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_SPI_MIB (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_MD_EINT0 (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(3) | 6) +#define PINMUX_GPIO3__FUNC_C2K_ARM_EINT3 (MTK_PIN_NO(3) | 7) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_CLKM2 (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_DPI_D8 (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_SPI_MOB (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_TDD_TCK (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_CONN_MCU_TCK_0 (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_UCTS2 (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_DPI_D9 (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_SPI_CSB (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_TDD_TDI (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_I2S1_DO (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_MD_URXD (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_URTS2 (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_DPI_D10 (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_SPI_CKB (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_TDD_TRSTN (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_I2S1_LRCK (MTK_PIN_NO(6) | 6) +#define PINMUX_GPIO6__FUNC_MD_UTXD (MTK_PIN_NO(6) | 7) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_UCTS3 (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_DPI_D11 (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_SDA1 (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_TDD_TMS (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_I2S1_BCK (MTK_PIN_NO(7) | 6) +#define PINMUX_GPIO7__FUNC_TDD_TXD (MTK_PIN_NO(7) | 7) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_URTS3 (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_C2K_UIM0_HOT_PLUG_IN (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_SCL1 (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_PCM1_DO1 (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_MD_EINT1 (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_KCOL4 (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_UTXD0 (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_PCM1_DO0 (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_I2S3_MCK (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_MD_EINT2 (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_CLKM2 (MTK_PIN_NO(9) | 5) +#define PINMUX_GPIO9__FUNC_I2S1_MCK (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_DBG_MON_A29 (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_PWM1 (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_CLKM1 (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_KROW2 (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_MD_EINT0 (MTK_PIN_NO(10) | 4) +#define PINMUX_GPIO10__FUNC_I2S1_MCK (MTK_PIN_NO(10) | 5) +#define PINMUX_GPIO10__FUNC_SDA3 (MTK_PIN_NO(10) | 6) +#define PINMUX_GPIO10__FUNC_DBG_MON_A30 (MTK_PIN_NO(10) | 7) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_MD_EINT1 (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_IRTX_OUT (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_C2K_UIM0_HOT_PLUG_IN (MTK_PIN_NO(11) | 3) +#define PINMUX_GPIO11__FUNC_CLKM0 (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_I2S2_MCK (MTK_PIN_NO(11) | 5) +#define PINMUX_GPIO11__FUNC_SCL3 (MTK_PIN_NO(11) | 6) +#define PINMUX_GPIO11__FUNC_URXD0 (MTK_PIN_NO(11) | 7) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_I2S0_MCK (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_KCOL2 (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_MD_EINT2 (MTK_PIN_NO(12) | 4) +#define PINMUX_GPIO12__FUNC_IRTX_OUT (MTK_PIN_NO(12) | 5) +#define PINMUX_GPIO12__FUNC_SRCLKENAI2 (MTK_PIN_NO(12) | 6) +#define PINMUX_GPIO12__FUNC_PCM1_DO1 (MTK_PIN_NO(12) | 7) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_WB_CTRL0 (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_C2K_ARM_EINT0 (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_DBG_MON_A0 (MTK_PIN_NO(13) | 7) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_WB_CTRL1 (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_C2K_ARM_EINT1 (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_DBG_MON_A1 (MTK_PIN_NO(14) | 7) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_WB_CTRL2 (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_C2K_ARM_EINT2 (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_DBG_MON_A2 (MTK_PIN_NO(15) | 7) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_WB_CTRL3 (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_C2K_ARM_EINT3 (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_DBG_MON_A3 (MTK_PIN_NO(16) | 7) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_WB_CTRL4 (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_WATCHDOG (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_DBG_MON_A4 (MTK_PIN_NO(17) | 7) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_WB_CTRL5 (MTK_PIN_NO(18) | 1) +#define PINMUX_GPIO18__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(18) | 3) +#define PINMUX_GPIO18__FUNC_DBG_MON_A5 (MTK_PIN_NO(18) | 7) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_ANT_SEL0 (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_IRTX_OUT (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_IRDA_TX (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_C2K_UART0_TXD (MTK_PIN_NO(19) | 4) +#define PINMUX_GPIO19__FUNC_GPS_FRAME_SYNC (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_LTE_UTXD (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_DBG_MON_A6 (MTK_PIN_NO(19) | 7) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_ANT_SEL1 (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_IRDA_RX (MTK_PIN_NO(20) | 3) +#define PINMUX_GPIO20__FUNC_C2K_UART0_RXD (MTK_PIN_NO(20) | 4) +#define PINMUX_GPIO20__FUNC_MD_EINT2 (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_LTE_URXD (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_DBG_MON_A7 (MTK_PIN_NO(20) | 7) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_ANT_SEL2 (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_PWM2 (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_IRDA_PDN (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_CORESONIC_SWCK (MTK_PIN_NO(21) | 4) +#define PINMUX_GPIO21__FUNC_MD_EINT1 (MTK_PIN_NO(21) | 5) +#define PINMUX_GPIO21__FUNC_C2K_UIM0_HOT_PLUG_IN (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_DBG_MON_A8 (MTK_PIN_NO(21) | 7) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_RDN0 (MTK_PIN_NO(22) | 1) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_RDP0 (MTK_PIN_NO(23) | 1) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_RDN1 (MTK_PIN_NO(24) | 1) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_RDP1 (MTK_PIN_NO(25) | 1) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_RCN (MTK_PIN_NO(26) | 1) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_RCP (MTK_PIN_NO(27) | 1) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_RDN2 (MTK_PIN_NO(28) | 1) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_RDP2 (MTK_PIN_NO(29) | 1) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_RDN3 (MTK_PIN_NO(30) | 1) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_RDP3 (MTK_PIN_NO(31) | 1) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_RDN0_A (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_CMHSYNC (MTK_PIN_NO(32) | 2) +#define PINMUX_GPIO32__FUNC_CMCSD0 (MTK_PIN_NO(32) | 3) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_RDP0_A (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_CMVSYNC (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_CMCSD1 (MTK_PIN_NO(33) | 3) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_RDN1_A (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_CMDAT9 (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_CMCSD2 (MTK_PIN_NO(34) | 3) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_RDP1_A (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_CMDAT8 (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_CMCSD3 (MTK_PIN_NO(35) | 3) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_RCN_A (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_CMDAT7 (MTK_PIN_NO(36) | 2) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_RCP_A (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_CMDAT6 (MTK_PIN_NO(37) | 2) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_RDN2_A (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_CMDAT5 (MTK_PIN_NO(38) | 2) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_RDP2_A (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_CMDAT4 (MTK_PIN_NO(39) | 2) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_RDN3_A (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_CMDAT3 (MTK_PIN_NO(40) | 2) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_RDP3_A (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_CMDAT2 (MTK_PIN_NO(41) | 2) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_CMDAT0 (MTK_PIN_NO(42) | 1) +#define PINMUX_GPIO42__FUNC_CMCSD0 (MTK_PIN_NO(42) | 2) +#define PINMUX_GPIO42__FUNC_CMMCLK1 (MTK_PIN_NO(42) | 3) +#define PINMUX_GPIO42__FUNC_ANT_SEL5 (MTK_PIN_NO(42) | 5) +#define PINMUX_GPIO42__FUNC_CLKM5 (MTK_PIN_NO(42) | 6) +#define PINMUX_GPIO42__FUNC_DBG_MON_A9 (MTK_PIN_NO(42) | 7) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_CMDAT1 (MTK_PIN_NO(43) | 1) +#define PINMUX_GPIO43__FUNC_CMCSD1 (MTK_PIN_NO(43) | 2) +#define PINMUX_GPIO43__FUNC_CMFLASH (MTK_PIN_NO(43) | 3) +#define PINMUX_GPIO43__FUNC_MD_EINT0 (MTK_PIN_NO(43) | 4) +#define PINMUX_GPIO43__FUNC_CMMCLK1 (MTK_PIN_NO(43) | 5) +#define PINMUX_GPIO43__FUNC_CLKM4 (MTK_PIN_NO(43) | 6) +#define PINMUX_GPIO43__FUNC_DBG_MON_A10 (MTK_PIN_NO(43) | 7) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_CMPCLK (MTK_PIN_NO(44) | 1) +#define PINMUX_GPIO44__FUNC_CMCSK (MTK_PIN_NO(44) | 2) +#define PINMUX_GPIO44__FUNC_CMCSD2 (MTK_PIN_NO(44) | 3) +#define PINMUX_GPIO44__FUNC_KCOL3 (MTK_PIN_NO(44) | 4) +#define PINMUX_GPIO44__FUNC_SRCLKENAI2 (MTK_PIN_NO(44) | 5) +#define PINMUX_GPIO44__FUNC_PWM0 (MTK_PIN_NO(44) | 6) +#define PINMUX_GPIO44__FUNC_DBG_MON_A11 (MTK_PIN_NO(44) | 7) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_CMMCLK0 (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_DBG_MON_A12 (MTK_PIN_NO(45) | 7) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_CMMCLK1 (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_IDDIG (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_LTE_MD32_JTAG_TRST (MTK_PIN_NO(46) | 3) +#define PINMUX_GPIO46__FUNC_TDD_TRSTN (MTK_PIN_NO(46) | 4) +#define PINMUX_GPIO46__FUNC_DM_JTINTP (MTK_PIN_NO(46) | 5) +#define PINMUX_GPIO46__FUNC_KCOL6 (MTK_PIN_NO(46) | 6) +#define PINMUX_GPIO46__FUNC_DBG_MON_A13 (MTK_PIN_NO(46) | 7) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_SDA0 (MTK_PIN_NO(47) | 1) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_SCL0 (MTK_PIN_NO(48) | 1) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_SDA1 (MTK_PIN_NO(49) | 1) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_SCL1 (MTK_PIN_NO(50) | 1) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_SDA2 (MTK_PIN_NO(51) | 1) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_SCL2 (MTK_PIN_NO(52) | 1) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_SDA3 (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_IDDIG (MTK_PIN_NO(53) | 3) +#define PINMUX_GPIO53__FUNC_MD_EINT2 (MTK_PIN_NO(53) | 5) +#define PINMUX_GPIO53__FUNC_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(53) | 6) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_SCL3 (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_IDDIG (MTK_PIN_NO(54) | 3) +#define PINMUX_GPIO54__FUNC_MD_EINT1 (MTK_PIN_NO(54) | 5) +#define PINMUX_GPIO54__FUNC_C2K_UIM0_HOT_PLUG_IN (MTK_PIN_NO(54) | 6) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_SRCLKENAI0 (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_PWM2 (MTK_PIN_NO(55) | 2) +#define PINMUX_GPIO55__FUNC_CLKM5 (MTK_PIN_NO(55) | 3) +#define PINMUX_GPIO55__FUNC_CORESONIC_SWD (MTK_PIN_NO(55) | 4) +#define PINMUX_GPIO55__FUNC_ANT_SEL6 (MTK_PIN_NO(55) | 5) +#define PINMUX_GPIO55__FUNC_KROW5 (MTK_PIN_NO(55) | 6) +#define PINMUX_GPIO55__FUNC_DISP_PWM (MTK_PIN_NO(55) | 7) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_SRCLKENA1 (MTK_PIN_NO(56) | 1) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_URXD2 (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_DPI_HSYNC0 (MTK_PIN_NO(57) | 2) +#define PINMUX_GPIO57__FUNC_UTXD2 (MTK_PIN_NO(57) | 3) +#define PINMUX_GPIO57__FUNC_MD_URXD (MTK_PIN_NO(57) | 4) +#define PINMUX_GPIO57__FUNC_SRCLKENAI1 (MTK_PIN_NO(57) | 5) +#define PINMUX_GPIO57__FUNC_KROW4 (MTK_PIN_NO(57) | 6) +#define PINMUX_GPIO57__FUNC_DBG_MON_A14 (MTK_PIN_NO(57) | 7) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_UTXD2 (MTK_PIN_NO(58) | 1) +#define PINMUX_GPIO58__FUNC_DPI_VSYNC0 (MTK_PIN_NO(58) | 2) +#define PINMUX_GPIO58__FUNC_URXD2 (MTK_PIN_NO(58) | 3) +#define PINMUX_GPIO58__FUNC_MD_UTXD (MTK_PIN_NO(58) | 4) +#define PINMUX_GPIO58__FUNC_TDD_TXD (MTK_PIN_NO(58) | 5) +#define PINMUX_GPIO58__FUNC_KROW5 (MTK_PIN_NO(58) | 6) +#define PINMUX_GPIO58__FUNC_DBG_MON_A15 (MTK_PIN_NO(58) | 7) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_URXD3 (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_DPI_CK0 (MTK_PIN_NO(59) | 2) +#define PINMUX_GPIO59__FUNC_UTXD3 (MTK_PIN_NO(59) | 3) +#define PINMUX_GPIO59__FUNC_UCTS2 (MTK_PIN_NO(59) | 4) +#define PINMUX_GPIO59__FUNC_PWM3 (MTK_PIN_NO(59) | 5) +#define PINMUX_GPIO59__FUNC_KROW6 (MTK_PIN_NO(59) | 6) +#define PINMUX_GPIO59__FUNC_DBG_MON_A16 (MTK_PIN_NO(59) | 7) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_UTXD3 (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_DPI_DE0 (MTK_PIN_NO(60) | 2) +#define PINMUX_GPIO60__FUNC_URXD3 (MTK_PIN_NO(60) | 3) +#define PINMUX_GPIO60__FUNC_URTS2 (MTK_PIN_NO(60) | 4) +#define PINMUX_GPIO60__FUNC_PWM4 (MTK_PIN_NO(60) | 5) +#define PINMUX_GPIO60__FUNC_KROW7 (MTK_PIN_NO(60) | 6) +#define PINMUX_GPIO60__FUNC_DBG_MON_A17 (MTK_PIN_NO(60) | 7) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_PCM1_CLK (MTK_PIN_NO(61) | 1) +#define PINMUX_GPIO61__FUNC_DPI_D0 (MTK_PIN_NO(61) | 2) +#define PINMUX_GPIO61__FUNC_I2S0_BCK (MTK_PIN_NO(61) | 3) +#define PINMUX_GPIO61__FUNC_KROW4 (MTK_PIN_NO(61) | 4) +#define PINMUX_GPIO61__FUNC_ANT_SEL3 (MTK_PIN_NO(61) | 5) +#define PINMUX_GPIO61__FUNC_IRTX_OUT (MTK_PIN_NO(61) | 6) +#define PINMUX_GPIO61__FUNC_DBG_MON_A18 (MTK_PIN_NO(61) | 7) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_PCM1_SYNC (MTK_PIN_NO(62) | 1) +#define PINMUX_GPIO62__FUNC_DPI_D1 (MTK_PIN_NO(62) | 2) +#define PINMUX_GPIO62__FUNC_I2S0_LRCK (MTK_PIN_NO(62) | 3) +#define PINMUX_GPIO62__FUNC_KCOL7 (MTK_PIN_NO(62) | 4) +#define PINMUX_GPIO62__FUNC_CLKM3 (MTK_PIN_NO(62) | 5) +#define PINMUX_GPIO62__FUNC_CMFLASH (MTK_PIN_NO(62) | 6) +#define PINMUX_GPIO62__FUNC_DBG_MON_A19 (MTK_PIN_NO(62) | 7) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_PCM1_DI (MTK_PIN_NO(63) | 1) +#define PINMUX_GPIO63__FUNC_DPI_D2 (MTK_PIN_NO(63) | 2) +#define PINMUX_GPIO63__FUNC_I2S0_DI (MTK_PIN_NO(63) | 3) +#define PINMUX_GPIO63__FUNC_PCM1_DO0 (MTK_PIN_NO(63) | 4) +#define PINMUX_GPIO63__FUNC_CLKM5 (MTK_PIN_NO(63) | 5) +#define PINMUX_GPIO63__FUNC_KROW3 (MTK_PIN_NO(63) | 6) +#define PINMUX_GPIO63__FUNC_DBG_MON_A20 (MTK_PIN_NO(63) | 7) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_PCM1_DO0 (MTK_PIN_NO(64) | 1) +#define PINMUX_GPIO64__FUNC_DPI_D3 (MTK_PIN_NO(64) | 2) +#define PINMUX_GPIO64__FUNC_I2S0_MCK (MTK_PIN_NO(64) | 3) +#define PINMUX_GPIO64__FUNC_PCM1_DI (MTK_PIN_NO(64) | 4) +#define PINMUX_GPIO64__FUNC_SRCLKENAI2 (MTK_PIN_NO(64) | 5) +#define PINMUX_GPIO64__FUNC_KCOL5 (MTK_PIN_NO(64) | 6) +#define PINMUX_GPIO64__FUNC_DBG_MON_A21 (MTK_PIN_NO(64) | 7) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_SPI_CSA (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(65) | 2) +#define PINMUX_GPIO65__FUNC_I2S3_MCK (MTK_PIN_NO(65) | 3) +#define PINMUX_GPIO65__FUNC_KROW2 (MTK_PIN_NO(65) | 4) +#define PINMUX_GPIO65__FUNC_GPS_FRAME_SYNC (MTK_PIN_NO(65) | 5) +#define PINMUX_GPIO65__FUNC_PTA_RXD (MTK_PIN_NO(65) | 6) +#define PINMUX_GPIO65__FUNC_DBG_MON_A22 (MTK_PIN_NO(65) | 7) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_SPI_CKA (MTK_PIN_NO(66) | 1) +#define PINMUX_GPIO66__FUNC_USB_DRVVBUS (MTK_PIN_NO(66) | 2) +#define PINMUX_GPIO66__FUNC_I2S3_BCK (MTK_PIN_NO(66) | 3) +#define PINMUX_GPIO66__FUNC_KCOL2 (MTK_PIN_NO(66) | 4) +#define PINMUX_GPIO66__FUNC_PTA_TXD (MTK_PIN_NO(66) | 6) +#define PINMUX_GPIO66__FUNC_DBG_MON_A23 (MTK_PIN_NO(66) | 7) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_SPI_MIA (MTK_PIN_NO(67) | 1) +#define PINMUX_GPIO67__FUNC_SPI_MOA (MTK_PIN_NO(67) | 2) +#define PINMUX_GPIO67__FUNC_I2S3_DO (MTK_PIN_NO(67) | 3) +#define PINMUX_GPIO67__FUNC_PTA_RXD (MTK_PIN_NO(67) | 4) +#define PINMUX_GPIO67__FUNC_IDDIG (MTK_PIN_NO(67) | 5) +#define PINMUX_GPIO67__FUNC_UCTS1 (MTK_PIN_NO(67) | 6) +#define PINMUX_GPIO67__FUNC_DBG_MON_A24 (MTK_PIN_NO(67) | 7) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_SPI_MOA (MTK_PIN_NO(68) | 1) +#define PINMUX_GPIO68__FUNC_SPI_MIA (MTK_PIN_NO(68) | 2) +#define PINMUX_GPIO68__FUNC_I2S3_LRCK (MTK_PIN_NO(68) | 3) +#define PINMUX_GPIO68__FUNC_PTA_TXD (MTK_PIN_NO(68) | 4) +#define PINMUX_GPIO68__FUNC_ANT_SEL4 (MTK_PIN_NO(68) | 5) +#define PINMUX_GPIO68__FUNC_URTS1 (MTK_PIN_NO(68) | 6) +#define PINMUX_GPIO68__FUNC_DBG_MON_A25 (MTK_PIN_NO(68) | 7) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_DISP_PWM (MTK_PIN_NO(69) | 1) +#define PINMUX_GPIO69__FUNC_PWM1 (MTK_PIN_NO(69) | 2) +#define PINMUX_GPIO69__FUNC_LTE_MD32_JTAG_TRST (MTK_PIN_NO(69) | 3) +#define PINMUX_GPIO69__FUNC_TDD_TRSTN (MTK_PIN_NO(69) | 4) +#define PINMUX_GPIO69__FUNC_ANT_SEL7 (MTK_PIN_NO(69) | 5) +#define PINMUX_GPIO69__FUNC_DM_JTINTP (MTK_PIN_NO(69) | 6) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_JTMS (MTK_PIN_NO(70) | 1) +#define PINMUX_GPIO70__FUNC_CONN_MCU_TMS (MTK_PIN_NO(70) | 2) +#define PINMUX_GPIO70__FUNC_LTE_MD32_JTAG_TMS (MTK_PIN_NO(70) | 3) +#define PINMUX_GPIO70__FUNC_TDD_TMS (MTK_PIN_NO(70) | 4) +#define PINMUX_GPIO70__FUNC_CORESONIC_SWD (MTK_PIN_NO(70) | 5) +#define PINMUX_GPIO70__FUNC_DM_OTMS (MTK_PIN_NO(70) | 6) +#define PINMUX_GPIO70__FUNC_DFD_TMS (MTK_PIN_NO(70) | 7) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_JTCK (MTK_PIN_NO(71) | 1) +#define PINMUX_GPIO71__FUNC_CONN_MCU_TCK_1 (MTK_PIN_NO(71) | 2) +#define PINMUX_GPIO71__FUNC_LTE_MD32_JTAG_TCK (MTK_PIN_NO(71) | 3) +#define PINMUX_GPIO71__FUNC_TDD_TCK (MTK_PIN_NO(71) | 4) +#define PINMUX_GPIO71__FUNC_CORESONIC_SWCK (MTK_PIN_NO(71) | 5) +#define PINMUX_GPIO71__FUNC_DM_OTCK (MTK_PIN_NO(71) | 6) +#define PINMUX_GPIO71__FUNC_DFD_TCK_XI (MTK_PIN_NO(71) | 7) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_JTDI (MTK_PIN_NO(72) | 1) +#define PINMUX_GPIO72__FUNC_CONN_MCU_TDI (MTK_PIN_NO(72) | 2) +#define PINMUX_GPIO72__FUNC_LTE_MD32_JTAG_TDI (MTK_PIN_NO(72) | 3) +#define PINMUX_GPIO72__FUNC_TDD_TDI (MTK_PIN_NO(72) | 4) +#define PINMUX_GPIO72__FUNC_DM_OTDI (MTK_PIN_NO(72) | 6) +#define PINMUX_GPIO72__FUNC_DFD_TDI (MTK_PIN_NO(72) | 7) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_JTDO (MTK_PIN_NO(73) | 1) +#define PINMUX_GPIO73__FUNC_CONN_MCU_TDO (MTK_PIN_NO(73) | 2) +#define PINMUX_GPIO73__FUNC_LTE_MD32_JTAG_TDO (MTK_PIN_NO(73) | 3) +#define PINMUX_GPIO73__FUNC_TDD_TDO (MTK_PIN_NO(73) | 4) +#define PINMUX_GPIO73__FUNC_DM_OTDO (MTK_PIN_NO(73) | 6) +#define PINMUX_GPIO73__FUNC_DFD_TDO (MTK_PIN_NO(73) | 7) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_URXD0 (MTK_PIN_NO(74) | 1) +#define PINMUX_GPIO74__FUNC_UTXD0 (MTK_PIN_NO(74) | 2) +#define PINMUX_GPIO74__FUNC_MD_URXD (MTK_PIN_NO(74) | 3) +#define PINMUX_GPIO74__FUNC_SDA3 (MTK_PIN_NO(74) | 4) +#define PINMUX_GPIO74__FUNC_C2K_UART0_RXD (MTK_PIN_NO(74) | 5) +#define PINMUX_GPIO74__FUNC_LTE_URXD (MTK_PIN_NO(74) | 6) +#define PINMUX_GPIO74__FUNC_AUXIF_ST (MTK_PIN_NO(74) | 7) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_UTXD0 (MTK_PIN_NO(75) | 1) +#define PINMUX_GPIO75__FUNC_URXD0 (MTK_PIN_NO(75) | 2) +#define PINMUX_GPIO75__FUNC_MD_UTXD (MTK_PIN_NO(75) | 3) +#define PINMUX_GPIO75__FUNC_TDD_TXD (MTK_PIN_NO(75) | 4) +#define PINMUX_GPIO75__FUNC_C2K_UART0_TXD (MTK_PIN_NO(75) | 5) +#define PINMUX_GPIO75__FUNC_LTE_UTXD (MTK_PIN_NO(75) | 6) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_URXD1 (MTK_PIN_NO(76) | 1) +#define PINMUX_GPIO76__FUNC_UTXD1 (MTK_PIN_NO(76) | 2) +#define PINMUX_GPIO76__FUNC_MD_URXD (MTK_PIN_NO(76) | 3) +#define PINMUX_GPIO76__FUNC_SCL3 (MTK_PIN_NO(76) | 4) +#define PINMUX_GPIO76__FUNC_LTE_URXD (MTK_PIN_NO(76) | 5) +#define PINMUX_GPIO76__FUNC_C2K_UART0_RXD (MTK_PIN_NO(76) | 6) +#define PINMUX_GPIO76__FUNC_AUXIF_CLK (MTK_PIN_NO(76) | 7) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_UTXD1 (MTK_PIN_NO(77) | 1) +#define PINMUX_GPIO77__FUNC_URXD1 (MTK_PIN_NO(77) | 2) +#define PINMUX_GPIO77__FUNC_MD_UTXD (MTK_PIN_NO(77) | 3) +#define PINMUX_GPIO77__FUNC_TDD_TXD (MTK_PIN_NO(77) | 4) +#define PINMUX_GPIO77__FUNC_LTE_UTXD (MTK_PIN_NO(77) | 5) +#define PINMUX_GPIO77__FUNC_C2K_UART0_TXD (MTK_PIN_NO(77) | 6) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_I2S0_DI (MTK_PIN_NO(78) | 1) +#define PINMUX_GPIO78__FUNC_PCM1_DI (MTK_PIN_NO(78) | 2) +#define PINMUX_GPIO78__FUNC_I2S3_DO (MTK_PIN_NO(78) | 3) +#define PINMUX_GPIO78__FUNC_I2S1_DO (MTK_PIN_NO(78) | 4) +#define PINMUX_GPIO78__FUNC_PWM0 (MTK_PIN_NO(78) | 5) +#define PINMUX_GPIO78__FUNC_I2S2_DI (MTK_PIN_NO(78) | 6) +#define PINMUX_GPIO78__FUNC_DBG_MON_A26 (MTK_PIN_NO(78) | 7) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_I2S0_LRCK (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_PCM1_SYNC (MTK_PIN_NO(79) | 2) +#define PINMUX_GPIO79__FUNC_I2S3_LRCK (MTK_PIN_NO(79) | 3) +#define PINMUX_GPIO79__FUNC_I2S1_LRCK (MTK_PIN_NO(79) | 4) +#define PINMUX_GPIO79__FUNC_PWM3 (MTK_PIN_NO(79) | 5) +#define PINMUX_GPIO79__FUNC_I2S2_LRCK (MTK_PIN_NO(79) | 6) +#define PINMUX_GPIO79__FUNC_DBG_MON_A27 (MTK_PIN_NO(79) | 7) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_I2S0_BCK (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_PCM1_CLK (MTK_PIN_NO(80) | 2) +#define PINMUX_GPIO80__FUNC_I2S3_BCK (MTK_PIN_NO(80) | 3) +#define PINMUX_GPIO80__FUNC_I2S1_BCK (MTK_PIN_NO(80) | 4) +#define PINMUX_GPIO80__FUNC_PWM4 (MTK_PIN_NO(80) | 5) +#define PINMUX_GPIO80__FUNC_I2S2_BCK (MTK_PIN_NO(80) | 6) +#define PINMUX_GPIO80__FUNC_DBG_MON_A28 (MTK_PIN_NO(80) | 7) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_KROW0 (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(81) | 3) +#define PINMUX_GPIO81__FUNC_CORESONIC_SWCK (MTK_PIN_NO(81) | 4) +#define PINMUX_GPIO81__FUNC_C2K_TCK (MTK_PIN_NO(81) | 5) +#define PINMUX_GPIO81__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(81) | 7) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_KROW1 (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(82) | 3) +#define PINMUX_GPIO82__FUNC_CORESONIC_SWD (MTK_PIN_NO(82) | 4) +#define PINMUX_GPIO82__FUNC_C2K_NTRST (MTK_PIN_NO(82) | 5) +#define PINMUX_GPIO82__FUNC_USB_DRVVBUS (MTK_PIN_NO(82) | 6) +#define PINMUX_GPIO82__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(82) | 7) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_KROW2 (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_USB_DRVVBUS (MTK_PIN_NO(83) | 2) +#define PINMUX_GPIO83__FUNC_C2K_TDI (MTK_PIN_NO(83) | 5) +#define PINMUX_GPIO83__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(83) | 7) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_KCOL0 (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_URTS0 (MTK_PIN_NO(84) | 2) +#define PINMUX_GPIO84__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(84) | 3) +#define PINMUX_GPIO84__FUNC_SCL2 (MTK_PIN_NO(84) | 4) +#define PINMUX_GPIO84__FUNC_C2K_TDO (MTK_PIN_NO(84) | 5) +#define PINMUX_GPIO84__FUNC_AUXIF_CLK (MTK_PIN_NO(84) | 6) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_KCOL1 (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_UCTS0 (MTK_PIN_NO(85) | 2) +#define PINMUX_GPIO85__FUNC_UCTS1 (MTK_PIN_NO(85) | 3) +#define PINMUX_GPIO85__FUNC_SDA2 (MTK_PIN_NO(85) | 4) +#define PINMUX_GPIO85__FUNC_C2K_TMS (MTK_PIN_NO(85) | 5) +#define PINMUX_GPIO85__FUNC_AUXIF_ST (MTK_PIN_NO(85) | 6) +#define PINMUX_GPIO85__FUNC_DBG_MON_A31 (MTK_PIN_NO(85) | 7) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_KCOL2 (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_URTS1 (MTK_PIN_NO(86) | 3) +#define PINMUX_GPIO86__FUNC_C2K_RTCK (MTK_PIN_NO(86) | 5) +#define PINMUX_GPIO86__FUNC_DBG_MON_A32 (MTK_PIN_NO(86) | 7) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_BPI_BUS5 (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_LTE_C2K_BPI_BUS5 (MTK_PIN_NO(87) | 2) +#define PINMUX_GPIO87__FUNC_C2K_BPI_BUS5 (MTK_PIN_NO(87) | 5) +#define PINMUX_GPIO87__FUNC_DBG_MON_B0 (MTK_PIN_NO(87) | 7) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_BPI_BUS6 (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_LTE_C2K_BPI_BUS6 (MTK_PIN_NO(88) | 2) +#define PINMUX_GPIO88__FUNC_C2K_BPI_BUS6 (MTK_PIN_NO(88) | 5) +#define PINMUX_GPIO88__FUNC_DBG_MON_B1 (MTK_PIN_NO(88) | 7) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_BPI_BUS7 (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_LTE_C2K_BPI_BUS7 (MTK_PIN_NO(89) | 2) +#define PINMUX_GPIO89__FUNC_CLKM0 (MTK_PIN_NO(89) | 3) +#define PINMUX_GPIO89__FUNC_C2K_BPI_BUS7 (MTK_PIN_NO(89) | 5) +#define PINMUX_GPIO89__FUNC_DBG_MON_B2 (MTK_PIN_NO(89) | 7) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_BPI_BUS8 (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_LTE_C2K_BPI_BUS8 (MTK_PIN_NO(90) | 2) +#define PINMUX_GPIO90__FUNC_CLKM1 (MTK_PIN_NO(90) | 3) +#define PINMUX_GPIO90__FUNC_C2K_BPI_BUS8 (MTK_PIN_NO(90) | 5) +#define PINMUX_GPIO90__FUNC_DBG_MON_B3 (MTK_PIN_NO(90) | 7) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_BPI_BUS9 (MTK_PIN_NO(91) | 1) +#define PINMUX_GPIO91__FUNC_LTE_C2K_BPI_BUS9 (MTK_PIN_NO(91) | 2) +#define PINMUX_GPIO91__FUNC_CLKM2 (MTK_PIN_NO(91) | 3) +#define PINMUX_GPIO91__FUNC_C2K_BPI_BUS9 (MTK_PIN_NO(91) | 5) +#define PINMUX_GPIO91__FUNC_DBG_MON_B4 (MTK_PIN_NO(91) | 7) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_BPI_BUS10 (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_LTE_C2K_BPI_BUS10 (MTK_PIN_NO(92) | 2) +#define PINMUX_GPIO92__FUNC_CLKM3 (MTK_PIN_NO(92) | 3) +#define PINMUX_GPIO92__FUNC_C2K_BPI_BUS10 (MTK_PIN_NO(92) | 5) +#define PINMUX_GPIO92__FUNC_DBG_MON_B5 (MTK_PIN_NO(92) | 7) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_BPI_BUS11 (MTK_PIN_NO(93) | 1) +#define PINMUX_GPIO93__FUNC_LTE_C2K_BPI_BUS11 (MTK_PIN_NO(93) | 2) +#define PINMUX_GPIO93__FUNC_C2K_BPI_BUS11 (MTK_PIN_NO(93) | 5) +#define PINMUX_GPIO93__FUNC_DBG_MON_B6 (MTK_PIN_NO(93) | 7) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_BPI_BUS12 (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_LTE_C2K_BPI_BUS12 (MTK_PIN_NO(94) | 2) +#define PINMUX_GPIO94__FUNC_C2K_BPI_BUS12 (MTK_PIN_NO(94) | 5) +#define PINMUX_GPIO94__FUNC_DBG_MON_B7 (MTK_PIN_NO(94) | 7) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_BPI_BUS13 (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_LTE_C2K_BPI_BUS13 (MTK_PIN_NO(95) | 2) +#define PINMUX_GPIO95__FUNC_C2K_BPI_BUS13 (MTK_PIN_NO(95) | 5) +#define PINMUX_GPIO95__FUNC_DBG_MON_B8 (MTK_PIN_NO(95) | 7) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_BPI_BUS14 (MTK_PIN_NO(96) | 1) +#define PINMUX_GPIO96__FUNC_LTE_C2K_BPI_BUS14 (MTK_PIN_NO(96) | 2) +#define PINMUX_GPIO96__FUNC_C2K_BPI_BUS14 (MTK_PIN_NO(96) | 5) +#define PINMUX_GPIO96__FUNC_DBG_MON_B9 (MTK_PIN_NO(96) | 7) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_BPI_BUS15 (MTK_PIN_NO(97) | 1) +#define PINMUX_GPIO97__FUNC_LTE_C2K_BPI_BUS15 (MTK_PIN_NO(97) | 2) +#define PINMUX_GPIO97__FUNC_C2K_BPI_BUS15 (MTK_PIN_NO(97) | 5) +#define PINMUX_GPIO97__FUNC_DBG_MON_B10 (MTK_PIN_NO(97) | 7) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_BPI_BUS16 (MTK_PIN_NO(98) | 1) +#define PINMUX_GPIO98__FUNC_LTE_C2K_BPI_BUS16 (MTK_PIN_NO(98) | 2) +#define PINMUX_GPIO98__FUNC_C2K_BPI_BUS16 (MTK_PIN_NO(98) | 5) +#define PINMUX_GPIO98__FUNC_DBG_MON_B11 (MTK_PIN_NO(98) | 7) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_BPI_BUS17 (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_LTE_C2K_BPI_BUS17 (MTK_PIN_NO(99) | 2) +#define PINMUX_GPIO99__FUNC_C2K_BPI_BUS17 (MTK_PIN_NO(99) | 5) +#define PINMUX_GPIO99__FUNC_DBG_MON_B12 (MTK_PIN_NO(99) | 7) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_BPI_BUS18 (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_LTE_C2K_BPI_BUS18 (MTK_PIN_NO(100) | 2) +#define PINMUX_GPIO100__FUNC_C2K_BPI_BUS18 (MTK_PIN_NO(100) | 5) +#define PINMUX_GPIO100__FUNC_DBG_MON_B13 (MTK_PIN_NO(100) | 7) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_BPI_BUS19 (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_LTE_C2K_BPI_BUS19 (MTK_PIN_NO(101) | 2) +#define PINMUX_GPIO101__FUNC_C2K_BPI_BUS19 (MTK_PIN_NO(101) | 5) +#define PINMUX_GPIO101__FUNC_DBG_MON_B14 (MTK_PIN_NO(101) | 7) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_BPI_BUS20 (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_LTE_C2K_BPI_BUS20 (MTK_PIN_NO(102) | 2) +#define PINMUX_GPIO102__FUNC_C2K_BPI_BUS20 (MTK_PIN_NO(102) | 5) +#define PINMUX_GPIO102__FUNC_DBG_MON_B15 (MTK_PIN_NO(102) | 7) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_C2K_TXBPI (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_DBG_MON_B16 (MTK_PIN_NO(103) | 7) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_RFIC1_BSI_EN (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_C2K_RX_BSI_EN (MTK_PIN_NO(104) | 5) +#define PINMUX_GPIO104__FUNC_DBG_MON_B17 (MTK_PIN_NO(104) | 7) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_RFIC1_BSI_CK (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_C2K_RX_BSI_CLK (MTK_PIN_NO(105) | 5) +#define PINMUX_GPIO105__FUNC_DBG_MON_B18 (MTK_PIN_NO(105) | 7) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_RFIC1_BSI_D0 (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_C2K_RX_BSI_DATA (MTK_PIN_NO(106) | 5) +#define PINMUX_GPIO106__FUNC_DBG_MON_B19 (MTK_PIN_NO(106) | 7) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_RFIC1_BSI_D1 (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_C2K_TX_BSI_EN (MTK_PIN_NO(107) | 5) +#define PINMUX_GPIO107__FUNC_DBG_MON_B20 (MTK_PIN_NO(107) | 7) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_RFIC1_BSI_D2 (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_C2K_TX_BSI_CLK (MTK_PIN_NO(108) | 5) +#define PINMUX_GPIO108__FUNC_DBG_MON_B21 (MTK_PIN_NO(108) | 7) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_C2K_TX_BSI_DATA (MTK_PIN_NO(109) | 5) +#define PINMUX_GPIO109__FUNC_DBG_MON_B22 (MTK_PIN_NO(109) | 7) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_SPM_BSI_EN (MTK_PIN_NO(110) | 4) +#define PINMUX_GPIO110__FUNC_DBG_MON_B23 (MTK_PIN_NO(110) | 7) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_SPM_BSI_CLK (MTK_PIN_NO(111) | 4) +#define PINMUX_GPIO111__FUNC_DBG_MON_B24 (MTK_PIN_NO(111) | 7) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_SPM_BSI_D2 (MTK_PIN_NO(112) | 4) +#define PINMUX_GPIO112__FUNC_DBG_MON_B25 (MTK_PIN_NO(112) | 7) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_SPM_BSI_D1 (MTK_PIN_NO(113) | 4) +#define PINMUX_GPIO113__FUNC_DBG_MON_B26 (MTK_PIN_NO(113) | 7) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_SPM_BSI_D0 (MTK_PIN_NO(114) | 4) +#define PINMUX_GPIO114__FUNC_DBG_MON_B27 (MTK_PIN_NO(114) | 7) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_AUXIN0 (MTK_PIN_NO(115) | 1) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_AUXIN1 (MTK_PIN_NO(116) | 1) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_AUXIN2 (MTK_PIN_NO(117) | 1) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_TXBPI (MTK_PIN_NO(118) | 1) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_BPI_BUS0 (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_DBG_MON_B28 (MTK_PIN_NO(119) | 7) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_BPI_BUS1 (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_DBG_MON_B29 (MTK_PIN_NO(120) | 7) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_BPI_BUS2 (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_DBG_MON_B30 (MTK_PIN_NO(121) | 7) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_BPI_BUS3 (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_DBG_MON_B31 (MTK_PIN_NO(122) | 7) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_BPI_BUS4 (MTK_PIN_NO(123) | 1) +#define PINMUX_GPIO123__FUNC_DBG_MON_B32 (MTK_PIN_NO(123) | 7) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_BPI_BUS21 (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_DPI_HSYNC1 (MTK_PIN_NO(124) | 5) +#define PINMUX_GPIO124__FUNC_KCOL2 (MTK_PIN_NO(124) | 6) +#define PINMUX_GPIO124__FUNC_TDD_TXD (MTK_PIN_NO(124) | 7) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_BPI_BUS22 (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_DPI_VSYNC1 (MTK_PIN_NO(125) | 5) +#define PINMUX_GPIO125__FUNC_KROW2 (MTK_PIN_NO(125) | 6) +#define PINMUX_GPIO125__FUNC_MD_URXD (MTK_PIN_NO(125) | 7) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_BPI_BUS23 (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_DPI_CK1 (MTK_PIN_NO(126) | 5) +#define PINMUX_GPIO126__FUNC_I2S2_MCK (MTK_PIN_NO(126) | 6) +#define PINMUX_GPIO126__FUNC_MD_UTXD (MTK_PIN_NO(126) | 7) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_BPI_BUS24 (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(127) | 3) +#define PINMUX_GPIO127__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(127) | 4) +#define PINMUX_GPIO127__FUNC_DPI_DE1 (MTK_PIN_NO(127) | 5) +#define PINMUX_GPIO127__FUNC_SRCLKENAI1 (MTK_PIN_NO(127) | 6) +#define PINMUX_GPIO127__FUNC_URXD0 (MTK_PIN_NO(127) | 7) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_BPI_BUS25 (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_GPS_FRAME_SYNC (MTK_PIN_NO(128) | 3) +#define PINMUX_GPIO128__FUNC_I2S2_DI (MTK_PIN_NO(128) | 5) +#define PINMUX_GPIO128__FUNC_PTA_RXD (MTK_PIN_NO(128) | 6) +#define PINMUX_GPIO128__FUNC_UTXD0 (MTK_PIN_NO(128) | 7) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_BPI_BUS26 (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_DISP_PWM (MTK_PIN_NO(129) | 2) +#define PINMUX_GPIO129__FUNC_I2S2_LRCK (MTK_PIN_NO(129) | 5) +#define PINMUX_GPIO129__FUNC_PTA_TXD (MTK_PIN_NO(129) | 6) +#define PINMUX_GPIO129__FUNC_LTE_URXD (MTK_PIN_NO(129) | 7) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_BPI_BUS27 (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_I2S2_BCK (MTK_PIN_NO(130) | 5) +#define PINMUX_GPIO130__FUNC_IRTX_OUT (MTK_PIN_NO(130) | 6) +#define PINMUX_GPIO130__FUNC_LTE_UTXD (MTK_PIN_NO(130) | 7) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_LTE_PAVM0 (MTK_PIN_NO(131) | 1) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_LTE_PAVM1 (MTK_PIN_NO(132) | 1) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_MIPI1_SCLK (MTK_PIN_NO(133) | 1) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_MIPI1_SDATA (MTK_PIN_NO(134) | 1) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_MIPI0_SCLK (MTK_PIN_NO(135) | 1) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_MIPI0_SDATA (MTK_PIN_NO(136) | 1) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_RTC32K_CK (MTK_PIN_NO(137) | 1) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_PWRAP_SPIDO (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_PWRAP_SPIDI (MTK_PIN_NO(138) | 2) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_PWRAP_SPIDI (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_PWRAP_SPIDO (MTK_PIN_NO(139) | 2) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_LTE_MD32_JTAG_TRST (MTK_PIN_NO(140) | 3) +#define PINMUX_GPIO140__FUNC_TDD_TRSTN (MTK_PIN_NO(140) | 4) +#define PINMUX_GPIO140__FUNC_DM_JTINTP (MTK_PIN_NO(140) | 5) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(141) | 1) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(142) | 1) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(143) | 1) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_AUD_DAT_MISO (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(144) | 3) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_AUD_DAT_MISO (MTK_PIN_NO(145) | 3) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_LCM_RST (MTK_PIN_NO(146) | 1) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_DSI_TE (MTK_PIN_NO(147) | 1) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_SRCLKENA (MTK_PIN_NO(148) | 1) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_WATCHDOG (MTK_PIN_NO(149) | 1) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_TDP0 (MTK_PIN_NO(150) | 1) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_TDN0 (MTK_PIN_NO(151) | 1) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_TDP1 (MTK_PIN_NO(152) | 1) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_TDN1 (MTK_PIN_NO(153) | 1) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_TCP (MTK_PIN_NO(154) | 1) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_TCN (MTK_PIN_NO(155) | 1) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_TDP2 (MTK_PIN_NO(156) | 1) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_TDN2 (MTK_PIN_NO(157) | 1) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_TDP3 (MTK_PIN_NO(158) | 1) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_TDN3 (MTK_PIN_NO(159) | 1) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_MD_SIM2_SCLK (MTK_PIN_NO(160) | 1) +#define PINMUX_GPIO160__FUNC_MD_SIM1_SCLK (MTK_PIN_NO(160) | 2) +#define PINMUX_GPIO160__FUNC_UIM0_CLK (MTK_PIN_NO(160) | 3) +#define PINMUX_GPIO160__FUNC_UIM1_CLK (MTK_PIN_NO(160) | 4) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_MD_SIM2_SRST (MTK_PIN_NO(161) | 1) +#define PINMUX_GPIO161__FUNC_MD_SIM1_SRST (MTK_PIN_NO(161) | 2) +#define PINMUX_GPIO161__FUNC_UIM0_RST (MTK_PIN_NO(161) | 3) +#define PINMUX_GPIO161__FUNC_UIM1_RST (MTK_PIN_NO(161) | 4) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_MD_SIM2_SDAT (MTK_PIN_NO(162) | 1) +#define PINMUX_GPIO162__FUNC_MD_SIM1_SDAT (MTK_PIN_NO(162) | 2) +#define PINMUX_GPIO162__FUNC_UIM0_IO (MTK_PIN_NO(162) | 3) +#define PINMUX_GPIO162__FUNC_UIM1_IO (MTK_PIN_NO(162) | 4) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_MD_SIM1_SCLK (MTK_PIN_NO(163) | 1) +#define PINMUX_GPIO163__FUNC_MD_SIM2_SCLK (MTK_PIN_NO(163) | 2) +#define PINMUX_GPIO163__FUNC_UIM1_CLK (MTK_PIN_NO(163) | 3) +#define PINMUX_GPIO163__FUNC_UIM0_CLK (MTK_PIN_NO(163) | 4) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_MD_SIM1_SRST (MTK_PIN_NO(164) | 1) +#define PINMUX_GPIO164__FUNC_MD_SIM2_SRST (MTK_PIN_NO(164) | 2) +#define PINMUX_GPIO164__FUNC_UIM1_RST (MTK_PIN_NO(164) | 3) +#define PINMUX_GPIO164__FUNC_UIM0_RST (MTK_PIN_NO(164) | 4) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_MD_SIM1_SDAT (MTK_PIN_NO(165) | 1) +#define PINMUX_GPIO165__FUNC_MD_SIM2_SDAT (MTK_PIN_NO(165) | 2) +#define PINMUX_GPIO165__FUNC_UIM1_IO (MTK_PIN_NO(165) | 3) +#define PINMUX_GPIO165__FUNC_UIM0_IO (MTK_PIN_NO(165) | 4) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_MSDC1_CMD (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_LTE_MD32_JTAG_TMS (MTK_PIN_NO(166) | 2) +#define PINMUX_GPIO166__FUNC_C2K_TMS (MTK_PIN_NO(166) | 3) +#define PINMUX_GPIO166__FUNC_TDD_TMS (MTK_PIN_NO(166) | 4) +#define PINMUX_GPIO166__FUNC_CONN_DSP_JMS (MTK_PIN_NO(166) | 5) +#define PINMUX_GPIO166__FUNC_JTMS (MTK_PIN_NO(166) | 6) +#define PINMUX_GPIO166__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(166) | 7) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_MSDC1_CLK (MTK_PIN_NO(167) | 1) +#define PINMUX_GPIO167__FUNC_LTE_MD32_JTAG_TCK (MTK_PIN_NO(167) | 2) +#define PINMUX_GPIO167__FUNC_C2K_TCK (MTK_PIN_NO(167) | 3) +#define PINMUX_GPIO167__FUNC_TDD_TCK (MTK_PIN_NO(167) | 4) +#define PINMUX_GPIO167__FUNC_CONN_DSP_JCK (MTK_PIN_NO(167) | 5) +#define PINMUX_GPIO167__FUNC_JTCK (MTK_PIN_NO(167) | 6) +#define PINMUX_GPIO167__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(167) | 7) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_MSDC1_DAT0 (MTK_PIN_NO(168) | 1) +#define PINMUX_GPIO168__FUNC_LTE_MD32_JTAG_TDI (MTK_PIN_NO(168) | 2) +#define PINMUX_GPIO168__FUNC_C2K_TDI (MTK_PIN_NO(168) | 3) +#define PINMUX_GPIO168__FUNC_TDD_TDI (MTK_PIN_NO(168) | 4) +#define PINMUX_GPIO168__FUNC_CONN_DSP_JDI (MTK_PIN_NO(168) | 5) +#define PINMUX_GPIO168__FUNC_JTDI (MTK_PIN_NO(168) | 6) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_MSDC1_DAT1 (MTK_PIN_NO(169) | 1) +#define PINMUX_GPIO169__FUNC_LTE_MD32_JTAG_TDO (MTK_PIN_NO(169) | 2) +#define PINMUX_GPIO169__FUNC_C2K_TDO (MTK_PIN_NO(169) | 3) +#define PINMUX_GPIO169__FUNC_TDD_TDO (MTK_PIN_NO(169) | 4) +#define PINMUX_GPIO169__FUNC_CONN_DSP_JDO (MTK_PIN_NO(169) | 5) +#define PINMUX_GPIO169__FUNC_JTDO (MTK_PIN_NO(169) | 6) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_MSDC1_DAT2 (MTK_PIN_NO(170) | 1) +#define PINMUX_GPIO170__FUNC_LTE_MD32_JTAG_TRST (MTK_PIN_NO(170) | 2) +#define PINMUX_GPIO170__FUNC_C2K_NTRST (MTK_PIN_NO(170) | 3) +#define PINMUX_GPIO170__FUNC_TDD_TRSTN (MTK_PIN_NO(170) | 4) +#define PINMUX_GPIO170__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(170) | 5) +#define PINMUX_GPIO170__FUNC_DM_JTINTP (MTK_PIN_NO(170) | 6) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_MSDC1_DAT3 (MTK_PIN_NO(171) | 1) +#define PINMUX_GPIO171__FUNC_C2K_RTCK (MTK_PIN_NO(171) | 3) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_MSDC0_CMD (MTK_PIN_NO(172) | 1) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_MSDC0_DSL (MTK_PIN_NO(173) | 1) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_MSDC0_CLK (MTK_PIN_NO(174) | 1) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_MSDC0_DAT0 (MTK_PIN_NO(175) | 1) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_MSDC0_DAT1 (MTK_PIN_NO(176) | 1) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define PINMUX_GPIO177__FUNC_MSDC0_DAT2 (MTK_PIN_NO(177) | 1) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define PINMUX_GPIO178__FUNC_MSDC0_DAT3 (MTK_PIN_NO(178) | 1) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define PINMUX_GPIO179__FUNC_MSDC0_DAT4 (MTK_PIN_NO(179) | 1) + +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define PINMUX_GPIO180__FUNC_MSDC0_DAT5 (MTK_PIN_NO(180) | 1) + +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define PINMUX_GPIO181__FUNC_MSDC0_DAT6 (MTK_PIN_NO(181) | 1) + +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define PINMUX_GPIO182__FUNC_MSDC0_DAT7 (MTK_PIN_NO(182) | 1) + +#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define PINMUX_GPIO183__FUNC_MSDC0_RSTB (MTK_PIN_NO(183) | 1) + +#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define PINMUX_GPIO184__FUNC_F2W_DATA (MTK_PIN_NO(184) | 1) +#define PINMUX_GPIO184__FUNC_MRG_CLK (MTK_PIN_NO(184) | 2) +#define PINMUX_GPIO184__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(184) | 3) +#define PINMUX_GPIO184__FUNC_PCM0_CLK (MTK_PIN_NO(184) | 4) + +#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define PINMUX_GPIO185__FUNC_F2W_CK (MTK_PIN_NO(185) | 1) +#define PINMUX_GPIO185__FUNC_MRG_DI (MTK_PIN_NO(185) | 2) +#define PINMUX_GPIO185__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(185) | 3) +#define PINMUX_GPIO185__FUNC_PCM0_DI (MTK_PIN_NO(185) | 4) + +#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define PINMUX_GPIO186__FUNC_WB_RSTB (MTK_PIN_NO(186) | 1) +#define PINMUX_GPIO186__FUNC_URXD3 (MTK_PIN_NO(186) | 4) +#define PINMUX_GPIO186__FUNC_UTXD3 (MTK_PIN_NO(186) | 5) + +#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define PINMUX_GPIO187__FUNC_WB_SCLK (MTK_PIN_NO(187) | 1) +#define PINMUX_GPIO187__FUNC_MRG_DO (MTK_PIN_NO(187) | 2) +#define PINMUX_GPIO187__FUNC_PCM0_DO (MTK_PIN_NO(187) | 4) + +#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define PINMUX_GPIO188__FUNC_WB_SDATA (MTK_PIN_NO(188) | 1) +#define PINMUX_GPIO188__FUNC_MRG_SYNC (MTK_PIN_NO(188) | 2) +#define PINMUX_GPIO188__FUNC_PCM0_SYNC (MTK_PIN_NO(188) | 4) + +#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define PINMUX_GPIO189__FUNC_WB_SEN (MTK_PIN_NO(189) | 1) +#define PINMUX_GPIO189__FUNC_UTXD3 (MTK_PIN_NO(189) | 4) +#define PINMUX_GPIO189__FUNC_URXD3 (MTK_PIN_NO(189) | 5) + +#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define PINMUX_GPIO190__FUNC_GPS_RXQN (MTK_PIN_NO(190) | 1) + +#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define PINMUX_GPIO191__FUNC_GPS_RXQP (MTK_PIN_NO(191) | 1) + +#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define PINMUX_GPIO192__FUNC_GPS_RXIN (MTK_PIN_NO(192) | 1) + +#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define PINMUX_GPIO193__FUNC_GPS_RXIP (MTK_PIN_NO(193) | 1) + +#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define PINMUX_GPIO194__FUNC_WB_RXQN (MTK_PIN_NO(194) | 1) + +#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define PINMUX_GPIO195__FUNC_WB_RXQP (MTK_PIN_NO(195) | 1) + +#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define PINMUX_GPIO196__FUNC_WB_RXIN (MTK_PIN_NO(196) | 1) + +#define PINMUX_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +#define PINMUX_GPIO197__FUNC_WB_RXIP (MTK_PIN_NO(197) | 1) + +#define PINMUX_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +#define PINMUX_GPIO198__FUNC_MSDC2_CMD (MTK_PIN_NO(198) | 1) +#define PINMUX_GPIO198__FUNC_SDA1 (MTK_PIN_NO(198) | 2) +#define PINMUX_GPIO198__FUNC_C2K_UART0_RXD (MTK_PIN_NO(198) | 3) +#define PINMUX_GPIO198__FUNC_C2K_TMS (MTK_PIN_NO(198) | 4) +#define PINMUX_GPIO198__FUNC_ANT_SEL6 (MTK_PIN_NO(198) | 5) +#define PINMUX_GPIO198__FUNC_DM_OTMS (MTK_PIN_NO(198) | 7) + +#define PINMUX_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define PINMUX_GPIO199__FUNC_MSDC2_CLK (MTK_PIN_NO(199) | 1) +#define PINMUX_GPIO199__FUNC_SCL1 (MTK_PIN_NO(199) | 2) +#define PINMUX_GPIO199__FUNC_C2K_UART0_TXD (MTK_PIN_NO(199) | 3) +#define PINMUX_GPIO199__FUNC_C2K_TCK (MTK_PIN_NO(199) | 4) +#define PINMUX_GPIO199__FUNC_ANT_SEL7 (MTK_PIN_NO(199) | 5) +#define PINMUX_GPIO199__FUNC_TDD_TXD (MTK_PIN_NO(199) | 6) +#define PINMUX_GPIO199__FUNC_DM_OTCK (MTK_PIN_NO(199) | 7) + +#define PINMUX_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define PINMUX_GPIO200__FUNC_MSDC2_DAT0 (MTK_PIN_NO(200) | 1) +#define PINMUX_GPIO200__FUNC_ANT_SEL6 (MTK_PIN_NO(200) | 2) +#define PINMUX_GPIO200__FUNC_GPS_FRAME_SYNC (MTK_PIN_NO(200) | 3) +#define PINMUX_GPIO200__FUNC_C2K_TDI (MTK_PIN_NO(200) | 4) +#define PINMUX_GPIO200__FUNC_UTXD0 (MTK_PIN_NO(200) | 5) +#define PINMUX_GPIO200__FUNC_DM_OTDI (MTK_PIN_NO(200) | 7) + +#define PINMUX_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define PINMUX_GPIO201__FUNC_MSDC2_DAT1 (MTK_PIN_NO(201) | 1) +#define PINMUX_GPIO201__FUNC_ANT_SEL3 (MTK_PIN_NO(201) | 2) +#define PINMUX_GPIO201__FUNC_PWM0 (MTK_PIN_NO(201) | 3) +#define PINMUX_GPIO201__FUNC_C2K_TDO (MTK_PIN_NO(201) | 4) +#define PINMUX_GPIO201__FUNC_URXD0 (MTK_PIN_NO(201) | 5) +#define PINMUX_GPIO201__FUNC_DM_OTDO (MTK_PIN_NO(201) | 7) + +#define PINMUX_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define PINMUX_GPIO202__FUNC_MSDC2_DAT2 (MTK_PIN_NO(202) | 1) +#define PINMUX_GPIO202__FUNC_ANT_SEL4 (MTK_PIN_NO(202) | 2) +#define PINMUX_GPIO202__FUNC_SDA2 (MTK_PIN_NO(202) | 3) +#define PINMUX_GPIO202__FUNC_C2K_NTRST (MTK_PIN_NO(202) | 4) +#define PINMUX_GPIO202__FUNC_UTXD1 (MTK_PIN_NO(202) | 5) +#define PINMUX_GPIO202__FUNC_KCOL3 (MTK_PIN_NO(202) | 6) +#define PINMUX_GPIO202__FUNC_DM_JTINTP (MTK_PIN_NO(202) | 7) + +#define PINMUX_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +#define PINMUX_GPIO203__FUNC_MSDC2_DAT3 (MTK_PIN_NO(203) | 1) +#define PINMUX_GPIO203__FUNC_ANT_SEL5 (MTK_PIN_NO(203) | 2) +#define PINMUX_GPIO203__FUNC_SCL2 (MTK_PIN_NO(203) | 3) +#define PINMUX_GPIO203__FUNC_C2K_RTCK (MTK_PIN_NO(203) | 4) +#define PINMUX_GPIO203__FUNC_URXD1 (MTK_PIN_NO(203) | 5) +#define PINMUX_GPIO203__FUNC_KCOL6 (MTK_PIN_NO(203) | 6) + +#endif /* _DT_BINDINGS_PINCTRL_MEDIATEK_MT6735_PINFUNC_H */ From 7c402485c56380fdc06e00c6fcdae903f63d9c89 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Fri, 25 Sep 2026 18:53:58 +0000 Subject: [PATCH 102/106] pinctrl: mediatek: Add MT6735 pinctrl driver Add a driver for the MediaTek MT6735 SoC pin controller. This driver also supports the pin controller on MT6735M, which lacks 6 physical pins (198-203) used for MSDC2 on MT6735. Signed-off-by: Yassine Oudjana Signed-off-by: Linus Walleij --- MAINTAINERS | 2 + drivers/pinctrl/mediatek/Kconfig | 7 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt6735.c | 1120 +++++ drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h | 3993 +++++++++++++++++ 5 files changed, 5123 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6735.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h diff --git a/MAINTAINERS b/MAINTAINERS index 92069eaad2cb..9270abea0e12 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21564,6 +21564,8 @@ M: Yassine Oudjana L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +F: drivers/pinctrl/mediatek/pinctrl-mt6735.c +F: drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h F: include/dt-bindings/pinctrl/mediatek,mt6735-pinfunc.h PIN CONTROLLER - MICROCHIP AT91 diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 30ef3dc5dfb1..912d782fb6a5 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -133,6 +133,13 @@ config PINCTRL_MT2712 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK +config PINCTRL_MT6735 + bool "MediaTek MT6735(M) pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + config PINCTRL_MT6765 tristate "MediaTek MT6765 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 6ee3833dc6e2..9982866359af 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o +obj-$(CONFIG_PINCTRL_MT6735) += pinctrl-mt6735.o obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6735.c b/drivers/pinctrl/mediatek/pinctrl-mt6735.c new file mode 100644 index 000000000000..3ee603351b5e --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6735.c @@ -0,0 +1,1120 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "pinctrl-mtk-mt6735.h" +#include "pinctrl-paris.h" + +/* Common registers */ +#define GPIO_DIR 0x000 +#define GPIO_DOUT 0x100 +#define GPIO_DIN 0x200 +#define GPIO_MODE1 0x300 +#define GPIO_MODE2 0x310 +#define GPIO_MODE3 0x320 +#define GPIO_MODE4 0x330 +#define GPIO_MODE5 0x340 +#define GPIO_MODE6 0x350 +#define GPIO_MODE7 0x360 +#define GPIO_MODE8 0x370 +#define GPIO_MODE9 0x380 +#define GPIO_MODE10 0x390 +#define GPIO_MODE11 0x3a0 +#define GPIO_MODE12 0x3b0 +#define GPIO_MODE13 0x3c0 +#define GPIO_MODE14 0x3d0 +#define GPIO_MODE15 0x3e0 +#define GPIO_MODE16 0x3f0 +#define GPIO_MODE17 0x400 +#define GPIO_MODE18 0x410 +#define GPIO_MODE19 0x420 +#define GPIO_MODE20 0x430 +#define GPIO_MODE21 0x440 + +/* Pin group registers */ +#define GPIO_IES 0x000 /* 16-bit */ +#define GPIO_SMT 0x010 /* 16-bit */ +#define GPIO_TDSEL 0x020 /* 32-bit */ +#define GPIO_RDSEL 0x028 /* 32-bit */ +#define GPIO_PULLEN 0x030 /* 32-bit */ +#define GPIO_PULLSEL 0x050 /* 32-bit */ +#define GPIO_DRV 0x070 /* 32-bit */ +#define GPIO_PUPD 0x080 /* 32-bit */ + +/* Every pin has its own bit(s) */ +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _s_width, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, _s_width, 0) + +/* All pins in the range share the same bit(s) */ +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _s_width, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, _s_width, 1) + +static const struct mtk_pin_field_calc mt6735_pin_dir_range[] = { + PIN_FIELD(0, 203, GPIO_DIR, 0x10, 0, 1) +}; + +static const struct mtk_pin_field_calc mt6735_pin_di_range[] = { + PIN_FIELD(0, 203, GPIO_DIN, 0x10, 0, 1) +}; + +static const struct mtk_pin_field_calc mt6735_pin_do_range[] = { + PIN_FIELD(0, 203, GPIO_DOUT, 0x10, 0, 1) +}; + +static const struct mtk_pin_field_calc mt6735_pin_mode_range[] = { + PIN_FIELD(0, 4, GPIO_MODE1, 0, 0, 3), + PIN_FIELD(5, 9, GPIO_MODE1, 0, 16, 3), + PIN_FIELD(10, 14, GPIO_MODE2, 0, 0, 3), + PIN_FIELD(15, 19, GPIO_MODE2, 0, 16, 3), + PIN_FIELD(20, 24, GPIO_MODE3, 0, 0, 3), + PIN_FIELD(25, 29, GPIO_MODE3, 0, 16, 3), + PIN_FIELD(30, 34, GPIO_MODE4, 0, 0, 3), + PIN_FIELD(35, 39, GPIO_MODE4, 0, 16, 3), + PIN_FIELD(40, 44, GPIO_MODE5, 0, 0, 3), + PIN_FIELD(45, 49, GPIO_MODE5, 0, 16, 3), + PIN_FIELD(50, 54, GPIO_MODE6, 0, 0, 3), + PIN_FIELD(55, 59, GPIO_MODE6, 0, 16, 3), + PIN_FIELD(60, 64, GPIO_MODE7, 0, 0, 3), + PIN_FIELD(65, 69, GPIO_MODE7, 0, 16, 3), + PIN_FIELD(70, 74, GPIO_MODE8, 0, 0, 3), + PIN_FIELD(75, 79, GPIO_MODE8, 0, 16, 3), + PIN_FIELD(80, 84, GPIO_MODE9, 0, 0, 3), + PIN_FIELD(85, 89, GPIO_MODE9, 0, 16, 3), + PIN_FIELD(90, 94, GPIO_MODE10, 0, 0, 3), + PIN_FIELD(95, 99, GPIO_MODE10, 0, 16, 3), + PIN_FIELD(100, 104, GPIO_MODE11, 0, 0, 3), + PIN_FIELD(105, 109, GPIO_MODE11, 0, 16, 3), + PIN_FIELD(110, 114, GPIO_MODE12, 0, 0, 3), + PIN_FIELD(115, 119, GPIO_MODE12, 0, 16, 3), + PIN_FIELD(120, 124, GPIO_MODE13, 0, 0, 3), + PIN_FIELD(125, 129, GPIO_MODE13, 0, 16, 3), + PIN_FIELD(130, 134, GPIO_MODE14, 0, 0, 3), + PIN_FIELD(135, 139, GPIO_MODE14, 0, 16, 3), + PIN_FIELD(140, 144, GPIO_MODE15, 0, 0, 3), + PIN_FIELD(145, 149, GPIO_MODE15, 0, 16, 3), + PIN_FIELD(150, 154, GPIO_MODE16, 0, 0, 3), + PIN_FIELD(155, 159, GPIO_MODE16, 0, 16, 3), + PIN_FIELD(160, 164, GPIO_MODE17, 0, 0, 3), + PIN_FIELD(165, 169, GPIO_MODE17, 0, 16, 3), + PIN_FIELD(170, 174, GPIO_MODE18, 0, 0, 3), + PIN_FIELD(175, 179, GPIO_MODE18, 0, 16, 3), + PIN_FIELD(180, 184, GPIO_MODE19, 0, 0, 3), + PIN_FIELD(185, 189, GPIO_MODE19, 0, 16, 3), + PIN_FIELD(190, 194, GPIO_MODE20, 0, 0, 3), + PIN_FIELD(195, 199, GPIO_MODE20, 0, 16, 3), + PIN_FIELD(200, 203, GPIO_MODE21, 0, 0, 3), +}; + + +static const struct mtk_pin_field_calc mt6735_pin_smt_range[] = { + PINS_FIELD_BASE(0, 4, 2, GPIO_SMT, 16, 0, 10, 1), /* EINT0~4 */ + PINS_FIELD_BASE(5, 8, 3, GPIO_SMT, 16, 0, 3, 1), /* EINT5~8 */ + PINS_FIELD_BASE(9, 12, 3, GPIO_SMT, 16, 0, 6, 1), /* EINT9~12 */ + PINS_FIELD_BASE(13, 18, 1, GPIO_SMT, 16, 0, 0, 1), /* WB_CTRL */ + PINS_FIELD_BASE(19, 21, 1, GPIO_SMT, 16, 0, 1, 1), /* ANTSEL */ + PINS_FIELD_BASE(45, 46, 2, GPIO_SMT, 16, 0, 1, 1), /* CMMCLK */ + PINS_FIELD_BASE(47, 48, 2, GPIO_SMT, 16, 0, 2, 1), /* I2C0 */ + PINS_FIELD_BASE(49, 50, 2, GPIO_SMT, 16, 0, 3, 1), /* I2C1 */ + PINS_FIELD_BASE(51, 52, 2, GPIO_SMT, 16, 0, 4, 1), /* I2C2 */ + PINS_FIELD_BASE(53, 54, 2, GPIO_SMT, 16, 0, 5, 1), /* I2C3 */ + PINS_FIELD_BASE(55, 55, 2, GPIO_SMT, 16, 0, 6, 1), /* SRCLKENAI */ + PINS_FIELD_BASE(56, 56, 2, GPIO_SMT, 16, 0, 7, 1), /* SRCLKENA1 */ + PINS_FIELD_BASE(57, 60, 2, GPIO_SMT, 16, 0, 8, 1), /* UART2/3 */ + PINS_FIELD_BASE(61, 64, 2, GPIO_SMT, 16, 0, 9, 1), /* PCM */ + PINS_FIELD_BASE(65, 68, 3, GPIO_SMT, 16, 0, 0, 1), /* SPI */ + PINS_FIELD_BASE(69, 69, 3, GPIO_SMT, 16, 0, 1, 1), /* DISP_PWM */ + PINS_FIELD_BASE(70, 73, 3, GPIO_SMT, 16, 0, 2, 1), /* JTAG */ + PINS_FIELD_BASE(74, 77, 3, GPIO_SMT, 16, 0, 4, 1), /* UART0/1 */ + PINS_FIELD_BASE(78, 80, 3, GPIO_SMT, 16, 0, 5, 1), /* I2S */ + PINS_FIELD_BASE(81, 86, 3, GPIO_SMT, 16, 0, 7, 1), /* KEYPAD */ + PINS_FIELD_BASE(87, 103, 3, GPIO_SMT, 16, 0, 8, 1), /* BPI5~20, C2K_TKBPI */ + PINS_FIELD_BASE(104, 114, 3, GPIO_SMT, 16, 0, 9, 1), /* RFIC0/1 */ + PINS_FIELD_BASE(118, 136, 4, GPIO_SMT, 16, 0, 0, 1), /* LTE_TXBPI, BPI0~4, BPI21~27, PAVM */ + PINS_FIELD_BASE(137, 137, 4, GPIO_SMT, 16, 0, 1, 1), /* RTC32K */ + PINS_FIELD_BASE(138, 142, 4, GPIO_SMT, 16, 0, 2, 1), /* PWRAP */ + PINS_FIELD_BASE(143, 145, 4, GPIO_SMT, 16, 0, 3, 1), /* AUD */ + PINS_FIELD_BASE(146, 147, 4, GPIO_SMT, 16, 0, 4, 1), /* LCM_RST, DSI_TE */ + PINS_FIELD_BASE(148, 148, 4, GPIO_SMT, 16, 0, 5, 1), /* SRCLKENA0 */ + PINS_FIELD_BASE(149, 149, 4, GPIO_SMT, 16, 0, 1, 1), /* WATCHDOG */ + PINS_FIELD_BASE(160, 162, 5, GPIO_SMT, 16, 0, 0, 1), /* SIM2 */ + PINS_FIELD_BASE(163, 165, 4, GPIO_SMT, 16, 0, 1, 1), /* SIM1 */ + PINS_FIELD_BASE(166, 166, 5, GPIO_SMT, 16, 0, 2, 1), /* MSDC1_CMD */ + PINS_FIELD_BASE(167, 167, 5, GPIO_SMT, 16, 0, 3, 1), /* MSDC1_CLK */ + PINS_FIELD_BASE(168, 171, 5, GPIO_SMT, 16, 0, 4, 1), /* MSDC1_DAT */ + PINS_FIELD_BASE(172, 172, 6, GPIO_SMT, 16, 0, 0, 1), /* MSDC0_CMD */ + PINS_FIELD_BASE(173, 173, 6, GPIO_SMT, 16, 0, 1, 1), /* MSDC0_DSL */ + PINS_FIELD_BASE(174, 174, 6, GPIO_SMT, 16, 0, 2, 1), /* MSDC0_CLK */ + PINS_FIELD_BASE(175, 182, 6, GPIO_SMT, 16, 0, 3, 1), /* MSDC0_DAT */ + PINS_FIELD_BASE(183, 183, 6, GPIO_SMT, 16, 0, 4, 1), /* MSDC0_RSTB */ + PINS_FIELD_BASE(184, 185, 6, GPIO_SMT, 16, 0, 5, 1), /* FM */ + PINS_FIELD_BASE(186, 189, 6, GPIO_SMT, 16, 0, 6, 1), /* WB SPI */ + PINS_FIELD_BASE(198, 198, 1, GPIO_SMT, 16, 0, 2, 1), /* MSDC2_CMD */ + PINS_FIELD_BASE(199, 199, 1, GPIO_SMT, 16, 0, 3, 1), /* MSDC2_CLK */ + PINS_FIELD_BASE(200, 203, 1, GPIO_SMT, 16, 0, 4, 1), /* MSDC2_DAT */ +}; + +static const struct mtk_pin_field_calc mt6735_pin_ies_range[] = { + PINS_FIELD_BASE(0, 4, 2, GPIO_IES, 16, 0, 10, 1), /* EINT0~4 */ + PINS_FIELD_BASE(5, 8, 3, GPIO_IES, 16, 0, 3, 1), /* EINT5~8 */ + PINS_FIELD_BASE(9, 12, 3, GPIO_IES, 16, 0, 6, 1), /* EINT9~12 */ + PINS_FIELD_BASE(13, 18, 1, GPIO_IES, 16, 0, 0, 1), /* WB_CTRL */ + PINS_FIELD_BASE(19, 21, 1, GPIO_IES, 16, 0, 1, 1), /* ANTSEL */ + PINS_FIELD_BASE(45, 46, 2, GPIO_IES, 16, 0, 1, 1), /* CMMCLK */ + PINS_FIELD_BASE(47, 48, 2, GPIO_IES, 16, 0, 2, 1), /* I2C0 */ + PINS_FIELD_BASE(49, 50, 2, GPIO_IES, 16, 0, 3, 1), /* I2C1 */ + PINS_FIELD_BASE(51, 52, 2, GPIO_IES, 16, 0, 4, 1), /* I2C2 */ + PINS_FIELD_BASE(53, 54, 2, GPIO_IES, 16, 0, 5, 1), /* I2C3 */ + PINS_FIELD_BASE(55, 55, 2, GPIO_IES, 16, 0, 6, 1), /* SRCLKENAI */ + PINS_FIELD_BASE(56, 56, 2, GPIO_IES, 16, 0, 7, 1), /* SRCLKENA1 */ + PINS_FIELD_BASE(57, 60, 2, GPIO_IES, 16, 0, 8, 1), /* UART2/3 */ + PINS_FIELD_BASE(61, 64, 2, GPIO_IES, 16, 0, 9, 1), /* PCM */ + PINS_FIELD_BASE(65, 68, 3, GPIO_IES, 16, 0, 0, 1), /* SPI */ + PINS_FIELD_BASE(69, 69, 3, GPIO_IES, 16, 0, 1, 1), /* DISP_PWM */ + PINS_FIELD_BASE(70, 73, 3, GPIO_IES, 16, 0, 2, 1), /* JTAG */ + PINS_FIELD_BASE(74, 77, 3, GPIO_IES, 16, 0, 4, 1), /* UART0/1 */ + PINS_FIELD_BASE(78, 80, 3, GPIO_IES, 16, 0, 5, 1), /* I2S */ + PINS_FIELD_BASE(81, 86, 3, GPIO_IES, 16, 0, 7, 1), /* KEYPAD */ + PINS_FIELD_BASE(87, 103, 3, GPIO_IES, 16, 0, 8, 1), /* BPI5~20, C2K_TKBPI */ + PINS_FIELD_BASE(104, 114, 3, GPIO_IES, 16, 0, 9, 1), /* RFIC0/1 */ + PINS_FIELD_BASE(118, 136, 4, GPIO_IES, 16, 0, 0, 1), /* LTE_TXBPI, BPI0~4, BPI21~27, PAVM */ + PINS_FIELD_BASE(137, 137, 4, GPIO_IES, 16, 0, 1, 1), /* RTC32K */ + PINS_FIELD_BASE(138, 142, 4, GPIO_IES, 16, 0, 2, 1), /* PWRAP */ + PINS_FIELD_BASE(143, 145, 4, GPIO_IES, 16, 0, 3, 1), /* AUD */ + PINS_FIELD_BASE(146, 147, 4, GPIO_IES, 16, 0, 4, 1), /* LCM_RST, DSI_TE */ + PINS_FIELD_BASE(148, 148, 4, GPIO_IES, 16, 0, 5, 1), /* SRCLKENA0 */ + PINS_FIELD_BASE(149, 149, 4, GPIO_IES, 16, 0, 1, 1), /* WATCHDOG */ + PINS_FIELD_BASE(160, 162, 5, GPIO_IES, 16, 0, 0, 1), /* SIM2 */ + PINS_FIELD_BASE(163, 165, 4, GPIO_IES, 16, 0, 1, 1), /* SIM1 */ + PINS_FIELD_BASE(166, 166, 5, GPIO_IES, 16, 0, 2, 1), /* MSDC1_CMD */ + PINS_FIELD_BASE(167, 167, 5, GPIO_IES, 16, 0, 3, 1), /* MSDC1_CLK */ + PINS_FIELD_BASE(168, 171, 5, GPIO_IES, 16, 0, 4, 1), /* MSDC1_DAT */ + PINS_FIELD_BASE(172, 172, 6, GPIO_IES, 16, 0, 0, 1), /* MSDC0_CMD */ + PINS_FIELD_BASE(173, 173, 6, GPIO_IES, 16, 0, 1, 1), /* MSDC0_DSL */ + PINS_FIELD_BASE(174, 174, 6, GPIO_IES, 16, 0, 2, 1), /* MSDC0_CLK */ + PINS_FIELD_BASE(175, 182, 6, GPIO_IES, 16, 0, 3, 1), /* MSDC0_DAT */ + PINS_FIELD_BASE(183, 183, 6, GPIO_IES, 16, 0, 4, 1), /* MSDC0_RSTB */ + PINS_FIELD_BASE(184, 185, 6, GPIO_IES, 16, 0, 5, 1), /* FM */ + PINS_FIELD_BASE(186, 189, 6, GPIO_IES, 16, 0, 6, 1), /* WB SPI */ + PINS_FIELD_BASE(198, 198, 1, GPIO_IES, 16, 0, 2, 1), /* MSDC2_CMD */ + PINS_FIELD_BASE(199, 199, 1, GPIO_IES, 16, 0, 3, 1), /* MSDC2_CLK */ + PINS_FIELD_BASE(200, 203, 1, GPIO_IES, 16, 0, 4, 1) /* MSDC2_DAT */ +}; + +static const struct mtk_pin_field_calc mt6735_pin_tdsel_range[] = { + PINS_FIELD_BASE(0, 4, 2, GPIO_TDSEL, 32, 0x04, 40, 4), /* EINT0~4 */ + PINS_FIELD_BASE(5, 8, 3, GPIO_TDSEL, 32, 0x04, 12, 4), /* EINT5~8 */ + PINS_FIELD_BASE(9, 12, 3, GPIO_TDSEL, 32, 0x04, 24, 4), /* EINT9~12 */ + PINS_FIELD_BASE(13, 18, 1, GPIO_TDSEL, 32, 0, 0, 4), /* WB_CTRL */ + PINS_FIELD_BASE(19, 21, 1, GPIO_TDSEL, 32, 0, 4, 4), /* ANTSEL */ + PINS_FIELD_BASE(45, 46, 2, GPIO_TDSEL, 32, 0x04, 4, 4), /* CMMCLK */ + PINS_FIELD_BASE(47, 48, 2, GPIO_TDSEL, 32, 0x04, 8, 4), /* I2C0 */ + PINS_FIELD_BASE(49, 50, 2, GPIO_TDSEL, 32, 0x04, 12, 4), /* I2C1 */ + PINS_FIELD_BASE(51, 52, 2, GPIO_TDSEL, 32, 0x04, 16, 4), /* I2C2 */ + PINS_FIELD_BASE(53, 54, 2, GPIO_TDSEL, 32, 0x04, 20, 4), /* I2C3 */ + PINS_FIELD_BASE(55, 55, 2, GPIO_TDSEL, 32, 0x04, 24, 4), /* SRCLKENAI */ + PINS_FIELD_BASE(56, 56, 2, GPIO_TDSEL, 32, 0x04, 28, 4), /* SRCLKENA1 */ + PINS_FIELD_BASE(57, 60, 2, GPIO_TDSEL, 32, 0x04, 32, 4), /* UART2/3 */ + PINS_FIELD_BASE(61, 64, 2, GPIO_TDSEL, 32, 0x04, 36, 4), /* PCM */ + PINS_FIELD_BASE(65, 68, 3, GPIO_TDSEL, 32, 0x04, 0, 4), /* SPI */ + PINS_FIELD_BASE(69, 69, 3, GPIO_TDSEL, 32, 0x04, 4, 4), /* DISP_PWM */ + PINS_FIELD_BASE(70, 73, 3, GPIO_TDSEL, 32, 0x04, 8, 4), /* JTAG */ + PINS_FIELD_BASE(74, 77, 3, GPIO_TDSEL, 32, 0x04, 16, 4), /* UART0/1 */ + PINS_FIELD_BASE(78, 80, 3, GPIO_TDSEL, 32, 0x04, 20, 4), /* I2S */ + PINS_FIELD_BASE(81, 86, 3, GPIO_TDSEL, 32, 0x04, 28, 4), /* KEYPAD */ + PINS_FIELD_BASE(87, 103, 3, GPIO_TDSEL, 32, 0x04, 32, 4), /* BPI5~20, C2K_TKBPI */ + PINS_FIELD_BASE(104, 114, 3, GPIO_TDSEL, 32, 0x04, 36, 4), /* RFIC0/1 */ + PINS_FIELD_BASE(118, 136, 4, GPIO_TDSEL, 32, 0, 0, 4), /* LTE_TXBPI, BPI0~4, BPI21~27, PAVM */ + PINS_FIELD_BASE(137, 137, 4, GPIO_TDSEL, 32, 0, 4, 4), /* RTC32K */ + PINS_FIELD_BASE(138, 142, 4, GPIO_TDSEL, 32, 0, 8, 4), /* PWRAP */ + PINS_FIELD_BASE(143, 145, 4, GPIO_TDSEL, 32, 0, 12, 4), /* AUD */ + PINS_FIELD_BASE(146, 147, 4, GPIO_TDSEL, 32, 0, 16, 4), /* LCM_RST, DSI_TE */ + PINS_FIELD_BASE(148, 148, 4, GPIO_TDSEL, 32, 0, 20, 4), /* SRCLKENA0 */ + PINS_FIELD_BASE(149, 149, 4, GPIO_TDSEL, 32, 0, 4, 4), /* WATCHDOG */ + PINS_FIELD_BASE(160, 162, 5, GPIO_TDSEL, 32, 0, 0, 4), /* SIM2 */ + PINS_FIELD_BASE(163, 165, 5, GPIO_TDSEL, 32, 0, 4, 4), /* SIM1 */ + PINS_FIELD_BASE(166, 166, 5, GPIO_TDSEL, 32, 0, 8, 4), /* MSDC1_CMD */ + PINS_FIELD_BASE(167, 167, 5, GPIO_TDSEL, 32, 0, 12, 4), /* MSDC1_CLK */ + PINS_FIELD_BASE(168, 171, 5, GPIO_TDSEL, 32, 0, 16, 4), /* MSDC1_DAT */ + PINS_FIELD_BASE(172, 172, 6, GPIO_TDSEL, 32, 0, 0, 4), /* MSDC0_CMD */ + PINS_FIELD_BASE(173, 173, 6, GPIO_TDSEL, 32, 0, 4, 4), /* MSDC0_DSL */ + PINS_FIELD_BASE(174, 174, 6, GPIO_TDSEL, 32, 0, 8, 4), /* MSDC0_CLK */ + PINS_FIELD_BASE(175, 182, 6, GPIO_TDSEL, 32, 0, 12, 4), /* MSDC0_DAT */ + PINS_FIELD_BASE(183, 183, 6, GPIO_TDSEL, 32, 0, 16, 4), /* MSDC0_RSTB */ + PINS_FIELD_BASE(184, 185, 6, GPIO_TDSEL, 32, 0, 20, 4), /* FM */ + PINS_FIELD_BASE(186, 189, 6, GPIO_TDSEL, 32, 0, 24, 4), /* WB SPI */ + PINS_FIELD_BASE(198, 198, 1, GPIO_TDSEL, 32, 0, 8, 4), /* MSDC2_CMD */ + PINS_FIELD_BASE(199, 199, 1, GPIO_TDSEL, 32, 0, 12, 4), /* MSDC2_CLK */ + PINS_FIELD_BASE(200, 203, 1, GPIO_TDSEL, 32, 0, 16, 4) /* MSDC2_DAT */ +}; + +static const struct mtk_pin_field_calc mt6735_pin_rdsel_range[] = { + PINS_FIELD_BASE(0, 4, 2, GPIO_RDSEL, 32, 0x04, 24, 2), /* EINT0~4 */ + PINS_FIELD_BASE(5, 8, 3, GPIO_RDSEL, 32, 0, 6, 2), /* EINT5~8 */ + PINS_FIELD_BASE(9, 12, 3, GPIO_RDSEL, 32, 0, 12, 2), /* EINT9~12 */ + PINS_FIELD_BASE(13, 18, 1, GPIO_RDSEL, 32, 0, 0, 2), /* WB_CTRL */ + PINS_FIELD_BASE(19, 21, 1, GPIO_RDSEL, 32, 0, 2, 2), /* ANTSEL */ + PINS_FIELD_BASE(45, 46, 2, GPIO_RDSEL, 32, 0x04, 2, 6), /* CMMCLK */ + PINS_FIELD_BASE(47, 48, 2, GPIO_RDSEL, 32, 0x04, 8, 2), /* I2C0 */ + PINS_FIELD_BASE(49, 50, 2, GPIO_RDSEL, 32, 0x04, 10, 2), /* I2C1 */ + PINS_FIELD_BASE(51, 52, 2, GPIO_RDSEL, 32, 0x04, 12, 2), /* I2C2 */ + PINS_FIELD_BASE(53, 54, 2, GPIO_RDSEL, 32, 0x04, 14, 2), /* I2C3 */ + PINS_FIELD_BASE(55, 55, 2, GPIO_RDSEL, 32, 0x04, 16, 2), /* SRCLKENAI */ + PINS_FIELD_BASE(56, 56, 2, GPIO_RDSEL, 32, 0x04, 18, 2), /* SRCLKENA1 */ + PINS_FIELD_BASE(57, 60, 2, GPIO_RDSEL, 32, 0x04, 20, 2), /* UART2/3 */ + PINS_FIELD_BASE(61, 64, 2, GPIO_RDSEL, 32, 0x04, 22, 2), /* PCM */ + PINS_FIELD_BASE(65, 68, 3, GPIO_RDSEL, 32, 0, 0, 2), /* SPI */ + PINS_FIELD_BASE(69, 69, 3, GPIO_RDSEL, 32, 0, 2, 2), /* DISP_PWM */ + PINS_FIELD_BASE(70, 73, 3, GPIO_RDSEL, 32, 0, 4, 2), /* JTAG */ + PINS_FIELD_BASE(74, 77, 3, GPIO_RDSEL, 32, 0, 8, 2), /* UART0/1 */ + PINS_FIELD_BASE(78, 80, 3, GPIO_RDSEL, 32, 0, 10, 2), /* I2S */ + PINS_FIELD_BASE(81, 86, 3, GPIO_RDSEL, 32, 0, 14, 2), /* KEYPAD */ + PINS_FIELD_BASE(87, 103, 3, GPIO_RDSEL, 32, 0, 16, 2), /* BPI5~20, C2K_TKBPI */ + PINS_FIELD_BASE(104, 114, 3, GPIO_RDSEL, 32, 0, 18, 2), /* RFIC0/1 */ + PINS_FIELD_BASE(118, 136, 4, GPIO_RDSEL, 32, 0, 0, 2), /* LTE_TXBPI, BPI0~4, BPI21~27, PAVM */ + PINS_FIELD_BASE(137, 137, 4, GPIO_RDSEL, 32, 0, 4, 2), /* RTC32K */ + PINS_FIELD_BASE(138, 142, 4, GPIO_RDSEL, 32, 0, 6, 2), /* PWRAP */ + PINS_FIELD_BASE(143, 145, 4, GPIO_RDSEL, 32, 0, 8, 2), /* AUD */ + PINS_FIELD_BASE(146, 147, 4, GPIO_RDSEL, 32, 0, 10, 2), /* LCM_RST, DSI_TE */ + PINS_FIELD_BASE(148, 148, 4, GPIO_RDSEL, 32, 0, 12, 2), /* SRCLKENA0 */ + PINS_FIELD_BASE(149, 149, 4, GPIO_RDSEL, 32, 0, 4, 2), /* WATCHDOG */ + PINS_FIELD_BASE(160, 162, 5, GPIO_RDSEL, 32, 0, 0, 6), /* SIM2 */ + PINS_FIELD_BASE(163, 165, 5, GPIO_RDSEL, 32, 0, 6, 6), /* SIM1 */ + PINS_FIELD_BASE(166, 166, 5, GPIO_RDSEL, 32, 0, 12, 6), /* MSDC1_CMD */ + PINS_FIELD_BASE(167, 167, 5, GPIO_RDSEL, 32, 0, 18, 6), /* MSDC1_CLK */ + PINS_FIELD_BASE(168, 171, 5, GPIO_RDSEL, 32, 0, 24, 6), /* MSDC1_DAT */ + PINS_FIELD_BASE(172, 172, 6, GPIO_RDSEL, 32, 4, 0, 6), /* MSDC0_CMD */ + PINS_FIELD_BASE(173, 173, 6, GPIO_RDSEL, 32, 4, 6, 6), /* MSDC0_DSL */ + PINS_FIELD_BASE(174, 174, 6, GPIO_RDSEL, 32, 4, 12, 6), /* MSDC0_CLK */ + PINS_FIELD_BASE(175, 182, 6, GPIO_RDSEL, 32, 4, 18, 6), /* MSDC0_DAT */ + PINS_FIELD_BASE(183, 183, 6, GPIO_RDSEL, 32, 4, 24, 6), /* MSDC0_RSTB */ + PINS_FIELD_BASE(184, 185, 6, GPIO_RDSEL, 32, 4, 30, 2), /* FM */ + PINS_FIELD_BASE(186, 189, 6, GPIO_RDSEL, 32, 4, 32, 2), /* WB SPI */ + PINS_FIELD_BASE(198, 198, 1, GPIO_RDSEL, 32, 0, 4, 6), /* MSDC2_CMD */ + PINS_FIELD_BASE(199, 199, 1, GPIO_RDSEL, 32, 0, 10, 6), /* MSDC2_CLK */ + PINS_FIELD_BASE(200, 203, 1, GPIO_RDSEL, 32, 0, 16, 6) /* MSDC2_DAT */ +}; + +static const struct mtk_pin_field_calc mt6735_pin_drv_range[] = { + PINS_FIELD_BASE(0, 4, 2, GPIO_DRV, 32, 0x04, 41, 2), /* EINT0~4 */ + PINS_FIELD_BASE(5, 8, 3, GPIO_DRV, 32, 0x04, 13, 2), /* EINT5~8 */ + PINS_FIELD_BASE(9, 12, 3, GPIO_DRV, 32, 0x04, 25, 2), /* EINT9~12 */ + PINS_FIELD_BASE(13, 18, 1, GPIO_DRV, 32, 0, 1, 2), /* WB_CTRL */ + PINS_FIELD_BASE(19, 21, 1, GPIO_DRV, 32, 0, 5, 2), /* ANTSEL */ + PINS_FIELD_BASE(45, 46, 2, GPIO_DRV, 32, 0x04, 4, 3), /* CMMCLK */ + PINS_FIELD_BASE(55, 55, 2, GPIO_DRV, 32, 0x04, 25, 2), /* SRCLKENAI */ + PINS_FIELD_BASE(56, 56, 2, GPIO_DRV, 32, 0x04, 29, 2), /* SRCLKENA1 */ + PINS_FIELD_BASE(57, 60, 2, GPIO_DRV, 32, 0x04, 33, 2), /* UART2/3 */ + PINS_FIELD_BASE(61, 64, 2, GPIO_DRV, 32, 0x04, 37, 2), /* PCM */ + PINS_FIELD_BASE(65, 68, 3, GPIO_DRV, 32, 0x04, 1, 2), /* SPI */ + PINS_FIELD_BASE(69, 69, 3, GPIO_DRV, 32, 0x04, 5, 2), /* DISP_PWM */ + PINS_FIELD_BASE(70, 73, 3, GPIO_DRV, 32, 0x04, 9, 2), /* JTAG */ + PINS_FIELD_BASE(74, 77, 3, GPIO_DRV, 32, 0x04, 17, 2), /* UART0/1 */ + PINS_FIELD_BASE(78, 80, 3, GPIO_DRV, 32, 0x04, 21, 2), /* I2S */ + PINS_FIELD_BASE(81, 86, 3, GPIO_DRV, 32, 0x04, 29, 2), /* KEYPAD */ + PINS_FIELD_BASE(87, 103, 3, GPIO_DRV, 32, 0x04, 33, 2), /* BPI5~20, C2K_TKBPI */ + PINS_FIELD_BASE(104, 114, 3, GPIO_DRV, 32, 0x04, 37, 2), /* RFIC0/1 */ + PINS_FIELD_BASE(118, 136, 4, GPIO_DRV, 32, 0, 1, 2), /* LTE_TXBPI, BPI0~4, BPI21~27, PAVM */ + PINS_FIELD_BASE(137, 137, 4, GPIO_DRV, 32, 0, 5, 2), /* RTC32K */ + PINS_FIELD_BASE(138, 142, 4, GPIO_DRV, 32, 0, 9, 2), /* PWRAP */ + PINS_FIELD_BASE(143, 145, 4, GPIO_DRV, 32, 0, 13, 2), /* AUD */ + PINS_FIELD_BASE(146, 147, 4, GPIO_DRV, 32, 0, 17, 2), /* LCM_RST, DSI_TE */ + PINS_FIELD_BASE(148, 148, 4, GPIO_DRV, 32, 0, 21, 2), /* SRCLKENA0 */ + PINS_FIELD_BASE(149, 149, 4, GPIO_DRV, 32, 0, 5, 2), /* WATCHDOG */ + PINS_FIELD_BASE(160, 162, 5, GPIO_DRV, 32, 0, 1, 2), /* SIM2 */ + PINS_FIELD_BASE(163, 165, 5, GPIO_DRV, 32, 0, 5, 2), /* SIM1 */ + PINS_FIELD_BASE(166, 166, 5, GPIO_DRV, 32, 0, 9, 3), /* MSDC1_CMD */ + PINS_FIELD_BASE(167, 167, 5, GPIO_DRV, 32, 0, 12, 3), /* MSDC1_CLK */ + PINS_FIELD_BASE(168, 171, 5, GPIO_DRV, 32, 0, 16, 3), /* MSDC1_DAT */ + PINS_FIELD_BASE(172, 172, 6, GPIO_DRV, 32, 0, 0, 3), /* MSDC0_CMD */ + PINS_FIELD_BASE(173, 173, 6, GPIO_DRV, 32, 0, 4, 3), /* MSDC0_DSL */ + PINS_FIELD_BASE(174, 174, 6, GPIO_DRV, 32, 0, 8, 3), /* MSDC0_CLK */ + PINS_FIELD_BASE(175, 182, 6, GPIO_DRV, 32, 0, 12, 3), /* MSDC0_DAT */ + PINS_FIELD_BASE(183, 183, 6, GPIO_DRV, 32, 0, 16, 3), /* MSDC0_RSTB */ + PINS_FIELD_BASE(184, 185, 6, GPIO_DRV, 32, 0, 21, 2), /* FM */ + PINS_FIELD_BASE(186, 189, 6, GPIO_DRV, 32, 0, 25, 2), /* WB SPI */ + PINS_FIELD_BASE(198, 198, 1, GPIO_DRV, 32, 0, 8, 3), /* MSDC2_CMD */ + PINS_FIELD_BASE(199, 199, 1, GPIO_DRV, 32, 0, 12, 3), /* MSDC2_CLK */ + PINS_FIELD_BASE(200, 203, 1, GPIO_DRV, 32, 0, 16, 3) /* MSDC2_DAT */ +}; + +static const struct mtk_pin_field_calc mt6735_pin_r0_range[] = { + PINS_FIELD_BASE(45, 45, 2, GPIO_PUPD, 32, 0, 0, 1), /* CMMCLK0 */ + PINS_FIELD_BASE(46, 46, 2, GPIO_PUPD, 32, 0, 4, 1), /* CMMCLK1 */ + PINS_FIELD_BASE(81, 81, 3, GPIO_PUPD, 32, 0, 0, 1), /* KPROW0 */ + PINS_FIELD_BASE(82, 82, 3, GPIO_PUPD, 32, 0, 4, 1), /* KPROW1 */ + PINS_FIELD_BASE(83, 83, 3, GPIO_PUPD, 32, 0, 8, 1), /* KPROW2 */ + PINS_FIELD_BASE(84, 84, 3, GPIO_PUPD, 32, 0, 16, 1), /* KPCOL0 */ + PINS_FIELD_BASE(85, 85, 3, GPIO_PUPD, 32, 0, 20, 1), /* KPCOL1 */ + PINS_FIELD_BASE(86, 86, 3, GPIO_PUPD, 32, 0, 24, 1), /* KPCOL2 */ + PINS_FIELD_BASE(160, 160, 5, GPIO_PUPD, 32, 0x10, 32, 1), /* SIM2_SCLK */ + PINS_FIELD_BASE(161, 161, 5, GPIO_PUPD, 32, 0x10, 36, 1), /* SIM2_SRST */ + PINS_FIELD_BASE(162, 162, 5, GPIO_PUPD, 32, 0x10, 44, 1), /* SIM2_SDAT */ + PINS_FIELD_BASE(163, 163, 5, GPIO_PUPD, 32, 0x10, 48, 1), /* SIM1_SCLK */ + PINS_FIELD_BASE(164, 164, 5, GPIO_PUPD, 32, 0x10, 52, 1), /* SIM1_SRST */ + PINS_FIELD_BASE(165, 165, 5, GPIO_PUPD, 32, 0x10, 56, 1), /* SIM1_SDAT */ + PINS_FIELD_BASE(166, 166, 5, GPIO_PUPD, 32, 0x10, 0, 1), /* MSDC1_CMD */ + PINS_FIELD_BASE(167, 167, 5, GPIO_PUPD, 32, 0x10, 4, 1), /* MSDC1_CLK */ + PINS_FIELD_BASE(168, 168, 5, GPIO_PUPD, 32, 0x10, 8, 1), /* MSDC1_DAT0 */ + PINS_FIELD_BASE(169, 169, 5, GPIO_PUPD, 32, 0x10, 12, 1), /* MSDC1_DAT1 */ + PINS_FIELD_BASE(170, 170, 5, GPIO_PUPD, 32, 0x10, 16, 1), /* MSDC1_DAT2 */ + PINS_FIELD_BASE(171, 171, 5, GPIO_PUPD, 32, 0x10, 20, 1), /* MSDC1_DAT3 */ + PINS_FIELD_BASE(172, 172, 6, GPIO_PUPD, 32, 0x10, 0, 1), /* MSDC0_CMD */ + PINS_FIELD_BASE(173, 173, 6, GPIO_PUPD, 32, 0x10, 8, 1), /* MSDC0_DSL */ + PINS_FIELD_BASE(174, 174, 6, GPIO_PUPD, 32, 0x10, 4, 1), /* MSDC0_CLK */ + PINS_FIELD_BASE(175, 175, 6, GPIO_PUPD, 32, 0x10, 12, 1), /* MSDC0_DAT0 */ + PINS_FIELD_BASE(176, 176, 6, GPIO_PUPD, 32, 0x10, 16, 1), /* MSDC0_DAT1 */ + PINS_FIELD_BASE(177, 177, 6, GPIO_PUPD, 32, 0x10, 20, 1), /* MSDC0_DAT2 */ + PINS_FIELD_BASE(178, 178, 6, GPIO_PUPD, 32, 0x10, 24, 1), /* MSDC0_DAT3 */ + PINS_FIELD_BASE(179, 179, 6, GPIO_PUPD, 32, 0x10, 28, 1), /* MSDC0_DAT4 */ + PINS_FIELD_BASE(180, 180, 6, GPIO_PUPD, 32, 0x10, 32, 1), /* MSDC0_DAT5 */ + PINS_FIELD_BASE(181, 181, 6, GPIO_PUPD, 32, 0x10, 36, 1), /* MSDC0_DAT6 */ + PINS_FIELD_BASE(182, 182, 6, GPIO_PUPD, 32, 0x10, 40, 1), /* MSDC0_DAT7 */ + PINS_FIELD_BASE(183, 183, 6, GPIO_PUPD, 32, 0x10, 44, 1), /* MSDC0_RSTB */ + PINS_FIELD_BASE(198, 198, 1, GPIO_PUPD, 32, 0, 0, 1), /* MSDC2_CMD */ + PINS_FIELD_BASE(199, 199, 1, GPIO_PUPD, 32, 0, 4, 1), /* MSDC2_CLK */ + PINS_FIELD_BASE(200, 200, 1, GPIO_PUPD, 32, 0, 8, 1), /* MSDC2_DAT0 */ + PINS_FIELD_BASE(201, 201, 1, GPIO_PUPD, 32, 0, 12, 1), /* MSDC2_DAT1 */ + PINS_FIELD_BASE(202, 202, 1, GPIO_PUPD, 32, 0, 16, 1), /* MSDC2_DAT2 */ + PINS_FIELD_BASE(203, 203, 1, GPIO_PUPD, 32, 0, 20, 1) /* MSDC2_DAT3 */ +}; + +static const struct mtk_pin_field_calc mt6735_pin_r1_range[] = { + PINS_FIELD_BASE(45, 45, 2, GPIO_PUPD, 32, 0, 1, 1), /* CMMCLK0 */ + PINS_FIELD_BASE(46, 46, 2, GPIO_PUPD, 32, 0, 5, 1), /* CMMCLK1 */ + PINS_FIELD_BASE(81, 81, 3, GPIO_PUPD, 32, 0, 1, 1), /* KPROW0 */ + PINS_FIELD_BASE(82, 82, 3, GPIO_PUPD, 32, 0, 5, 1), /* KPROW1 */ + PINS_FIELD_BASE(83, 83, 3, GPIO_PUPD, 32, 0, 9, 1), /* KPROW2 */ + PINS_FIELD_BASE(84, 84, 3, GPIO_PUPD, 32, 0, 17, 1), /* KPCOL0 */ + PINS_FIELD_BASE(85, 85, 3, GPIO_PUPD, 32, 0, 21, 1), /* KPCOL1 */ + PINS_FIELD_BASE(86, 86, 3, GPIO_PUPD, 32, 0, 25, 1), /* KPCOL2 */ + PINS_FIELD_BASE(160, 160, 5, GPIO_PUPD, 32, 0x10, 33, 1), /* SIM2_SCLK */ + PINS_FIELD_BASE(161, 161, 5, GPIO_PUPD, 32, 0x10, 37, 1), /* SIM2_SRST */ + PINS_FIELD_BASE(162, 162, 5, GPIO_PUPD, 32, 0x10, 45, 1), /* SIM2_SDAT */ + PINS_FIELD_BASE(163, 163, 5, GPIO_PUPD, 32, 0x10, 49, 1), /* SIM1_SCLK */ + PINS_FIELD_BASE(164, 164, 5, GPIO_PUPD, 32, 0x10, 53, 1), /* SIM1_SRST */ + PINS_FIELD_BASE(165, 165, 5, GPIO_PUPD, 32, 0x10, 57, 1), /* SIM1_SDAT */ + PINS_FIELD_BASE(166, 166, 5, GPIO_PUPD, 32, 0x10, 1, 1), /* MSDC1_CMD */ + PINS_FIELD_BASE(167, 167, 5, GPIO_PUPD, 32, 0x10, 5, 1), /* MSDC1_CLK */ + PINS_FIELD_BASE(168, 168, 5, GPIO_PUPD, 32, 0x10, 9, 1), /* MSDC1_DAT0 */ + PINS_FIELD_BASE(169, 169, 5, GPIO_PUPD, 32, 0x10, 13, 1), /* MSDC1_DAT1 */ + PINS_FIELD_BASE(170, 170, 5, GPIO_PUPD, 32, 0x10, 17, 1), /* MSDC1_DAT2 */ + PINS_FIELD_BASE(171, 171, 5, GPIO_PUPD, 32, 0x10, 21, 1), /* MSDC1_DAT3 */ + PINS_FIELD_BASE(172, 172, 6, GPIO_PUPD, 32, 0x10, 1, 1), /* MSDC0_CMD */ + PINS_FIELD_BASE(173, 173, 6, GPIO_PUPD, 32, 0x10, 9, 1), /* MSDC0_DSL */ + PINS_FIELD_BASE(174, 174, 6, GPIO_PUPD, 32, 0x10, 5, 1), /* MSDC0_CLK */ + PINS_FIELD_BASE(175, 175, 6, GPIO_PUPD, 32, 0x10, 13, 1), /* MSDC0_DAT0 */ + PINS_FIELD_BASE(176, 176, 6, GPIO_PUPD, 32, 0x10, 17, 1), /* MSDC0_DAT1 */ + PINS_FIELD_BASE(177, 177, 6, GPIO_PUPD, 32, 0x10, 21, 1), /* MSDC0_DAT2 */ + PINS_FIELD_BASE(178, 178, 6, GPIO_PUPD, 32, 0x10, 25, 1), /* MSDC0_DAT3 */ + PINS_FIELD_BASE(179, 179, 6, GPIO_PUPD, 32, 0x10, 29, 1), /* MSDC0_DAT4 */ + PINS_FIELD_BASE(180, 180, 6, GPIO_PUPD, 32, 0x10, 33, 1), /* MSDC0_DAT5 */ + PINS_FIELD_BASE(181, 181, 6, GPIO_PUPD, 32, 0x10, 37, 1), /* MSDC0_DAT6 */ + PINS_FIELD_BASE(182, 182, 6, GPIO_PUPD, 32, 0x10, 41, 1), /* MSDC0_DAT7 */ + PINS_FIELD_BASE(183, 183, 6, GPIO_PUPD, 32, 0x10, 45, 1), /* MSDC0_RSTB */ + PINS_FIELD_BASE(198, 198, 1, GPIO_PUPD, 32, 0, 1, 1), /* MSDC2_CMD */ + PINS_FIELD_BASE(199, 199, 1, GPIO_PUPD, 32, 0, 5, 1), /* MSDC2_CLK */ + PINS_FIELD_BASE(200, 200, 1, GPIO_PUPD, 32, 0, 9, 1), /* MSDC2_DAT0 */ + PINS_FIELD_BASE(201, 201, 1, GPIO_PUPD, 32, 0, 13, 1), /* MSDC2_DAT1 */ + PINS_FIELD_BASE(202, 202, 1, GPIO_PUPD, 32, 0, 17, 1), /* MSDC2_DAT2 */ + PINS_FIELD_BASE(203, 203, 1, GPIO_PUPD, 32, 0, 21, 1) /* MSDC2_DAT3 */ +}; + +static const struct mtk_pin_field_calc mt6735_pin_pupd_range[] = { + PINS_FIELD_BASE(45, 45, 2, GPIO_PUPD, 32, 0, 2, 1), /* CMMCLK0 */ + PINS_FIELD_BASE(46, 46, 2, GPIO_PUPD, 32, 0, 6, 1), /* CMMCLK1 */ + PINS_FIELD_BASE(81, 81, 3, GPIO_PUPD, 32, 0, 2, 1), /* KPROW0 */ + PINS_FIELD_BASE(82, 82, 3, GPIO_PUPD, 32, 0, 6, 1), /* KPROW1 */ + PINS_FIELD_BASE(83, 83, 3, GPIO_PUPD, 32, 0, 10, 1), /* KPROW2 */ + PINS_FIELD_BASE(84, 84, 3, GPIO_PUPD, 32, 0, 18, 1), /* KPCOL0 */ + PINS_FIELD_BASE(85, 85, 3, GPIO_PUPD, 32, 0, 22, 1), /* KPCOL1 */ + PINS_FIELD_BASE(86, 86, 3, GPIO_PUPD, 32, 0, 26, 1), /* KPCOL2 */ + PINS_FIELD_BASE(160, 160, 5, GPIO_PUPD, 32, 0x10, 34, 1), /* SIM2_SCLK */ + PINS_FIELD_BASE(161, 161, 5, GPIO_PUPD, 32, 0x10, 38, 1), /* SIM2_SRST */ + PINS_FIELD_BASE(162, 162, 5, GPIO_PUPD, 32, 0x10, 46, 1), /* SIM2_SDAT */ + PINS_FIELD_BASE(163, 163, 5, GPIO_PUPD, 32, 0x10, 50, 1), /* SIM1_SCLK */ + PINS_FIELD_BASE(164, 164, 5, GPIO_PUPD, 32, 0x10, 54, 1), /* SIM1_SRST */ + PINS_FIELD_BASE(165, 165, 5, GPIO_PUPD, 32, 0x10, 58, 1), /* SIM1_SDAT */ + PINS_FIELD_BASE(166, 166, 5, GPIO_PUPD, 32, 0x10, 2, 1), /* MSDC1_CMD */ + PINS_FIELD_BASE(167, 167, 5, GPIO_PUPD, 32, 0x10, 6, 1), /* MSDC1_CLK */ + PINS_FIELD_BASE(168, 168, 5, GPIO_PUPD, 32, 0x10, 10, 1), /* MSDC1_DAT0 */ + PINS_FIELD_BASE(169, 169, 5, GPIO_PUPD, 32, 0x10, 14, 1), /* MSDC1_DAT1 */ + PINS_FIELD_BASE(170, 170, 5, GPIO_PUPD, 32, 0x10, 18, 1), /* MSDC1_DAT2 */ + PINS_FIELD_BASE(171, 171, 5, GPIO_PUPD, 32, 0x10, 22, 1), /* MSDC1_DAT3 */ + PINS_FIELD_BASE(172, 172, 6, GPIO_PUPD, 32, 0x10, 2, 1), /* MSDC0_CMD */ + PINS_FIELD_BASE(173, 173, 6, GPIO_PUPD, 32, 0x10, 10, 1), /* MSDC0_DSL */ + PINS_FIELD_BASE(174, 174, 6, GPIO_PUPD, 32, 0x10, 6, 1), /* MSDC0_CLK */ + PINS_FIELD_BASE(175, 175, 6, GPIO_PUPD, 32, 0x10, 14, 1), /* MSDC0_DAT0 */ + PINS_FIELD_BASE(176, 176, 6, GPIO_PUPD, 32, 0x10, 18, 1), /* MSDC0_DAT1 */ + PINS_FIELD_BASE(177, 177, 6, GPIO_PUPD, 32, 0x10, 22, 1), /* MSDC0_DAT2 */ + PINS_FIELD_BASE(178, 178, 6, GPIO_PUPD, 32, 0x10, 26, 1), /* MSDC0_DAT3 */ + PINS_FIELD_BASE(179, 179, 6, GPIO_PUPD, 32, 0x10, 30, 1), /* MSDC0_DAT4 */ + PINS_FIELD_BASE(180, 180, 6, GPIO_PUPD, 32, 0x10, 34, 1), /* MSDC0_DAT5 */ + PINS_FIELD_BASE(181, 181, 6, GPIO_PUPD, 32, 0x10, 38, 1), /* MSDC0_DAT6 */ + PINS_FIELD_BASE(182, 182, 6, GPIO_PUPD, 32, 0x10, 42, 1), /* MSDC0_DAT7 */ + PINS_FIELD_BASE(183, 183, 6, GPIO_PUPD, 32, 0x10, 46, 1), /* MSDC0_RSTB */ + PINS_FIELD_BASE(198, 198, 1, GPIO_PUPD, 32, 0, 2, 1), /* MSDC2_CMD */ + PINS_FIELD_BASE(199, 199, 1, GPIO_PUPD, 32, 0, 6, 1), /* MSDC2_CLK */ + PINS_FIELD_BASE(200, 200, 1, GPIO_PUPD, 32, 0, 10, 1), /* MSDC2_DAT0 */ + PINS_FIELD_BASE(201, 201, 1, GPIO_PUPD, 32, 0, 14, 1), /* MSDC2_DAT1 */ + PINS_FIELD_BASE(202, 202, 1, GPIO_PUPD, 32, 0, 18, 1), /* MSDC2_DAT2 */ + PINS_FIELD_BASE(203, 203, 1, GPIO_PUPD, 32, 0, 22, 1) /* MSDC2_DAT3 */ +}; + +static const struct mtk_pin_field_calc mt6735_pin_pullen_range[] = { + PIN_FIELD_BASE(0, 4, 2, GPIO_PULLEN, 32, 0, 23, 1), + PIN_FIELD_BASE(5, 8, 3, GPIO_PULLEN, 32, 0x10, 9, 1), + PIN_FIELD_BASE(9, 12, 3, GPIO_PULLEN, 32, 0x10, 20, 1), + PIN_FIELD_BASE(13, 21, 1, GPIO_PULLEN, 32, 0, 0, 1), + PIN_FIELD_BASE(42, 44, 2, GPIO_PULLEN, 32, 0, 0, 1), + PIN_FIELD_BASE(47, 64, 2, GPIO_PULLEN, 32, 0, 5, 1), + PIN_FIELD_BASE(65, 73, 3, GPIO_PULLEN, 32, 0x10, 0, 1), + PIN_FIELD_BASE(74, 80, 3, GPIO_PULLEN, 32, 0x10, 13, 1), + PIN_FIELD_BASE(87, 114, 3, GPIO_PULLEN, 32, 0x10, 30, 1), + PIN_FIELD_BASE(118, 149, 4, GPIO_PULLEN, 32, 0, 0, 1), + PIN_FIELD_BASE(184, 189, 6, GPIO_PULLEN, 32, 0x10, 12, 1) +}; + +static const struct mtk_pin_field_calc mt6735_pin_pullsel_range[] = { + PIN_FIELD_BASE(0, 4, 2, GPIO_PULLSEL, 32, 0, 23, 1), + PIN_FIELD_BASE(5, 8, 3, GPIO_PULLSEL, 32, 0x10, 9, 1), + PIN_FIELD_BASE(9, 12, 3, GPIO_PULLSEL, 32, 0x10, 20, 1), + PIN_FIELD_BASE(13, 21, 1, GPIO_PULLSEL, 32, 0, 0, 1), + PIN_FIELD_BASE(42, 44, 2, GPIO_PULLSEL, 32, 0, 0, 1), + PIN_FIELD_BASE(47, 64, 2, GPIO_PULLSEL, 32, 0, 5, 1), + PIN_FIELD_BASE(65, 73, 3, GPIO_PULLSEL, 32, 0x10, 0, 1), + PIN_FIELD_BASE(74, 80, 3, GPIO_PULLSEL, 32, 0x10, 13, 1), + PIN_FIELD_BASE(87, 114, 3, GPIO_PULLSEL, 32, 0x10, 30, 1), + PIN_FIELD_BASE(118, 149, 4, GPIO_PULLSEL, 32, 0, 0, 1), + PIN_FIELD_BASE(184, 189, 6, GPIO_PULLSEL, 32, 0x10, 12, 1) +}; + +static const struct mtk_pin_reg_calc mt6735_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6735_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6735_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6735_pin_do_range), + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6735_pin_mode_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6735_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6735_pin_ies_range), + [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt6735_pin_tdsel_range), + [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt6735_pin_rdsel_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6735_pin_drv_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6735_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6735_pin_r1_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6735_pin_pupd_range), + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt6735_pin_pullen_range), + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt6735_pin_pullsel_range), +}; + +static const struct mtk_pin_field_calc mt6735m_pin_dir_range[] = { + PIN_FIELD(0, 197, GPIO_DIR, 0x10, 0, 1) +}; + +static const struct mtk_pin_field_calc mt6735m_pin_di_range[] = { + PIN_FIELD(0, 197, GPIO_DIN, 0x10, 0, 1) +}; + +static const struct mtk_pin_field_calc mt6735m_pin_do_range[] = { + PIN_FIELD(0, 197, GPIO_DOUT, 0x10, 0, 1) +}; + +static const struct mtk_pin_field_calc mt6735m_pin_mode_range[] = { + PIN_FIELD(0, 4, GPIO_MODE1, 0, 0, 3), + PIN_FIELD(5, 9, GPIO_MODE1, 0, 16, 3), + PIN_FIELD(10, 14, GPIO_MODE2, 0, 0, 3), + PIN_FIELD(15, 19, GPIO_MODE2, 0, 16, 3), + PIN_FIELD(20, 24, GPIO_MODE3, 0, 0, 3), + PIN_FIELD(25, 29, GPIO_MODE3, 0, 16, 3), + PIN_FIELD(30, 34, GPIO_MODE4, 0, 0, 3), + PIN_FIELD(35, 39, GPIO_MODE4, 0, 16, 3), + PIN_FIELD(40, 44, GPIO_MODE5, 0, 0, 3), + PIN_FIELD(45, 49, GPIO_MODE5, 0, 16, 3), + PIN_FIELD(50, 54, GPIO_MODE6, 0, 0, 3), + PIN_FIELD(55, 59, GPIO_MODE6, 0, 16, 3), + PIN_FIELD(60, 64, GPIO_MODE7, 0, 0, 3), + PIN_FIELD(65, 69, GPIO_MODE7, 0, 16, 3), + PIN_FIELD(70, 74, GPIO_MODE8, 0, 0, 3), + PIN_FIELD(75, 79, GPIO_MODE8, 0, 16, 3), + PIN_FIELD(80, 84, GPIO_MODE9, 0, 0, 3), + PIN_FIELD(85, 89, GPIO_MODE9, 0, 16, 3), + PIN_FIELD(90, 94, GPIO_MODE10, 0, 0, 3), + PIN_FIELD(95, 99, GPIO_MODE10, 0, 16, 3), + PIN_FIELD(100, 104, GPIO_MODE11, 0, 0, 3), + PIN_FIELD(105, 109, GPIO_MODE11, 0, 16, 3), + PIN_FIELD(110, 114, GPIO_MODE12, 0, 0, 3), + PIN_FIELD(115, 119, GPIO_MODE12, 0, 16, 3), + PIN_FIELD(120, 124, GPIO_MODE13, 0, 0, 3), + PIN_FIELD(125, 129, GPIO_MODE13, 0, 16, 3), + PIN_FIELD(130, 134, GPIO_MODE14, 0, 0, 3), + PIN_FIELD(135, 139, GPIO_MODE14, 0, 16, 3), + PIN_FIELD(140, 144, GPIO_MODE15, 0, 0, 3), + PIN_FIELD(145, 149, GPIO_MODE15, 0, 16, 3), + PIN_FIELD(150, 154, GPIO_MODE16, 0, 0, 3), + PIN_FIELD(155, 159, GPIO_MODE16, 0, 16, 3), + PIN_FIELD(160, 164, GPIO_MODE17, 0, 0, 3), + PIN_FIELD(165, 169, GPIO_MODE17, 0, 16, 3), + PIN_FIELD(170, 174, GPIO_MODE18, 0, 0, 3), + PIN_FIELD(175, 179, GPIO_MODE18, 0, 16, 3), + PIN_FIELD(180, 184, GPIO_MODE19, 0, 0, 3), + PIN_FIELD(185, 189, GPIO_MODE19, 0, 16, 3), + PIN_FIELD(190, 194, GPIO_MODE20, 0, 0, 3), + PIN_FIELD(195, 197, GPIO_MODE20, 0, 16, 3), +}; + +/* + * Rather than redefining all tables for MT6735M just to remove the 6 MSDC2 + * pins at the end, reuse the MT6735 tables and exclude the MSDC2 pin fields + * by subtracting their count from the array size when possible + */ +static const struct mtk_pin_reg_calc mt6735m_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6735m_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6735m_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6735m_pin_do_range), + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6735m_pin_mode_range), + [PINCTRL_PIN_REG_SMT] = { mt6735_pin_smt_range, + ARRAY_SIZE(mt6735_pin_smt_range) - 3 }, + [PINCTRL_PIN_REG_IES] = { mt6735_pin_ies_range, + ARRAY_SIZE(mt6735_pin_ies_range) - 3 }, + [PINCTRL_PIN_REG_TDSEL] = { mt6735_pin_tdsel_range, + ARRAY_SIZE(mt6735_pin_tdsel_range) - 3 }, + [PINCTRL_PIN_REG_RDSEL] = { mt6735_pin_rdsel_range, + ARRAY_SIZE(mt6735_pin_rdsel_range) - 3 }, + [PINCTRL_PIN_REG_DRV] = { mt6735_pin_drv_range, + ARRAY_SIZE(mt6735_pin_drv_range) - 3 }, + [PINCTRL_PIN_REG_R0] = { mt6735_pin_r0_range, + ARRAY_SIZE(mt6735_pin_r0_range) - 6 }, + [PINCTRL_PIN_REG_R1] = { mt6735_pin_r1_range, + ARRAY_SIZE(mt6735_pin_r1_range) - 6 }, + [PINCTRL_PIN_REG_PUPD] = { mt6735_pin_pupd_range, + ARRAY_SIZE(mt6735_pin_pupd_range) - 6 }, + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt6735_pin_pullen_range), + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt6735_pin_pullsel_range), +}; + +static const unsigned int mt6735_pull_type[] = { + MTK_PULL_PULLSEL_TYPE, /* 0 */ + MTK_PULL_PULLSEL_TYPE, /* 1 */ + MTK_PULL_PULLSEL_TYPE, /* 2 */ + MTK_PULL_PULLSEL_TYPE, /* 3 */ + MTK_PULL_PULLSEL_TYPE, /* 4 */ + MTK_PULL_PULLSEL_TYPE, /* 5 */ + MTK_PULL_PULLSEL_TYPE, /* 6 */ + MTK_PULL_PULLSEL_TYPE, /* 7 */ + MTK_PULL_PULLSEL_TYPE, /* 8 */ + MTK_PULL_PULLSEL_TYPE, /* 9 */ + MTK_PULL_PULLSEL_TYPE, /* 10 */ + MTK_PULL_PULLSEL_TYPE, /* 11 */ + MTK_PULL_PULLSEL_TYPE, /* 12 */ + MTK_PULL_PULLSEL_TYPE, /* 13 */ + MTK_PULL_PULLSEL_TYPE, /* 14 */ + MTK_PULL_PULLSEL_TYPE, /* 15 */ + MTK_PULL_PULLSEL_TYPE, /* 16 */ + MTK_PULL_PULLSEL_TYPE, /* 17 */ + MTK_PULL_PULLSEL_TYPE, /* 18 */ + MTK_PULL_PULLSEL_TYPE, /* 19 */ + MTK_PULL_PULLSEL_TYPE, /* 20 */ + MTK_PULL_PULLSEL_TYPE, /* 21 */ + /* MIPI CSI pins have no configurable pull resistors */ + 0, /* 22 RDN0 */ + 0, /* 23 RDP0 */ + 0, /* 24 RDN1 */ + 0, /* 25 RDP1 */ + 0, /* 26 RCN */ + 0, /* 27 RCP */ + 0, /* 28 RDN2 */ + 0, /* 29 RDP2 */ + 0, /* 30 RDN3 */ + 0, /* 31 RDP3 */ + 0, /* 32 RDN0_A */ + 0, /* 33 RDP0_A */ + 0, /* 34 RDN1_A */ + 0, /* 35 RDP1_A */ + 0, /* 36 RCN_A */ + 0, /* 37 RCP_A */ + 0, /* 38 RDN2_A */ + 0, /* 39 RDP2_A */ + 0, /* 40 RDN3_A */ + 0, /* 41 RDP3_A */ + MTK_PULL_PULLSEL_TYPE, /* 42 */ + MTK_PULL_PULLSEL_TYPE, /* 43 */ + MTK_PULL_PULLSEL_TYPE, /* 44 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 45 CMMCLK0 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 46 CMMCLK1 */ + MTK_PULL_PULLSEL_TYPE, /* 47 */ + MTK_PULL_PULLSEL_TYPE, /* 48 */ + MTK_PULL_PULLSEL_TYPE, /* 49 */ + MTK_PULL_PULLSEL_TYPE, /* 50 */ + MTK_PULL_PULLSEL_TYPE, /* 51 */ + MTK_PULL_PULLSEL_TYPE, /* 52 */ + MTK_PULL_PULLSEL_TYPE, /* 53 */ + MTK_PULL_PULLSEL_TYPE, /* 54 */ + MTK_PULL_PULLSEL_TYPE, /* 55 */ + MTK_PULL_PULLSEL_TYPE, /* 56 */ + MTK_PULL_PULLSEL_TYPE, /* 57 */ + MTK_PULL_PULLSEL_TYPE, /* 58 */ + MTK_PULL_PULLSEL_TYPE, /* 59 */ + MTK_PULL_PULLSEL_TYPE, /* 60 */ + MTK_PULL_PULLSEL_TYPE, /* 61 */ + MTK_PULL_PULLSEL_TYPE, /* 62 */ + MTK_PULL_PULLSEL_TYPE, /* 63 */ + MTK_PULL_PULLSEL_TYPE, /* 64 */ + MTK_PULL_PULLSEL_TYPE, /* 65 */ + MTK_PULL_PULLSEL_TYPE, /* 66 */ + MTK_PULL_PULLSEL_TYPE, /* 67 */ + MTK_PULL_PULLSEL_TYPE, /* 68 */ + MTK_PULL_PULLSEL_TYPE, /* 69 */ + MTK_PULL_PULLSEL_TYPE, /* 70 */ + MTK_PULL_PULLSEL_TYPE, /* 71 */ + MTK_PULL_PULLSEL_TYPE, /* 72 */ + MTK_PULL_PULLSEL_TYPE, /* 73 */ + MTK_PULL_PULLSEL_TYPE, /* 74 */ + MTK_PULL_PULLSEL_TYPE, /* 75 */ + MTK_PULL_PULLSEL_TYPE, /* 76 */ + MTK_PULL_PULLSEL_TYPE, /* 77 */ + MTK_PULL_PULLSEL_TYPE, /* 78 */ + MTK_PULL_PULLSEL_TYPE, /* 79 */ + MTK_PULL_PULLSEL_TYPE, /* 80 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 81 KROW0 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 82 KROW1 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 83 KROW2 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 84 KCOL0 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 85 KCOL1 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 86 KCOL2 */ + MTK_PULL_PULLSEL_TYPE, /* 87 */ + MTK_PULL_PULLSEL_TYPE, /* 88 */ + MTK_PULL_PULLSEL_TYPE, /* 89 */ + MTK_PULL_PULLSEL_TYPE, /* 90 */ + MTK_PULL_PULLSEL_TYPE, /* 91 */ + MTK_PULL_PULLSEL_TYPE, /* 92 */ + MTK_PULL_PULLSEL_TYPE, /* 93 */ + MTK_PULL_PULLSEL_TYPE, /* 94 */ + MTK_PULL_PULLSEL_TYPE, /* 95 */ + MTK_PULL_PULLSEL_TYPE, /* 96 */ + MTK_PULL_PULLSEL_TYPE, /* 97 */ + MTK_PULL_PULLSEL_TYPE, /* 98 */ + MTK_PULL_PULLSEL_TYPE, /* 99 */ + MTK_PULL_PULLSEL_TYPE, /* 100 */ + MTK_PULL_PULLSEL_TYPE, /* 101 */ + MTK_PULL_PULLSEL_TYPE, /* 102 */ + MTK_PULL_PULLSEL_TYPE, /* 103 */ + MTK_PULL_PULLSEL_TYPE, /* 104 */ + MTK_PULL_PULLSEL_TYPE, /* 105 */ + MTK_PULL_PULLSEL_TYPE, /* 106 */ + MTK_PULL_PULLSEL_TYPE, /* 107 */ + MTK_PULL_PULLSEL_TYPE, /* 108 */ + MTK_PULL_PULLSEL_TYPE, /* 109 */ + MTK_PULL_PULLSEL_TYPE, /* 110 */ + MTK_PULL_PULLSEL_TYPE, /* 111 */ + MTK_PULL_PULLSEL_TYPE, /* 112 */ + MTK_PULL_PULLSEL_TYPE, /* 113 */ + MTK_PULL_PULLSEL_TYPE, /* 114 */ + /* Configuration for AUXADC pins is set by APMIXEDSYS */ + 0, /* 115 AUXIN0 */ + 0, /* 116 AUXIN1 */ + 0, /* 117 AUXIN2 */ + MTK_PULL_PULLSEL_TYPE, /* 118 */ + MTK_PULL_PULLSEL_TYPE, /* 119 */ + MTK_PULL_PULLSEL_TYPE, /* 120 */ + MTK_PULL_PULLSEL_TYPE, /* 121 */ + MTK_PULL_PULLSEL_TYPE, /* 122 */ + MTK_PULL_PULLSEL_TYPE, /* 123 */ + MTK_PULL_PULLSEL_TYPE, /* 124 */ + MTK_PULL_PULLSEL_TYPE, /* 125 */ + MTK_PULL_PULLSEL_TYPE, /* 126 */ + MTK_PULL_PULLSEL_TYPE, /* 127 */ + MTK_PULL_PULLSEL_TYPE, /* 128 */ + MTK_PULL_PULLSEL_TYPE, /* 129 */ + MTK_PULL_PULLSEL_TYPE, /* 130 */ + MTK_PULL_PULLSEL_TYPE, /* 131 */ + MTK_PULL_PULLSEL_TYPE, /* 132 */ + MTK_PULL_PULLSEL_TYPE, /* 133 */ + MTK_PULL_PULLSEL_TYPE, /* 134 */ + MTK_PULL_PULLSEL_TYPE, /* 135 */ + MTK_PULL_PULLSEL_TYPE, /* 136 */ + MTK_PULL_PULLSEL_TYPE, /* 137 */ + MTK_PULL_PULLSEL_TYPE, /* 138 */ + MTK_PULL_PULLSEL_TYPE, /* 139 */ + MTK_PULL_PULLSEL_TYPE, /* 140 */ + MTK_PULL_PULLSEL_TYPE, /* 141 */ + MTK_PULL_PULLSEL_TYPE, /* 142 */ + MTK_PULL_PULLSEL_TYPE, /* 143 */ + MTK_PULL_PULLSEL_TYPE, /* 144 */ + MTK_PULL_PULLSEL_TYPE, /* 145 */ + MTK_PULL_PULLSEL_TYPE, /* 146 */ + MTK_PULL_PULLSEL_TYPE, /* 147 */ + MTK_PULL_PULLSEL_TYPE, /* 148 */ + MTK_PULL_PULLSEL_TYPE, /* 149 */ + /* MIPI DSI pins have no configurable pull resistors */ + 0, /* 150 TDP0 */ + 0, /* 151 TDN0 */ + 0, /* 152 TDP1 */ + 0, /* 153 TDN1 */ + 0, /* 154 TCP */ + 0, /* 155 TCN */ + 0, /* 156 TDP2 */ + 0, /* 157 TDN2 */ + 0, /* 158 TDP3 */ + 0, /* 159 TDN3 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 160 MD_SIM2_SCLK */ + MTK_PULL_PUPD_R1R0_TYPE, /* 161 MD_SIM2_SRST */ + MTK_PULL_PUPD_R1R0_TYPE, /* 162 MD_SIM2_SDAT */ + MTK_PULL_PUPD_R1R0_TYPE, /* 163 MD_SIM1_SCLK */ + MTK_PULL_PUPD_R1R0_TYPE, /* 164 MD_SIM1_SRST */ + MTK_PULL_PUPD_R1R0_TYPE, /* 165 MD_SIM1_SDAT */ + MTK_PULL_PUPD_R1R0_TYPE, /* 166 MSDC1_CMD */ + MTK_PULL_PUPD_R1R0_TYPE, /* 167 MSDC1_CLK */ + MTK_PULL_PUPD_R1R0_TYPE, /* 168 MSDC1_DAT0 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 169 MSDC1_DAT1 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 170 MSDC1_DAT2 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 171 MSDC1_DAT3 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 172 MSDC0_CMD */ + MTK_PULL_PUPD_R1R0_TYPE, /* 173 MSDC0_DSL */ + MTK_PULL_PUPD_R1R0_TYPE, /* 174 MSDC0_CLK */ + MTK_PULL_PUPD_R1R0_TYPE, /* 175 MSDC0_DAT0 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 176 MSDC0_DAT1 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 177 MSDC0_DAT2 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 178 MSDC0_DAT3 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 179 MSDC0_DAT4 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 180 MSDC0_DAT5 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 181 MSDC0_DAT6 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 182 MSDC0_DAT7 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 183 MSDC0_RSTB */ + MTK_PULL_PULLSEL_TYPE, /* 184 */ + MTK_PULL_PULLSEL_TYPE, /* 185 */ + MTK_PULL_PULLSEL_TYPE, /* 186 */ + MTK_PULL_PULLSEL_TYPE, /* 187 */ + MTK_PULL_PULLSEL_TYPE, /* 188 */ + MTK_PULL_PULLSEL_TYPE, /* 189 */ + /* + * GPS/WIFI/BT pins have no pull resistors configurable by the GPIO + * controller. They might be configured by CONSYS but we can't know + * for sure due to lack of documentation. + */ + 0, /* 190 GPS_RXQN */ + 0, /* 191 GPS_RXQP */ + 0, /* 192 GPS_RXIN */ + 0, /* 193 GPS_RXIP */ + 0, /* 194 WB_RXQN */ + 0, /* 195 WB_RXQP */ + 0, /* 196 WB_RXIN */ + 0, /* 197 WB_RXIP */ + MTK_PULL_PUPD_R1R0_TYPE, /* 198 MSDC2_CMD */ + MTK_PULL_PUPD_R1R0_TYPE, /* 199 MSDC2_CLK */ + MTK_PULL_PUPD_R1R0_TYPE, /* 200 MSDC2_DAT0 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 201 MSDC2_DAT1 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 202 MSDC2_DAT2 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 203 MSDC2_DAT3 */ + /* No pull resistors for virtual EINT pins */ + 0, /* 204 */ + 0, /* 205 */ + 0, /* 206 */ + 0, /* 207 */ + 0, /* 208 */ + 0, /* 209 */ + 0, /* 210 */ + 0, /* 211 */ + 0, /* 212 */ + 0 /* 213 */ +}; + +static const unsigned int mt6735m_pull_type[] = { + MTK_PULL_PULLSEL_TYPE, /* 0 */ + MTK_PULL_PULLSEL_TYPE, /* 1 */ + MTK_PULL_PULLSEL_TYPE, /* 2 */ + MTK_PULL_PULLSEL_TYPE, /* 3 */ + MTK_PULL_PULLSEL_TYPE, /* 4 */ + MTK_PULL_PULLSEL_TYPE, /* 5 */ + MTK_PULL_PULLSEL_TYPE, /* 6 */ + MTK_PULL_PULLSEL_TYPE, /* 7 */ + MTK_PULL_PULLSEL_TYPE, /* 8 */ + MTK_PULL_PULLSEL_TYPE, /* 9 */ + MTK_PULL_PULLSEL_TYPE, /* 10 */ + MTK_PULL_PULLSEL_TYPE, /* 11 */ + MTK_PULL_PULLSEL_TYPE, /* 12 */ + MTK_PULL_PULLSEL_TYPE, /* 13 */ + MTK_PULL_PULLSEL_TYPE, /* 14 */ + MTK_PULL_PULLSEL_TYPE, /* 15 */ + MTK_PULL_PULLSEL_TYPE, /* 16 */ + MTK_PULL_PULLSEL_TYPE, /* 17 */ + MTK_PULL_PULLSEL_TYPE, /* 18 */ + MTK_PULL_PULLSEL_TYPE, /* 19 */ + MTK_PULL_PULLSEL_TYPE, /* 20 */ + MTK_PULL_PULLSEL_TYPE, /* 21 */ + /* MIPI CSI pins have no configurable pull resistors */ + 0, /* 22 RDN0 */ + 0, /* 23 RDP0 */ + 0, /* 24 RDN1 */ + 0, /* 25 RDP1 */ + 0, /* 26 RCN */ + 0, /* 27 RCP */ + 0, /* 28 RDN2 */ + 0, /* 29 RDP2 */ + 0, /* 30 RDN3 */ + 0, /* 31 RDP3 */ + 0, /* 32 RDN0_A */ + 0, /* 33 RDP0_A */ + 0, /* 34 RDN1_A */ + 0, /* 35 RDP1_A */ + 0, /* 36 RCN_A */ + 0, /* 37 RCP_A */ + 0, /* 38 RDN2_A */ + 0, /* 39 RDP2_A */ + 0, /* 40 RDN3_A */ + 0, /* 41 RDP3_A */ + MTK_PULL_PULLSEL_TYPE, /* 42 */ + MTK_PULL_PULLSEL_TYPE, /* 43 */ + MTK_PULL_PULLSEL_TYPE, /* 44 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 45 CMMCLK0 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 46 CMMCLK1 */ + MTK_PULL_PULLSEL_TYPE, /* 47 */ + MTK_PULL_PULLSEL_TYPE, /* 48 */ + MTK_PULL_PULLSEL_TYPE, /* 49 */ + MTK_PULL_PULLSEL_TYPE, /* 50 */ + MTK_PULL_PULLSEL_TYPE, /* 51 */ + MTK_PULL_PULLSEL_TYPE, /* 52 */ + MTK_PULL_PULLSEL_TYPE, /* 53 */ + MTK_PULL_PULLSEL_TYPE, /* 54 */ + MTK_PULL_PULLSEL_TYPE, /* 55 */ + MTK_PULL_PULLSEL_TYPE, /* 56 */ + MTK_PULL_PULLSEL_TYPE, /* 57 */ + MTK_PULL_PULLSEL_TYPE, /* 58 */ + MTK_PULL_PULLSEL_TYPE, /* 59 */ + MTK_PULL_PULLSEL_TYPE, /* 60 */ + MTK_PULL_PULLSEL_TYPE, /* 61 */ + MTK_PULL_PULLSEL_TYPE, /* 62 */ + MTK_PULL_PULLSEL_TYPE, /* 63 */ + MTK_PULL_PULLSEL_TYPE, /* 64 */ + MTK_PULL_PULLSEL_TYPE, /* 65 */ + MTK_PULL_PULLSEL_TYPE, /* 66 */ + MTK_PULL_PULLSEL_TYPE, /* 67 */ + MTK_PULL_PULLSEL_TYPE, /* 68 */ + MTK_PULL_PULLSEL_TYPE, /* 69 */ + MTK_PULL_PULLSEL_TYPE, /* 70 */ + MTK_PULL_PULLSEL_TYPE, /* 71 */ + MTK_PULL_PULLSEL_TYPE, /* 72 */ + MTK_PULL_PULLSEL_TYPE, /* 73 */ + MTK_PULL_PULLSEL_TYPE, /* 74 */ + MTK_PULL_PULLSEL_TYPE, /* 75 */ + MTK_PULL_PULLSEL_TYPE, /* 76 */ + MTK_PULL_PULLSEL_TYPE, /* 77 */ + MTK_PULL_PULLSEL_TYPE, /* 78 */ + MTK_PULL_PULLSEL_TYPE, /* 79 */ + MTK_PULL_PULLSEL_TYPE, /* 80 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 81 KROW0 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 82 KROW1 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 83 KROW2 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 84 KCOL0 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 85 KCOL1 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 86 KCOL2 */ + MTK_PULL_PULLSEL_TYPE, /* 87 */ + MTK_PULL_PULLSEL_TYPE, /* 88 */ + MTK_PULL_PULLSEL_TYPE, /* 89 */ + MTK_PULL_PULLSEL_TYPE, /* 90 */ + MTK_PULL_PULLSEL_TYPE, /* 91 */ + MTK_PULL_PULLSEL_TYPE, /* 92 */ + MTK_PULL_PULLSEL_TYPE, /* 93 */ + MTK_PULL_PULLSEL_TYPE, /* 94 */ + MTK_PULL_PULLSEL_TYPE, /* 95 */ + MTK_PULL_PULLSEL_TYPE, /* 96 */ + MTK_PULL_PULLSEL_TYPE, /* 97 */ + MTK_PULL_PULLSEL_TYPE, /* 98 */ + MTK_PULL_PULLSEL_TYPE, /* 99 */ + MTK_PULL_PULLSEL_TYPE, /* 100 */ + MTK_PULL_PULLSEL_TYPE, /* 101 */ + MTK_PULL_PULLSEL_TYPE, /* 102 */ + MTK_PULL_PULLSEL_TYPE, /* 103 */ + MTK_PULL_PULLSEL_TYPE, /* 104 */ + MTK_PULL_PULLSEL_TYPE, /* 105 */ + MTK_PULL_PULLSEL_TYPE, /* 106 */ + MTK_PULL_PULLSEL_TYPE, /* 107 */ + MTK_PULL_PULLSEL_TYPE, /* 108 */ + MTK_PULL_PULLSEL_TYPE, /* 109 */ + MTK_PULL_PULLSEL_TYPE, /* 110 */ + MTK_PULL_PULLSEL_TYPE, /* 111 */ + MTK_PULL_PULLSEL_TYPE, /* 112 */ + MTK_PULL_PULLSEL_TYPE, /* 113 */ + MTK_PULL_PULLSEL_TYPE, /* 114 */ + /* Configuration for AUXADC pins is set by APMIXEDSYS */ + 0, /* 115 AUXIN0 */ + 0, /* 116 AUXIN1 */ + 0, /* 117 AUXIN2 */ + MTK_PULL_PULLSEL_TYPE, /* 118 */ + MTK_PULL_PULLSEL_TYPE, /* 119 */ + MTK_PULL_PULLSEL_TYPE, /* 120 */ + MTK_PULL_PULLSEL_TYPE, /* 121 */ + MTK_PULL_PULLSEL_TYPE, /* 122 */ + MTK_PULL_PULLSEL_TYPE, /* 123 */ + MTK_PULL_PULLSEL_TYPE, /* 124 */ + MTK_PULL_PULLSEL_TYPE, /* 125 */ + MTK_PULL_PULLSEL_TYPE, /* 126 */ + MTK_PULL_PULLSEL_TYPE, /* 127 */ + MTK_PULL_PULLSEL_TYPE, /* 128 */ + MTK_PULL_PULLSEL_TYPE, /* 129 */ + MTK_PULL_PULLSEL_TYPE, /* 130 */ + MTK_PULL_PULLSEL_TYPE, /* 131 */ + MTK_PULL_PULLSEL_TYPE, /* 132 */ + MTK_PULL_PULLSEL_TYPE, /* 133 */ + MTK_PULL_PULLSEL_TYPE, /* 134 */ + MTK_PULL_PULLSEL_TYPE, /* 135 */ + MTK_PULL_PULLSEL_TYPE, /* 136 */ + MTK_PULL_PULLSEL_TYPE, /* 137 */ + MTK_PULL_PULLSEL_TYPE, /* 138 */ + MTK_PULL_PULLSEL_TYPE, /* 139 */ + MTK_PULL_PULLSEL_TYPE, /* 140 */ + MTK_PULL_PULLSEL_TYPE, /* 141 */ + MTK_PULL_PULLSEL_TYPE, /* 142 */ + MTK_PULL_PULLSEL_TYPE, /* 143 */ + MTK_PULL_PULLSEL_TYPE, /* 144 */ + MTK_PULL_PULLSEL_TYPE, /* 145 */ + MTK_PULL_PULLSEL_TYPE, /* 146 */ + MTK_PULL_PULLSEL_TYPE, /* 147 */ + MTK_PULL_PULLSEL_TYPE, /* 148 */ + MTK_PULL_PULLSEL_TYPE, /* 149 */ + /* MIPI DSI pins have no configurable pull resistors */ + 0, /* 150 TDP0 */ + 0, /* 151 TDN0 */ + 0, /* 152 TDP1 */ + 0, /* 153 TDN1 */ + 0, /* 154 TCP */ + 0, /* 155 TCN */ + 0, /* 156 TDP2 */ + 0, /* 157 TDN2 */ + 0, /* 158 TDP3 */ + 0, /* 159 TDN3 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 160 MD_SIM2_SCLK */ + MTK_PULL_PUPD_R1R0_TYPE, /* 161 MD_SIM2_SRST */ + MTK_PULL_PUPD_R1R0_TYPE, /* 162 MD_SIM2_SDAT */ + MTK_PULL_PUPD_R1R0_TYPE, /* 163 MD_SIM1_SCLK */ + MTK_PULL_PUPD_R1R0_TYPE, /* 164 MD_SIM1_SRST */ + MTK_PULL_PUPD_R1R0_TYPE, /* 165 MD_SIM1_SDAT */ + MTK_PULL_PUPD_R1R0_TYPE, /* 166 MSDC1_CMD */ + MTK_PULL_PUPD_R1R0_TYPE, /* 167 MSDC1_CLK */ + MTK_PULL_PUPD_R1R0_TYPE, /* 168 MSDC1_DAT0 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 169 MSDC1_DAT1 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 170 MSDC1_DAT2 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 171 MSDC1_DAT3 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 172 MSDC0_CMD */ + MTK_PULL_PUPD_R1R0_TYPE, /* 173 MSDC0_DSL */ + MTK_PULL_PUPD_R1R0_TYPE, /* 174 MSDC0_CLK */ + MTK_PULL_PUPD_R1R0_TYPE, /* 175 MSDC0_DAT0 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 176 MSDC0_DAT1 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 177 MSDC0_DAT2 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 178 MSDC0_DAT3 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 179 MSDC0_DAT4 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 180 MSDC0_DAT5 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 181 MSDC0_DAT6 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 182 MSDC0_DAT7 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 183 MSDC0_RSTB */ + MTK_PULL_PULLSEL_TYPE, /* 184 */ + MTK_PULL_PULLSEL_TYPE, /* 185 */ + MTK_PULL_PULLSEL_TYPE, /* 186 */ + MTK_PULL_PULLSEL_TYPE, /* 187 */ + MTK_PULL_PULLSEL_TYPE, /* 188 */ + MTK_PULL_PULLSEL_TYPE, /* 189 */ + /* + * GPS/WIFI/BT pins have no pull resistors configurable by the GPIO + * controller. They might be configured by CONSYS but we can't know + * for sure due to lack of documentation. + */ + 0, /* 190 GPS_RXQN */ + 0, /* 191 GPS_RXQP */ + 0, /* 192 GPS_RXIN */ + 0, /* 193 GPS_RXIP */ + 0, /* 194 WB_RXQN */ + 0, /* 195 WB_RXQP */ + 0, /* 196 WB_RXIN */ + 0, /* 197 WB_RXIP */ + /* No pull resistors for virtual EINT pins */ + 0, /* 198 */ + 0, /* 199 */ + 0, /* 200 */ + 0, /* 201 */ + 0, /* 202 */ + 0, /* 203 */ + 0, /* 204 */ + 0, /* 205 */ + 0, /* 206 */ + 0, /* 207 */ + 0, /* 208 */ + 0, /* 209 */ + 0, /* 210 */ + 0, /* 211 */ + 0, /* 212 */ + 0 /* 213 */ +}; + +static const char * const mt6735_pinctrl_register_base_names[] = { + "gpio", "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", "iocfg5" +}; + +static const struct mtk_eint_hw mt6735_eint_hw = { + .port_mask = 7, + .ports = 6, + .ap_num = 224, + .db_cnt = 16, + .db_time = debounce_time_mt6765, +}; + +static const struct mtk_pin_soc mt6735_data = { + .reg_cal = mt6735_reg_cals, + .pins = mtk_pins_mt6735, + .npins = ARRAY_SIZE(mtk_pins_mt6735), + .ngrps = ARRAY_SIZE(mtk_pins_mt6735), + .eint_hw = &mt6735_eint_hw, + .gpio_m = 0, + .ies_present = true, + .base_names = mt6735_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt6735_pinctrl_register_base_names), + .pull_type = mt6735_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, +}; + +static const struct mtk_pin_soc mt6735m_data = { + .reg_cal = mt6735m_reg_cals, + .pins = mtk_pins_mt6735m, + .npins = ARRAY_SIZE(mtk_pins_mt6735m), + .ngrps = ARRAY_SIZE(mtk_pins_mt6735m), + .eint_hw = &mt6735_eint_hw, + .gpio_m = 0, + .ies_present = true, + .base_names = mt6735_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt6735_pinctrl_register_base_names), + .pull_type = mt6735m_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, +}; + +static const struct of_device_id mt6735_pinctrl_match[] = { + { .compatible = "mediatek,mt6735-pinctrl", .data = &mt6735_data }, + { .compatible = "mediatek,mt6735m-pinctrl", .data = &mt6735m_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mt6735_pinctrl_match); + +static struct platform_driver mt6735_pinctrl_driver = { + .probe = mtk_paris_pinctrl_probe, + .driver = { + .name = "mt6735-pinctrl", + .of_match_table = mt6735_pinctrl_match, + .pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops), + }, +}; +module_platform_driver(mt6735_pinctrl_driver); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("MediaTek MT6735 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h new file mode 100644 index 000000000000..883648a41308 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h @@ -0,0 +1,3993 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#ifndef __PINCTRL_MTK_MT6735_H +#define __PINCTRL_MTK_MT6735_H + +#include "pinctrl-paris.h" + +static const struct mtk_pin_desc mtk_pins_mt6735[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "IDDIG"), + MTK_FUNCTION(2, "DPI_D4"), + MTK_FUNCTION(3, "CLKM4"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "PWM3"), + MTK_FUNCTION(6, "KCOL2"), + MTK_FUNCTION(7, "C2K_ARM_EINT0") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "PWM2"), + MTK_FUNCTION(2, "DPI_D5"), + MTK_FUNCTION(3, "MD_EINT0"), + MTK_FUNCTION(4, "TDD_TDO"), + MTK_FUNCTION(5, "CONN_MCU_TDO"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(7, "C2K_ARM_EINT1") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "CLKM0"), + MTK_FUNCTION(2, "DPI_D6"), + MTK_FUNCTION(3, "MD_EINT0"), + MTK_FUNCTION(4, "USB_DRVVBUS"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(7, "C2K_ARM_EINT2") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "CLKM1"), + MTK_FUNCTION(2, "DPI_D7"), + MTK_FUNCTION(3, "SPI_MIB"), + MTK_FUNCTION(4, "MD_EINT0"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"), + MTK_FUNCTION(7, "C2K_ARM_EINT3") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "CLKM2"), + MTK_FUNCTION(2, "DPI_D8"), + MTK_FUNCTION(3, "SPI_MOB"), + MTK_FUNCTION(4, "TDD_TCK"), + MTK_FUNCTION(5, "CONN_MCU_TCK_0"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"), + MTK_FUNCTION(7, "C2K_DM_EINT0") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "UCTS2"), + MTK_FUNCTION(2, "DPI_D9"), + MTK_FUNCTION(3, "SPI_CSB"), + MTK_FUNCTION(4, "TDD_TDI"), + MTK_FUNCTION(5, "CONN_MCU_TDI"), + MTK_FUNCTION(6, "I2S1_DO"), + MTK_FUNCTION(7, "MD_URXD") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "URTS2"), + MTK_FUNCTION(2, "DPI_D10"), + MTK_FUNCTION(3, "SPI_CKB"), + MTK_FUNCTION(4, "TDD_TRSTN"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B"), + MTK_FUNCTION(6, "I2S1_LRCK"), + MTK_FUNCTION(7, "MD_UTXD") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "UCTS3"), + MTK_FUNCTION(2, "DPI_D11"), + MTK_FUNCTION(3, "SDA1"), + MTK_FUNCTION(4, "TDD_TMS"), + MTK_FUNCTION(5, "CONN_MCU_TMS"), + MTK_FUNCTION(6, "I2S1_BCK"), + MTK_FUNCTION(7, "TDD_TXD") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "URTS3"), + MTK_FUNCTION(2, "C2K_UIM0_HOT_PLUG_IN"), + MTK_FUNCTION(3, "SCL1"), + MTK_FUNCTION(4, "PCM1_DO1"), + MTK_FUNCTION(5, "MD_EINT1"), + MTK_FUNCTION(6, "KCOL4"), + MTK_FUNCTION(7, "UTXD0") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "C2K_UIM1_HOT_PLUG_IN"), + MTK_FUNCTION(2, "PCM1_DO0"), + MTK_FUNCTION(3, "I2S3_MCK"), + MTK_FUNCTION(4, "MD_EINT2"), + MTK_FUNCTION(5, "CLKM2"), + MTK_FUNCTION(6, "I2S1_MCK"), + MTK_FUNCTION(7, "DBG_MON_A29") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "PWM1"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "KROW2"), + MTK_FUNCTION(4, "MD_EINT0"), + MTK_FUNCTION(5, "I2S1_MCK"), + MTK_FUNCTION(6, "SDA3"), + MTK_FUNCTION(7, "DBG_MON_A30") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "MD_EINT1"), + MTK_FUNCTION(2, "IRTX_OUT"), + MTK_FUNCTION(3, "C2K_UIM0_HOT_PLUG_IN"), + MTK_FUNCTION(4, "CLKM0"), + MTK_FUNCTION(5, "I2S2_MCK"), + MTK_FUNCTION(6, "SCL3"), + MTK_FUNCTION(7, "URXD0") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "I2S0_MCK"), + MTK_FUNCTION(2, "C2K_UIM1_HOT_PLUG_IN"), + MTK_FUNCTION(3, "KCOL2"), + MTK_FUNCTION(4, "MD_EINT2"), + MTK_FUNCTION(5, "IRTX_OUT"), + MTK_FUNCTION(6, "SRCLKENAI2"), + MTK_FUNCTION(7, "PCM1_DO1") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "WB_CTRL0"), + MTK_FUNCTION(3, "C2K_ARM_EINT0"), + MTK_FUNCTION(7, "DBG_MON_A0") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "WB_CTRL1"), + MTK_FUNCTION(3, "C2K_ARM_EINT1"), + MTK_FUNCTION(7, "DBG_MON_A1") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "WB_CTRL2"), + MTK_FUNCTION(3, "C2K_ARM_EINT2"), + MTK_FUNCTION(7, "DBG_MON_A2") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "WB_CTRL3"), + MTK_FUNCTION(3, "C2K_ARM_EINT3"), + MTK_FUNCTION(7, "DBG_MON_A3") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "WB_CTRL4"), + MTK_FUNCTION(3, "C2K_DM_EINT0"), + MTK_FUNCTION(4, "WATCHDOG"), + MTK_FUNCTION(7, "DBG_MON_A4") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "WB_CTRL5"), + MTK_FUNCTION(3, "C2K_DM_EINT1"), + MTK_FUNCTION(7, "DBG_MON_A5") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "ANT_SEL0"), + MTK_FUNCTION(2, "IRTX_OUT"), + MTK_FUNCTION(3, "IRDA_TX"), + MTK_FUNCTION(4, "C2K_UART0_TXD"), + MTK_FUNCTION(5, "GPS_FRAME_SYNC"), + MTK_FUNCTION(6, "LTE_UTXD"), + MTK_FUNCTION(7, "DBG_MON_A6") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "ANT_SEL1"), + MTK_FUNCTION(2, "C2K_UIM1_HOT_PLUG_IN"), + MTK_FUNCTION(3, "IRDA_RX"), + MTK_FUNCTION(4, "C2K_UART0_RXD"), + MTK_FUNCTION(5, "MD_EINT2"), + MTK_FUNCTION(6, "LTE_URXD"), + MTK_FUNCTION(7, "DBG_MON_A7") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "ANT_SEL2"), + MTK_FUNCTION(2, "PWM2"), + MTK_FUNCTION(3, "IRDA_PDN"), + MTK_FUNCTION(4, "CORESONIC_SWCK"), + MTK_FUNCTION(5, "MD_EINT1"), + MTK_FUNCTION(6, "C2K_UIM0_HOT_PLUG_IN"), + MTK_FUNCTION(7, "DBG_MON_A8") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "RDN0") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "RDP0") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "RDN1") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "RDP1") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "RCN") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "RCP") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "RDN2") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "RDP2") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "RDN3") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "RDP3") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "RDN0_A"), + MTK_FUNCTION(2, "CMHSYNC"), + MTK_FUNCTION(3, "CMCSD0") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "RDP0_A"), + MTK_FUNCTION(2, "CMVSYNC"), + MTK_FUNCTION(3, "CMCSD1") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "RDN1_A"), + MTK_FUNCTION(2, "CMDAT9"), + MTK_FUNCTION(3, "CMCSD2") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "RDP1_A"), + MTK_FUNCTION(2, "CMDAT8"), + MTK_FUNCTION(3, "CMCSD3") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "RCN_A"), + MTK_FUNCTION(2, "CMDAT7") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "RCP_A"), + MTK_FUNCTION(2, "CMDAT6") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "RDN2_A"), + MTK_FUNCTION(2, "CMDAT5") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "RDP2_A"), + MTK_FUNCTION(2, "CMDAT4") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "RDN3_A"), + MTK_FUNCTION(2, "CMDAT3") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "RDP3_A"), + MTK_FUNCTION(2, "CMDAT2") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "CMDAT0"), + MTK_FUNCTION(2, "CMCSD0"), + MTK_FUNCTION(3, "CMMCLK1"), + MTK_FUNCTION(5, "ANT_SEL5"), + MTK_FUNCTION(6, "CLKM5"), + MTK_FUNCTION(7, "DBG_MON_A9") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "CMDAT1"), + MTK_FUNCTION(2, "CMCSD1"), + MTK_FUNCTION(3, "CMFLASH"), + MTK_FUNCTION(4, "MD_EINT0"), + MTK_FUNCTION(5, "CMMCLK1"), + MTK_FUNCTION(6, "CLKM4"), + MTK_FUNCTION(7, "DBG_MON_A10") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "CMPCLK"), + MTK_FUNCTION(2, "CMCSK"), + MTK_FUNCTION(3, "CMCSD2"), + MTK_FUNCTION(4, "KCOL3"), + MTK_FUNCTION(5, "SRCLKENAI2"), + MTK_FUNCTION(6, "PWM0"), + MTK_FUNCTION(7, "DBG_MON_A11") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(7, "DBG_MON_A12") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "LTE_MD32_JTAG_TRST"), + MTK_FUNCTION(4, "TDD_TRSTN"), + MTK_FUNCTION(5, "DM_JTINTP"), + MTK_FUNCTION(6, "KCOL6"), + MTK_FUNCTION(7, "DBG_MON_A13") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "SDA0") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "SCL0") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "SDA1") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "SCL1") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "SDA2") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(0, 52), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "SCL2") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(0, 53), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(3, "IDDIG"), + MTK_FUNCTION(5, "MD_EINT2"), + MTK_FUNCTION(6, "C2K_UIM1_HOT_PLUG_IN") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(0, 54), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(3, "IDDIG"), + MTK_FUNCTION(5, "MD_EINT1"), + MTK_FUNCTION(6, "C2K_UIM0_HOT_PLUG_IN") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(0, 55), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "PWM2"), + MTK_FUNCTION(3, "CLKM5"), + MTK_FUNCTION(4, "CORESONIC_SWD"), + MTK_FUNCTION(5, "ANT_SEL6"), + MTK_FUNCTION(6, "KROW5"), + MTK_FUNCTION(7, "DISP_PWM") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(0, 56), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "SRCLKENA1") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(0, 57), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "URXD2"), + MTK_FUNCTION(2, "DPI_HSYNC0"), + MTK_FUNCTION(3, "UTXD2"), + MTK_FUNCTION(4, "MD_URXD"), + MTK_FUNCTION(5, "SRCLKENAI1"), + MTK_FUNCTION(6, "KROW4"), + MTK_FUNCTION(7, "DBG_MON_A14") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(0, 58), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "UTXD2"), + MTK_FUNCTION(2, "DPI_VSYNC0"), + MTK_FUNCTION(3, "URXD2"), + MTK_FUNCTION(4, "MD_UTXD"), + MTK_FUNCTION(5, "TDD_TXD"), + MTK_FUNCTION(6, "KROW5"), + MTK_FUNCTION(7, "DBG_MON_A15") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(0, 59), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "URXD3"), + MTK_FUNCTION(2, "DPI_CK0"), + MTK_FUNCTION(3, "UTXD3"), + MTK_FUNCTION(4, "UCTS2"), + MTK_FUNCTION(5, "PWM3"), + MTK_FUNCTION(6, "KROW6"), + MTK_FUNCTION(7, "DBG_MON_A16") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "UTXD3"), + MTK_FUNCTION(2, "DPI_DE0"), + MTK_FUNCTION(3, "URXD3"), + MTK_FUNCTION(4, "URTS2"), + MTK_FUNCTION(5, "PWM4"), + MTK_FUNCTION(6, "KROW7"), + MTK_FUNCTION(7, "DBG_MON_A17") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "PCM1_CLK"), + MTK_FUNCTION(2, "DPI_D0"), + MTK_FUNCTION(3, "I2S0_BCK"), + MTK_FUNCTION(4, "KROW4"), + MTK_FUNCTION(5, "ANT_SEL3"), + MTK_FUNCTION(6, "IRTX_OUT"), + MTK_FUNCTION(7, "DBG_MON_A18") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "PCM1_SYNC"), + MTK_FUNCTION(2, "DPI_D1"), + MTK_FUNCTION(3, "I2S0_LRCK"), + MTK_FUNCTION(4, "KCOL7"), + MTK_FUNCTION(5, "CLKM3"), + MTK_FUNCTION(6, "CMFLASH"), + MTK_FUNCTION(7, "DBG_MON_A19") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "PCM1_DI"), + MTK_FUNCTION(2, "DPI_D2"), + MTK_FUNCTION(3, "I2S0_DI"), + MTK_FUNCTION(4, "PCM1_DO0"), + MTK_FUNCTION(5, "CLKM5"), + MTK_FUNCTION(6, "KROW3"), + MTK_FUNCTION(7, "DBG_MON_A20") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "PCM1_DO0"), + MTK_FUNCTION(2, "DPI_D3"), + MTK_FUNCTION(3, "I2S0_MCK"), + MTK_FUNCTION(4, "PCM1_DI"), + MTK_FUNCTION(5, "SRCLKENAI2"), + MTK_FUNCTION(6, "KCOL5"), + MTK_FUNCTION(7, "DBG_MON_A21") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "SPI_CSA"), + MTK_FUNCTION(2, "EXT_FRAME_SYNC"), + MTK_FUNCTION(3, "I2S3_MCK"), + MTK_FUNCTION(4, "KROW2"), + MTK_FUNCTION(5, "GPS_FRAME_SYNC"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(7, "DBG_MON_A22") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(0, 66), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "SPI_CKA"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "I2S3_BCK"), + MTK_FUNCTION(4, "KCOL2"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(7, "DBG_MON_A23") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(0, 67), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "SPI_MIA"), + MTK_FUNCTION(2, "SPI_MOA"), + MTK_FUNCTION(3, "I2S3_DO"), + MTK_FUNCTION(4, "PTA_RXD"), + MTK_FUNCTION(5, "IDDIG"), + MTK_FUNCTION(6, "UCTS1"), + MTK_FUNCTION(7, "DBG_MON_A24") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(0, 68), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "SPI_MOA"), + MTK_FUNCTION(2, "SPI_MIA"), + MTK_FUNCTION(3, "I2S3_LRCK"), + MTK_FUNCTION(4, "PTA_TXD"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "URTS1"), + MTK_FUNCTION(7, "DBG_MON_A25") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(0, 69), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "PWM1"), + MTK_FUNCTION(3, "LTE_MD32_JTAG_TRST"), + MTK_FUNCTION(4, "TDD_TRSTN"), + MTK_FUNCTION(5, "ANT_SEL7"), + MTK_FUNCTION(6, "DM_JTINTP") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "JTMS"), + MTK_FUNCTION(2, "CONN_MCU_TMS"), + MTK_FUNCTION(3, "LTE_MD32_JTAG_TMS"), + MTK_FUNCTION(4, "TDD_TMS"), + MTK_FUNCTION(5, "CORESONIC_SWD"), + MTK_FUNCTION(6, "DM_OTMS"), + MTK_FUNCTION(7, "DFD_TMS") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "JTCK"), + MTK_FUNCTION(2, "CONN_MCU_TCK_1"), + MTK_FUNCTION(3, "LTE_MD32_JTAG_TCK"), + MTK_FUNCTION(4, "TDD_TCK"), + MTK_FUNCTION(5, "CORESONIC_SWCK"), + MTK_FUNCTION(6, "DM_OTCK"), + MTK_FUNCTION(7, "DFD_TCK_XI") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "JTDI"), + MTK_FUNCTION(2, "CONN_MCU_TDI"), + MTK_FUNCTION(3, "LTE_MD32_JTAG_TDI"), + MTK_FUNCTION(4, "TDD_TDI"), + MTK_FUNCTION(6, "DM_OTDI"), + MTK_FUNCTION(7, "DFD_TDI") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "JTDO"), + MTK_FUNCTION(2, "CONN_MCU_TDO"), + MTK_FUNCTION(3, "LTE_MD32_JTAG_TDO"), + MTK_FUNCTION(4, "TDD_TDO"), + MTK_FUNCTION(6, "DM_OTDO"), + MTK_FUNCTION(7, "DFD_TDO") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "UTXD0"), + MTK_FUNCTION(3, "MD_URXD"), + MTK_FUNCTION(4, "SDA3"), + MTK_FUNCTION(5, "C2K_UART0_RXD"), + MTK_FUNCTION(6, "LTE_URXD"), + MTK_FUNCTION(7, "AUXIF_ST") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(0, 75), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "URXD0"), + MTK_FUNCTION(3, "MD_UTXD"), + MTK_FUNCTION(4, "TDD_TXD"), + MTK_FUNCTION(5, "C2K_UART0_TXD"), + MTK_FUNCTION(6, "LTE_UTXD") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(0, 76), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "UTXD1"), + MTK_FUNCTION(3, "MD_URXD"), + MTK_FUNCTION(4, "SCL3"), + MTK_FUNCTION(5, "LTE_URXD"), + MTK_FUNCTION(6, "C2K_UART0_RXD"), + MTK_FUNCTION(7, "AUXIF_CLK") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(0, 77), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "URXD1"), + MTK_FUNCTION(3, "MD_UTXD"), + MTK_FUNCTION(4, "TDD_TXD"), + MTK_FUNCTION(5, "LTE_UTXD"), + MTK_FUNCTION(6, "C2K_UART0_TXD") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(0, 78), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "PCM1_DI"), + MTK_FUNCTION(3, "I2S3_DO"), + MTK_FUNCTION(4, "I2S1_DO"), + MTK_FUNCTION(5, "PWM0"), + MTK_FUNCTION(6, "I2S2_DI"), + MTK_FUNCTION(7, "DBG_MON_A26") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "I2S0_LRCK"), + MTK_FUNCTION(2, "PCM1_SYNC"), + MTK_FUNCTION(3, "I2S3_LRCK"), + MTK_FUNCTION(4, "I2S1_LRCK"), + MTK_FUNCTION(5, "PWM3"), + MTK_FUNCTION(6, "I2S2_LRCK"), + MTK_FUNCTION(7, "DBG_MON_A27") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "I2S0_BCK"), + MTK_FUNCTION(2, "PCM1_CLK_1"), + MTK_FUNCTION(3, "I2S3_BCK"), + MTK_FUNCTION(4, "I2S1_BCK"), + MTK_FUNCTION(5, "PWM4"), + MTK_FUNCTION(6, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_A28") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "KROW0"), + MTK_FUNCTION(3, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(4, "CORESONIC_SWCK"), + MTK_FUNCTION(5, "C2K_TCK"), + MTK_FUNCTION(7, "C2K_DM_EINT1") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "KROW1"), + MTK_FUNCTION(3, "CONN_MCU_TRST_B"), + MTK_FUNCTION(4, "CORESONIC_SWD"), + MTK_FUNCTION(5, "C2K_NTRST"), + MTK_FUNCTION(6, "USB_DRVVBUS"), + MTK_FUNCTION(7, "C2K_DM_EINT2") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "KROW2"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(5, "C2K_TDI"), + MTK_FUNCTION(7, "C2K_DM_EINT3") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "KCOL0"), + MTK_FUNCTION(2, "URTS0"), + MTK_FUNCTION(3, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(4, "SCL2"), + MTK_FUNCTION(5, "C2K_TDO"), + MTK_FUNCTION(6, "AUXIF_CLK") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "KCOL1"), + MTK_FUNCTION(2, "UCTS0"), + MTK_FUNCTION(3, "UCTS1"), + MTK_FUNCTION(4, "SDA2"), + MTK_FUNCTION(5, "C2K_TMS"), + MTK_FUNCTION(6, "AUXIF_ST"), + MTK_FUNCTION(7, "DBG_MON_A31") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "KCOL2"), + MTK_FUNCTION(3, "URTS1"), + MTK_FUNCTION(5, "C2K_RTCK"), + MTK_FUNCTION(7, "DBG_MON_A32") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "BPI_BUS5"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS5"), + MTK_FUNCTION(5, "C2K_BPI_BUS5"), + MTK_FUNCTION(7, "DBG_MON_B0") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "BPI_BUS6"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS6"), + MTK_FUNCTION(5, "C2K_BPI_BUS6"), + MTK_FUNCTION(7, "DBG_MON_B1") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "BPI_BUS7"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS7"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(5, "C2K_BPI_BUS7"), + MTK_FUNCTION(7, "DBG_MON_B2") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "BPI_BUS8"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS8"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(5, "C2K_BPI_BUS8"), + MTK_FUNCTION(7, "DBG_MON_B3") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "BPI_BUS9"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS9"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(5, "C2K_BPI_BUS9"), + MTK_FUNCTION(7, "DBG_MON_B4") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "BPI_BUS10"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS10"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(5, "C2K_BPI_BUS10"), + MTK_FUNCTION(7, "DBG_MON_B5") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "BPI_BUS11"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS11"), + MTK_FUNCTION(5, "C2K_BPI_BUS11"), + MTK_FUNCTION(7, "DBG_MON_B6") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "BPI_BUS12"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS12"), + MTK_FUNCTION(5, "C2K_BPI_BUS12"), + MTK_FUNCTION(7, "DBG_MON_B7") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "BPI_BUS13"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS13"), + MTK_FUNCTION(5, "C2K_BPI_BUS13"), + MTK_FUNCTION(7, "DBG_MON_B8") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "BPI_BUS14"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS14"), + MTK_FUNCTION(5, "C2K_BPI_BUS14"), + MTK_FUNCTION(7, "DBG_MON_B9") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "BPI_BUS15"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS15"), + MTK_FUNCTION(5, "C2K_BPI_BUS15"), + MTK_FUNCTION(7, "DBG_MON_B10") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "BPI_BUS16"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS16"), + MTK_FUNCTION(5, "C2K_BPI_BUS16"), + MTK_FUNCTION(7, "DBG_MON_B11") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(0, 99), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "BPI_BUS17"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS17"), + MTK_FUNCTION(5, "C2K_BPI_BUS17"), + MTK_FUNCTION(7, "DBG_MON_B12") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(0, 100), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "BPI_BUS18"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS18"), + MTK_FUNCTION(5, "C2K_BPI_BUS18"), + MTK_FUNCTION(7, "DBG_MON_B13") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(0, 101), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "BPI_BUS19"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS19"), + MTK_FUNCTION(5, "C2K_BPI_BUS19"), + MTK_FUNCTION(7, "DBG_MON_B14") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(0, 102), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "BPI_BUS20"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS20"), + MTK_FUNCTION(5, "C2K_BPI_BUS20"), + MTK_FUNCTION(7, "DBG_MON_B15") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "C2K_TXBPI"), + MTK_FUNCTION(7, "DBG_MON_B16") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(0, 104), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "RFIC1_BSI_EN"), + MTK_FUNCTION(5, "C2K_RX_BSI_EN"), + MTK_FUNCTION(7, "DBG_MON_B17") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(0, 105), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "RFIC1_BSI_CK"), + MTK_FUNCTION(5, "C2K_RX_BSI_CLK"), + MTK_FUNCTION(7, "DBG_MON_B18") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "RFIC1_BSI_D0"), + MTK_FUNCTION(5, "C2K_RX_BSI_DATA"), + MTK_FUNCTION(7, "DBG_MON_B19") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "RFIC1_BSI_D1"), + MTK_FUNCTION(5, "C2K_TX_BSI_EN"), + MTK_FUNCTION(7, "DBG_MON_B20") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "RFIC1_BSI_D2"), + MTK_FUNCTION(5, "C2K_TX_BSI_CLK"), + MTK_FUNCTION(7, "DBG_MON_B21") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(5, "C2K_TX_BSI_DATA"), + MTK_FUNCTION(7, "DBG_MON_B22") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "RFIC0_BSI_EN"), + MTK_FUNCTION(4, "SPM_BSI_EN"), + MTK_FUNCTION(7, "DBG_MON_B23") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "RFIC0_BSI_CK"), + MTK_FUNCTION(4, "SPM_BSI_CLK"), + MTK_FUNCTION(7, "DBG_MON_B24") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "RFIC0_BSI_D2"), + MTK_FUNCTION(4, "SPM_BSI_D2"), + MTK_FUNCTION(7, "DBG_MON_B25") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, 113), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "RFIC0_BSI_D1"), + MTK_FUNCTION(4, "SPM_BSI_D1"), + MTK_FUNCTION(7, "DBG_MON_B26") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, 114), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "RFIC0_BSI_D0"), + MTK_FUNCTION(4, "SPM_BSI_D0"), + MTK_FUNCTION(7, "DBG_MON_B27") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, 115), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "AUXIN0") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, 116), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "AUXIN1") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(0, 117), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "AUXIN2") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(0, 118), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "TXBPI") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(0, 119), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "BPI_BUS0"), + MTK_FUNCTION(7, "DBG_MON_B28") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(0, 120), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "BPI_BUS1"), + MTK_FUNCTION(7, "DBG_MON_B29") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(0, 121), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "BPI_BUS2"), + MTK_FUNCTION(7, "DBG_MON_B30") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(0, 122), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "BPI_BUS3"), + MTK_FUNCTION(7, "DBG_MON_B31") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(0, 123), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "BPI_BUS4"), + MTK_FUNCTION(7, "DBG_MON_B32") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(0, 124), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "BPI_BUS21"), + MTK_FUNCTION(5, "DPI_HSYNC1"), + MTK_FUNCTION(6, "KCOL2"), + MTK_FUNCTION(7, "TDD_TXD") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(0, 125), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "BPI_BUS22"), + MTK_FUNCTION(5, "DPI_VSYNC1"), + MTK_FUNCTION(6, "KROW2"), + MTK_FUNCTION(7, "MD_URXD") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(0, 126), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "BPI_BUS23"), + MTK_FUNCTION(5, "DPI_CK1"), + MTK_FUNCTION(6, "I2S2_MCK"), + MTK_FUNCTION(7, "MD_UTXD") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(0, 127), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "BPI_BUS24"), + MTK_FUNCTION(3, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "DPI_DE1"), + MTK_FUNCTION(6, "SRCLKENAI1"), + MTK_FUNCTION(7, "URXD0") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(0, 128), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "BPI_BUS25"), + MTK_FUNCTION(3, "GPS_FRAME_SYNC"), + MTK_FUNCTION(5, "I2S2_DI"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(7, "UTXD0") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(0, 129), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "BPI_BUS26"), + MTK_FUNCTION(2, "DISP_PWM"), + MTK_FUNCTION(5, "I2S2_LRCK"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(7, "LTE_URXD") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(0, 130), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "BPI_BUS27"), + MTK_FUNCTION(5, "I2S2_BCK"), + MTK_FUNCTION(6, "IRTX_OUT"), + MTK_FUNCTION(7, "LTE_UTXD") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(0, 131), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "LTE_PAVM0") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(0, 132), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "LTE_PAVM1") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(0, 133), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "MIPI1_SCLK") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(0, 134), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "MIPI1_SDATA") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(0, 135), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "MIPI0_SCLK") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(0, 136), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "MIPI0_SDATA") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(0, 137), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(0, 138), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "PWRAP_SPIDO"), + MTK_FUNCTION(2, "PWRAP_SPIDI") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(0, 139), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "PWRAP_SPIDI"), + MTK_FUNCTION(2, "PWRAP_SPIDO") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(0, 140), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(3, "LTE_MD32_JTAG_TRST"), + MTK_FUNCTION(4, "TDD_TRSTN"), + MTK_FUNCTION(5, "DM_JTINTP") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(0, 141), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "PWRAP_SPICK_I") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(0, 142), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "PWRAP_SPICS_B_I") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(0, 143), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "AUD_CLK_MOSI") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(0, 144), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "AUD_DAT_MISO"), + MTK_FUNCTION(3, "AUD_DAT_MOSI") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(0, 145), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "AUD_DAT_MOSI"), + MTK_FUNCTION(3, "AUD_DAT_MISO") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(0, 146), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "LCM_RST") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(0, 147), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "DSI_TE") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(0, 148), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "SRCLKENA") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(0, 149), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(0, 150), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "TDP0") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(0, 151), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "TDN0") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(0, 152), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "TDP1") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(0, 153), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "TDN1") + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(0, 154), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "TCP") + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(0, 155), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "TCN") + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(0, 156), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "TDP2") + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(0, 157), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "TDN2") + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(0, 158), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "TDP3") + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(0, 159), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "TDN3") + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(0, 160), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "MD_SIM2_SCLK"), + MTK_FUNCTION(2, "MD_SIM1_SCLK"), + MTK_FUNCTION(3, "UIM0_CLK"), + MTK_FUNCTION(4, "UIM1_CLK") + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(0, 161), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "MD_SIM2_SRST"), + MTK_FUNCTION(2, "MD_SIM1_SRST"), + MTK_FUNCTION(3, "UIM0_RST"), + MTK_FUNCTION(4, "UIM1_RST") + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(0, 162), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "MD_SIM2_SDAT"), + MTK_FUNCTION(2, "MD_SIM1_SDAT"), + MTK_FUNCTION(3, "UIM0_IO"), + MTK_FUNCTION(4, "UIM1_IO") + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(0, 163), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "MD_SIM1_SCLK"), + MTK_FUNCTION(2, "MD_SIM2_SCLK"), + MTK_FUNCTION(3, "UIM1_CLK"), + MTK_FUNCTION(4, "UIM0_CLK") + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(0, 164), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "MD_SIM1_SRST"), + MTK_FUNCTION(2, "MD_SIM2_SRST"), + MTK_FUNCTION(3, "UIM1_RST"), + MTK_FUNCTION(4, "UIM0_RST") + ), + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(0, 165), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "MD_SIM1_SDAT"), + MTK_FUNCTION(2, "MD_SIM2_SDAT"), + MTK_FUNCTION(3, "UIM1_IO"), + MTK_FUNCTION(4, "UIM0_IO") + ), + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(0, 166), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "LTE_MD32_JTAG_TMS"), + MTK_FUNCTION(3, "C2K_TMS"), + MTK_FUNCTION(4, "TDD_TMS"), + MTK_FUNCTION(5, "CONN_DSP_JMS"), + MTK_FUNCTION(6, "JTMS"), + MTK_FUNCTION(7, "CONN_MCU_AICE_TMSC") + ), + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(0, 167), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "LTE_MD32_JTAG_TCK"), + MTK_FUNCTION(3, "C2K_TCK"), + MTK_FUNCTION(4, "TDD_TCK"), + MTK_FUNCTION(5, "CONN_DSP_JCK"), + MTK_FUNCTION(6, "JTCK"), + MTK_FUNCTION(7, "CONN_MCU_AICE_TCKC") + ), + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(0, 168), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "LTE_MD32_JTAG_TDI"), + MTK_FUNCTION(3, "C2K_TDI"), + MTK_FUNCTION(4, "TDD_TDI"), + MTK_FUNCTION(5, "CONN_DSP_JDI"), + MTK_FUNCTION(6, "JTDI") + ), + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(0, 169), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "LTE_MD32_JTAG_TDO"), + MTK_FUNCTION(3, "C2K_TDO"), + MTK_FUNCTION(4, "TDD_TDO"), + MTK_FUNCTION(5, "CONN_DSP_JDO"), + MTK_FUNCTION(6, "JTDO") + ), + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(0, 170), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "LTE_MD32_JTAG_TRST"), + MTK_FUNCTION(3, "C2K_NTRST"), + MTK_FUNCTION(4, "TDD_TRSTN"), + MTK_FUNCTION(5, "CONN_DSP_JINTP"), + MTK_FUNCTION(6, "DM_JTINTP") + ), + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(0, 171), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(3, "C2K_RTCK") + ), + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(0, 172), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "MSDC0_CMD") + ), + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(0, 173), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "MSDC0_DSL") + ), + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(0, 174), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "MSDC0_CLK") + ), + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(0, 175), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "MSDC0_DAT0") + ), + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(0, 176), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "MSDC0_DAT1") + ), + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(0, 177), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "MSDC0_DAT2") + ), + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(0, 178), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "MSDC0_DAT3") + ), + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(0, 179), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "MSDC0_DAT4") + ), + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(0, 180), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "MSDC0_DAT5") + ), + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(0, 181), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "MSDC0_DAT6") + ), + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(0, 182), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "MSDC0_DAT7") + ), + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(0, 183), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "MSDC0_RSTB") + ), + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(0, 184), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "F2W_DATA"), + MTK_FUNCTION(2, "MRG_CLK"), + MTK_FUNCTION(3, "C2K_DM_EINT2"), + MTK_FUNCTION(4, "PCM0_CLK") + ), + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(0, 185), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO185"), + MTK_FUNCTION(1, "F2W_CK"), + MTK_FUNCTION(2, "MRG_DI"), + MTK_FUNCTION(3, "C2K_DM_EINT3"), + MTK_FUNCTION(4, "PCM0_DI") + ), + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(0, 186), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO186"), + MTK_FUNCTION(1, "WB_RSTB"), + MTK_FUNCTION(4, "URXD3"), + MTK_FUNCTION(5, "UTXD3") + ), + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(0, 187), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO187"), + MTK_FUNCTION(1, "WB_SCLK"), + MTK_FUNCTION(2, "MRG_DO"), + MTK_FUNCTION(4, "PCM0_DO") + ), + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(0, 188), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO188"), + MTK_FUNCTION(1, "WB_SDATA"), + MTK_FUNCTION(2, "MRG_SYNC"), + MTK_FUNCTION(4, "PCM0_SYNC") + ), + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(0, 189), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO189"), + MTK_FUNCTION(1, "WB_SEN"), + MTK_FUNCTION(4, "UTXD3"), + MTK_FUNCTION(5, "URXD3") + ), + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(0, 190), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO190"), + MTK_FUNCTION(1, "GPS_RXQN") + ), + MTK_PIN( + 191, "GPIO191", + MTK_EINT_FUNCTION(0, 191), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO191"), + MTK_FUNCTION(1, "GPS_RXQP") + ), + MTK_PIN( + 192, "GPIO192", + MTK_EINT_FUNCTION(0, 192), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO192"), + MTK_FUNCTION(1, "GPS_RXIN") + ), + MTK_PIN( + 193, "GPIO193", + MTK_EINT_FUNCTION(0, 193), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO193"), + MTK_FUNCTION(1, "GPS_RXIP") + ), + MTK_PIN( + 194, "GPIO194", + MTK_EINT_FUNCTION(0, 194), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO194"), + MTK_FUNCTION(1, "WB_RXQN") + ), + MTK_PIN( + 195, "GPIO195", + MTK_EINT_FUNCTION(0, 195), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO195"), + MTK_FUNCTION(1, "WB_RXQP") + ), + MTK_PIN( + 196, "GPIO196", + MTK_EINT_FUNCTION(0, 196), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO196"), + MTK_FUNCTION(1, "WB_RXIN") + ), + MTK_PIN( + 197, "GPIO197", + MTK_EINT_FUNCTION(0, 197), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO197"), + MTK_FUNCTION(1, "WB_RXIP") + ), + MTK_PIN( + 198, "GPIO198", + MTK_EINT_FUNCTION(0, 198), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO198"), + MTK_FUNCTION(1, "MSDC2_CMD"), + MTK_FUNCTION(2, "SDA1"), + MTK_FUNCTION(3, "C2K_UART0_RXD"), + MTK_FUNCTION(4, "C2K_TMS"), + MTK_FUNCTION(5, "ANT_SEL6"), + MTK_FUNCTION(7, "DM_OTMS") + ), + MTK_PIN( + 199, "GPIO199", + MTK_EINT_FUNCTION(0, 199), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO199"), + MTK_FUNCTION(1, "MSDC2_CLK"), + MTK_FUNCTION(2, "SCL1"), + MTK_FUNCTION(3, "C2K_UART0_TXD"), + MTK_FUNCTION(4, "C2K_TCK"), + MTK_FUNCTION(5, "ANT_SEL7"), + MTK_FUNCTION(6, "TDD_TXD"), + MTK_FUNCTION(7, "DM_OTCK") + ), + MTK_PIN( + 200, "GPIO200", + MTK_EINT_FUNCTION(0, 200), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO200"), + MTK_FUNCTION(1, "MSDC2_DAT0"), + MTK_FUNCTION(2, "ANT_SEL6"), + MTK_FUNCTION(3, "GPS_FRAME_SYNC"), + MTK_FUNCTION(4, "C2K_TDI"), + MTK_FUNCTION(5, "UTXD0"), + MTK_FUNCTION(7, "DM_OTDI") + ), + MTK_PIN( + 201, "GPIO201", + MTK_EINT_FUNCTION(0, 201), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO201"), + MTK_FUNCTION(1, "MSDC2_DAT1"), + MTK_FUNCTION(2, "ANT_SEL3"), + MTK_FUNCTION(3, "PWM0"), + MTK_FUNCTION(4, "C2K_TDO"), + MTK_FUNCTION(5, "URXD0"), + MTK_FUNCTION(7, "DM_OTDO") + ), + MTK_PIN( + 202, "GPIO202", + MTK_EINT_FUNCTION(0, 202), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO202"), + MTK_FUNCTION(1, "MSDC2_DAT2"), + MTK_FUNCTION(2, "ANT_SEL4"), + MTK_FUNCTION(3, "SDA2"), + MTK_FUNCTION(4, "C2K_NTRST"), + MTK_FUNCTION(5, "UTXD1"), + MTK_FUNCTION(6, "KCOL3"), + MTK_FUNCTION(7, "DM_JTINTP") + ), + MTK_PIN( + 203, "GPIO203", + MTK_EINT_FUNCTION(0, 203), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO203"), + MTK_FUNCTION(1, "MSDC2_DAT3"), + MTK_FUNCTION(2, "ANT_SEL5"), + MTK_FUNCTION(3, "SCL2"), + MTK_FUNCTION(4, "C2K_RTCK"), + MTK_FUNCTION(5, "URXD1"), + MTK_FUNCTION(6, "KCOL6") + ), + MTK_PIN( + 204, "GPIO204", + MTK_EINT_FUNCTION(0, 204), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 205, "GPIO205", + MTK_EINT_FUNCTION(0, 205), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 206, "GPIO206", + MTK_EINT_FUNCTION(0, 206), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 207, "GPIO207", + MTK_EINT_FUNCTION(0, 207), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 208, "GPIO208", + MTK_EINT_FUNCTION(0, 208), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 209, "GPIO209", + MTK_EINT_FUNCTION(0, 209), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 210, "GPIO210", + MTK_EINT_FUNCTION(0, 210), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 211, "GPIO211", + MTK_EINT_FUNCTION(0, 211), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 212, "GPIO212", + MTK_EINT_FUNCTION(0, 212), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), +}; + +static const struct mtk_pin_desc mtk_pins_mt6735m[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "IDDIG"), + MTK_FUNCTION(2, "DPI_D4"), + MTK_FUNCTION(3, "CLKM4"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "PWM3"), + MTK_FUNCTION(6, "KCOL2"), + MTK_FUNCTION(7, "C2K_ARM_EINT0") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "PWM2"), + MTK_FUNCTION(2, "DPI_D5"), + MTK_FUNCTION(3, "MD_EINT0"), + MTK_FUNCTION(4, "TDD_TDO"), + MTK_FUNCTION(5, "CONN_MCU_TDO"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(7, "C2K_ARM_EINT1") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "CLKM0"), + MTK_FUNCTION(2, "DPI_D6"), + MTK_FUNCTION(3, "MD_EINT0"), + MTK_FUNCTION(4, "USB_DRVVBUS"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(7, "C2K_ARM_EINT2") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "CLKM1"), + MTK_FUNCTION(2, "DPI_D7"), + MTK_FUNCTION(3, "SPI_MIB"), + MTK_FUNCTION(4, "MD_EINT0"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"), + MTK_FUNCTION(7, "C2K_ARM_EINT3") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "CLKM2"), + MTK_FUNCTION(2, "DPI_D8"), + MTK_FUNCTION(3, "SPI_MOB"), + MTK_FUNCTION(4, "TDD_TCK"), + MTK_FUNCTION(5, "CONN_MCU_TCK_0"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"), + MTK_FUNCTION(7, "C2K_DM_EINT0") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "UCTS2"), + MTK_FUNCTION(2, "DPI_D9"), + MTK_FUNCTION(3, "SPI_CSB"), + MTK_FUNCTION(4, "TDD_TDI"), + MTK_FUNCTION(5, "CONN_MCU_TDI"), + MTK_FUNCTION(6, "I2S1_DO"), + MTK_FUNCTION(7, "MD_URXD") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "URTS2"), + MTK_FUNCTION(2, "DPI_D10"), + MTK_FUNCTION(3, "SPI_CKB"), + MTK_FUNCTION(4, "TDD_TRSTN"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B"), + MTK_FUNCTION(6, "I2S1_LRCK"), + MTK_FUNCTION(7, "MD_UTXD") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "UCTS3"), + MTK_FUNCTION(2, "DPI_D11"), + MTK_FUNCTION(3, "SDA1"), + MTK_FUNCTION(4, "TDD_TMS"), + MTK_FUNCTION(5, "CONN_MCU_TMS"), + MTK_FUNCTION(6, "I2S1_BCK"), + MTK_FUNCTION(7, "TDD_TXD") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "URTS3"), + MTK_FUNCTION(2, "C2K_UIM0_HOT_PLUG_IN"), + MTK_FUNCTION(3, "SCL1"), + MTK_FUNCTION(4, "PCM1_DO1"), + MTK_FUNCTION(5, "MD_EINT1"), + MTK_FUNCTION(6, "KCOL4"), + MTK_FUNCTION(7, "UTXD0") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "C2K_UIM1_HOT_PLUG_IN"), + MTK_FUNCTION(2, "PCM1_DO0"), + MTK_FUNCTION(3, "I2S3_MCK"), + MTK_FUNCTION(4, "MD_EINT2"), + MTK_FUNCTION(5, "CLKM2"), + MTK_FUNCTION(6, "I2S1_MCK"), + MTK_FUNCTION(7, "DBG_MON_A29") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "PWM1"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "KROW2"), + MTK_FUNCTION(4, "MD_EINT0"), + MTK_FUNCTION(5, "I2S1_MCK"), + MTK_FUNCTION(6, "SDA3"), + MTK_FUNCTION(7, "DBG_MON_A30") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "MD_EINT1"), + MTK_FUNCTION(2, "IRTX_OUT"), + MTK_FUNCTION(3, "C2K_UIM0_HOT_PLUG_IN"), + MTK_FUNCTION(4, "CLKM0"), + MTK_FUNCTION(5, "I2S2_MCK"), + MTK_FUNCTION(6, "SCL3"), + MTK_FUNCTION(7, "URXD0") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "I2S0_MCK"), + MTK_FUNCTION(2, "C2K_UIM1_HOT_PLUG_IN"), + MTK_FUNCTION(3, "KCOL2"), + MTK_FUNCTION(4, "MD_EINT2"), + MTK_FUNCTION(5, "IRTX_OUT"), + MTK_FUNCTION(6, "SRCLKENAI2"), + MTK_FUNCTION(7, "PCM1_DO1") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "WB_CTRL0"), + MTK_FUNCTION(3, "C2K_ARM_EINT0"), + MTK_FUNCTION(7, "DBG_MON_A0") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "WB_CTRL1"), + MTK_FUNCTION(3, "C2K_ARM_EINT1"), + MTK_FUNCTION(7, "DBG_MON_A1") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "WB_CTRL2"), + MTK_FUNCTION(3, "C2K_ARM_EINT2"), + MTK_FUNCTION(7, "DBG_MON_A2") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "WB_CTRL3"), + MTK_FUNCTION(3, "C2K_ARM_EINT3"), + MTK_FUNCTION(7, "DBG_MON_A3") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "WB_CTRL4"), + MTK_FUNCTION(3, "C2K_DM_EINT0"), + MTK_FUNCTION(4, "WATCHDOG"), + MTK_FUNCTION(7, "DBG_MON_A4") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "WB_CTRL5"), + MTK_FUNCTION(3, "C2K_DM_EINT1"), + MTK_FUNCTION(7, "DBG_MON_A5") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "ANT_SEL0"), + MTK_FUNCTION(2, "IRTX_OUT"), + MTK_FUNCTION(3, "IRDA_TX"), + MTK_FUNCTION(4, "C2K_UART0_TXD"), + MTK_FUNCTION(5, "GPS_FRAME_SYNC"), + MTK_FUNCTION(6, "LTE_UTXD"), + MTK_FUNCTION(7, "DBG_MON_A6") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "ANT_SEL1"), + MTK_FUNCTION(2, "C2K_UIM1_HOT_PLUG_IN"), + MTK_FUNCTION(3, "IRDA_RX"), + MTK_FUNCTION(4, "C2K_UART0_RXD"), + MTK_FUNCTION(5, "MD_EINT2"), + MTK_FUNCTION(6, "LTE_URXD"), + MTK_FUNCTION(7, "DBG_MON_A7") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "ANT_SEL2"), + MTK_FUNCTION(2, "PWM2"), + MTK_FUNCTION(3, "IRDA_PDN"), + MTK_FUNCTION(4, "CORESONIC_SWCK"), + MTK_FUNCTION(5, "MD_EINT1"), + MTK_FUNCTION(6, "C2K_UIM0_HOT_PLUG_IN"), + MTK_FUNCTION(7, "DBG_MON_A8") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "RDN0") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "RDP0") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "RDN1") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "RDP1") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "RCN") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "RCP") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "RDN2") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "RDP2") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "RDN3") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "RDP3") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "RDN0_A"), + MTK_FUNCTION(2, "CMHSYNC"), + MTK_FUNCTION(3, "CMCSD0") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "RDP0_A"), + MTK_FUNCTION(2, "CMVSYNC"), + MTK_FUNCTION(3, "CMCSD1") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "RDN1_A"), + MTK_FUNCTION(2, "CMDAT9"), + MTK_FUNCTION(3, "CMCSD2") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "RDP1_A"), + MTK_FUNCTION(2, "CMDAT8"), + MTK_FUNCTION(3, "CMCSD3") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "RCN_A"), + MTK_FUNCTION(2, "CMDAT7") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "RCP_A"), + MTK_FUNCTION(2, "CMDAT6") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "RDN2_A"), + MTK_FUNCTION(2, "CMDAT5") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "RDP2_A"), + MTK_FUNCTION(2, "CMDAT4") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "RDN3_A"), + MTK_FUNCTION(2, "CMDAT3") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "RDP3_A"), + MTK_FUNCTION(2, "CMDAT2") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "CMDAT0"), + MTK_FUNCTION(2, "CMCSD0"), + MTK_FUNCTION(3, "CMMCLK1"), + MTK_FUNCTION(5, "ANT_SEL5"), + MTK_FUNCTION(6, "CLKM5"), + MTK_FUNCTION(7, "DBG_MON_A9") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "CMDAT1"), + MTK_FUNCTION(2, "CMCSD1"), + MTK_FUNCTION(3, "CMFLASH"), + MTK_FUNCTION(4, "MD_EINT0"), + MTK_FUNCTION(5, "CMMCLK1"), + MTK_FUNCTION(6, "CLKM4"), + MTK_FUNCTION(7, "DBG_MON_A10") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "CMPCLK"), + MTK_FUNCTION(2, "CMCSK"), + MTK_FUNCTION(3, "CMCSD2"), + MTK_FUNCTION(4, "KCOL3"), + MTK_FUNCTION(5, "SRCLKENAI2"), + MTK_FUNCTION(6, "PWM0"), + MTK_FUNCTION(7, "DBG_MON_A11") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(7, "DBG_MON_A12") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "LTE_MD32_JTAG_TRST"), + MTK_FUNCTION(4, "TDD_TRSTN"), + MTK_FUNCTION(5, "DM_JTINTP"), + MTK_FUNCTION(6, "KCOL6"), + MTK_FUNCTION(7, "DBG_MON_A13") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "SDA0") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "SCL0") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "SDA1") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "SCL1") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "SDA2") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(0, 52), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "SCL2") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(0, 53), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(3, "IDDIG"), + MTK_FUNCTION(5, "MD_EINT2"), + MTK_FUNCTION(6, "C2K_UIM1_HOT_PLUG_IN") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(0, 54), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(3, "IDDIG"), + MTK_FUNCTION(5, "MD_EINT1"), + MTK_FUNCTION(6, "C2K_UIM0_HOT_PLUG_IN") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(0, 55), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "PWM2"), + MTK_FUNCTION(3, "CLKM5"), + MTK_FUNCTION(4, "CORESONIC_SWD"), + MTK_FUNCTION(5, "ANT_SEL6"), + MTK_FUNCTION(6, "KROW5"), + MTK_FUNCTION(7, "DISP_PWM") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(0, 56), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "SRCLKENA1") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(0, 57), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "URXD2"), + MTK_FUNCTION(2, "DPI_HSYNC0"), + MTK_FUNCTION(3, "UTXD2"), + MTK_FUNCTION(4, "MD_URXD"), + MTK_FUNCTION(5, "SRCLKENAI1"), + MTK_FUNCTION(6, "KROW4"), + MTK_FUNCTION(7, "DBG_MON_A14") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(0, 58), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "UTXD2"), + MTK_FUNCTION(2, "DPI_VSYNC0"), + MTK_FUNCTION(3, "URXD2"), + MTK_FUNCTION(4, "MD_UTXD"), + MTK_FUNCTION(5, "TDD_TXD"), + MTK_FUNCTION(6, "KROW5"), + MTK_FUNCTION(7, "DBG_MON_A15") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(0, 59), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "URXD3"), + MTK_FUNCTION(2, "DPI_CK0"), + MTK_FUNCTION(3, "UTXD3"), + MTK_FUNCTION(4, "UCTS2"), + MTK_FUNCTION(5, "PWM3"), + MTK_FUNCTION(6, "KROW6"), + MTK_FUNCTION(7, "DBG_MON_A16") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "UTXD3"), + MTK_FUNCTION(2, "DPI_DE0"), + MTK_FUNCTION(3, "URXD3"), + MTK_FUNCTION(4, "URTS2"), + MTK_FUNCTION(5, "PWM4"), + MTK_FUNCTION(6, "KROW7"), + MTK_FUNCTION(7, "DBG_MON_A17") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "PCM1_CLK"), + MTK_FUNCTION(2, "DPI_D0"), + MTK_FUNCTION(3, "I2S0_BCK"), + MTK_FUNCTION(4, "KROW4"), + MTK_FUNCTION(5, "ANT_SEL3"), + MTK_FUNCTION(6, "IRTX_OUT"), + MTK_FUNCTION(7, "DBG_MON_A18") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "PCM1_SYNC"), + MTK_FUNCTION(2, "DPI_D1"), + MTK_FUNCTION(3, "I2S0_LRCK"), + MTK_FUNCTION(4, "KCOL7"), + MTK_FUNCTION(5, "CLKM3"), + MTK_FUNCTION(6, "CMFLASH"), + MTK_FUNCTION(7, "DBG_MON_A19") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "PCM1_DI"), + MTK_FUNCTION(2, "DPI_D2"), + MTK_FUNCTION(3, "I2S0_DI"), + MTK_FUNCTION(4, "PCM1_DO0"), + MTK_FUNCTION(5, "CLKM5"), + MTK_FUNCTION(6, "KROW3"), + MTK_FUNCTION(7, "DBG_MON_A20") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "PCM1_DO0"), + MTK_FUNCTION(2, "DPI_D3"), + MTK_FUNCTION(3, "I2S0_MCK"), + MTK_FUNCTION(4, "PCM1_DI"), + MTK_FUNCTION(5, "SRCLKENAI2"), + MTK_FUNCTION(6, "KCOL5"), + MTK_FUNCTION(7, "DBG_MON_A21") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "SPI_CSA"), + MTK_FUNCTION(2, "EXT_FRAME_SYNC"), + MTK_FUNCTION(3, "I2S3_MCK"), + MTK_FUNCTION(4, "KROW2"), + MTK_FUNCTION(5, "GPS_FRAME_SYNC"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(7, "DBG_MON_A22") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(0, 66), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "SPI_CKA"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "I2S3_BCK"), + MTK_FUNCTION(4, "KCOL2"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(7, "DBG_MON_A23") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(0, 67), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "SPI_MIA"), + MTK_FUNCTION(2, "SPI_MOA"), + MTK_FUNCTION(3, "I2S3_DO"), + MTK_FUNCTION(4, "PTA_RXD"), + MTK_FUNCTION(5, "IDDIG"), + MTK_FUNCTION(6, "UCTS1"), + MTK_FUNCTION(7, "DBG_MON_A24") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(0, 68), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "SPI_MOA"), + MTK_FUNCTION(2, "SPI_MIA"), + MTK_FUNCTION(3, "I2S3_LRCK"), + MTK_FUNCTION(4, "PTA_TXD"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "URTS1"), + MTK_FUNCTION(7, "DBG_MON_A25") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(0, 69), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "PWM1"), + MTK_FUNCTION(3, "LTE_MD32_JTAG_TRST"), + MTK_FUNCTION(4, "TDD_TRSTN"), + MTK_FUNCTION(5, "ANT_SEL7"), + MTK_FUNCTION(6, "DM_JTINTP") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "JTMS"), + MTK_FUNCTION(2, "CONN_MCU_TMS"), + MTK_FUNCTION(3, "LTE_MD32_JTAG_TMS"), + MTK_FUNCTION(4, "TDD_TMS"), + MTK_FUNCTION(5, "CORESONIC_SWD"), + MTK_FUNCTION(6, "DM_OTMS"), + MTK_FUNCTION(7, "DFD_TMS") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "JTCK"), + MTK_FUNCTION(2, "CONN_MCU_TCK_1"), + MTK_FUNCTION(3, "LTE_MD32_JTAG_TCK"), + MTK_FUNCTION(4, "TDD_TCK"), + MTK_FUNCTION(5, "CORESONIC_SWCK"), + MTK_FUNCTION(6, "DM_OTCK"), + MTK_FUNCTION(7, "DFD_TCK_XI") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "JTDI"), + MTK_FUNCTION(2, "CONN_MCU_TDI"), + MTK_FUNCTION(3, "LTE_MD32_JTAG_TDI"), + MTK_FUNCTION(4, "TDD_TDI"), + MTK_FUNCTION(6, "DM_OTDI"), + MTK_FUNCTION(7, "DFD_TDI") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "JTDO"), + MTK_FUNCTION(2, "CONN_MCU_TDO"), + MTK_FUNCTION(3, "LTE_MD32_JTAG_TDO"), + MTK_FUNCTION(4, "TDD_TDO"), + MTK_FUNCTION(6, "DM_OTDO"), + MTK_FUNCTION(7, "DFD_TDO") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "UTXD0"), + MTK_FUNCTION(3, "MD_URXD"), + MTK_FUNCTION(4, "SDA3"), + MTK_FUNCTION(5, "C2K_UART0_RXD"), + MTK_FUNCTION(6, "LTE_URXD"), + MTK_FUNCTION(7, "AUXIF_ST") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(0, 75), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "URXD0"), + MTK_FUNCTION(3, "MD_UTXD"), + MTK_FUNCTION(4, "TDD_TXD"), + MTK_FUNCTION(5, "C2K_UART0_TXD"), + MTK_FUNCTION(6, "LTE_UTXD") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(0, 76), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "UTXD1"), + MTK_FUNCTION(3, "MD_URXD"), + MTK_FUNCTION(4, "SCL3"), + MTK_FUNCTION(5, "LTE_URXD"), + MTK_FUNCTION(6, "C2K_UART0_RXD"), + MTK_FUNCTION(7, "AUXIF_CLK") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(0, 77), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "URXD1"), + MTK_FUNCTION(3, "MD_UTXD"), + MTK_FUNCTION(4, "TDD_TXD"), + MTK_FUNCTION(5, "LTE_UTXD"), + MTK_FUNCTION(6, "C2K_UART0_TXD") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(0, 78), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "PCM1_DI"), + MTK_FUNCTION(3, "I2S3_DO"), + MTK_FUNCTION(4, "I2S1_DO"), + MTK_FUNCTION(5, "PWM0"), + MTK_FUNCTION(6, "I2S2_DI"), + MTK_FUNCTION(7, "DBG_MON_A26") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "I2S0_LRCK"), + MTK_FUNCTION(2, "PCM1_SYNC"), + MTK_FUNCTION(3, "I2S3_LRCK"), + MTK_FUNCTION(4, "I2S1_LRCK"), + MTK_FUNCTION(5, "PWM3"), + MTK_FUNCTION(6, "I2S2_LRCK"), + MTK_FUNCTION(7, "DBG_MON_A27") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "I2S0_BCK"), + MTK_FUNCTION(2, "PCM1_CLK_1"), + MTK_FUNCTION(3, "I2S3_BCK"), + MTK_FUNCTION(4, "I2S1_BCK"), + MTK_FUNCTION(5, "PWM4"), + MTK_FUNCTION(6, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_A28") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "KROW0"), + MTK_FUNCTION(3, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(4, "CORESONIC_SWCK"), + MTK_FUNCTION(5, "C2K_TCK"), + MTK_FUNCTION(7, "C2K_DM_EINT1") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "KROW1"), + MTK_FUNCTION(3, "CONN_MCU_TRST_B"), + MTK_FUNCTION(4, "CORESONIC_SWD"), + MTK_FUNCTION(5, "C2K_NTRST"), + MTK_FUNCTION(6, "USB_DRVVBUS"), + MTK_FUNCTION(7, "C2K_DM_EINT2") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "KROW2"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(5, "C2K_TDI"), + MTK_FUNCTION(7, "C2K_DM_EINT3") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "KCOL0"), + MTK_FUNCTION(2, "URTS0"), + MTK_FUNCTION(3, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(4, "SCL2"), + MTK_FUNCTION(5, "C2K_TDO"), + MTK_FUNCTION(6, "AUXIF_CLK") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "KCOL1"), + MTK_FUNCTION(2, "UCTS0"), + MTK_FUNCTION(3, "UCTS1"), + MTK_FUNCTION(4, "SDA2"), + MTK_FUNCTION(5, "C2K_TMS"), + MTK_FUNCTION(6, "AUXIF_ST"), + MTK_FUNCTION(7, "DBG_MON_A31") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "KCOL2"), + MTK_FUNCTION(3, "URTS1"), + MTK_FUNCTION(5, "C2K_RTCK"), + MTK_FUNCTION(7, "DBG_MON_A32") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "BPI_BUS5"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS5"), + MTK_FUNCTION(5, "C2K_BPI_BUS5"), + MTK_FUNCTION(7, "DBG_MON_B0") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "BPI_BUS6"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS6"), + MTK_FUNCTION(5, "C2K_BPI_BUS6"), + MTK_FUNCTION(7, "DBG_MON_B1") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "BPI_BUS7"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS7"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(5, "C2K_BPI_BUS7"), + MTK_FUNCTION(7, "DBG_MON_B2") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "BPI_BUS8"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS8"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(5, "C2K_BPI_BUS8"), + MTK_FUNCTION(7, "DBG_MON_B3") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "BPI_BUS9"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS9"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(5, "C2K_BPI_BUS9"), + MTK_FUNCTION(7, "DBG_MON_B4") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "BPI_BUS10"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS10"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(5, "C2K_BPI_BUS10"), + MTK_FUNCTION(7, "DBG_MON_B5") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "BPI_BUS11"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS11"), + MTK_FUNCTION(5, "C2K_BPI_BUS11"), + MTK_FUNCTION(7, "DBG_MON_B6") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "BPI_BUS12"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS12"), + MTK_FUNCTION(5, "C2K_BPI_BUS12"), + MTK_FUNCTION(7, "DBG_MON_B7") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "BPI_BUS13"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS13"), + MTK_FUNCTION(5, "C2K_BPI_BUS13"), + MTK_FUNCTION(7, "DBG_MON_B8") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "BPI_BUS14"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS14"), + MTK_FUNCTION(5, "C2K_BPI_BUS14"), + MTK_FUNCTION(7, "DBG_MON_B9") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "BPI_BUS15"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS15"), + MTK_FUNCTION(5, "C2K_BPI_BUS15"), + MTK_FUNCTION(7, "DBG_MON_B10") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "BPI_BUS16"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS16"), + MTK_FUNCTION(5, "C2K_BPI_BUS16"), + MTK_FUNCTION(7, "DBG_MON_B11") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(0, 99), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "BPI_BUS17"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS17"), + MTK_FUNCTION(5, "C2K_BPI_BUS17"), + MTK_FUNCTION(7, "DBG_MON_B12") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(0, 100), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "BPI_BUS18"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS18"), + MTK_FUNCTION(5, "C2K_BPI_BUS18"), + MTK_FUNCTION(7, "DBG_MON_B13") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(0, 101), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "BPI_BUS19"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS19"), + MTK_FUNCTION(5, "C2K_BPI_BUS19"), + MTK_FUNCTION(7, "DBG_MON_B14") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(0, 102), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "BPI_BUS20"), + MTK_FUNCTION(2, "LTE_C2K_BPI_BUS20"), + MTK_FUNCTION(5, "C2K_BPI_BUS20"), + MTK_FUNCTION(7, "DBG_MON_B15") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "C2K_TXBPI"), + MTK_FUNCTION(7, "DBG_MON_B16") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(0, 104), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "RFIC1_BSI_EN"), + MTK_FUNCTION(5, "C2K_RX_BSI_EN"), + MTK_FUNCTION(7, "DBG_MON_B17") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(0, 105), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "RFIC1_BSI_CK"), + MTK_FUNCTION(5, "C2K_RX_BSI_CLK"), + MTK_FUNCTION(7, "DBG_MON_B18") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "RFIC1_BSI_D0"), + MTK_FUNCTION(5, "C2K_RX_BSI_DATA"), + MTK_FUNCTION(7, "DBG_MON_B19") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "RFIC1_BSI_D1"), + MTK_FUNCTION(5, "C2K_TX_BSI_EN"), + MTK_FUNCTION(7, "DBG_MON_B20") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "RFIC1_BSI_D2"), + MTK_FUNCTION(5, "C2K_TX_BSI_CLK"), + MTK_FUNCTION(7, "DBG_MON_B21") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(5, "C2K_TX_BSI_DATA"), + MTK_FUNCTION(7, "DBG_MON_B22") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "RFIC0_BSI_EN"), + MTK_FUNCTION(4, "SPM_BSI_EN"), + MTK_FUNCTION(7, "DBG_MON_B23") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "RFIC0_BSI_CK"), + MTK_FUNCTION(4, "SPM_BSI_CLK"), + MTK_FUNCTION(7, "DBG_MON_B24") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "RFIC0_BSI_D2"), + MTK_FUNCTION(4, "SPM_BSI_D2"), + MTK_FUNCTION(7, "DBG_MON_B25") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, 113), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "RFIC0_BSI_D1"), + MTK_FUNCTION(4, "SPM_BSI_D1"), + MTK_FUNCTION(7, "DBG_MON_B26") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, 114), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "RFIC0_BSI_D0"), + MTK_FUNCTION(4, "SPM_BSI_D0"), + MTK_FUNCTION(7, "DBG_MON_B27") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, 115), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "AUXIN0") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, 116), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "AUXIN1") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(0, 117), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "AUXIN2") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(0, 118), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "TXBPI") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(0, 119), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "BPI_BUS0"), + MTK_FUNCTION(7, "DBG_MON_B28") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(0, 120), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "BPI_BUS1"), + MTK_FUNCTION(7, "DBG_MON_B29") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(0, 121), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "BPI_BUS2"), + MTK_FUNCTION(7, "DBG_MON_B30") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(0, 122), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "BPI_BUS3"), + MTK_FUNCTION(7, "DBG_MON_B31") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(0, 123), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "BPI_BUS4"), + MTK_FUNCTION(7, "DBG_MON_B32") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(0, 124), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "BPI_BUS21"), + MTK_FUNCTION(5, "DPI_HSYNC1"), + MTK_FUNCTION(6, "KCOL2"), + MTK_FUNCTION(7, "TDD_TXD") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(0, 125), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "BPI_BUS22"), + MTK_FUNCTION(5, "DPI_VSYNC1"), + MTK_FUNCTION(6, "KROW2"), + MTK_FUNCTION(7, "MD_URXD") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(0, 126), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "BPI_BUS23"), + MTK_FUNCTION(5, "DPI_CK1"), + MTK_FUNCTION(6, "I2S2_MCK"), + MTK_FUNCTION(7, "MD_UTXD") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(0, 127), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "BPI_BUS24"), + MTK_FUNCTION(3, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "DPI_DE1"), + MTK_FUNCTION(6, "SRCLKENAI1"), + MTK_FUNCTION(7, "URXD0") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(0, 128), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "BPI_BUS25"), + MTK_FUNCTION(3, "GPS_FRAME_SYNC"), + MTK_FUNCTION(5, "I2S2_DI"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(7, "UTXD0") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(0, 129), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "BPI_BUS26"), + MTK_FUNCTION(2, "DISP_PWM"), + MTK_FUNCTION(5, "I2S2_LRCK"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(7, "LTE_URXD") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(0, 130), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "BPI_BUS27"), + MTK_FUNCTION(5, "I2S2_BCK"), + MTK_FUNCTION(6, "IRTX_OUT"), + MTK_FUNCTION(7, "LTE_UTXD") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(0, 131), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "LTE_PAVM0") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(0, 132), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "LTE_PAVM1") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(0, 133), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "MIPI1_SCLK") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(0, 134), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "MIPI1_SDATA") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(0, 135), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "MIPI0_SCLK") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(0, 136), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "MIPI0_SDATA") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(0, 137), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(0, 138), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "PWRAP_SPIDO"), + MTK_FUNCTION(2, "PWRAP_SPIDI") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(0, 139), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "PWRAP_SPIDI"), + MTK_FUNCTION(2, "PWRAP_SPIDO") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(0, 140), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(3, "LTE_MD32_JTAG_TRST"), + MTK_FUNCTION(4, "TDD_TRSTN"), + MTK_FUNCTION(5, "DM_JTINTP") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(0, 141), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "PWRAP_SPICK_I") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(0, 142), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "PWRAP_SPICS_B_I") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(0, 143), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "AUD_CLK_MOSI") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(0, 144), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "AUD_DAT_MISO"), + MTK_FUNCTION(3, "AUD_DAT_MOSI") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(0, 145), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "AUD_DAT_MOSI"), + MTK_FUNCTION(3, "AUD_DAT_MISO") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(0, 146), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "LCM_RST") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(0, 147), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "DSI_TE") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(0, 148), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "SRCLKENA") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(0, 149), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(0, 150), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "TDP0") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(0, 151), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "TDN0") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(0, 152), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "TDP1") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(0, 153), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "TDN1") + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(0, 154), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "TCP") + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(0, 155), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "TCN") + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(0, 156), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "TDP2") + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(0, 157), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "TDN2") + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(0, 158), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "TDP3") + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(0, 159), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "TDN3") + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(0, 160), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "MD_SIM2_SCLK"), + MTK_FUNCTION(2, "MD_SIM1_SCLK"), + MTK_FUNCTION(3, "UIM0_CLK"), + MTK_FUNCTION(4, "UIM1_CLK") + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(0, 161), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "MD_SIM2_SRST"), + MTK_FUNCTION(2, "MD_SIM1_SRST"), + MTK_FUNCTION(3, "UIM0_RST"), + MTK_FUNCTION(4, "UIM1_RST") + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(0, 162), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "MD_SIM2_SDAT"), + MTK_FUNCTION(2, "MD_SIM1_SDAT"), + MTK_FUNCTION(3, "UIM0_IO"), + MTK_FUNCTION(4, "UIM1_IO") + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(0, 163), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "MD_SIM1_SCLK"), + MTK_FUNCTION(2, "MD_SIM2_SCLK"), + MTK_FUNCTION(3, "UIM1_CLK"), + MTK_FUNCTION(4, "UIM0_CLK") + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(0, 164), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "MD_SIM1_SRST"), + MTK_FUNCTION(2, "MD_SIM2_SRST"), + MTK_FUNCTION(3, "UIM1_RST"), + MTK_FUNCTION(4, "UIM0_RST") + ), + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(0, 165), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "MD_SIM1_SDAT"), + MTK_FUNCTION(2, "MD_SIM2_SDAT"), + MTK_FUNCTION(3, "UIM1_IO"), + MTK_FUNCTION(4, "UIM0_IO") + ), + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(0, 166), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "LTE_MD32_JTAG_TMS"), + MTK_FUNCTION(3, "C2K_TMS"), + MTK_FUNCTION(4, "TDD_TMS"), + MTK_FUNCTION(5, "CONN_DSP_JMS"), + MTK_FUNCTION(6, "JTMS"), + MTK_FUNCTION(7, "CONN_MCU_AICE_TMSC") + ), + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(0, 167), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "LTE_MD32_JTAG_TCK"), + MTK_FUNCTION(3, "C2K_TCK"), + MTK_FUNCTION(4, "TDD_TCK"), + MTK_FUNCTION(5, "CONN_DSP_JCK"), + MTK_FUNCTION(6, "JTCK"), + MTK_FUNCTION(7, "CONN_MCU_AICE_TCKC") + ), + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(0, 168), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "LTE_MD32_JTAG_TDI"), + MTK_FUNCTION(3, "C2K_TDI"), + MTK_FUNCTION(4, "TDD_TDI"), + MTK_FUNCTION(5, "CONN_DSP_JDI"), + MTK_FUNCTION(6, "JTDI") + ), + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(0, 169), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "LTE_MD32_JTAG_TDO"), + MTK_FUNCTION(3, "C2K_TDO"), + MTK_FUNCTION(4, "TDD_TDO"), + MTK_FUNCTION(5, "CONN_DSP_JDO"), + MTK_FUNCTION(6, "JTDO") + ), + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(0, 170), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "LTE_MD32_JTAG_TRST"), + MTK_FUNCTION(3, "C2K_NTRST"), + MTK_FUNCTION(4, "TDD_TRSTN"), + MTK_FUNCTION(5, "CONN_DSP_JINTP"), + MTK_FUNCTION(6, "DM_JTINTP") + ), + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(0, 171), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(3, "C2K_RTCK") + ), + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(0, 172), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "MSDC0_CMD") + ), + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(0, 173), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "MSDC0_DSL") + ), + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(0, 174), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "MSDC0_CLK") + ), + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(0, 175), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "MSDC0_DAT0") + ), + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(0, 176), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "MSDC0_DAT1") + ), + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(0, 177), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "MSDC0_DAT2") + ), + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(0, 178), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "MSDC0_DAT3") + ), + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(0, 179), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "MSDC0_DAT4") + ), + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(0, 180), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "MSDC0_DAT5") + ), + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(0, 181), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "MSDC0_DAT6") + ), + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(0, 182), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "MSDC0_DAT7") + ), + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(0, 183), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "MSDC0_RSTB") + ), + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(0, 184), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "F2W_DATA"), + MTK_FUNCTION(2, "MRG_CLK"), + MTK_FUNCTION(3, "C2K_DM_EINT2"), + MTK_FUNCTION(4, "PCM0_CLK") + ), + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(0, 185), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO185"), + MTK_FUNCTION(1, "F2W_CK"), + MTK_FUNCTION(2, "MRG_DI"), + MTK_FUNCTION(3, "C2K_DM_EINT3"), + MTK_FUNCTION(4, "PCM0_DI") + ), + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(0, 186), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO186"), + MTK_FUNCTION(1, "WB_RSTB"), + MTK_FUNCTION(4, "URXD3"), + MTK_FUNCTION(5, "UTXD3") + ), + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(0, 187), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO187"), + MTK_FUNCTION(1, "WB_SCLK"), + MTK_FUNCTION(2, "MRG_DO"), + MTK_FUNCTION(4, "PCM0_DO") + ), + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(0, 188), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO188"), + MTK_FUNCTION(1, "WB_SDATA"), + MTK_FUNCTION(2, "MRG_SYNC"), + MTK_FUNCTION(4, "PCM0_SYNC") + ), + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(0, 189), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO189"), + MTK_FUNCTION(1, "WB_SEN"), + MTK_FUNCTION(4, "UTXD3"), + MTK_FUNCTION(5, "URXD3") + ), + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(0, 190), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO190"), + MTK_FUNCTION(1, "GPS_RXQN") + ), + MTK_PIN( + 191, "GPIO191", + MTK_EINT_FUNCTION(0, 191), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO191"), + MTK_FUNCTION(1, "GPS_RXQP") + ), + MTK_PIN( + 192, "GPIO192", + MTK_EINT_FUNCTION(0, 192), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO192"), + MTK_FUNCTION(1, "GPS_RXIN") + ), + MTK_PIN( + 193, "GPIO193", + MTK_EINT_FUNCTION(0, 193), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO193"), + MTK_FUNCTION(1, "GPS_RXIP") + ), + MTK_PIN( + 194, "GPIO194", + MTK_EINT_FUNCTION(0, 194), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO194"), + MTK_FUNCTION(1, "WB_RXQN") + ), + MTK_PIN( + 195, "GPIO195", + MTK_EINT_FUNCTION(0, 195), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO195"), + MTK_FUNCTION(1, "WB_RXQP") + ), + MTK_PIN( + 196, "GPIO196", + MTK_EINT_FUNCTION(0, 196), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO196"), + MTK_FUNCTION(1, "WB_RXIN") + ), + MTK_PIN( + 197, "GPIO197", + MTK_EINT_FUNCTION(0, 197), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO197"), + MTK_FUNCTION(1, "WB_RXIP") + ), + MTK_PIN( + 198, "GPIO198", + MTK_EINT_FUNCTION(0, 198), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 199, "GPIO199", + MTK_EINT_FUNCTION(0, 199), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 200, "GPIO200", + MTK_EINT_FUNCTION(0, 200), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 201, "GPIO201", + MTK_EINT_FUNCTION(0, 201), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 202, "GPIO202", + MTK_EINT_FUNCTION(0, 202), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 203, "GPIO203", + MTK_EINT_FUNCTION(0, 203), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 204, "GPIO204", + MTK_EINT_FUNCTION(0, 204), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 205, "GPIO205", + MTK_EINT_FUNCTION(0, 205), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 206, "GPIO206", + MTK_EINT_FUNCTION(0, 206), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 207, "GPIO207", + MTK_EINT_FUNCTION(0, 207), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 208, "GPIO208", + MTK_EINT_FUNCTION(0, 208), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 209, "GPIO209", + MTK_EINT_FUNCTION(0, 209), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 210, "GPIO210", + MTK_EINT_FUNCTION(0, 210), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 211, "GPIO211", + MTK_EINT_FUNCTION(0, 211), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 212, "GPIO212", + MTK_EINT_FUNCTION(0, 212), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), +}; + +#endif From 4f0dbdbdb3ad122e8bbfb1d722fd584bac7124db Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sun, 4 Oct 2026 12:36:47 -0700 Subject: [PATCH 103/106] dt-bindings: pinctrl: brcm,nsp-gpio: Convert to DT schema The brcm,nsp-gpio-a compatible used by the NSP GPIO controller was only documented in the legacy text binding, so dtbs_check reported "failed to match any schema" for the gpio@20 node in bcm-nsp.dtsi. Convert the text binding to DT schema. Beyond a direct conversion: - Require pin configuration nodes to use a '-pins' suffix and GPIO hogs a '-hog' suffix, as the old example used arbitrary node names. No in-tree DTS has child nodes under this controller, so nothing is affected. - Document slew-rate, which the driver supports but the text binding never listed. - Add #interrupt-cells and gpio-line-names, and make #interrupt-cells depend on interrupt-controller. Assisted-by: LLM Signed-off-by: Rosen Penev Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../bindings/pinctrl/brcm,nsp-gpio.txt | 80 ----------- .../bindings/pinctrl/brcm,nsp-gpio.yaml | 130 ++++++++++++++++++ 2 files changed, 130 insertions(+), 80 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt deleted file mode 100644 index 0844168a6dd4..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt +++ /dev/null @@ -1,80 +0,0 @@ -Broadcom Northstar plus (NSP) GPIO/PINCONF Controller - -Required properties: -- compatible: - Must be "brcm,nsp-gpio-a" - -- reg: - Should contain the register physical address and length for each of - GPIO base, IO control registers - -- #gpio-cells: - Must be two. The first cell is the GPIO pin number (within the - controller's pin space) and the second cell is used for the following: - bit[0]: polarity (0 for active high and 1 for active low) - -- gpio-controller: - Specifies that the node is a GPIO controller - -- ngpios: - Number of gpios supported (58x25 supports 32 and 58x23 supports 24) - -Optional properties: -- interrupts: - Interrupt ID - -- interrupt-controller: - Specifies that the node is an interrupt controller - -- gpio-ranges: - Specifies the mapping between gpio controller and pin-controllers pins. - This requires 4 fields in cells defined as - - 1. Phandle of pin-controller. - 2. GPIO base pin offset. - 3 Pin-control base pin offset. - 4. number of gpio pins which are linearly mapped from pin base. - -Supported generic PINCONF properties in child nodes: -- pins: - The list of pins (within the controller's own pin space) that properties - in the node apply to. Pin names are "gpio-" - -- bias-disable: - Disable pin bias - -- bias-pull-up: - Enable internal pull up resistor - -- bias-pull-down: - Enable internal pull down resistor - -- drive-strength: - Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) - -Example: - - gpioa: gpio@18000020 { - compatible = "brcm,nsp-gpio-a"; - reg = <0x18000020 0x100>, - <0x1803f1c4 0x1c>; - #gpio-cells = <2>; - gpio-controller; - ngpios = <32>; - gpio-ranges = <&pinctrl 0 0 31>; - interrupt-controller; - interrupts = ; - - /* Hog a few default settings */ - pinctrl-names = "default"; - pinctrl-0 = <&led>; - led: led { - pins = "gpio-1"; - bias-pull-up; - }; - - pwr: pwr { - gpio-hog; - gpios = <3 1>; - output-high; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.yaml new file mode 100644 index 000000000000..e32b2cde0f17 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,nsp-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Northstar Plus (NSP) GPIO/PINCONF Controller + +maintainers: + - Ray Jui + - Scott Branden + +description: | + The chipCommonA GPIO block also provides generic pin configuration for the + pins it controls: bias, pull up/down, slew rate and drive strength. Pin + configuration is described in '-pins' child nodes, referenced through the + standard pinctrl-0/pinctrl-names properties. Child nodes named '*-hog' are + treated as GPIO hogs. + +properties: + compatible: + const: brcm,nsp-gpio-a + + reg: + items: + - description: GPIO base registers + - description: IO control registers + + "#gpio-cells": + const: 2 + description: | + The first cell is the GPIO pin number (within the controller's pin + space) and the second cell is used for the following: + bit[0]: polarity (0 for active high and 1 for active low) + + gpio-controller: true + + ngpios: + description: Number of GPIOs supported (58x25 supports 32 and 58x23 supports 24) + maximum: 32 + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + + interrupt-controller: true + + gpio-ranges: true + + gpio-line-names: true + +required: + - compatible + - reg + - "#gpio-cells" + - gpio-controller + - ngpios + +dependencies: + interrupt-controller: ['#interrupt-cells'] + +patternProperties: + '-pins$': + type: object + $ref: pincfg-node.yaml# + + properties: + pins: + $ref: /schemas/types.yaml#/definitions/string-array + items: + pattern: '^gpio-' + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + + drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ] + + slew-rate: + description: 0 disables and 1 enables slew rate control + enum: [ 0, 1 ] + + required: + - pins + + additionalProperties: false + + '-hog(-[0-9]+)?$': + type: object + required: + - gpio-hog + +additionalProperties: false + +examples: + - | + #include + + gpio@18000020 { + compatible = "brcm,nsp-gpio-a"; + reg = <0x18000020 0x100>, + <0x1803f1c4 0x1c>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <32>; + gpio-ranges = <&pinctrl 0 0 31>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led_pins: led-pins { + pins = "gpio-1"; + bias-pull-up; + drive-strength = <16>; + }; + + /* GPIO hog */ + pwr-hog { + gpio-hog; + gpios = <3 1>; + output-high; + }; + }; From 54c66b5e47a9b10cbf4a1efe9b01301b7ffee205 Mon Sep 17 00:00:00 2001 From: Ma Ke Date: Sun, 11 Oct 2026 14:17:22 +0800 Subject: [PATCH 104/106] pinctrl: stm32: Fix fwnode reference leak in stm32_gpiolib_register_bank() stm32_gpiolib_register_bank() walks the "gpio-ranges" property with fwnode_property_get_reference_args(). As documented in drivers/base/property.c: * The caller is responsible for calling fwnode_handle_put() on the * returned @args->fwnode pointer. The returned reference is never put. The function calls the helper twice, once directly and then repeatedly in a while loop, and each call overwrites args, so only the last reference is even reachable and all the earlier ones are leaked for good. Put the reference as soon as args.args[] has been consumed, both for the initial call and for every iteration of the loop. Found by code review. Cc: stable@vger.kernel.org Fixes: bb949ed9b16b ("pinctrl: stm32: Switch to use for_each_gpiochip_node() helper") Signed-off-by: Ma Ke Reviewed-by: Antonio Borneo Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 587dbf1512dc..6ebb8ea260d1 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -1666,8 +1666,12 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode /* get the last defined gpio line (offset + nb of pins) */ npins = args.args[0] + args.args[2]; - while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args)) + fwnode_handle_put(args.fwnode); + + while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args)) { npins = max(npins, (int)(args.args[0] + args.args[2])); + fwnode_handle_put(args.fwnode); + } } else { bank_nr = pctl->nbanks; bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; From 544b3f8042dd7c18baa48dcb1a393ff8b6742322 Mon Sep 17 00:00:00 2001 From: Ju Nan Date: Thu, 15 Oct 2026 00:09:17 +0800 Subject: [PATCH 105/106] pinctrl: stm32: Fix the unit of the hwspinlock timeout HWSPNLCK_TIMEOUT is passed to hwspin_lock_timeout_in_atomic(), whose timeout argument is in milliseconds, not microseconds: atomic_delay += HWSPINLOCK_RETRY_DELAY_US; if (atomic_delay > to * 1000) return -ETIMEDOUT; The hwspinlock core documents this explicitly: If the mode is HWLOCK_IN_ATOMIC (called from an atomic context) the timeout is handled with busy-waiting delays, hence shall not exceed few msecs. Fixes: 290a9f937e5a ("pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() API") Signed-off-by: Ju Nan Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 6ebb8ea260d1..241684cd383b 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -87,7 +87,7 @@ #define gpio_range_to_bank(chip) \ container_of(chip, struct stm32_gpio_bank, range) -#define HWSPNLCK_TIMEOUT 1000 /* usec */ +#define HWSPNLCK_TIMEOUT_MS 1 static const char * const stm32_gpio_functions[] = { "gpio", "af0", "af1", @@ -609,7 +609,7 @@ static int stm32_gpio_domain_activate(struct irq_domain *d, if (pctl->hwlock) { ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, - HWSPNLCK_TIMEOUT); + HWSPNLCK_TIMEOUT_MS); if (ret) { dev_err(pctl->dev, "Can't get hwspinlock\n"); return ret; @@ -946,7 +946,7 @@ static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, if (pctl->hwlock) { err = hwspin_lock_timeout_in_atomic(pctl->hwlock, - HWSPNLCK_TIMEOUT); + HWSPNLCK_TIMEOUT_MS); if (err) { dev_err(pctl->dev, "Can't get hwspinlock\n"); goto unlock; @@ -1089,7 +1089,7 @@ static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, if (pctl->hwlock) { err = hwspin_lock_timeout_in_atomic(pctl->hwlock, - HWSPNLCK_TIMEOUT); + HWSPNLCK_TIMEOUT_MS); if (err) { dev_err(pctl->dev, "Can't get hwspinlock\n"); goto unlock; @@ -1135,7 +1135,7 @@ static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, if (pctl->hwlock) { err = hwspin_lock_timeout_in_atomic(pctl->hwlock, - HWSPNLCK_TIMEOUT); + HWSPNLCK_TIMEOUT_MS); if (err) { dev_err(pctl->dev, "Can't get hwspinlock\n"); goto unlock; @@ -1181,7 +1181,7 @@ static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, if (pctl->hwlock) { err = hwspin_lock_timeout_in_atomic(pctl->hwlock, - HWSPNLCK_TIMEOUT); + HWSPNLCK_TIMEOUT_MS); if (err) { dev_err(pctl->dev, "Can't get hwspinlock\n"); goto unlock; @@ -1242,7 +1242,7 @@ static int stm32_pconf_set_advcfgr(struct stm32_gpio_bank *bank, int offset, u32 spin_lock_irqsave(&bank->lock, flags); if (pctl->hwlock) { - err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT); + err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT_MS); if (err) { dev_err(pctl->dev, "Can't get hwspinlock\n"); goto unlock; @@ -1320,7 +1320,7 @@ stm32_pconf_set_skew_delay(struct stm32_gpio_bank *bank, int offset, u32 delay, spin_lock_irqsave(&bank->lock, flags); if (pctl->hwlock) { - err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT); + err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT_MS); if (err) { dev_err(pctl->dev, "Can't get hwspinlock\n"); goto unlock; From f33a24cc012d34f25bb9942681bd478a1757b806 Mon Sep 17 00:00:00 2001 From: Ju Nan Date: Thu, 15 Oct 2026 00:09:18 +0800 Subject: [PATCH 106/106] pinctrl: stm32: program the EXTI mux from .alloc instead of .activate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit stm32_gpio_domain_activate() writes the EXTI interrupt multiplexer through a regmap obtained from the generic syscon driver. The irq core calls .activate from __setup_irq() with the raw desc->lock held, so this happens in a raw atomic section. regmap-mmio sets fast_io, and syscon does not ask for a raw spinlock, so the regmap is protected by a spinlock_t. On PREEMPT_RT that is a sleeping lock, which must not be taken there. lockdep reports it as soon as a GPIO interrupt is requested: [ BUG: Invalid wait context ] 7.1.13 #7 Not tainted ----------------------------- kworker/u8:1/29 is trying to lock: (syscon:117:(&syscon_config)->lock){....}-{3:3}, at: regmap_lock_spinlock other info that might help us debug this: context-{5:5} 5 locks held by kworker/u8:1/29: #0: ((wq_completion)async){+.+.}-{0:0}, at: process_one_work #1: ((work_completion)(&entry->work)){+.+.}-{0:0}, at: process_one_work #2: (&dev->mutex){....}-{4:4}, at: __device_attach_async_helper #3: (&desc->request_mutex){+.+.}-{4:4}, at: __setup_irq #4: (&irq_desc_lock_class){-...}-{2:2}, at: __setup_irq The driver was already aware of running in atomic context there: it uses the _in_atomic() hwspinlock primitives around the very same access. The syscon lock is the one lock in that section it does not control. Program the mux from .alloc instead, which runs in a sleepable context. That callback already owns this resource: it reserves the mux line in pctl->irqmux_map under irqmux_lock, so writing the value it just claimed is a natural fit, and the value only depends on the bank. Nothing requires the mux to be reprogrammed at interrupt startup time: the domain has no .deactivate, .free() only releases the irqmux_map bit without touching the registers. Keep the access inside the existing irqmux_lock section rather than after it. hwspin_lock_timeout_in_atomic() deliberately skips the local lock that the other hwspinlock modes take, so its caller is responsible for disabling preemption and for excluding other local contexts; every other hwspinlock user in this driver relies on bank->lock for that. irqmux_lock plays the same role here, and it also turns the mux reservation and the mux write into a single critical section. Nesting the regmap spinlock_t inside irqmux_lock, itself a spinlock_t, is what the wait-context checker expects. Note that this bounds the semaphore hold time on !PREEMPT_RT only. On PREEMPT_RT spinlock_t disables neither interrupts nor preemption, so the hardware semaphore can be held across a preemptible section and a coprocessor contending for it may poll for an unbounded time. That is not introduced here: bank->lock is a spinlock_t too, so every existing hwspinlock user in this driver behaves the same way on PREEMPT_RT. Removing that exposure requires the EXTI mux regmap to be raw-spinlock based, which the syscon core does not currently offer, and is left for a separate change. While moving the code, release the mux reservation when the hwspinlock cannot be taken, which the .activate callback had no way of doing. Reported-by: Uwe Kleine-König Closes: https://lore.kernel.org/all/20220202174430.pf37tt6lua2op3gc@pengutronix.de/ Signed-off-by: Ju Nan Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 46 +++++++++++---------------- 1 file changed, 19 insertions(+), 27 deletions(-) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 241684cd383b..98cf9c6f4b59 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -600,30 +600,6 @@ static int stm32_gpio_domain_translate(struct irq_domain *d, return 0; } -static int stm32_gpio_domain_activate(struct irq_domain *d, - struct irq_data *irq_data, bool reserve) -{ - struct stm32_gpio_bank *bank = d->host_data; - struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); - int ret = 0; - - if (pctl->hwlock) { - ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, - HWSPNLCK_TIMEOUT_MS); - if (ret) { - dev_err(pctl->dev, "Can't get hwspinlock\n"); - return ret; - } - } - - regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); - - if (pctl->hwlock) - hwspin_unlock_in_atomic(pctl->hwlock); - - return ret; -} - static int stm32_gpio_domain_alloc(struct irq_domain *d, unsigned int virq, unsigned int nr_irqs, void *data) @@ -645,10 +621,27 @@ static int stm32_gpio_domain_alloc(struct irq_domain *d, if (pctl->irqmux_map & BIT(hwirq)) { dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq); ret = -EBUSY; - } else { - pctl->irqmux_map |= BIT(hwirq); + goto unlock; } + pctl->irqmux_map |= BIT(hwirq); + + if (pctl->hwlock) { + ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, + HWSPNLCK_TIMEOUT_MS); + if (ret) { + dev_err(pctl->dev, "Can't get hwspinlock\n"); + pctl->irqmux_map &= ~BIT(hwirq); + goto unlock; + } + } + + regmap_field_write(pctl->irqmux[hwirq], bank->bank_ioport_nr); + + if (pctl->hwlock) + hwspin_unlock_in_atomic(pctl->hwlock); + +unlock: spin_unlock_irqrestore(&pctl->irqmux_lock, flags); if (ret) return ret; @@ -683,7 +676,6 @@ static const struct irq_domain_ops stm32_gpio_domain_ops = { .translate = stm32_gpio_domain_translate, .alloc = stm32_gpio_domain_alloc, .free = stm32_gpio_domain_free, - .activate = stm32_gpio_domain_activate, }; /* Pinctrl functions */