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Renesas DTS updates for v7.3

Browse Source 
- Add sound support for the RZ/G3E SoC and the RZ/G3E SMARC EVK board,
   - Add more serial and SPI support for the RZ/G3L SoC and the RZ/G3L
     SMARC EVK board,
   - Add SMP support (32x Cortex-A720AE) for the R-Car X5H SoC,
   - Add hwspinlock and mailbox (MFIS) support for the R-Car V4H SoC,
   - Add GPU support for R-Car M3-N-based Salvator-X(S) and ULCB
     development boards,
   - Add SPI and FRAM support for the RZ/N1D SoC and the RZN1D Expansion
     Board,
   - Add PCIe support for the RZ/V2H SoC and the RZ/V2H EVK development
     board,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v7.3-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v7.3

  - Add sound support for the RZ/G3E SoC and the RZ/G3E SMARC EVK board,
  - Add more serial and SPI support for the RZ/G3L SoC and the RZ/G3L
    SMARC EVK board,
  - Add SMP support (32x Cortex-A720AE) for the R-Car X5H SoC,
  - Add hwspinlock and mailbox (MFIS) support for the R-Car V4H SoC,
  - Add GPU support for R-Car M3-N-based Salvator-X(S) and ULCB
    development boards,
  - Add SPI and FRAM support for the RZ/N1D SoC and the RZN1D Expansion
    Board,
  - Add PCIe support for the RZ/V2H SoC and the RZ/V2H EVK development
    board,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v7.3-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (29 commits)
  arm64: dts: renesas: r9a09g047: Fix PCIe dma-ranges memory space code
  arm64: dts: renesas: r9a09g056: Fix PCIe dma-ranges memory space code
  arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable PCIe
  arm64: dts: renesas: r9a09g057: Add PCIe nodes
  ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI-FRAM
  ARM: dts: renesas: r9a06g032: Describe SPI controllers
  arm64: dts: renesas: rzt2h-n2h-evk-common: Add memory nodes
  arm64: dts: renesas: Add soc: labels to soc nodes
  arm64: dts: renesas: r9a09g047e57-smarc: Add DA7212 audio codec support
  arm64: dts: renesas: rzg3e-smarc-som: Add audio pinmux definitions
  arm64: dts: renesas: rzg3e-smarc-som: Add Versa3 clock generator
  arm64: dts: renesas: r9a09g047: Add RZ/G3E Sound support
  arm64: dts: renesas: r8a77965-ulcb: Enable GPU support
  arm64: dts: renesas: r8a77965-salvator-xs: Enable GPU support
  arm64: dts: renesas: r8a77965-salvator-x: Enable GPU support
  ARM: dts: renesas: r8a7740: Add FSI clocks
  arm64: dts: renesas: r9a09g047: Add max-frequency to SDHI nodes
  arm64: dts: renesas: r9a09g047e57-smarc: Drop SW_SER0_PMOD condition for rsci4
  arm64: dts: renesas: r8a779g0: Add MFIS node
  arm64: dts: renesas: r8a78000: Enable application CPU cores via PSCI
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-07-27 10:31:39 +02:00
commit a4bc8e323d
29 changed files with 1461 additions and 112 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/boot/dts/renesas/r8a7740.dtsi
View File

@ -501,7 +501,11 @@ sh_fsi2: sound@fe1f0000 {
compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
reg = <0xfe1f0000 0x400>;
interrupts = <GIC_SPI 9 0x4>;
clocks = <&mstp3_clks R8A7740_CLK_FSI>;
clocks = <&mstp3_clks R8A7740_CLK_FSI>, <&spu_clk>,
<&fsia_clk>, <&fsib_clk>, <&fsiack_clk>,
<&fsibck_clk>;
clock-names = "fck", "spu", "icka", "ickb", "xcka",
"xckb";
power-domains = <&pd_a4mp>;
status = "disabled";
};
@ -722,6 +726,12 @@ vou_clk: vou@e6150088 {
<0>;
#clock-cells = <0>;
};
fsib_clk: fsib@e6150090 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150090 4>;
clocks = <&pllc1_div2_clk>, <&fsibck_clk>, <0>, <0>;
#clock-cells = <0>;
};
stpro_clk: stpro@e615009c {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615009c 4>;

25
arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
View File

@ -53,6 +53,10 @@ led@1 {
};
};
&gpio2 {
status = "okay";
};
&i2c2 {
/* Sensors are different across revisions. All are LM75B compatible */
sensor@49 {
@ -152,6 +156,13 @@ pins_sdio1_clk: pins-sdio1-clk {
drive-strength = <12>;
};
pins_spi1: pins-spi1 {
pinmux = <RZN1_PINMUX(156, RZN1_FUNC_SPI0_M)>,
<RZN1_PINMUX(157, RZN1_FUNC_SPI0_M)>,
<RZN1_PINMUX(158, RZN1_FUNC_SPI0_M)>,
<RZN1_PINMUX(159, RZN1_FUNC_GPIO)>;
};
pins_uart2: pins-uart2 {
pinmux = <RZN1_PINMUX(105, RZN1_FUNC_UART2)>,
<RZN1_PINMUX(106, RZN1_FUNC_UART2)>,
@ -168,6 +179,20 @@ &sdio1 {
status = "okay";
};
&spi1 {
pinctrl-0 = <&pins_spi1>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&gpio2a 31 GPIO_ACTIVE_LOW>;
fram: fram@0 {
compatible = "cypress,fm25", "atmel,at25";
reg = <0>;
spi-max-frequency = <12500000>;
};
};
&switch {
pinctrl-0 = <&pins_eth1>, <&pins_eth2>, <&pins_eth3>, <&pins_eth4>,
<&pins_mdio1>;

84
arch/arm/boot/dts/renesas/r9a06g032.dtsi
View File

@ -563,6 +563,90 @@ gic: interrupt-controller@44101000 {
<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
/* Controller only */
spi1: spi@50005000 {
compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi";
reg = <0x50005000 0x200>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_CLK_SPI0>, <&sysctrl R9A06G032_HCLK_SPI0>;
clock-names = "ssi_clk", "pclk";
power-domains = <&sysctrl>;
num-cs = <4>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
/* Controller only */
spi2: spi@50006000 {
compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi";
reg = <0x50006000 0x200>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_CLK_SPI1>, <&sysctrl R9A06G032_HCLK_SPI1>;
clock-names = "ssi_clk", "pclk";
power-domains = <&sysctrl>;
num-cs = <4>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
/* Controller only */
spi3: spi@50007000 {
compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi";
reg = <0x50007000 0x200>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_CLK_SPI2>, <&sysctrl R9A06G032_HCLK_SPI2>;
clock-names = "ssi_clk", "pclk";
power-domains = <&sysctrl>;
num-cs = <4>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
/* Controller only */
spi4: spi@50008000 {
compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi";
reg = <0x50008000 0x200>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_CLK_SPI3>, <&sysctrl R9A06G032_HCLK_SPI3>;
clock-names = "ssi_clk", "pclk";
power-domains = <&sysctrl>;
num-cs = <4>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
/* Target only */
spi5: spi@50009000 {
compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi";
reg = <0x50009000 0x200>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_CLK_SPI4>, <&sysctrl R9A06G032_HCLK_SPI4>;
clock-names = "ssi_clk", "pclk";
power-domains = <&sysctrl>;
spi-slave;
#address-cells = <0>;
#size-cells = <0>;
status = "disabled";
};
/* Target only */
spi6: spi@5000a000 {
compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi";
reg = <0x5000a000 0x200>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_CLK_SPI5>, <&sysctrl R9A06G032_HCLK_SPI5>;
clock-names = "ssi_clk", "pclk";
power-domains = <&sysctrl>;
spi-slave;
#address-cells = <0>;
#size-cells = <0>;
status = "disabled";
};
/*
* The GPIO mapping to the corresponding pins is not obvious.
* See the hardware documentation for details.

2
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View File

@ -262,7 +262,7 @@ scif_clk: scif {
clock-frequency = <0>;
};
soc {
soc: soc {
compatible = "simple-bus";
bootph-all;

2
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View File

@ -146,7 +146,7 @@ scif_clk: scif {
clock-frequency = <0>;
};
soc {
soc: soc {
compatible = "simple-bus";
bootph-all;

2
arch/arm64/boot/dts/renesas/r8a774e1.dtsi
View File

@ -326,7 +326,7 @@ scif_clk: scif {
clock-frequency = <0>;
};
soc {
soc: soc {
compatible = "simple-bus";
bootph-all;

2
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View File

@ -311,7 +311,7 @@ scif_clk: scif {
clock-frequency = <0>;
};
soc {
soc: soc {
compatible = "simple-bus";
bootph-all;

2
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View File

@ -311,7 +311,7 @@ scif_clk: scif {
clock-frequency = <0>;
};
soc {
soc: soc {
compatible = "simple-bus";
bootph-all;

4
arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
View File

@ -30,3 +30,7 @@ &du {
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&gpu {
status = "okay";
};

4
arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
View File

@ -30,3 +30,7 @@ &du {
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&gpu {
status = "okay";
};

4
arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts
View File

@ -31,3 +31,7 @@ &du {
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&gpu {
status = "okay";
};

2
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View File

@ -182,7 +182,7 @@ scif_clk: scif {
clock-frequency = <0>;
};
soc {
soc: soc {
compatible = "simple-bus";
bootph-all;

2
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View File

@ -91,7 +91,7 @@ scif_clk: scif {
clock-frequency = <0>;
};
soc {
soc: soc {
compatible = "simple-bus";
bootph-all;

2
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View File

@ -120,7 +120,7 @@ scif_clk: scif {
clock-frequency = <0>;
};
soc {
soc: soc {
compatible = "simple-bus";
bootph-all;

2
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View File

@ -85,7 +85,7 @@ scif_clk: scif {
clock-frequency = <0>;
};
soc {
soc: soc {
compatible = "simple-bus";
bootph-all;

17
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
View File

@ -589,6 +589,23 @@ tmu4: timer@ffc00000 {
status = "disabled";
};
mfis: system-controller@e6260000 {
compatible = "renesas,r8a779g0-mfis";
reg = <0 0xe6260000 0 0x10000>;
reg-names = "common";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0e", "ch1e", "ch2e", "ch3e", "ch4e", "ch5e",
"ch6e", "ch7e", "ch8e", "ch9e", "ch10e", "ch11e";
#hwlock-cells = <1>;
#mbox-cells = <2>;
status = "disabled";
};
tsn0: ethernet@e6460000 {
compatible = "renesas,r8a779g0-ethertsn", "renesas,rcar-gen4-ethertsn";
reg = <0 0xe6460000 0 0x7000>,

41
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
View File

@ -107,6 +107,47 @@ tee@8c400000 {
reg = <0x0 0x8c400000 0x0 0x02000000>;
no-map;
};
/* DRAM controller inline ECC areas */
ecc@10cccc0000 {
reg = <0x10 0xcccc0000 0x0 0x33340000>;
no-map;
};
ecc@12cccc0000 {
reg = <0x12 0xcccc0000 0x0 0x33340000>;
no-map;
};
ecc@14cccc0000 {
reg = <0x14 0xcccc0000 0x0 0x33340000>;
no-map;
};
ecc@16cccc0000 {
reg = <0x16 0xcccc0000 0x0 0x33340000>;
no-map;
};
ecc@18cccc0000 {
reg = <0x18 0xcccc0000 0x0 0x33340000>;
no-map;
};
ecc@1a66660000 {
reg = <0x1a 0x66660000 0x0 0x999a0000>;
no-map;
};
ecc@1c66660000 {
reg = <0x1c 0x66660000 0x0 0x999a0000>;
no-map;
};
ecc@1e66660000 {
reg = <0x1e 0x66660000 0x0 0x999a0000>;
no-map;
};
};
};

32
arch/arm64/boot/dts/renesas/r8a78000.dtsi
View File

@ -143,6 +143,7 @@ a720_0: cpu@0 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_0>;
};
@ -150,6 +151,7 @@ a720_1: cpu@100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_1>;
};
@ -157,6 +159,7 @@ a720_2: cpu@200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_2>;
};
@ -164,6 +167,7 @@ a720_3: cpu@300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_3>;
};
@ -171,6 +175,7 @@ a720_4: cpu@10000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10000>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_4>;
};
@ -178,6 +183,7 @@ a720_5: cpu@10100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_5>;
};
@ -185,6 +191,7 @@ a720_6: cpu@10200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_6>;
};
@ -192,6 +199,7 @@ a720_7: cpu@10300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_7>;
};
@ -199,6 +207,7 @@ a720_8: cpu@20000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20000>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_8>;
};
@ -206,6 +215,7 @@ a720_9: cpu@20100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_9>;
};
@ -213,6 +223,7 @@ a720_10: cpu@20200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_10>;
};
@ -220,6 +231,7 @@ a720_11: cpu@20300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_11>;
};
@ -227,6 +239,7 @@ a720_12: cpu@30000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30000>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_12>;
};
@ -234,6 +247,7 @@ a720_13: cpu@30100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_13>;
};
@ -241,6 +255,7 @@ a720_14: cpu@30200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_14>;
};
@ -248,6 +263,7 @@ a720_15: cpu@30300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_15>;
};
@ -255,6 +271,7 @@ a720_16: cpu@40000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40000>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_16>;
};
@ -262,6 +279,7 @@ a720_17: cpu@40100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_17>;
};
@ -269,6 +287,7 @@ a720_18: cpu@40200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_18>;
};
@ -276,6 +295,7 @@ a720_19: cpu@40300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_19>;
};
@ -283,6 +303,7 @@ a720_20: cpu@50000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50000>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_20>;
};
@ -290,6 +311,7 @@ a720_21: cpu@50100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_21>;
};
@ -297,6 +319,7 @@ a720_22: cpu@50200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_22>;
};
@ -304,6 +327,7 @@ a720_23: cpu@50300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_23>;
};
@ -311,6 +335,7 @@ a720_24: cpu@60000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60000>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_24>;
};
@ -318,6 +343,7 @@ a720_25: cpu@60100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_25>;
};
@ -325,6 +351,7 @@ a720_26: cpu@60200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_26>;
};
@ -332,6 +359,7 @@ a720_27: cpu@60300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_27>;
};
@ -339,6 +367,7 @@ a720_28: cpu@70000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70000>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_28>;
};
@ -346,6 +375,7 @@ a720_29: cpu@70100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_29>;
};
@ -353,6 +383,7 @@ a720_30: cpu@70200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_30>;
};
@ -360,6 +391,7 @@ a720_31: cpu@70300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_31>;
};

69
arch/arm64/boot/dts/renesas/r9a08g046.dtsi
View File

@ -358,6 +358,75 @@ i2c3: i2c@10090c00 {
status = "disabled";
};
rspi0: spi@100b0000 {
compatible = "renesas,r9a08g046-rspi";
reg = <0 0x100b0000 0 0x1000>;
interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 442 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 443 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 444 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "idle", "error", "end", "rx", "tx";
clocks = <&cpg CPG_MOD R9A08G046_RSPI0_PCLK>,
<&cpg CPG_MOD R9A08G046_RSPI0_TCLK>;
clock-names = "pclk", "tclk";
resets = <&cpg R9A08G046_RSPI0_PRESETN>,
<&cpg R9A08G046_RSPI0_TRESETN>;
reset-names = "presetn", "tresetn";
dmas = <&dmac 0x26f2>, <&dmac 0x26f1>;
dma-names = "rx", "tx";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rspi1: spi@100e9000 {
compatible = "renesas,r9a08g046-rspi";
reg = <0 0x100e9000 0 0x1000>;
interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 447 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "idle", "error", "end", "rx", "tx";
clocks = <&cpg CPG_MOD R9A08G046_RSPI1_PCLK>,
<&cpg CPG_MOD R9A08G046_RSPI1_TCLK>;
clock-names = "pclk", "tclk";
resets = <&cpg R9A08G046_RSPI1_PRESETN>,
<&cpg R9A08G046_RSPI1_TRESETN>;
reset-names = "presetn", "tresetn";
dmas = <&dmac 0x26f6>, <&dmac 0x26f5>;
dma-names = "rx", "tx";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rspi2: spi@100ea000 {
compatible = "renesas,r9a08g046-rspi";
reg = <0 0x100ea000 0 0x1000>;
interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 452 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 453 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 454 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "idle", "error", "end", "rx", "tx";
clocks = <&cpg CPG_MOD R9A08G046_RSPI2_PCLK>,
<&cpg CPG_MOD R9A08G046_RSPI2_TCLK>;
clock-names = "pclk", "tclk";
resets = <&cpg R9A08G046_RSPI2_PRESETN>,
<&cpg R9A08G046_RSPI2_TRESETN>;
reset-names = "presetn", "tresetn";
dmas = <&dmac 0x26fa>, <&dmac 0x26f9>;
dma-names = "rx", "tx";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rsci0: serial@100b8000 {
compatible = "renesas,r9a08g046-rsci";
reg = <0 0x100b8000 0 0x1000>;

78
arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
View File

@ -13,6 +13,7 @@
#define SW_DPI_EN 0
#define SW_GPIO4 1
#define SW_I3C_EN 0
#define SW_SER0_PMOD 1
#define PMOD_GPIO4 0
#define PMOD_GPIO6 0
@ -37,6 +38,9 @@ / {
aliases {
i2c2 = &i2c2;
i2c3 = &i2c3;
serial0 = &rsci2;
serial1 = &rsci3;
serial2 = &rsci1;
serial3 = &scif0;
};
@ -134,6 +138,38 @@ i2c3_pins: i2c3 {
<RZG3L_PORT_PINMUX(2, 1, 4)>; /* RIIC3_SDA */
};
rsci1_pins: rsci1 {
pinmux = <RZG3L_PORT_PINMUX(D, 4, 5)>, /* RSCI1_RXD_MISO_SCL */
<RZG3L_PORT_PINMUX(D, 5, 5)>, /* RSCI1_TXD_MOSI_SDA */
<RZG3L_PORT_PINMUX(D, 6, 6)>, /* RSCI1_CTS */
<RZG3L_PORT_PINMUX(D, 7, 5)>; /* RSCI1_SS_CTS#_RTS# */
bias-pull-up;
};
rsci2_pins: rsci2 {
pinmux = <RZG3L_PORT_PINMUX(7, 6, 5)>, /* RSCI2_RXD_MISO_SCL */
<RZG3L_PORT_PINMUX(7, 7, 5)>, /* RSCI2_TXD_MOSI_SDA */
<RZG3L_PORT_PINMUX(8, 0, 6)>, /* RSCI2_CTS */
<RZG3L_PORT_PINMUX(8, 1, 5)>; /* RSCI2_SS_CTS#_RTS# */
bias-pull-up;
power-source = <1800>;
};
rsci3_pins: rsci3 {
pinmux = <RZG3L_PORT_PINMUX(8, 2, 5)>, /* RSCI3_RXD_MISO_SCL */
<RZG3L_PORT_PINMUX(8, 3, 5)>; /* RSCI3_TXD_MOSI_SDA */
bias-pull-up;
power-source = <1800>;
};
rspi2_pins: rspi2 {
pinmux = <RZG3L_PORT_PINMUX(6, 0, 2)>, /* RSPI2_MISO */
<RZG3L_PORT_PINMUX(6, 1, 2)>, /* RSPI2_MOSI */
<RZG3L_PORT_PINMUX(6, 2, 2)>, /* RSPI2_SCK */
<RZG3L_PORT_PINMUX(6, 3, 2)>; /* RSPI2_SSLA */
power-source = <1800>;
};
scif0_pins: scif0 {
pins = "SCIF0_TXD", "SCIF0_RXD";
power-source = <1800>;
@ -147,6 +183,48 @@ ssi0_pins: ssi0 {
};
};
#if SW_SER0_PMOD
&rsci1 {
pinctrl-0 = <&rsci1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
#endif
#if !SW_DPI_EN
&rsci2 {
pinctrl-0 = <&rsci2_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
#endif
#if (!SW_DPI_EN)
&rsci3 {
pinctrl-0 = <&rsci3_pins>;
pinctrl-names = "default";
status = "okay";
};
#endif
#if !SW_DPI_EN
&rspi2 {
pinctrl-0 = <&rspi2_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
#endif
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";

525
arch/arm64/boot/dts/renesas/r9a09g047.dtsi
View File

@ -21,6 +21,20 @@ audio_extal_clk: audio-clk {
clock-frequency = <0>;
};
audio_clkb: audio-b-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
audio_clkc: audio-c-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
/*
* The default cluster table is based on the assumption that the PLLCA55 clock
* frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
@ -271,8 +285,10 @@ pinctrl: pinctrl@10410000 {
cpg: clock-controller@10420000 {
compatible = "renesas,r9a09g047-cpg";
reg = <0 0x10420000 0 0x10000>;
clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
clock-names = "audio_extal", "rtxin", "qextal";
clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>,
<&audio_clkb>, <&audio_clkc>;
clock-names = "audio_extal", "rtxin", "qextal",
"audio_clkb", "audio_clkc";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
@ -896,6 +912,506 @@ rsci9: serial@12803000 {
status = "disabled";
};
snd_rzg3e: sound@13c00000 {
compatible = "renesas,r9a09g047-sound";
reg = <0 0x13c00000 0 0x20000>, /* SCU */
<0 0x13c20000 0 0x10000>, /* ADG */
<0 0x13c30000 0 0x1000>, /* SSIU */
<0 0x13c31000 0 0x1f000>, /* SSI */
<0 0x13c50000 0 0x10000>; /* Audio DMAC peri peri */
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 0xf5>,
<&cpg CPG_MOD 0x181>, <&cpg CPG_MOD 0x182>,
<&cpg CPG_MOD 0x183>, <&cpg CPG_MOD 0x184>,
<&cpg CPG_MOD 0x185>, <&cpg CPG_MOD 0x186>,
<&cpg CPG_MOD 0x187>, <&cpg CPG_MOD 0x188>,
<&cpg CPG_MOD 0x189>, <&cpg CPG_MOD 0x18a>,
<&cpg CPG_MOD 0x174>, <&cpg CPG_MOD 0x175>,
<&cpg CPG_MOD 0x176>, <&cpg CPG_MOD 0x177>,
<&cpg CPG_MOD 0x178>, <&cpg CPG_MOD 0x179>,
<&cpg CPG_MOD 0x17a>, <&cpg CPG_MOD 0x17b>,
<&cpg CPG_MOD 0x17c>, <&cpg CPG_MOD 0x17d>,
<&cpg CPG_MOD 0x172>, <&cpg CPG_MOD 0x173>,
<&cpg CPG_MOD 0x172>, <&cpg CPG_MOD 0x173>,
<&cpg CPG_MOD 0x170>, <&cpg CPG_MOD 0x171>,
<&cpg CPG_MOD 0xfb>, <&cpg CPG_MOD 0xfc>,
<&cpg CPG_MOD 0xfd>, <&cpg CPG_MOD 0xfa>,
<&cpg CPG_MOD 0x180>,
<&cpg CPG_MOD 0xf6>, <&cpg CPG_MOD 0xf7>,
<&cpg CPG_MOD 0x17e>,
<&cpg CPG_MOD 0x160>, <&cpg CPG_MOD 0x161>,
<&cpg CPG_MOD 0x162>, <&cpg CPG_MOD 0x163>,
<&cpg CPG_MOD 0x164>, <&cpg CPG_MOD 0x165>,
<&cpg CPG_MOD 0x166>, <&cpg CPG_MOD 0x167>,
<&cpg CPG_MOD 0x168>, <&cpg CPG_MOD 0x169>,
<&cpg CPG_MOD 0xf8>, <&cpg CPG_MOD 0xf9>;
clock-names = "ssi-all",
"ssi-0", "ssi-1",
"ssi-2", "ssi-3",
"ssi-4", "ssi-5",
"ssi-6", "ssi-7",
"ssi-8", "ssi-9",
"src-0", "src-1",
"src-2", "src-3",
"src-4", "src-5",
"src-6", "src-7",
"src-8", "src-9",
"mix-0", "mix-1",
"ctu-0", "ctu-1",
"dvc-0", "dvc-1",
"audio-clka", "audio-clkb",
"audio-clkc", "audio-clki",
"ssif_supply",
"scu", "scu_x2",
"scu_supply",
"adg-ssi-0", "adg-ssi-1",
"adg-ssi-2", "adg-ssi-3",
"adg-ssi-4", "adg-ssi-5",
"adg-ssi-6", "adg-ssi-7",
"adg-ssi-8", "adg-ssi-9",
"audmapp", "adg";
power-domains = <&cpg>;
resets = <&cpg 0xe1>,
<&cpg 0xe2>, <&cpg 0xe3>,
<&cpg 0xe4>, <&cpg 0xe5>,
<&cpg 0xe6>, <&cpg 0xe7>,
<&cpg 0xe8>, <&cpg 0xe9>,
<&cpg 0xea>, <&cpg 0xeb>,
<&cpg 0xec>, <&cpg 0xee>,
<&cpg 0xed>;
reset-names = "ssi-all",
"ssi-0", "ssi-1",
"ssi-2", "ssi-3",
"ssi-4", "ssi-5",
"ssi-6", "ssi-7",
"ssi-8", "ssi-9",
"scu", "adg",
"audmapp";
status = "disabled";
ctu {
ctu00: ctu-0 { };
ctu01: ctu-1 { };
ctu02: ctu-2 { };
ctu03: ctu-3 { };
ctu10: ctu-4 { };
ctu11: ctu-5 { };
ctu12: ctu-6 { };
ctu13: ctu-7 { };
};
dvc {
dvc0: dvc-0 {
dmas = <&dmac0 0x1db3>, <&dmac1 0x1db3>,
<&dmac2 0x1db3>, <&dmac3 0x1db3>,
<&dmac4 0x1db3>;
dma-names = "tx", "tx", "tx", "tx", "tx";
};
dvc1: dvc-1 {
dmas = <&dmac0 0x1db4>, <&dmac1 0x1db4>,
<&dmac2 0x1db4>, <&dmac3 0x1db4>,
<&dmac4 0x1db4>;
dma-names = "tx", "tx", "tx", "tx", "tx";
};
};
mix {
mix0: mix-0 { };
mix1: mix-1 { };
};
src {
src0: src-0 {
interrupts = <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac0 0x1d9f>, <&dmac0 0x1da9>,
<&dmac1 0x1d9f>, <&dmac1 0x1da9>,
<&dmac2 0x1d9f>, <&dmac2 0x1da9>,
<&dmac3 0x1d9f>, <&dmac3 0x1da9>,
<&dmac4 0x1d9f>, <&dmac4 0x1da9>;
dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx",
"rx", "tx";
};
src1: src-1 {
interrupts = <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac0 0x1da0>, <&dmac0 0x1daa>,
<&dmac1 0x1da0>, <&dmac1 0x1daa>,
<&dmac2 0x1da0>, <&dmac2 0x1daa>,
<&dmac3 0x1da0>, <&dmac3 0x1daa>,
<&dmac4 0x1da0>, <&dmac4 0x1daa>;
dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx",
"rx", "tx";
};
src2: src-2 {
interrupts = <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac0 0x1da1>, <&dmac0 0x1dab>,
<&dmac1 0x1da1>, <&dmac1 0x1dab>,
<&dmac2 0x1da1>, <&dmac2 0x1dab>,
<&dmac3 0x1da1>, <&dmac3 0x1dab>,
<&dmac4 0x1da1>, <&dmac4 0x1dab>;
dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx",
"rx", "tx";
};
src3: src-3 {
interrupts = <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac0 0x1da2>, <&dmac0 0x1dac>,
<&dmac1 0x1da2>, <&dmac1 0x1dac>,
<&dmac2 0x1da2>, <&dmac2 0x1dac>,
<&dmac3 0x1da2>, <&dmac3 0x1dac>,
<&dmac4 0x1da2>, <&dmac4 0x1dac>;
dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx",
"rx", "tx";
};
src4: src-4 {
interrupts = <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac0 0x1da3>, <&dmac0 0x1dad>,
<&dmac1 0x1da3>, <&dmac1 0x1dad>,
<&dmac2 0x1da3>, <&dmac2 0x1dad>,
<&dmac3 0x1da3>, <&dmac3 0x1dad>,
<&dmac4 0x1da3>, <&dmac4 0x1dad>;
dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx",
"rx", "tx";
};
src5: src-5 {
interrupts = <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac0 0x1da4>, <&dmac0 0x1dae>,
<&dmac1 0x1da4>, <&dmac1 0x1dae>,
<&dmac2 0x1da4>, <&dmac2 0x1dae>,
<&dmac3 0x1da4>, <&dmac3 0x1dae>,
<&dmac4 0x1da4>, <&dmac4 0x1dae>;
dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx",
"rx", "tx";
};
src6: src-6 {
interrupts = <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac0 0x1da5>, <&dmac0 0x1daf>,
<&dmac1 0x1da5>, <&dmac1 0x1daf>,
<&dmac2 0x1da5>, <&dmac2 0x1daf>,
<&dmac3 0x1da5>, <&dmac3 0x1daf>,
<&dmac4 0x1da5>, <&dmac4 0x1daf>;
dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx",
"rx", "tx";
};
src7: src-7 {
interrupts = <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac0 0x1da6>, <&dmac0 0x1db0>,
<&dmac1 0x1da6>, <&dmac1 0x1db0>,
<&dmac2 0x1da6>, <&dmac2 0x1db0>,
<&dmac3 0x1da6>, <&dmac3 0x1db0>,
<&dmac4 0x1da6>, <&dmac4 0x1db0>;
dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx",
"rx", "tx";
};
src8: src-8 {
interrupts = <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac0 0x1da7>, <&dmac0 0x1db1>,
<&dmac1 0x1da7>, <&dmac1 0x1db1>,
<&dmac2 0x1da7>, <&dmac2 0x1db1>,
<&dmac3 0x1da7>, <&dmac3 0x1db1>,
<&dmac4 0x1da7>, <&dmac4 0x1db1>;
dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx",
"rx", "tx";
};
src9: src-9 {
interrupts = <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac0 0x1da8>, <&dmac0 0x1db2>,
<&dmac1 0x1da8>, <&dmac1 0x1db2>,
<&dmac2 0x1da8>, <&dmac2 0x1db2>,
<&dmac3 0x1da8>, <&dmac3 0x1db2>,
<&dmac4 0x1da8>, <&dmac4 0x1db2>;
dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx",
"rx", "tx";
};
};
ssi {
ssi0: ssi-0 {
interrupts = <GIC_SPI 889 IRQ_TYPE_LEVEL_HIGH>;
};
ssi1: ssi-1 {
interrupts = <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
};
ssi2: ssi-2 {
interrupts = <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
};
ssi3: ssi-3 {
interrupts = <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>;
};
ssi4: ssi-4 {
interrupts = <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>;
};
ssi5: ssi-5 {
interrupts = <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>;
};
ssi6: ssi-6 {
interrupts = <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>;
};
ssi7: ssi-7 {
interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
};
ssi8: ssi-8 {
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
};
ssi9: ssi-9 {
interrupts = <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>;
};
};
ssiu {
ssiu00: ssiu-0 {
dmas = <&dmac0 0x1d61>, <&dmac0 0x1d62>,
<&dmac1 0x1d61>, <&dmac1 0x1d62>,
<&dmac2 0x1d61>, <&dmac2 0x1d62>,
<&dmac3 0x1d61>, <&dmac3 0x1d62>,
<&dmac4 0x1d61>, <&dmac4 0x1d62>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu01: ssiu-1 {
dmas = <&dmac0 0x1d63>, <&dmac0 0x1d64>,
<&dmac1 0x1d63>, <&dmac1 0x1d64>,
<&dmac2 0x1d63>, <&dmac2 0x1d64>,
<&dmac3 0x1d63>, <&dmac3 0x1d64>,
<&dmac4 0x1d63>, <&dmac4 0x1d64>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu02: ssiu-2 {
dmas = <&dmac0 0x1d65>, <&dmac0 0x1d66>,
<&dmac1 0x1d65>, <&dmac1 0x1d66>,
<&dmac2 0x1d65>, <&dmac2 0x1d66>,
<&dmac3 0x1d65>, <&dmac3 0x1d66>,
<&dmac4 0x1d65>, <&dmac4 0x1d66>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu03: ssiu-3 {
dmas = <&dmac0 0x1d67>, <&dmac0 0x1d68>,
<&dmac1 0x1d67>, <&dmac1 0x1d68>,
<&dmac2 0x1d67>, <&dmac2 0x1d68>,
<&dmac3 0x1d67>, <&dmac3 0x1d68>,
<&dmac4 0x1d67>, <&dmac4 0x1d68>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu10: ssiu-4 {
dmas = <&dmac0 0x1d69>, <&dmac0 0x1d6a>,
<&dmac1 0x1d69>, <&dmac1 0x1d6a>,
<&dmac2 0x1d69>, <&dmac2 0x1d6a>,
<&dmac3 0x1d69>, <&dmac3 0x1d6a>,
<&dmac4 0x1d69>, <&dmac4 0x1d6a>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu11: ssiu-5 {
dmas = <&dmac0 0x1d6b>, <&dmac0 0x1d6c>,
<&dmac1 0x1d6b>, <&dmac1 0x1d6c>,
<&dmac2 0x1d6b>, <&dmac2 0x1d6c>,
<&dmac3 0x1d6b>, <&dmac3 0x1d6c>,
<&dmac4 0x1d6b>, <&dmac4 0x1d6c>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu12: ssiu-6 {
dmas = <&dmac0 0x1d6d>, <&dmac0 0x1d6e>,
<&dmac1 0x1d6d>, <&dmac1 0x1d6e>,
<&dmac2 0x1d6d>, <&dmac2 0x1d6e>,
<&dmac3 0x1d6d>, <&dmac3 0x1d6e>,
<&dmac4 0x1d6d>, <&dmac4 0x1d6e>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu13: ssiu-7 {
dmas = <&dmac0 0x1d6f>, <&dmac0 0x1d70>,
<&dmac1 0x1d6f>, <&dmac1 0x1d70>,
<&dmac2 0x1d6f>, <&dmac2 0x1d70>,
<&dmac3 0x1d6f>, <&dmac3 0x1d70>,
<&dmac4 0x1d6f>, <&dmac4 0x1d70>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu20: ssiu-8 {
dmas = <&dmac0 0x1d71>, <&dmac0 0x1d72>,
<&dmac1 0x1d71>, <&dmac1 0x1d72>,
<&dmac2 0x1d71>, <&dmac2 0x1d72>,
<&dmac3 0x1d71>, <&dmac3 0x1d72>,
<&dmac4 0x1d71>, <&dmac4 0x1d72>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu21: ssiu-9 {
dmas = <&dmac0 0x1d73>, <&dmac0 0x1d74>,
<&dmac1 0x1d73>, <&dmac1 0x1d74>,
<&dmac2 0x1d73>, <&dmac2 0x1d74>,
<&dmac3 0x1d73>, <&dmac3 0x1d74>,
<&dmac4 0x1d73>, <&dmac4 0x1d74>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu22: ssiu-10 {
dmas = <&dmac0 0x1d75>, <&dmac0 0x1d76>,
<&dmac1 0x1d75>, <&dmac1 0x1d76>,
<&dmac2 0x1d75>, <&dmac2 0x1d76>,
<&dmac3 0x1d75>, <&dmac3 0x1d76>,
<&dmac4 0x1d75>, <&dmac4 0x1d76>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu23: ssiu-11 {
dmas = <&dmac0 0x1d77>, <&dmac0 0x1d78>,
<&dmac1 0x1d77>, <&dmac1 0x1d78>,
<&dmac2 0x1d77>, <&dmac2 0x1d78>,
<&dmac3 0x1d77>, <&dmac3 0x1d78>,
<&dmac4 0x1d77>, <&dmac4 0x1d78>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu30: ssiu-12 {
dmas = <&dmac0 0x1d79>, <&dmac0 0x1d7a>,
<&dmac1 0x1d79>, <&dmac1 0x1d7a>,
<&dmac2 0x1d79>, <&dmac2 0x1d7a>,
<&dmac3 0x1d79>, <&dmac3 0x1d7a>,
<&dmac4 0x1d79>, <&dmac4 0x1d7a>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu31: ssiu-13 {
dmas = <&dmac0 0x1d7b>, <&dmac0 0x1d7c>,
<&dmac1 0x1d7b>, <&dmac1 0x1d7c>,
<&dmac2 0x1d7b>, <&dmac2 0x1d7c>,
<&dmac3 0x1d7b>, <&dmac3 0x1d7c>,
<&dmac4 0x1d7b>, <&dmac4 0x1d7c>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu32: ssiu-14 {
dmas = <&dmac0 0x1d7d>, <&dmac0 0x1d7e>,
<&dmac1 0x1d7d>, <&dmac1 0x1d7e>,
<&dmac2 0x1d7d>, <&dmac2 0x1d7e>,
<&dmac3 0x1d7d>, <&dmac3 0x1d7e>,
<&dmac4 0x1d7d>, <&dmac4 0x1d7e>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu33: ssiu-15 {
dmas = <&dmac0 0x1d7f>, <&dmac0 0x1d80>,
<&dmac1 0x1d7f>, <&dmac1 0x1d80>,
<&dmac2 0x1d7f>, <&dmac2 0x1d80>,
<&dmac3 0x1d7f>, <&dmac3 0x1d80>,
<&dmac4 0x1d7f>, <&dmac4 0x1d80>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu40: ssiu-16 {
dmas = <&dmac0 0x1d81>, <&dmac0 0x1d82>,
<&dmac1 0x1d81>, <&dmac1 0x1d82>,
<&dmac2 0x1d81>, <&dmac2 0x1d82>,
<&dmac3 0x1d81>, <&dmac3 0x1d82>,
<&dmac4 0x1d81>, <&dmac4 0x1d82>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu41: ssiu-17 {
dmas = <&dmac0 0x1d83>, <&dmac0 0x1d84>,
<&dmac1 0x1d83>, <&dmac1 0x1d84>,
<&dmac2 0x1d83>, <&dmac2 0x1d84>,
<&dmac3 0x1d83>, <&dmac3 0x1d84>,
<&dmac4 0x1d83>, <&dmac4 0x1d84>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu42: ssiu-18 {
dmas = <&dmac0 0x1d85>, <&dmac0 0x1d86>,
<&dmac1 0x1d85>, <&dmac1 0x1d86>,
<&dmac2 0x1d85>, <&dmac2 0x1d86>,
<&dmac3 0x1d85>, <&dmac3 0x1d86>,
<&dmac4 0x1d85>, <&dmac4 0x1d86>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu43: ssiu-19 {
dmas = <&dmac0 0x1d87>, <&dmac0 0x1d88>,
<&dmac1 0x1d87>, <&dmac1 0x1d88>,
<&dmac2 0x1d87>, <&dmac2 0x1d88>,
<&dmac3 0x1d87>, <&dmac3 0x1d88>,
<&dmac4 0x1d87>, <&dmac4 0x1d88>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu50: ssiu-20 {
dmas = <&dmac0 0x1d89>, <&dmac0 0x1d8a>,
<&dmac1 0x1d89>, <&dmac1 0x1d8a>,
<&dmac2 0x1d89>, <&dmac2 0x1d8a>,
<&dmac3 0x1d89>, <&dmac3 0x1d8a>,
<&dmac4 0x1d89>, <&dmac4 0x1d8a>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu60: ssiu-21 {
dmas = <&dmac0 0x1d8b>, <&dmac0 0x1d8c>,
<&dmac1 0x1d8b>, <&dmac1 0x1d8c>,
<&dmac2 0x1d8b>, <&dmac2 0x1d8c>,
<&dmac3 0x1d8b>, <&dmac3 0x1d8c>,
<&dmac4 0x1d8b>, <&dmac4 0x1d8c>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu70: ssiu-22 {
dmas = <&dmac0 0x1d8d>, <&dmac0 0x1d8e>,
<&dmac1 0x1d8d>, <&dmac1 0x1d8e>,
<&dmac2 0x1d8d>, <&dmac2 0x1d8e>,
<&dmac3 0x1d8d>, <&dmac3 0x1d8e>,
<&dmac4 0x1d8d>, <&dmac4 0x1d8e>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu80: ssiu-23 {
dmas = <&dmac0 0x1d8f>, <&dmac0 0x1d90>,
<&dmac1 0x1d8f>, <&dmac1 0x1d90>,
<&dmac2 0x1d8f>, <&dmac2 0x1d90>,
<&dmac3 0x1d8f>, <&dmac3 0x1d90>,
<&dmac4 0x1d8f>, <&dmac4 0x1d90>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu90: ssiu-24 {
dmas = <&dmac0 0x1d91>, <&dmac0 0x1d92>,
<&dmac1 0x1d91>, <&dmac1 0x1d92>,
<&dmac2 0x1d91>, <&dmac2 0x1d92>,
<&dmac3 0x1d91>, <&dmac3 0x1d92>,
<&dmac4 0x1d91>, <&dmac4 0x1d92>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu91: ssiu-25 {
dmas = <&dmac0 0x1d93>, <&dmac0 0x1d94>,
<&dmac1 0x1d93>, <&dmac1 0x1d94>,
<&dmac2 0x1d93>, <&dmac2 0x1d94>,
<&dmac3 0x1d93>, <&dmac3 0x1d94>,
<&dmac4 0x1d93>, <&dmac4 0x1d94>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu92: ssiu-26 {
dmas = <&dmac0 0x1d95>, <&dmac0 0x1d96>,
<&dmac1 0x1d95>, <&dmac1 0x1d96>,
<&dmac2 0x1d95>, <&dmac2 0x1d96>,
<&dmac3 0x1d95>, <&dmac3 0x1d96>,
<&dmac4 0x1d95>, <&dmac4 0x1d96>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
ssiu93: ssiu-27 {
dmas = <&dmac0 0x1d97>, <&dmac0 0x1d98>,
<&dmac1 0x1d97>, <&dmac1 0x1d98>,
<&dmac2 0x1d97>, <&dmac2 0x1d98>,
<&dmac3 0x1d97>, <&dmac3 0x1d98>,
<&dmac4 0x1d97>, <&dmac4 0x1d98>;
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx",
"tx", "rx";
};
};
};
wdt1: watchdog@14400000 {
compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
reg = <0 0x14400000 0 0x400>;
@ -931,7 +1447,7 @@ pcie: pcie@13400000 {
reg = <0 0x13400000 0 0x10000>;
ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x43000000 4 0x40000000 4 0x40000000 6 0x00000000>;
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 2 0x00000000>;
dma-ranges = <0x43000000 0 0x40000000 0 0x40000000 2 0x00000000>;
bus-range = <0x0 0xff>;
interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>,
@ -1265,6 +1781,7 @@ sdhi0: mmc@15c00000 {
clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>,
<&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>;
clock-names = "core", "clkh", "cd", "aclk";
max-frequency = <200000000>;
resets = <&cpg 0xa7>;
power-domains = <&cpg>;
status = "disabled";
@ -1285,6 +1802,7 @@ sdhi1: mmc@15c10000 {
clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>,
<&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>;
clock-names = "core", "clkh", "cd", "aclk";
max-frequency = <200000000>;
resets = <&cpg 0xa8>;
power-domains = <&cpg>;
status = "disabled";
@ -1305,6 +1823,7 @@ sdhi2: mmc@15c20000 {
clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>,
<&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>;
clock-names = "core", "clkh", "cd", "aclk";
max-frequency = <200000000>;
resets = <&cpg 0xa9>;
power-domains = <&cpg>;
status = "disabled";

114
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
View File

@ -32,6 +32,37 @@
#include "rzg3e-smarc-som.dtsi"
#include "renesas-smarc2.dtsi"
/*
* SSI-DA7212
*
* These commands are required when Playback/Capture
*
* amixer -q cset name='Aux Switch' on
* amixer -q cset name='Mixin Left Aux Left Switch' on
* amixer -q cset name='Mixin Right Aux Right Switch' on
* amixer -q cset name='ADC Switch' on
* amixer -q cset name='Mixout Right Mixin Right Switch' off
* amixer -q cset name='Mixout Left Mixin Left Switch' off
* amixer -q cset name='Headphone Volume' 70%
* amixer -q cset name='Headphone Switch' on
* amixer -q cset name='Mixout Left DAC Left Switch' on
* amixer -q cset name='Mixout Right DAC Right Switch' on
* amixer -q cset name='DAC Left Source MUX' 'DAI Input Left'
* amixer -q cset name='DAC Right Source MUX' 'DAI Input Right'
* amixer -q sset 'Mic 1 Amp Source MUX' 'MIC_P'
* amixer -q sset 'Mic 2 Amp Source MUX' 'MIC_P'
* amixer -q sset 'Mixin Left Mic 1' on
* amixer -q sset 'Mixin Right Mic 2' on
* amixer -q sset 'Mic 1' 90% on
* amixer -q sset 'Mic 2' 90% on
* amixer -q sset 'Lineout' 80% on
* amixer -q set "Headphone" 100% on
*
* When Capture chained with DVC, use this command to amplify sound
* amixer set 'DVC In',0 80%
* For playback, use: amixer set 'DVC Out',0 80%
*/
/ {
model = "Renesas SMARC EVK version 2 based on r9a09g047e57";
compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm",
@ -55,6 +86,22 @@ vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd {
gpios-states = <0>;
states = <3300000 0>, <1800000 1>;
};
sound_card: sound {
compatible = "audio-graph-card";
label = "snd-rzg3e";
dais = <&rsnd_port0>; /* DA7212 */
};
};
&audio_clkb {
clock-frequency = <11289600>;
};
&audio_clkc {
clock-frequency = <12288000>;
};
&canfd {
@ -99,6 +146,35 @@ &i2c0 {
pinctrl-names = "default";
};
&i2c1 {
da7212: codec@1a {
compatible = "dlg,da7212";
#sound-dai-cells = <0>;
reg = <0x1a>;
clocks = <&versa3 1>;
clock-names = "mclk";
dlg,micbias1-lvl = <2500>;
dlg,micbias2-lvl = <2500>;
dlg,dmic-data-sel = "lrise_rfall";
dlg,dmic-samplephase = "between_clkedge";
dlg,dmic-clkrate = <3000000>;
VDDA-supply = <&reg_1p8v>;
VDDSP-supply = <&reg_3p3v>;
VDDMIC-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_1p8v>;
port {
da7212_endpoint: endpoint {
remote-endpoint = <&rsnd_endpoint0>;
mclk-fs = <256>;
};
};
};
};
&keys {
pinctrl-0 = <&nmi_pins>;
pinctrl-names = "default";
@ -237,7 +313,7 @@ &rsci2 {
};
#endif
#if (!SW_LCD_EN) && (SW_SER0_PMOD)
#if !SW_LCD_EN
&rsci4 {
pinctrl-0 = <&rsci4_pins>;
pinctrl-names = "default";
@ -280,6 +356,42 @@ &sdhi1 {
vqmmc-supply = <&vqmmc_sd1_pvdd>;
};
&snd_rzg3e {
pinctrl-0 = <&sound_clk_pins &sound_pins>;
pinctrl-names = "default";
status = "okay";
/* audio_clkout */
#clock-cells = <0>;
clock-frequency = <11289600>;
/* Multi DAI */
#sound-dai-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
rsnd_port0: port@0 {
reg = <0>;
rsnd_endpoint0: endpoint {
remote-endpoint = <&da7212_endpoint>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint0>;
frame-master = <&rsnd_endpoint0>;
playback = <&ssi3>, <&src1>, <&dvc1>;
capture = <&ssi4>, <&src0>, <&dvc0>;
};
};
};
};
&ssi4 {
shared-pin;
};
&usb3_phy {
status = "okay";
};

22
arch/arm64/boot/dts/renesas/r9a09g056.dtsi
View File

@ -39,6 +39,20 @@ audio_extal_clk: audio-clk {
clock-frequency = <0>;
};
audio_clkb: audio-b-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
audio_clkc: audio-c-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
/*
* The default cluster table is based on the assumption that the PLLCA55 clock
* frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
@ -294,8 +308,10 @@ pinctrl: pinctrl@10410000 {
cpg: clock-controller@10420000 {
compatible = "renesas,r9a09g056-cpg";
reg = <0 0x10420000 0 0x10000>;
clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
clock-names = "audio_extal", "rtxin", "qextal";
clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>,
<&audio_clkb>, <&audio_clkc>;
clock-names = "audio_extal", "rtxin", "qextal",
"audio_clkb", "audio_clkc";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
@ -1049,7 +1065,7 @@ pcie: pcie@13400000 {
reg = <0 0x13400000 0 0x10000>;
ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
<0x43000000 4 0x40000000 4 0x40000000 6 0x00000000>;
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 2 0x00000000>;
dma-ranges = <0x43000000 0 0x40000000 0 0x40000000 2 0x00000000>;
bus-range = <0x0 0xff>;
interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>,

160
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
View File

@ -21,6 +21,20 @@ audio_extal_clk: audio-clk {
clock-frequency = <0>;
};
audio_clkb: audio-b-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
audio_clkc: audio-c-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
/*
* The default cluster table is based on the assumption that the PLLCA55 clock
* frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
@ -276,8 +290,10 @@ pinctrl: pinctrl@10410000 {
cpg: clock-controller@10420000 {
compatible = "renesas,r9a09g057-cpg";
reg = <0 0x10420000 0 0x10000>;
clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
clock-names = "audio_extal", "rtxin", "qextal";
clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>,
<&audio_clkb>, <&audio_clkc>;
clock-names = "audio_extal", "rtxin", "qextal",
"audio_clkb", "audio_clkc";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
@ -1025,6 +1041,146 @@ rsci9: serial@12803000 {
status = "disabled";
};
pcie0: pcie@13400000 {
compatible = "renesas,r9a09g057-pcie";
reg = <0 0x13400000 0 0x10000>;
ranges = <0x02000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
<0x43000000 0x4 0x40000000 0x4 0x40000000 0x6 0x00000000>;
dma-ranges = <0x43000000 0x0 0x40000000 0x0 0x40000000 0x4 0x00000000>;
bus-range = <0x0 0xff>;
interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "serr", "serr_cor", "serr_nonfatal",
"serr_fatal", "axi_err", "inta",
"intb", "intc", "intd", "msi",
"link_bandwidth", "pm_pme", "dma",
"pcie_evt", "msg", "all",
"link_equalization_request",
"turn_off_event", "pmu_poweroff",
"d3_event_f0", "d3_event_f1",
"cfg_pmcsr_writeclear_f0",
"cfg_pmcsr_writeclear_f1";
#interrupt-cells = <1>;
interrupt-controller;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie0 0 0 0 0>, /* INTA */
<0 0 0 2 &pcie0 0 0 0 1>, /* INTB */
<0 0 0 3 &pcie0 0 0 0 2>, /* INTC */
<0 0 0 4 &pcie0 0 0 0 3>; /* INTD */
clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>;
clock-names = "aclk", "pmu";
resets = <&cpg 0xb2>;
reset-names = "aresetn";
power-domains = <&cpg>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
num-lanes = <2>;
renesas,sysc = <&sys 0>;
status = "disabled";
pcie_port0: pcie@0,0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
ranges;
device_type = "pci";
vendor-id = <0x1912>;
device-id = <0x003b>;
#address-cells = <3>;
#size-cells = <2>;
};
};
pcie1: pcie@13410000 {
compatible = "renesas,r9a09g057-pcie";
reg = <0 0x13410000 0 0x10000>;
ranges = <0x02000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
<0x43000000 0xa 0x40000000 0xa 0x40000000 0x5 0xc0000000>;
dma-ranges = <0x43000000 0x0 0x40000000 0x0 0x40000000 0x4 0x00000000>;
bus-range = <0x0 0xff>;
interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 826 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 829 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 827 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 828 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "serr", "serr_cor", "serr_nonfatal",
"serr_fatal", "axi_err", "inta",
"intb", "intc", "intd", "msi",
"link_bandwidth", "pm_pme", "dma",
"pcie_evt", "msg", "all",
"link_equalization_request",
"turn_off_event", "pmu_poweroff",
"d3_event_f0", "d3_event_f1",
"cfg_pmcsr_writeclear_f0",
"cfg_pmcsr_writeclear_f1";
#interrupt-cells = <1>;
interrupt-controller;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1 0 0 0 0>, /* INTA */
<0 0 0 2 &pcie1 0 0 0 1>, /* INTB */
<0 0 0 3 &pcie1 0 0 0 2>, /* INTC */
<0 0 0 4 &pcie1 0 0 0 3>; /* INTD */
clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>;
clock-names = "aclk", "pmu";
resets = <&cpg 0xb2>;
reset-names = "aresetn";
power-domains = <&cpg>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
num-lanes = <2>;
renesas,sysc = <&sys 1>;
status = "disabled";
pcie_port1: pcie@0,0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
ranges;
device_type = "pci";
vendor-id = <0x1912>;
device-id = <0x003b>;
#address-cells = <3>;
#size-cells = <2>;
};
};
i2c0: i2c@14400400 {
compatible = "renesas,riic-r9a09g057";
reg = <0 0x14400400 0 0x400>;

18
arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
View File

@ -384,6 +384,18 @@ &ostm7 {
status = "okay";
};
&pcie0 {
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
num-lanes = <4>;
status = "okay";
};
&pcie_port0 {
clocks = <&versa3 5>;
clock-names = "ref";
};
&pinctrl {
eth0_pins: eth0 {
pins = "ET0_TXC_TXCLK";
@ -430,6 +442,12 @@ i2c8_pins: i2c8 {
<RZV2H_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
};
pcie0_pins: pcie0 {
pins = "PCIE0_RSTOUTB";
slew-rate = <0>;
renesas,output-impedance = <2>;
};
scif_pins: scif {
pins = "SCIF_TXD", "SCIF_RXD";
renesas,output-impedance = <1>;

144
arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
View File

@ -256,60 +256,112 @@ can0_pins: can0-pins {
/*
* GMAC1 Pin Configuration:
*
* SW2[8] ON - use pins P33_2-P33_7, P34_0-P34_5, P34_7 and
* P35_0-P35_2 for Ethernet port 3
* SW2[8] ON - use pins P33_2-P33_7 and P34_0-P34_5 for Ethernet port 3
*/
gmac1_pins: gmac1-pins {
pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
<RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD0 */
<RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD1 */
<RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD2 */
<RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD3 */
<RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
<RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
<RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD0 */
<RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD1 */
<RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2 */
<RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3 */
<RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
<RZT2H_PORT_PINMUX(34, 7, 0xf)>, /* ETH3_TXER */
<RZT2H_PORT_PINMUX(35, 0, 0xf)>, /* ETH3_RXER */
<RZT2H_PORT_PINMUX(35, 1, 0xf)>, /* ETH3_CRS */
<RZT2H_PORT_PINMUX(35, 2, 0xf)>, /* ETH3_COL */
<RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
<RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */
<RZT2H_PORT_PINMUX(34, 6, 0x2)>, /* ETH3_REFCLK */
<RZT2H_PORT_PINMUX(27, 2, 0x0)>; /* IRQ3 */
gmac1_pins: gmac1-group {
irq-pins {
pinmux = <RZT2H_PORT_PINMUX(27, 2, 0x0)>; /* IRQ3 */
drive-strength-microamp = <5000>;
slew-rate = <0>;
input-schmitt-disable;
};
md-pins {
pinmux = <RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
<RZT2H_PORT_PINMUX(26, 2, 0x10)>; /* GMAC1_MDIO */
drive-strength-microamp = <5000>;
slew-rate = <0>;
input-schmitt-disable;
};
refclk-pins {
pinmux = <RZT2H_PORT_PINMUX(34, 6, 0x2)>; /* ETH3_REFCLK */
drive-strength-microamp = <5000>;
slew-rate = <1>;
};
rx-pins {
pinmux = <RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
<RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD0 */
<RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD1 */
<RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2 */
<RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3 */
<RZT2H_PORT_PINMUX(34, 5, 0xf)>; /* ETH3_RXDV */
input-schmitt-disable;
};
txclk-pins {
pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>; /* ETH3_TXCLK */
drive-strength-microamp = <11800>;
slew-rate = <1>;
input-schmitt-disable;
};
txd-en-pins {
pinmux = <RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD0 */
<RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD1 */
<RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD2 */
<RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD3 */
<RZT2H_PORT_PINMUX(33, 7, 0xf)>; /* ETH3_TXEN */
drive-strength-microamp = <11800>;
slew-rate = <1>;
};
};
/*
* GMAC2 Pin Configuration:
*
* SW2[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2
* SW2[7] ON - use pins P29_1-P29_7, P30_0-P30_4, and P31_2-P31_5
* for Ethernet port 2
* SW2[7] ON - use pins P29_1-P29_7 and P30_0-P30_4 for Ethernet port 2
*/
gmac2_pins: gmac2-pins {
pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
<RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD0 */
<RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD1 */
<RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD2 */
<RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD3 */
<RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
<RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
<RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD0 */
<RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD1 */
<RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD2 */
<RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD3 */
<RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
<RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
<RZT2H_PORT_PINMUX(31, 3, 0xf)>, /* ETH2_RXER */
<RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
<RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
<RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
<RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */
<RZT2H_PORT_PINMUX(31, 0, 0x2)>, /* ETH2_REFCLK */
<RZT2H_PORT_PINMUX(31, 1, 0x0)>; /* IRQ13 */
gmac2_pins: gmac2-group {
irq-pins {
pinmux = <RZT2H_PORT_PINMUX(31, 1, 0x0)>; /* IRQ13 */
drive-strength-microamp = <5000>;
slew-rate = <0>;
input-schmitt-disable;
};
md-pins {
pinmux = <RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
<RZT2H_PORT_PINMUX(30, 6, 0x10)>; /* GMAC2_MDIO */
drive-strength-microamp = <5000>;
slew-rate = <0>;
input-schmitt-disable;
};
refclk-pins {
pinmux = <RZT2H_PORT_PINMUX(31, 0, 0x2)>; /* ETH2_REFCLK */
drive-strength-microamp = <5000>;
slew-rate = <1>;
};
rx-pins {
pinmux = <RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
<RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD0 */
<RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD1 */
<RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD2 */
<RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD3 */
<RZT2H_PORT_PINMUX(30, 4, 0xf)>; /* ETH2_RXDV */
input-schmitt-disable;
};
txclk-pins {
pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>; /* ETH2_TXCLK */
drive-strength-microamp = <11800>;
slew-rate = <1>;
input-schmitt-disable;
};
txd-en-pins {
pinmux = <RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD0 */
<RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD1 */
<RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD2 */
<RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD3 */
<RZT2H_PORT_PINMUX(29, 6, 0xf)>; /* ETH2_TXEN */
drive-strength-microamp = <11800>;
slew-rate = <1>;
};
};
/*

144
arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
View File

@ -339,63 +339,113 @@ can1_pins: can1-pins {
/*
* GMAC1 Pin Configuration:
*
* DSW5[8] ON - use pins P00_0-P00_2, P33_2-P33_7, P34_0-P34_6
* for Ethernet port 3
* DSW12[1] OFF; DSW12[2] ON - use pin P00_3 for Ethernet port 3
* DSW5[8] ON - use pins P33_2-P33_7 and P34_0-P34_6 for Ethernet port 3
*/
gmac1_pins: gmac1-pins {
pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
<RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD0 */
<RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD0 */
<RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD2 */
<RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD3 */
<RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
<RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
<RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD0 */
<RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD1 */
<RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2 */
<RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3 */
<RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
<RZT2H_PORT_PINMUX(0, 0, 0xf)>, /* ETH3_TXER */
<RZT2H_PORT_PINMUX(0, 1, 0xf)>, /* ETH3_RXER */
<RZT2H_PORT_PINMUX(0, 2, 0xf)>, /* ETH3_CRS */
<RZT2H_PORT_PINMUX(0, 3, 0xf)>, /* ETH3_COL */
<RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
<RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */
<RZT2H_PORT_PINMUX(34, 6, 0x2)>, /* ETH3_REFCLK */
<RZT2H_PORT_PINMUX(17, 3, 0x0)>; /* IRQ15 */
gmac1_pins: gmac1-group {
irq-pins {
pinmux = <RZT2H_PORT_PINMUX(17, 3, 0x0)>; /* IRQ15 */
drive-strength-microamp = <5000>;
slew-rate = <0>;
input-schmitt-disable;
};
md-pins {
pinmux = <RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
<RZT2H_PORT_PINMUX(26, 2, 0x10)>; /* GMAC1_MDIO */
drive-strength-microamp = <5000>;
slew-rate = <0>;
input-schmitt-disable;
};
refclk-pins {
pinmux = <RZT2H_PORT_PINMUX(34, 6, 0x2)>; /* ETH3_REFCLK */
drive-strength-microamp = <5000>;
slew-rate = <1>;
};
rx-pins {
pinmux = <RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
<RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD0 */
<RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD1 */
<RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2 */
<RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3 */
<RZT2H_PORT_PINMUX(34, 5, 0xf)>; /* ETH3_RXDV */
input-schmitt-disable;
};
txclk-pins {
pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>; /* ETH3_TXCLK */
drive-strength-microamp = <11800>;
slew-rate = <1>;
input-schmitt-disable;
};
txd-en-pins {
pinmux = <RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD0 */
<RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD1 */
<RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD2 */
<RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD3 */
<RZT2H_PORT_PINMUX(33, 7, 0xf)>; /* ETH3_TXEN */
drive-strength-microamp = <11800>;
slew-rate = <1>;
};
};
/*
* GMAC2 Pin Configuration:
*
* DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2
* DSW5[7] ON - use pins P29_1-P29_7, P30_0-P30_4, P30_7,
* P31_2, P31_4 and P31_5 are used for Ethernet port 2
* DSW5[7] ON - use pins P29_1-P29_7 and P30_0-P30_4 for Ethernet port 2
* DSW13[7] OFF; DSW13[8] ON - use pin P13_7 for IRQ14
*/
gmac2_pins: gmac2-pins {
pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
<RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD0 */
<RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD1 */
<RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD2 */
<RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD3 */
<RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
<RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
<RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD0 */
<RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD1 */
<RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD2 */
<RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD3 */
<RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
<RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
<RZT2H_PORT_PINMUX(31, 1, 0xf)>, /* ETH2_RXER */
<RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
<RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
<RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
<RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */
<RZT2H_PORT_PINMUX(31, 0, 0x2)>, /* ETH2_REFCLK */
<RZT2H_PORT_PINMUX(13, 7, 0x0)>; /* IRQ14 */
gmac2_pins: gmac2-group {
irq-pins {
pinmux = <RZT2H_PORT_PINMUX(13, 7, 0x0)>; /* IRQ14 */
drive-strength-microamp = <5000>;
slew-rate = <0>;
input-schmitt-disable;
};
md-pins {
pinmux = <RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
<RZT2H_PORT_PINMUX(30, 6, 0x10)>; /* GMAC2_MDIO */
drive-strength-microamp = <5000>;
slew-rate = <0>;
input-schmitt-disable;
};
refclk-pins {
pinmux = <RZT2H_PORT_PINMUX(31, 0, 0x2)>; /* ETH2_REFCLK */
drive-strength-microamp = <5000>;
slew-rate = <1>;
};
rx-pins {
pinmux = <RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
<RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD0 */
<RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD1 */
<RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD2 */
<RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD3 */
<RZT2H_PORT_PINMUX(30, 4, 0xf)>; /* ETH2_RXDV */
input-schmitt-disable;
};
txclk-pins {
pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>; /* ETH2_TXCLK */
drive-strength-microamp = <11800>;
slew-rate = <1>;
input-schmitt-disable;
};
txd-en-pins {
pinmux = <RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD0 */
<RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD1 */
<RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD2 */
<RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD3 */
<RZT2H_PORT_PINMUX(29, 6, 0xf)>; /* ETH2_TXEN */
drive-strength-microamp = <11800>;
slew-rate = <1>;
};
};
/*

44
arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
View File

@ -32,6 +32,7 @@ / {
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
i2c1 = &i2c1;
i2c2 = &i2c2;
mmc0 = &sdhi0;
mmc2 = &sdhi2;
@ -77,6 +78,12 @@ reg_vdd0p8v_others: regulator-vdd0p8v-others {
regulator-always-on;
};
x2: x2-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
/* 32.768kHz crystal */
x3: x3-clock {
compatible = "fixed-clock";
@ -112,6 +119,12 @@ &gpu {
mali-supply = <&reg_vdd0p8v_others>;
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
@ -130,6 +143,20 @@ raa215300: pmic@12 {
interrupts-extended = <&pinctrl RZG3E_GPIO(S, 1) IRQ_TYPE_EDGE_FALLING>;
};
versa3: clock-generator@68 {
compatible = "renesas,5p35023";
reg = <0x68>;
#clock-cells = <1>;
clocks = <&x2>;
assigned-clocks = <&versa3 0>, <&versa3 1>,
<&versa3 2>, <&versa3 3>,
<&versa3 4>;
assigned-clock-rates = <24000000>, <12288000>,
<11289600>, <12288000>,
<25000000>;
};
};
&i3c {
@ -234,6 +261,11 @@ ctrl {
};
};
i2c1_pins: i2c1 {
pinmux = <RZG3E_PORT_PINMUX(3, 2, 1)>, /* SCL1 */
<RZG3E_PORT_PINMUX(3, 3, 1)>; /* SDA1 */
};
i2c2_pins: i2c {
pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
<RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
@ -320,6 +352,18 @@ sd2-pwen {
};
};
sound_clk_pins: sound-clk {
pinmux = <RZG3E_PORT_PINMUX(4, 2, 8)>, /* AUDIO_CLKB */
<RZG3E_PORT_PINMUX(4, 3, 8)>; /* AUDIO_CLKC */
};
sound_pins: sound {
pinmux = <RZG3E_PORT_PINMUX(0, 2, 9)>, /* SSI3_SDATA */
<RZG3E_PORT_PINMUX(0, 3, 9)>, /* SSI3_SCK */
<RZG3E_PORT_PINMUX(0, 4, 9)>, /* SSI3_WS */
<RZG3E_PORT_PINMUX(0, 5, 9)>; /* SSI4_SDATA */
};
xspi_pins: xspi0 {
pinmux = <RZG3E_PORT_PINMUX(M, 0, 0)>, /* XSPI0_IO0 */
<RZG3E_PORT_PINMUX(M, 1, 0)>, /* XSPI0_IO1 */

14
arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
View File

@ -29,6 +29,17 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory@c8000000 {
device_type = "memory";
/* first 128MiB is reserved for secure area. */
reg = <0x0 0xc8000000 0x0 0x38000000>;
};
memory@240000000 {
device_type = "memory";
reg = <0x2 0x40000000 0x1 0xc0000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
@ -257,6 +268,9 @@ &pinctrl {
sci0_pins: sci0-pins {
pinmux = <RZT2H_PORT_PINMUX(27, 4, 0x14)>,
<RZT2H_PORT_PINMUX(27, 5, 0x14)>;
drive-strength-microamp = <9000>;
slew-rate = <1>;
input-schmitt-disable;
};
#if SD0_EMMC