From 6fa6ee724d8dadf392139e242ac936b5da730c4b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 10 Jul 2026 18:04:22 +0200 Subject: [PATCH 01/29] arm64: dts: renesas: ironhide: Describe inline ECC carveouts The DBSC5 DRAM controller protects DRAM content using inline ECC. The inline ECC utilizes areas of DRAM for its operation, which are in the DRAM address range, but must not be accessed or modified. Describe the inline ECC carveout areas used by the DBSC5 controller on this hardware as reserved-memory, which must not be accessed. Include DRAM areas which are unprotected by ECC as well, those are parts of the DRAM which directly precede the ECC carveout. In case of high DRAM utilization, unless the inline ECC carveouts are properly reserved, Linux may use and corrupt the memory used by the DBSC5 DRAM controller for inline ECC, which would lead to the system becoming unstable. Fixes: ad142a4ef710 ("arm64: dts: renesas: r8a78000: Add initial Ironhide board support") Cc: stable@vger.kernel.org Signed-off-by: Marek Vasut Tested-by: Geert Uytterhoeven Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260710160450.64967-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a78000-ironhide.dts | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts index d2b3fc08954a..0ab303863155 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts +++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts @@ -107,6 +107,47 @@ tee@8c400000 { reg = <0x0 0x8c400000 0x0 0x02000000>; no-map; }; + + /* DRAM controller inline ECC areas */ + ecc@10cccc0000 { + reg = <0x10 0xcccc0000 0x0 0x33340000>; + no-map; + }; + + ecc@12cccc0000 { + reg = <0x12 0xcccc0000 0x0 0x33340000>; + no-map; + }; + + ecc@14cccc0000 { + reg = <0x14 0xcccc0000 0x0 0x33340000>; + no-map; + }; + + ecc@16cccc0000 { + reg = <0x16 0xcccc0000 0x0 0x33340000>; + no-map; + }; + + ecc@18cccc0000 { + reg = <0x18 0xcccc0000 0x0 0x33340000>; + no-map; + }; + + ecc@1a66660000 { + reg = <0x1a 0x66660000 0x0 0x999a0000>; + no-map; + }; + + ecc@1c66660000 { + reg = <0x1c 0x66660000 0x0 0x999a0000>; + no-map; + }; + + ecc@1e66660000 { + reg = <0x1e 0x66660000 0x0 0x999a0000>; + no-map; + }; }; }; From 35cf35e239477cb28e5f6ccd987933d70c21061f Mon Sep 17 00:00:00 2001 From: John Madieu Date: Mon, 25 May 2026 11:05:58 +0000 Subject: [PATCH 02/29] arm64: dts: renesas: rzv2h: Add audio clock inputs Model the optional external audio clock inputs as CPG input clocks for RZ/V2H family SoCs (RZ/V2H, RZ/V2N, RZ/G3E), allowing the Audio Clock Generator (ADG) to derive internal audio clocks from these external sources. The clock frequencies are board-specific and must be overridden in the board DTS files. Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260525110603.4018170-4-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 20 ++++++++++++++++++-- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 20 ++++++++++++++++++-- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 20 ++++++++++++++++++-- 3 files changed, 54 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index b48da8534a3d..be11cdde3cfe 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -21,6 +21,20 @@ audio_extal_clk: audio-clk { clock-frequency = <0>; }; + audio_clkb: audio-b-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + audio_clkc: audio-c-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + /* * The default cluster table is based on the assumption that the PLLCA55 clock * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to @@ -271,8 +285,10 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible = "renesas,r9a09g047-cpg"; reg = <0 0x10420000 0 0x10000>; - clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names = "audio_extal", "rtxin", "qextal"; + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clkb>, <&audio_clkc>; + clock-names = "audio_extal", "rtxin", "qextal", + "audio_clkb", "audio_clkc"; #clock-cells = <2>; #reset-cells = <1>; #power-domain-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index d6c8c39df2a4..3a308dbf733c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -39,6 +39,20 @@ audio_extal_clk: audio-clk { clock-frequency = <0>; }; + audio_clkb: audio-b-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + audio_clkc: audio-c-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + /* * The default cluster table is based on the assumption that the PLLCA55 clock * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to @@ -294,8 +308,10 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible = "renesas,r9a09g056-cpg"; reg = <0 0x10420000 0 0x10000>; - clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names = "audio_extal", "rtxin", "qextal"; + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clkb>, <&audio_clkc>; + clock-names = "audio_extal", "rtxin", "qextal", + "audio_clkb", "audio_clkc"; #clock-cells = <2>; #reset-cells = <1>; #power-domain-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 1e94366bb7ee..8af0f0f2f2f7 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -21,6 +21,20 @@ audio_extal_clk: audio-clk { clock-frequency = <0>; }; + audio_clkb: audio-b-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + audio_clkc: audio-c-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + /* * The default cluster table is based on the assumption that the PLLCA55 clock * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to @@ -276,8 +290,10 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible = "renesas,r9a09g057-cpg"; reg = <0 0x10420000 0 0x10000>; - clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names = "audio_extal", "rtxin", "qextal"; + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clkb>, <&audio_clkc>; + clock-names = "audio_extal", "rtxin", "qextal", + "audio_clkb", "audio_clkc"; #clock-cells = <2>; #reset-cells = <1>; #power-domain-cells = <0>; From 4e66920563d718732b743ae418860cde13265242 Mon Sep 17 00:00:00 2001 From: John Madieu Date: Mon, 25 May 2026 11:06:01 +0000 Subject: [PATCH 03/29] arm64: dts: renesas: rzg3e-smarc-som: Add I2C1 support Add and enable I2C1 controller support with pin configuration. The I2C1 bus is routed to the carrier board and used for peripherals such as the audio codec. Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260525110603.4018170-7-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 2e1d9686df88..15c22dbf0ad3 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -32,6 +32,7 @@ / { aliases { ethernet0 = ð0; ethernet1 = ð1; + i2c1 = &i2c1; i2c2 = &i2c2; mmc0 = &sdhi0; mmc2 = &sdhi2; @@ -112,6 +113,12 @@ &gpu { mali-supply = <®_vdd0p8v_others>; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &i2c2 { pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; @@ -234,6 +241,11 @@ ctrl { }; }; + i2c1_pins: i2c1 { + pinmux = , /* SCL1 */ + ; /* SDA1 */ + }; + i2c2_pins: i2c { pinmux = , /* SCL2 */ ; /* SDA2 */ From c49ad13019771d5161290dc0eacb3ff6186c0953 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 28 May 2026 14:47:50 +0100 Subject: [PATCH 04/29] arm64: dts: renesas: rzt2h-n2h-evk: Remove unused MII/GMII pins Remove the unused TXER, RXER, CRS, and COL pinmux configurations from the gmac1 (ETH3) and gmac2 (ETH2) pin groups. The Ethernet interfaces on both the RZ/T2H and RZ/N2H EVK boards operate in RGMII mode, which does not utilize these extra MII/GMII sideband signal pins. Update the board switch configuration comments to accurately reflect the pin ranges that are actually in use. Fixes: b272b94fd2239 ("arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260528134752.79813-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts | 14 ++------------ .../boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts | 15 ++------------- 2 files changed, 4 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index e9ed2de128f6..987e44d0bf95 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -256,8 +256,7 @@ can0_pins: can0-pins { /* * GMAC1 Pin Configuration: * - * SW2[8] ON - use pins P33_2-P33_7, P34_0-P34_5, P34_7 and - * P35_0-P35_2 for Ethernet port 3 + * SW2[8] ON - use pins P33_2-P33_7 and P34_0-P34_5 for Ethernet port 3 */ gmac1_pins: gmac1-pins { pinmux = , /* ETH3_TXCLK */ @@ -272,10 +271,6 @@ gmac1_pins: gmac1-pins { , /* ETH3_RXD2 */ , /* ETH3_RXD3 */ , /* ETH3_RXDV */ - , /* ETH3_TXER */ - , /* ETH3_RXER */ - , /* ETH3_CRS */ - , /* ETH3_COL */ , /* GMAC1_MDC */ , /* GMAC1_MDIO */ , /* ETH3_REFCLK */ @@ -286,8 +281,7 @@ gmac1_pins: gmac1-pins { * GMAC2 Pin Configuration: * * SW2[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 - * SW2[7] ON - use pins P29_1-P29_7, P30_0-P30_4, and P31_2-P31_5 - * for Ethernet port 2 + * SW2[7] ON - use pins P29_1-P29_7 and P30_0-P30_4 for Ethernet port 2 */ gmac2_pins: gmac2-pins { pinmux = , /* ETH2_TXCLK */ @@ -302,10 +296,6 @@ gmac2_pins: gmac2-pins { , /* ETH2_RXD2 */ , /* ETH2_RXD3 */ , /* ETH2_RXDV */ - , /* ETH2_TXER */ - , /* ETH2_RXER */ - , /* ETH2_CRS */ - , /* ETH2_COL */ , /* GMAC2_MDC */ , /* GMAC2_MDIO */ , /* ETH2_REFCLK */ diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index ef6cc7497c2c..a66502d8d82b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -339,9 +339,7 @@ can1_pins: can1-pins { /* * GMAC1 Pin Configuration: * - * DSW5[8] ON - use pins P00_0-P00_2, P33_2-P33_7, P34_0-P34_6 - * for Ethernet port 3 - * DSW12[1] OFF; DSW12[2] ON - use pin P00_3 for Ethernet port 3 + * DSW5[8] ON - use pins P33_2-P33_7 and P34_0-P34_6 for Ethernet port 3 */ gmac1_pins: gmac1-pins { pinmux = , /* ETH3_TXCLK */ @@ -356,10 +354,6 @@ gmac1_pins: gmac1-pins { , /* ETH3_RXD2 */ , /* ETH3_RXD3 */ , /* ETH3_RXDV */ - , /* ETH3_TXER */ - , /* ETH3_RXER */ - , /* ETH3_CRS */ - , /* ETH3_COL */ , /* GMAC1_MDC */ , /* GMAC1_MDIO */ , /* ETH3_REFCLK */ @@ -370,8 +364,7 @@ gmac1_pins: gmac1-pins { * GMAC2 Pin Configuration: * * DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 - * DSW5[7] ON - use pins P29_1-P29_7, P30_0-P30_4, P30_7, - * P31_2, P31_4 and P31_5 are used for Ethernet port 2 + * DSW5[7] ON - use pins P29_1-P29_7 and P30_0-P30_4 for Ethernet port 2 * DSW13[7] OFF; DSW13[8] ON - use pin P13_7 for IRQ14 */ gmac2_pins: gmac2-pins { @@ -387,10 +380,6 @@ gmac2_pins: gmac2-pins { , /* ETH2_RXD2 */ , /* ETH2_RXD3 */ , /* ETH2_RXDV */ - , /* ETH2_TXER */ - , /* ETH2_RXER */ - , /* ETH2_CRS */ - , /* ETH2_COL */ , /* GMAC2_MDC */ , /* GMAC2_MDIO */ , /* ETH2_REFCLK */ From 1f90a38214d52f773edd02bf02805aa905164ee0 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 28 May 2026 14:47:51 +0100 Subject: [PATCH 05/29] arm64: dts: renesas: rzt2h-n2h-evk: Configure ETH pins Update the gmac1 (ETH3) and gmac2 (ETH2) pin configurations on the RZ/T2H and RZ/N2H EVK boards to comply with the electrical specifications defined in Table 58.11 of the hardware user manual. While restructuring the nodes into pin groups, fix a copy-paste comment typo in the RZ/N2H device tree where the ETH3_TXD1 pin mux configuration was mistakenly labeled as ETH3_TXD0. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260528134752.79813-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 130 +++++++++++++----- .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 129 ++++++++++++----- 2 files changed, 191 insertions(+), 68 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 987e44d0bf95..572be8aa6d7e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -258,23 +258,54 @@ can0_pins: can0-pins { * * SW2[8] ON - use pins P33_2-P33_7 and P34_0-P34_5 for Ethernet port 3 */ - gmac1_pins: gmac1-pins { - pinmux = , /* ETH3_TXCLK */ - , /* ETH3_TXD0 */ - , /* ETH3_TXD1 */ - , /* ETH3_TXD2 */ - , /* ETH3_TXD3 */ - , /* ETH3_TXEN */ - , /* ETH3_RXCLK */ - , /* ETH3_RXD0 */ - , /* ETH3_RXD1 */ - , /* ETH3_RXD2 */ - , /* ETH3_RXD3 */ - , /* ETH3_RXDV */ - , /* GMAC1_MDC */ - , /* GMAC1_MDIO */ - , /* ETH3_REFCLK */ - ; /* IRQ3 */ + gmac1_pins: gmac1-group { + irq-pins { + pinmux = ; /* IRQ3 */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + + md-pins { + pinmux = , /* GMAC1_MDC */ + ; /* GMAC1_MDIO */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + + refclk-pins { + pinmux = ; /* ETH3_REFCLK */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + }; + + rx-pins { + pinmux = , /* ETH3_RXCLK */ + , /* ETH3_RXD0 */ + , /* ETH3_RXD1 */ + , /* ETH3_RXD2 */ + , /* ETH3_RXD3 */ + ; /* ETH3_RXDV */ + input-schmitt-disable; + }; + + txclk-pins { + pinmux = ; /* ETH3_TXCLK */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + input-schmitt-disable; + }; + + txd-en-pins { + pinmux = , /* ETH3_TXD0 */ + , /* ETH3_TXD1 */ + , /* ETH3_TXD2 */ + , /* ETH3_TXD3 */ + ; /* ETH3_TXEN */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + }; }; /* @@ -283,23 +314,54 @@ gmac1_pins: gmac1-pins { * SW2[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 * SW2[7] ON - use pins P29_1-P29_7 and P30_0-P30_4 for Ethernet port 2 */ - gmac2_pins: gmac2-pins { - pinmux = , /* ETH2_TXCLK */ - , /* ETH2_TXD0 */ - , /* ETH2_TXD1 */ - , /* ETH2_TXD2 */ - , /* ETH2_TXD3 */ - , /* ETH2_TXEN */ - , /* ETH2_RXCLK */ - , /* ETH2_RXD0 */ - , /* ETH2_RXD1 */ - , /* ETH2_RXD2 */ - , /* ETH2_RXD3 */ - , /* ETH2_RXDV */ - , /* GMAC2_MDC */ - , /* GMAC2_MDIO */ - , /* ETH2_REFCLK */ - ; /* IRQ13 */ + gmac2_pins: gmac2-group { + irq-pins { + pinmux = ; /* IRQ13 */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + + md-pins { + pinmux = , /* GMAC2_MDC */ + ; /* GMAC2_MDIO */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + + refclk-pins { + pinmux = ; /* ETH2_REFCLK */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + }; + + rx-pins { + pinmux = , /* ETH2_RXCLK */ + , /* ETH2_RXD0 */ + , /* ETH2_RXD1 */ + , /* ETH2_RXD2 */ + , /* ETH2_RXD3 */ + ; /* ETH2_RXDV */ + input-schmitt-disable; + }; + + txclk-pins { + pinmux = ; /* ETH2_TXCLK */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + input-schmitt-disable; + }; + + txd-en-pins { + pinmux = , /* ETH2_TXD0 */ + , /* ETH2_TXD1 */ + , /* ETH2_TXD2 */ + , /* ETH2_TXD3 */ + ; /* ETH2_TXEN */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + }; }; /* diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index a66502d8d82b..4e57d4fe195c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -341,23 +341,54 @@ can1_pins: can1-pins { * * DSW5[8] ON - use pins P33_2-P33_7 and P34_0-P34_6 for Ethernet port 3 */ - gmac1_pins: gmac1-pins { - pinmux = , /* ETH3_TXCLK */ - , /* ETH3_TXD0 */ - , /* ETH3_TXD0 */ - , /* ETH3_TXD2 */ - , /* ETH3_TXD3 */ - , /* ETH3_TXEN */ - , /* ETH3_RXCLK */ - , /* ETH3_RXD0 */ - , /* ETH3_RXD1 */ - , /* ETH3_RXD2 */ - , /* ETH3_RXD3 */ - , /* ETH3_RXDV */ - , /* GMAC1_MDC */ - , /* GMAC1_MDIO */ - , /* ETH3_REFCLK */ - ; /* IRQ15 */ + gmac1_pins: gmac1-group { + irq-pins { + pinmux = ; /* IRQ15 */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + + md-pins { + pinmux = , /* GMAC1_MDC */ + ; /* GMAC1_MDIO */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + + refclk-pins { + pinmux = ; /* ETH3_REFCLK */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + }; + + rx-pins { + pinmux = , /* ETH3_RXCLK */ + , /* ETH3_RXD0 */ + , /* ETH3_RXD1 */ + , /* ETH3_RXD2 */ + , /* ETH3_RXD3 */ + ; /* ETH3_RXDV */ + input-schmitt-disable; + }; + + txclk-pins { + pinmux = ; /* ETH3_TXCLK */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + input-schmitt-disable; + }; + + txd-en-pins { + pinmux = , /* ETH3_TXD0 */ + , /* ETH3_TXD1 */ + , /* ETH3_TXD2 */ + , /* ETH3_TXD3 */ + ; /* ETH3_TXEN */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + }; }; /* @@ -367,24 +398,54 @@ gmac1_pins: gmac1-pins { * DSW5[7] ON - use pins P29_1-P29_7 and P30_0-P30_4 for Ethernet port 2 * DSW13[7] OFF; DSW13[8] ON - use pin P13_7 for IRQ14 */ - gmac2_pins: gmac2-pins { - pinmux = , /* ETH2_TXCLK */ - , /* ETH2_TXD0 */ - , /* ETH2_TXD1 */ - , /* ETH2_TXD2 */ - , /* ETH2_TXD3 */ - , /* ETH2_TXEN */ - , /* ETH2_RXCLK */ - , /* ETH2_RXD0 */ - , /* ETH2_RXD1 */ - , /* ETH2_RXD2 */ - , /* ETH2_RXD3 */ - , /* ETH2_RXDV */ - , /* GMAC2_MDC */ - , /* GMAC2_MDIO */ - , /* ETH2_REFCLK */ - ; /* IRQ14 */ + gmac2_pins: gmac2-group { + irq-pins { + pinmux = ; /* IRQ14 */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + md-pins { + pinmux = , /* GMAC2_MDC */ + ; /* GMAC2_MDIO */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + + refclk-pins { + pinmux = ; /* ETH2_REFCLK */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + }; + + rx-pins { + pinmux = , /* ETH2_RXCLK */ + , /* ETH2_RXD0 */ + , /* ETH2_RXD1 */ + , /* ETH2_RXD2 */ + , /* ETH2_RXD3 */ + ; /* ETH2_RXDV */ + input-schmitt-disable; + }; + + txclk-pins { + pinmux = ; /* ETH2_TXCLK */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + input-schmitt-disable; + }; + + txd-en-pins { + pinmux = , /* ETH2_TXD0 */ + , /* ETH2_TXD1 */ + , /* ETH2_TXD2 */ + , /* ETH2_TXD3 */ + ; /* ETH2_TXEN */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + }; }; /* From 1417a63d16ba5681fe137e546aaa9c5b2828c5d5 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 28 May 2026 14:47:52 +0100 Subject: [PATCH 06/29] arm64: dts: renesas: rzt2h-n2h-evk: Configure SCI0 pins Configure the drive strength, slew rate, and Schmitt trigger settings for the sci0 pin group shared by the RZ/T2H and RZ/N2H EVK boards. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260528134752.79813-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index e86e6d3aa8a3..ceccddb92d40 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -257,6 +257,9 @@ &pinctrl { sci0_pins: sci0-pins { pinmux = , ; + drive-strength-microamp = <9000>; + slew-rate = <1>; + input-schmitt-disable; }; #if SD0_EMMC From 4fb32d9e4836c33ea9861f7c3e57beab6f546eb1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 29 May 2026 13:54:40 +0100 Subject: [PATCH 07/29] arm64: dts: renesas: r9a08g046l48-smarc: Enable rsci{1,2,3} nodes Enable rsci{1,2,3} device nodes for the RZ/G3L SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260529125442.327290-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts index 32d3b08a3cf3..3ce24b66cb8d 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -13,6 +13,7 @@ #define SW_DPI_EN 0 #define SW_GPIO4 1 #define SW_I3C_EN 0 +#define SW_SER0_PMOD 1 #define PMOD_GPIO4 0 #define PMOD_GPIO6 0 @@ -37,6 +38,9 @@ / { aliases { i2c2 = &i2c2; i2c3 = &i2c3; + serial0 = &rsci2; + serial1 = &rsci3; + serial2 = &rsci1; serial3 = &scif0; }; @@ -134,6 +138,30 @@ i2c3_pins: i2c3 { ; /* RIIC3_SDA */ }; + rsci1_pins: rsci1 { + pinmux = , /* RSCI1_RXD_MISO_SCL */ + , /* RSCI1_TXD_MOSI_SDA */ + , /* RSCI1_CTS */ + ; /* RSCI1_SS_CTS#_RTS# */ + bias-pull-up; + }; + + rsci2_pins: rsci2 { + pinmux = , /* RSCI2_RXD_MISO_SCL */ + , /* RSCI2_TXD_MOSI_SDA */ + , /* RSCI2_CTS */ + ; /* RSCI2_SS_CTS#_RTS# */ + bias-pull-up; + power-source = <1800>; + }; + + rsci3_pins: rsci3 { + pinmux = , /* RSCI3_RXD_MISO_SCL */ + ; /* RSCI3_TXD_MOSI_SDA */ + bias-pull-up; + power-source = <1800>; + }; + scif0_pins: scif0 { pins = "SCIF0_TXD", "SCIF0_RXD"; power-source = <1800>; @@ -147,6 +175,37 @@ ssi0_pins: ssi0 { }; }; +#if SW_SER0_PMOD +&rsci1 { + pinctrl-0 = <&rsci1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + + status = "okay"; +}; +#endif + +#if !SW_DPI_EN +&rsci2 { + pinctrl-0 = <&rsci2_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + + status = "okay"; +}; +#endif + +#if (!SW_DPI_EN) +&rsci3 { + pinctrl-0 = <&rsci3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; +#endif + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; From ba82a7f75e8a33963354c1be109793f2bccccb79 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 29 May 2026 14:07:00 +0100 Subject: [PATCH 08/29] arm64: dts: renesas: r9a08g046: Add RSPI{0..2} nodes Add device tree nodes for the three RSPI channels on the RZ/G3L (R9A08G046) SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260529130704.327505-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 03bdee870528..c63a857f0e5b 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -358,6 +358,75 @@ i2c3: i2c@10090c00 { status = "disabled"; }; + rspi0: spi@100b0000 { + compatible = "renesas,r9a08g046-rspi"; + reg = <0 0x100b0000 0 0x1000>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A08G046_RSPI0_PCLK>, + <&cpg CPG_MOD R9A08G046_RSPI0_TCLK>; + clock-names = "pclk", "tclk"; + resets = <&cpg R9A08G046_RSPI0_PRESETN>, + <&cpg R9A08G046_RSPI0_TRESETN>; + reset-names = "presetn", "tresetn"; + dmas = <&dmac 0x26f2>, <&dmac 0x26f1>; + dma-names = "rx", "tx"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi1: spi@100e9000 { + compatible = "renesas,r9a08g046-rspi"; + reg = <0 0x100e9000 0 0x1000>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A08G046_RSPI1_PCLK>, + <&cpg CPG_MOD R9A08G046_RSPI1_TCLK>; + clock-names = "pclk", "tclk"; + resets = <&cpg R9A08G046_RSPI1_PRESETN>, + <&cpg R9A08G046_RSPI1_TRESETN>; + reset-names = "presetn", "tresetn"; + dmas = <&dmac 0x26f6>, <&dmac 0x26f5>; + dma-names = "rx", "tx"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi2: spi@100ea000 { + compatible = "renesas,r9a08g046-rspi"; + reg = <0 0x100ea000 0 0x1000>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A08G046_RSPI2_PCLK>, + <&cpg CPG_MOD R9A08G046_RSPI2_TCLK>; + clock-names = "pclk", "tclk"; + resets = <&cpg R9A08G046_RSPI2_PRESETN>, + <&cpg R9A08G046_RSPI2_TRESETN>; + reset-names = "presetn", "tresetn"; + dmas = <&dmac 0x26fa>, <&dmac 0x26f9>; + dma-names = "rx", "tx"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + rsci0: serial@100b8000 { compatible = "renesas,r9a08g046-rsci"; reg = <0 0x100b8000 0 0x1000>; From db60b8a6154af4221954065c695a0b35cee34b72 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 29 May 2026 14:07:01 +0100 Subject: [PATCH 09/29] arm64: dts: renesas: r9a08g046l48-smarc: Enable RSPI2 Enable RSPI2 on the RZ/G3L SMARC EVK board by adding pin control configuration and activating the rspi2 node. The RSPI2 pins are shared with the DPI display interface and the two cannot be used simultaneously. This is controlled by switch SW_DPI_EN. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260529130704.327505-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts index 3ce24b66cb8d..5289efd1a430 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -162,6 +162,14 @@ rsci3_pins: rsci3 { power-source = <1800>; }; + rspi2_pins: rspi2 { + pinmux = , /* RSPI2_MISO */ + , /* RSPI2_MOSI */ + , /* RSPI2_SCK */ + ; /* RSPI2_SSLA */ + power-source = <1800>; + }; + scif0_pins: scif0 { pins = "SCIF0_TXD", "SCIF0_RXD"; power-source = <1800>; @@ -206,6 +214,17 @@ &rsci3 { }; #endif +#if !SW_DPI_EN +&rspi2 { + pinctrl-0 = <&rspi2_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; +}; +#endif + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; From 9f115f9c3133294dfe149fe2e8376a854b0124a5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 1 Jun 2026 13:38:51 +0200 Subject: [PATCH 10/29] arm64: dts: renesas: r8a78000: Enable application CPU cores via PSCI Add PSCI "enable-method" DT properties to all application CPU cores. This allows the OS to bring application CPU cores up and down. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260601113919.8327-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a78000.dtsi | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi index 7780fb4e8351..fb71974ef390 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi @@ -143,6 +143,7 @@ a720_0: cpu@0 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x0>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_0>; }; @@ -150,6 +151,7 @@ a720_1: cpu@100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_1>; }; @@ -157,6 +159,7 @@ a720_2: cpu@200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_2>; }; @@ -164,6 +167,7 @@ a720_3: cpu@300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_3>; }; @@ -171,6 +175,7 @@ a720_4: cpu@10000 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x10000>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_4>; }; @@ -178,6 +183,7 @@ a720_5: cpu@10100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x10100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_5>; }; @@ -185,6 +191,7 @@ a720_6: cpu@10200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x10200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_6>; }; @@ -192,6 +199,7 @@ a720_7: cpu@10300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x10300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_7>; }; @@ -199,6 +207,7 @@ a720_8: cpu@20000 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x20000>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_8>; }; @@ -206,6 +215,7 @@ a720_9: cpu@20100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x20100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_9>; }; @@ -213,6 +223,7 @@ a720_10: cpu@20200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x20200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_10>; }; @@ -220,6 +231,7 @@ a720_11: cpu@20300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x20300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_11>; }; @@ -227,6 +239,7 @@ a720_12: cpu@30000 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x30000>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_12>; }; @@ -234,6 +247,7 @@ a720_13: cpu@30100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x30100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_13>; }; @@ -241,6 +255,7 @@ a720_14: cpu@30200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x30200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_14>; }; @@ -248,6 +263,7 @@ a720_15: cpu@30300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x30300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_15>; }; @@ -255,6 +271,7 @@ a720_16: cpu@40000 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x40000>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_16>; }; @@ -262,6 +279,7 @@ a720_17: cpu@40100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x40100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_17>; }; @@ -269,6 +287,7 @@ a720_18: cpu@40200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x40200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_18>; }; @@ -276,6 +295,7 @@ a720_19: cpu@40300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x40300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_19>; }; @@ -283,6 +303,7 @@ a720_20: cpu@50000 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x50000>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_20>; }; @@ -290,6 +311,7 @@ a720_21: cpu@50100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x50100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_21>; }; @@ -297,6 +319,7 @@ a720_22: cpu@50200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x50200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_22>; }; @@ -304,6 +327,7 @@ a720_23: cpu@50300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x50300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_23>; }; @@ -311,6 +335,7 @@ a720_24: cpu@60000 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x60000>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_24>; }; @@ -318,6 +343,7 @@ a720_25: cpu@60100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x60100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_25>; }; @@ -325,6 +351,7 @@ a720_26: cpu@60200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x60200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_26>; }; @@ -332,6 +359,7 @@ a720_27: cpu@60300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x60300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_27>; }; @@ -339,6 +367,7 @@ a720_28: cpu@70000 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x70000>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_28>; }; @@ -346,6 +375,7 @@ a720_29: cpu@70100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x70100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_29>; }; @@ -353,6 +383,7 @@ a720_30: cpu@70200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x70200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_30>; }; @@ -360,6 +391,7 @@ a720_31: cpu@70300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x70300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_31>; }; From f0de09f7de324b2deed7ebdb26d775a0abe9e10d Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 2 Jun 2026 20:21:09 +0200 Subject: [PATCH 11/29] arm64: dts: renesas: r8a779g0: Add MFIS node Describe the MFIS core which is used for various tasks including inter-processor communication. Interrupt numbers look irregular but they all work as expected on a Renesas R-Car V4H SparrowHawk board. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260602182157.304964-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 82a7278836e5..8a291447b904 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -589,6 +589,23 @@ tmu4: timer@ffc00000 { status = "disabled"; }; + mfis: system-controller@e6260000 { + compatible = "renesas,r8a779g0-mfis"; + reg = <0 0xe6260000 0 0x10000>; + reg-names = "common"; + interrupts = , , + , , + , , + , , + , , + , ; + interrupt-names = "ch0e", "ch1e", "ch2e", "ch3e", "ch4e", "ch5e", + "ch6e", "ch7e", "ch8e", "ch9e", "ch10e", "ch11e"; + #hwlock-cells = <1>; + #mbox-cells = <2>; + status = "disabled"; + }; + tsn0: ethernet@e6460000 { compatible = "renesas,r8a779g0-ethertsn", "renesas,rcar-gen4-ethertsn"; reg = <0 0xe6460000 0 0x7000>, From 31fd71751e699117d71ed998c58fc7fe9ec471fa Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 3 Jun 2026 15:33:35 +0100 Subject: [PATCH 12/29] arm64: dts: renesas: r9a09g047e57-smarc: Drop SW_SER0_PMOD condition for rsci4 Rsci4 is routed to either the PMOD connector or the M.2 connector, depending on the SW_SER0_PMOD switch state. In both cases, rsci4 is available for use, so there is no need to guard it with SW_SER0_PMOD. Drop the SW_SER0_PMOD condition and retain only the SW_LCD_EN check, as rsci4 is unavailable only when the LCD is enabled. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260603143340.162457-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 6372f582a7c4..07db9e434521 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -237,7 +237,7 @@ &rsci2 { }; #endif -#if (!SW_LCD_EN) && (SW_SER0_PMOD) +#if !SW_LCD_EN &rsci4 { pinctrl-0 = <&rsci4_pins>; pinctrl-names = "default"; From e3203a81238d59833adfe551ccad929245a1ea92 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 3 Jun 2026 15:33:36 +0100 Subject: [PATCH 13/29] arm64: dts: renesas: r9a09g047: Add max-frequency to SDHI nodes Add max-frequency properties of 200MHz to the sdhi0, sdhi1, and sdhi2 MMC controllers in the R9A09G047 SoC DTSI to define the maximum supported bus frequency. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260603143340.162457-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index be11cdde3cfe..cf3f77e5551a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -1281,6 +1281,7 @@ sdhi0: mmc@15c00000 { clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <200000000>; resets = <&cpg 0xa7>; power-domains = <&cpg>; status = "disabled"; @@ -1301,6 +1302,7 @@ sdhi1: mmc@15c10000 { clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <200000000>; resets = <&cpg 0xa8>; power-domains = <&cpg>; status = "disabled"; @@ -1321,6 +1323,7 @@ sdhi2: mmc@15c20000 { clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <200000000>; resets = <&cpg 0xa9>; power-domains = <&cpg>; status = "disabled"; From 2cc5ac6e859bcf3ec5d4c8725909918f8bb907a2 Mon Sep 17 00:00:00 2001 From: bui duc phuc Date: Tue, 9 Jun 2026 18:38:27 +0700 Subject: [PATCH 14/29] ARM: dts: renesas: r8a7740: Add FSI clocks Add the SPU bus clock, icka/b functional clocks, and xcka/b external clock inputs to the FSI device node. This prepares for subsequent driver changes that explicitly manage the SPU clock required for FSI register access on R-Mobile A1. Signed-off-by: bui duc phuc Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260609113836.45079-3-phucduc.bui@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r8a7740.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi index c7056b96ec0b..d4776a7877ff 100644 --- a/arch/arm/boot/dts/renesas/r8a7740.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -501,7 +501,11 @@ sh_fsi2: sound@fe1f0000 { compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; reg = <0xfe1f0000 0x400>; interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_FSI>; + clocks = <&mstp3_clks R8A7740_CLK_FSI>, <&spu_clk>, + <&fsia_clk>, <&fsib_clk>, <&fsiack_clk>, + <&fsibck_clk>; + clock-names = "fck", "spu", "icka", "ickb", "xcka", + "xckb"; power-domains = <&pd_a4mp>; status = "disabled"; }; @@ -722,6 +726,12 @@ vou_clk: vou@e6150088 { <0>; #clock-cells = <0>; }; + fsib_clk: fsib@e6150090 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150090 4>; + clocks = <&pllc1_div2_clk>, <&fsibck_clk>, <0>, <0>; + #clock-cells = <0>; + }; stpro_clk: stpro@e615009c { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615009c 4>; From e2b5bacc8e2056ca81b08a59529ae182cd80e3ff Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 11 Jun 2026 02:57:29 +0200 Subject: [PATCH 15/29] arm64: dts: renesas: r8a77965-salvator-x: Enable GPU support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable GPU on Salvator-X with R-Car M3-N. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://patch.msgid.link/20260611005952.146825-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts index f84c64ed4df7..af8cfdccd210 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts @@ -30,3 +30,7 @@ &du { clock-names = "du.0", "du.1", "du.3", "dclkin.0", "dclkin.1", "dclkin.3"; }; + +&gpu { + status = "okay"; +}; From 0d501c2fbcd931815380dc3db07f1dd77d151422 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 11 Jun 2026 02:57:30 +0200 Subject: [PATCH 16/29] arm64: dts: renesas: r8a77965-salvator-xs: Enable GPU support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable GPU on Salvator-X 2nd version with R-Car M3-N. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://patch.msgid.link/20260611005952.146825-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts index a1d3c8d531cf..f0d9c0124f69 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts @@ -30,3 +30,7 @@ &du { clock-names = "du.0", "du.1", "du.3", "dclkin.0", "dclkin.1", "dclkin.3"; }; + +&gpu { + status = "okay"; +}; From e7f8013a1306ac9af01e43f1e05f13d235b566a7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 11 Jun 2026 02:57:31 +0200 Subject: [PATCH 17/29] arm64: dts: renesas: r8a77965-ulcb: Enable GPU support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable GPU on M3NULCB with R-Car M3-N. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://patch.msgid.link/20260611005952.146825-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts index 71704b67a20e..127eb2ea3c92 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts @@ -31,3 +31,7 @@ &du { clock-names = "du.0", "du.1", "du.3", "dclkin.0", "dclkin.1", "dclkin.3"; }; + +&gpu { + status = "okay"; +}; From 7cb769eb22d1f6b0536b2979b92c50cb5873e07a Mon Sep 17 00:00:00 2001 From: John Madieu Date: Fri, 19 Jun 2026 08:39:48 +0000 Subject: [PATCH 18/29] arm64: dts: renesas: r9a09g047: Add RZ/G3E Sound support Add the snd_rzg3e node for the RZ/G3E SoC with all sub-components: - SSI (Serial Sound Interface) units 0-9, - SSIU (Serial Sound Interface Unit) units 0-27, - SRC (Sample Rate Converter) units 0-9, - CTU (Channel Transfer Unit) units 0-7, - DVC (Digital Volume Control) units 0-1, - MIX (Mixer) units 0-1. Sub-node names follow the new RZ/G3E sound binding: unprefixed 'ssi', 'ssiu', 'src', 'dvc', 'mix', 'ctu' wrapper nodes instead of the legacy 'rcar_sound,xxx' R-Car prefix. Wire up all 5 DMA controllers (dmac0-dmac4) for each audio sub-node with repeated channel names, so that the DMA core can pick the first available controller. Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260619083951.3777556-2-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 500 +++++++++++++++++++++ 1 file changed, 500 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index cf3f77e5551a..310f988a63c4 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -912,6 +912,506 @@ rsci9: serial@12803000 { status = "disabled"; }; + snd_rzg3e: sound@13c00000 { + compatible = "renesas,r9a09g047-sound"; + reg = <0 0x13c00000 0 0x20000>, /* SCU */ + <0 0x13c20000 0 0x10000>, /* ADG */ + <0 0x13c30000 0 0x1000>, /* SSIU */ + <0 0x13c31000 0 0x1f000>, /* SSI */ + <0 0x13c50000 0 0x10000>; /* Audio DMAC peri peri */ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + clocks = <&cpg CPG_MOD 0xf5>, + <&cpg CPG_MOD 0x181>, <&cpg CPG_MOD 0x182>, + <&cpg CPG_MOD 0x183>, <&cpg CPG_MOD 0x184>, + <&cpg CPG_MOD 0x185>, <&cpg CPG_MOD 0x186>, + <&cpg CPG_MOD 0x187>, <&cpg CPG_MOD 0x188>, + <&cpg CPG_MOD 0x189>, <&cpg CPG_MOD 0x18a>, + <&cpg CPG_MOD 0x174>, <&cpg CPG_MOD 0x175>, + <&cpg CPG_MOD 0x176>, <&cpg CPG_MOD 0x177>, + <&cpg CPG_MOD 0x178>, <&cpg CPG_MOD 0x179>, + <&cpg CPG_MOD 0x17a>, <&cpg CPG_MOD 0x17b>, + <&cpg CPG_MOD 0x17c>, <&cpg CPG_MOD 0x17d>, + <&cpg CPG_MOD 0x172>, <&cpg CPG_MOD 0x173>, + <&cpg CPG_MOD 0x172>, <&cpg CPG_MOD 0x173>, + <&cpg CPG_MOD 0x170>, <&cpg CPG_MOD 0x171>, + <&cpg CPG_MOD 0xfb>, <&cpg CPG_MOD 0xfc>, + <&cpg CPG_MOD 0xfd>, <&cpg CPG_MOD 0xfa>, + <&cpg CPG_MOD 0x180>, + <&cpg CPG_MOD 0xf6>, <&cpg CPG_MOD 0xf7>, + <&cpg CPG_MOD 0x17e>, + <&cpg CPG_MOD 0x160>, <&cpg CPG_MOD 0x161>, + <&cpg CPG_MOD 0x162>, <&cpg CPG_MOD 0x163>, + <&cpg CPG_MOD 0x164>, <&cpg CPG_MOD 0x165>, + <&cpg CPG_MOD 0x166>, <&cpg CPG_MOD 0x167>, + <&cpg CPG_MOD 0x168>, <&cpg CPG_MOD 0x169>, + <&cpg CPG_MOD 0xf8>, <&cpg CPG_MOD 0xf9>; + clock-names = "ssi-all", + "ssi-0", "ssi-1", + "ssi-2", "ssi-3", + "ssi-4", "ssi-5", + "ssi-6", "ssi-7", + "ssi-8", "ssi-9", + "src-0", "src-1", + "src-2", "src-3", + "src-4", "src-5", + "src-6", "src-7", + "src-8", "src-9", + "mix-0", "mix-1", + "ctu-0", "ctu-1", + "dvc-0", "dvc-1", + "audio-clka", "audio-clkb", + "audio-clkc", "audio-clki", + "ssif_supply", + "scu", "scu_x2", + "scu_supply", + "adg-ssi-0", "adg-ssi-1", + "adg-ssi-2", "adg-ssi-3", + "adg-ssi-4", "adg-ssi-5", + "adg-ssi-6", "adg-ssi-7", + "adg-ssi-8", "adg-ssi-9", + "audmapp", "adg"; + power-domains = <&cpg>; + resets = <&cpg 0xe1>, + <&cpg 0xe2>, <&cpg 0xe3>, + <&cpg 0xe4>, <&cpg 0xe5>, + <&cpg 0xe6>, <&cpg 0xe7>, + <&cpg 0xe8>, <&cpg 0xe9>, + <&cpg 0xea>, <&cpg 0xeb>, + <&cpg 0xec>, <&cpg 0xee>, + <&cpg 0xed>; + reset-names = "ssi-all", + "ssi-0", "ssi-1", + "ssi-2", "ssi-3", + "ssi-4", "ssi-5", + "ssi-6", "ssi-7", + "ssi-8", "ssi-9", + "scu", "adg", + "audmapp"; + status = "disabled"; + + ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + dvc { + dvc0: dvc-0 { + dmas = <&dmac0 0x1db3>, <&dmac1 0x1db3>, + <&dmac2 0x1db3>, <&dmac3 0x1db3>, + <&dmac4 0x1db3>; + dma-names = "tx", "tx", "tx", "tx", "tx"; + }; + dvc1: dvc-1 { + dmas = <&dmac0 0x1db4>, <&dmac1 0x1db4>, + <&dmac2 0x1db4>, <&dmac3 0x1db4>, + <&dmac4 0x1db4>; + dma-names = "tx", "tx", "tx", "tx", "tx"; + }; + }; + + mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + src { + src0: src-0 { + interrupts = ; + dmas = <&dmac0 0x1d9f>, <&dmac0 0x1da9>, + <&dmac1 0x1d9f>, <&dmac1 0x1da9>, + <&dmac2 0x1d9f>, <&dmac2 0x1da9>, + <&dmac3 0x1d9f>, <&dmac3 0x1da9>, + <&dmac4 0x1d9f>, <&dmac4 0x1da9>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&dmac0 0x1da0>, <&dmac0 0x1daa>, + <&dmac1 0x1da0>, <&dmac1 0x1daa>, + <&dmac2 0x1da0>, <&dmac2 0x1daa>, + <&dmac3 0x1da0>, <&dmac3 0x1daa>, + <&dmac4 0x1da0>, <&dmac4 0x1daa>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&dmac0 0x1da1>, <&dmac0 0x1dab>, + <&dmac1 0x1da1>, <&dmac1 0x1dab>, + <&dmac2 0x1da1>, <&dmac2 0x1dab>, + <&dmac3 0x1da1>, <&dmac3 0x1dab>, + <&dmac4 0x1da1>, <&dmac4 0x1dab>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&dmac0 0x1da2>, <&dmac0 0x1dac>, + <&dmac1 0x1da2>, <&dmac1 0x1dac>, + <&dmac2 0x1da2>, <&dmac2 0x1dac>, + <&dmac3 0x1da2>, <&dmac3 0x1dac>, + <&dmac4 0x1da2>, <&dmac4 0x1dac>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&dmac0 0x1da3>, <&dmac0 0x1dad>, + <&dmac1 0x1da3>, <&dmac1 0x1dad>, + <&dmac2 0x1da3>, <&dmac2 0x1dad>, + <&dmac3 0x1da3>, <&dmac3 0x1dad>, + <&dmac4 0x1da3>, <&dmac4 0x1dad>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&dmac0 0x1da4>, <&dmac0 0x1dae>, + <&dmac1 0x1da4>, <&dmac1 0x1dae>, + <&dmac2 0x1da4>, <&dmac2 0x1dae>, + <&dmac3 0x1da4>, <&dmac3 0x1dae>, + <&dmac4 0x1da4>, <&dmac4 0x1dae>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&dmac0 0x1da5>, <&dmac0 0x1daf>, + <&dmac1 0x1da5>, <&dmac1 0x1daf>, + <&dmac2 0x1da5>, <&dmac2 0x1daf>, + <&dmac3 0x1da5>, <&dmac3 0x1daf>, + <&dmac4 0x1da5>, <&dmac4 0x1daf>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&dmac0 0x1da6>, <&dmac0 0x1db0>, + <&dmac1 0x1da6>, <&dmac1 0x1db0>, + <&dmac2 0x1da6>, <&dmac2 0x1db0>, + <&dmac3 0x1da6>, <&dmac3 0x1db0>, + <&dmac4 0x1da6>, <&dmac4 0x1db0>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&dmac0 0x1da7>, <&dmac0 0x1db1>, + <&dmac1 0x1da7>, <&dmac1 0x1db1>, + <&dmac2 0x1da7>, <&dmac2 0x1db1>, + <&dmac3 0x1da7>, <&dmac3 0x1db1>, + <&dmac4 0x1da7>, <&dmac4 0x1db1>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&dmac0 0x1da8>, <&dmac0 0x1db2>, + <&dmac1 0x1da8>, <&dmac1 0x1db2>, + <&dmac2 0x1da8>, <&dmac2 0x1db2>, + <&dmac3 0x1da8>, <&dmac3 0x1db2>, + <&dmac4 0x1da8>, <&dmac4 0x1db2>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + }; + + ssi { + ssi0: ssi-0 { + interrupts = ; + }; + ssi1: ssi-1 { + interrupts = ; + }; + ssi2: ssi-2 { + interrupts = ; + }; + ssi3: ssi-3 { + interrupts = ; + }; + ssi4: ssi-4 { + interrupts = ; + }; + ssi5: ssi-5 { + interrupts = ; + }; + ssi6: ssi-6 { + interrupts = ; + }; + ssi7: ssi-7 { + interrupts = ; + }; + ssi8: ssi-8 { + interrupts = ; + }; + ssi9: ssi-9 { + interrupts = ; + }; + }; + + ssiu { + ssiu00: ssiu-0 { + dmas = <&dmac0 0x1d61>, <&dmac0 0x1d62>, + <&dmac1 0x1d61>, <&dmac1 0x1d62>, + <&dmac2 0x1d61>, <&dmac2 0x1d62>, + <&dmac3 0x1d61>, <&dmac3 0x1d62>, + <&dmac4 0x1d61>, <&dmac4 0x1d62>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu01: ssiu-1 { + dmas = <&dmac0 0x1d63>, <&dmac0 0x1d64>, + <&dmac1 0x1d63>, <&dmac1 0x1d64>, + <&dmac2 0x1d63>, <&dmac2 0x1d64>, + <&dmac3 0x1d63>, <&dmac3 0x1d64>, + <&dmac4 0x1d63>, <&dmac4 0x1d64>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu02: ssiu-2 { + dmas = <&dmac0 0x1d65>, <&dmac0 0x1d66>, + <&dmac1 0x1d65>, <&dmac1 0x1d66>, + <&dmac2 0x1d65>, <&dmac2 0x1d66>, + <&dmac3 0x1d65>, <&dmac3 0x1d66>, + <&dmac4 0x1d65>, <&dmac4 0x1d66>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu03: ssiu-3 { + dmas = <&dmac0 0x1d67>, <&dmac0 0x1d68>, + <&dmac1 0x1d67>, <&dmac1 0x1d68>, + <&dmac2 0x1d67>, <&dmac2 0x1d68>, + <&dmac3 0x1d67>, <&dmac3 0x1d68>, + <&dmac4 0x1d67>, <&dmac4 0x1d68>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu10: ssiu-4 { + dmas = <&dmac0 0x1d69>, <&dmac0 0x1d6a>, + <&dmac1 0x1d69>, <&dmac1 0x1d6a>, + <&dmac2 0x1d69>, <&dmac2 0x1d6a>, + <&dmac3 0x1d69>, <&dmac3 0x1d6a>, + <&dmac4 0x1d69>, <&dmac4 0x1d6a>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu11: ssiu-5 { + dmas = <&dmac0 0x1d6b>, <&dmac0 0x1d6c>, + <&dmac1 0x1d6b>, <&dmac1 0x1d6c>, + <&dmac2 0x1d6b>, <&dmac2 0x1d6c>, + <&dmac3 0x1d6b>, <&dmac3 0x1d6c>, + <&dmac4 0x1d6b>, <&dmac4 0x1d6c>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu12: ssiu-6 { + dmas = <&dmac0 0x1d6d>, <&dmac0 0x1d6e>, + <&dmac1 0x1d6d>, <&dmac1 0x1d6e>, + <&dmac2 0x1d6d>, <&dmac2 0x1d6e>, + <&dmac3 0x1d6d>, <&dmac3 0x1d6e>, + <&dmac4 0x1d6d>, <&dmac4 0x1d6e>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu13: ssiu-7 { + dmas = <&dmac0 0x1d6f>, <&dmac0 0x1d70>, + <&dmac1 0x1d6f>, <&dmac1 0x1d70>, + <&dmac2 0x1d6f>, <&dmac2 0x1d70>, + <&dmac3 0x1d6f>, <&dmac3 0x1d70>, + <&dmac4 0x1d6f>, <&dmac4 0x1d70>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu20: ssiu-8 { + dmas = <&dmac0 0x1d71>, <&dmac0 0x1d72>, + <&dmac1 0x1d71>, <&dmac1 0x1d72>, + <&dmac2 0x1d71>, <&dmac2 0x1d72>, + <&dmac3 0x1d71>, <&dmac3 0x1d72>, + <&dmac4 0x1d71>, <&dmac4 0x1d72>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu21: ssiu-9 { + dmas = <&dmac0 0x1d73>, <&dmac0 0x1d74>, + <&dmac1 0x1d73>, <&dmac1 0x1d74>, + <&dmac2 0x1d73>, <&dmac2 0x1d74>, + <&dmac3 0x1d73>, <&dmac3 0x1d74>, + <&dmac4 0x1d73>, <&dmac4 0x1d74>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu22: ssiu-10 { + dmas = <&dmac0 0x1d75>, <&dmac0 0x1d76>, + <&dmac1 0x1d75>, <&dmac1 0x1d76>, + <&dmac2 0x1d75>, <&dmac2 0x1d76>, + <&dmac3 0x1d75>, <&dmac3 0x1d76>, + <&dmac4 0x1d75>, <&dmac4 0x1d76>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu23: ssiu-11 { + dmas = <&dmac0 0x1d77>, <&dmac0 0x1d78>, + <&dmac1 0x1d77>, <&dmac1 0x1d78>, + <&dmac2 0x1d77>, <&dmac2 0x1d78>, + <&dmac3 0x1d77>, <&dmac3 0x1d78>, + <&dmac4 0x1d77>, <&dmac4 0x1d78>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu30: ssiu-12 { + dmas = <&dmac0 0x1d79>, <&dmac0 0x1d7a>, + <&dmac1 0x1d79>, <&dmac1 0x1d7a>, + <&dmac2 0x1d79>, <&dmac2 0x1d7a>, + <&dmac3 0x1d79>, <&dmac3 0x1d7a>, + <&dmac4 0x1d79>, <&dmac4 0x1d7a>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu31: ssiu-13 { + dmas = <&dmac0 0x1d7b>, <&dmac0 0x1d7c>, + <&dmac1 0x1d7b>, <&dmac1 0x1d7c>, + <&dmac2 0x1d7b>, <&dmac2 0x1d7c>, + <&dmac3 0x1d7b>, <&dmac3 0x1d7c>, + <&dmac4 0x1d7b>, <&dmac4 0x1d7c>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu32: ssiu-14 { + dmas = <&dmac0 0x1d7d>, <&dmac0 0x1d7e>, + <&dmac1 0x1d7d>, <&dmac1 0x1d7e>, + <&dmac2 0x1d7d>, <&dmac2 0x1d7e>, + <&dmac3 0x1d7d>, <&dmac3 0x1d7e>, + <&dmac4 0x1d7d>, <&dmac4 0x1d7e>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu33: ssiu-15 { + dmas = <&dmac0 0x1d7f>, <&dmac0 0x1d80>, + <&dmac1 0x1d7f>, <&dmac1 0x1d80>, + <&dmac2 0x1d7f>, <&dmac2 0x1d80>, + <&dmac3 0x1d7f>, <&dmac3 0x1d80>, + <&dmac4 0x1d7f>, <&dmac4 0x1d80>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu40: ssiu-16 { + dmas = <&dmac0 0x1d81>, <&dmac0 0x1d82>, + <&dmac1 0x1d81>, <&dmac1 0x1d82>, + <&dmac2 0x1d81>, <&dmac2 0x1d82>, + <&dmac3 0x1d81>, <&dmac3 0x1d82>, + <&dmac4 0x1d81>, <&dmac4 0x1d82>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu41: ssiu-17 { + dmas = <&dmac0 0x1d83>, <&dmac0 0x1d84>, + <&dmac1 0x1d83>, <&dmac1 0x1d84>, + <&dmac2 0x1d83>, <&dmac2 0x1d84>, + <&dmac3 0x1d83>, <&dmac3 0x1d84>, + <&dmac4 0x1d83>, <&dmac4 0x1d84>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu42: ssiu-18 { + dmas = <&dmac0 0x1d85>, <&dmac0 0x1d86>, + <&dmac1 0x1d85>, <&dmac1 0x1d86>, + <&dmac2 0x1d85>, <&dmac2 0x1d86>, + <&dmac3 0x1d85>, <&dmac3 0x1d86>, + <&dmac4 0x1d85>, <&dmac4 0x1d86>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu43: ssiu-19 { + dmas = <&dmac0 0x1d87>, <&dmac0 0x1d88>, + <&dmac1 0x1d87>, <&dmac1 0x1d88>, + <&dmac2 0x1d87>, <&dmac2 0x1d88>, + <&dmac3 0x1d87>, <&dmac3 0x1d88>, + <&dmac4 0x1d87>, <&dmac4 0x1d88>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu50: ssiu-20 { + dmas = <&dmac0 0x1d89>, <&dmac0 0x1d8a>, + <&dmac1 0x1d89>, <&dmac1 0x1d8a>, + <&dmac2 0x1d89>, <&dmac2 0x1d8a>, + <&dmac3 0x1d89>, <&dmac3 0x1d8a>, + <&dmac4 0x1d89>, <&dmac4 0x1d8a>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu60: ssiu-21 { + dmas = <&dmac0 0x1d8b>, <&dmac0 0x1d8c>, + <&dmac1 0x1d8b>, <&dmac1 0x1d8c>, + <&dmac2 0x1d8b>, <&dmac2 0x1d8c>, + <&dmac3 0x1d8b>, <&dmac3 0x1d8c>, + <&dmac4 0x1d8b>, <&dmac4 0x1d8c>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu70: ssiu-22 { + dmas = <&dmac0 0x1d8d>, <&dmac0 0x1d8e>, + <&dmac1 0x1d8d>, <&dmac1 0x1d8e>, + <&dmac2 0x1d8d>, <&dmac2 0x1d8e>, + <&dmac3 0x1d8d>, <&dmac3 0x1d8e>, + <&dmac4 0x1d8d>, <&dmac4 0x1d8e>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu80: ssiu-23 { + dmas = <&dmac0 0x1d8f>, <&dmac0 0x1d90>, + <&dmac1 0x1d8f>, <&dmac1 0x1d90>, + <&dmac2 0x1d8f>, <&dmac2 0x1d90>, + <&dmac3 0x1d8f>, <&dmac3 0x1d90>, + <&dmac4 0x1d8f>, <&dmac4 0x1d90>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu90: ssiu-24 { + dmas = <&dmac0 0x1d91>, <&dmac0 0x1d92>, + <&dmac1 0x1d91>, <&dmac1 0x1d92>, + <&dmac2 0x1d91>, <&dmac2 0x1d92>, + <&dmac3 0x1d91>, <&dmac3 0x1d92>, + <&dmac4 0x1d91>, <&dmac4 0x1d92>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu91: ssiu-25 { + dmas = <&dmac0 0x1d93>, <&dmac0 0x1d94>, + <&dmac1 0x1d93>, <&dmac1 0x1d94>, + <&dmac2 0x1d93>, <&dmac2 0x1d94>, + <&dmac3 0x1d93>, <&dmac3 0x1d94>, + <&dmac4 0x1d93>, <&dmac4 0x1d94>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu92: ssiu-26 { + dmas = <&dmac0 0x1d95>, <&dmac0 0x1d96>, + <&dmac1 0x1d95>, <&dmac1 0x1d96>, + <&dmac2 0x1d95>, <&dmac2 0x1d96>, + <&dmac3 0x1d95>, <&dmac3 0x1d96>, + <&dmac4 0x1d95>, <&dmac4 0x1d96>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu93: ssiu-27 { + dmas = <&dmac0 0x1d97>, <&dmac0 0x1d98>, + <&dmac1 0x1d97>, <&dmac1 0x1d98>, + <&dmac2 0x1d97>, <&dmac2 0x1d98>, + <&dmac3 0x1d97>, <&dmac3 0x1d98>, + <&dmac4 0x1d97>, <&dmac4 0x1d98>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + }; + }; + wdt1: watchdog@14400000 { compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; reg = <0 0x14400000 0 0x400>; From c42be528a5a4da70eefa7d2e531dc719a8d103a4 Mon Sep 17 00:00:00 2001 From: John Madieu Date: Fri, 19 Jun 2026 08:39:49 +0000 Subject: [PATCH 19/29] arm64: dts: renesas: rzg3e-smarc-som: Add Versa3 clock generator Add the Renesas 5P35023 (Versa3) programmable clock generator on the I2C2 bus along with its 24MHz input clock (x2 oscillator) to feed the audio subsystem. The Versa3 provides the following clock outputs: - Output 0: 24MHz (reference), - Output 1: 12.288MHz (audio, 48kHz family), - Output 2: 11.2896MHz (audio, 44.1kHz family), - Output 3: 12.288MHz (audio), - Output 4: 25MHz (DIFF1, Ethernet). These clocks are required for the audio codec and the Ethernet controller found on the RZ/G3E SMARC EVK. Output 5 (DIFF2) is left out, as it is not connected on this board. Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260619083951.3777556-3-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 15c22dbf0ad3..455ed35ae5d3 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -78,6 +78,12 @@ reg_vdd0p8v_others: regulator-vdd0p8v-others { regulator-always-on; }; + x2: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + /* 32.768kHz crystal */ x3: x3-clock { compatible = "fixed-clock"; @@ -137,6 +143,20 @@ raa215300: pmic@12 { interrupts-extended = <&pinctrl RZG3E_GPIO(S, 1) IRQ_TYPE_EDGE_FALLING>; }; + + versa3: clock-generator@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x2>; + + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>; + assigned-clock-rates = <24000000>, <12288000>, + <11289600>, <12288000>, + <25000000>; + }; }; &i3c { From 14d21efe16dc5b92774a987ada0868e0bcf3dd91 Mon Sep 17 00:00:00 2001 From: John Madieu Date: Fri, 19 Jun 2026 08:39:50 +0000 Subject: [PATCH 20/29] arm64: dts: renesas: rzg3e-smarc-som: Add audio pinmux definitions Add pinmux definitions for SSI3/SSI4 audio interface on RZ/G3E SMARC SoM: - sound_clk_pins: AUDIO_CLKB and AUDIO_CLKC clock outputs, - sound_pins: SSI3_SCK, SSI3_WS, SSI3_SDATA (playback) and SSI4_SDATA (capture). Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260619083951.3777556-4-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 455ed35ae5d3..0e6dc84e0199 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -352,6 +352,18 @@ sd2-pwen { }; }; + sound_clk_pins: sound-clk { + pinmux = , /* AUDIO_CLKB */ + ; /* AUDIO_CLKC */ + }; + + sound_pins: sound { + pinmux = , /* SSI3_SDATA */ + , /* SSI3_SCK */ + , /* SSI3_WS */ + ; /* SSI4_SDATA */ + }; + xspi_pins: xspi0 { pinmux = , /* XSPI0_IO0 */ , /* XSPI0_IO1 */ From 3e23d2548ddb2d73b26b85c990a77925a9cf7f86 Mon Sep 17 00:00:00 2001 From: John Madieu Date: Fri, 19 Jun 2026 08:39:51 +0000 Subject: [PATCH 21/29] arm64: dts: renesas: r9a09g047e57-smarc: Add DA7212 audio codec support RZ/G3E SMARC board has a DA7212 audio codec connected via I2C1 for sound input/output using SSI3/SSI4 where: - The codec receives its master clock from the Versa3 clock generator present on the SoM, - SSI4 shares clock pins with SSI3 to provide a separate data line for full-duplex audio capture. Enable audio support on RZ/G3E SMARC2 EVK boards with a DA7212 audio codec. Reviewed-by: Geert Uytterhoeven Signed-off-by: John Madieu Link: https://patch.msgid.link/20260619083951.3777556-5-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g047e57-smarc.dts | 112 ++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 07db9e434521..4eed095b683b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -32,6 +32,37 @@ #include "rzg3e-smarc-som.dtsi" #include "renesas-smarc2.dtsi" +/* + * SSI-DA7212 + * + * These commands are required when Playback/Capture + * + * amixer -q cset name='Aux Switch' on + * amixer -q cset name='Mixin Left Aux Left Switch' on + * amixer -q cset name='Mixin Right Aux Right Switch' on + * amixer -q cset name='ADC Switch' on + * amixer -q cset name='Mixout Right Mixin Right Switch' off + * amixer -q cset name='Mixout Left Mixin Left Switch' off + * amixer -q cset name='Headphone Volume' 70% + * amixer -q cset name='Headphone Switch' on + * amixer -q cset name='Mixout Left DAC Left Switch' on + * amixer -q cset name='Mixout Right DAC Right Switch' on + * amixer -q cset name='DAC Left Source MUX' 'DAI Input Left' + * amixer -q cset name='DAC Right Source MUX' 'DAI Input Right' + * amixer -q sset 'Mic 1 Amp Source MUX' 'MIC_P' + * amixer -q sset 'Mic 2 Amp Source MUX' 'MIC_P' + * amixer -q sset 'Mixin Left Mic 1' on + * amixer -q sset 'Mixin Right Mic 2' on + * amixer -q sset 'Mic 1' 90% on + * amixer -q sset 'Mic 2' 90% on + * amixer -q sset 'Lineout' 80% on + * amixer -q set "Headphone" 100% on + * + * When Capture chained with DVC, use this command to amplify sound + * amixer set 'DVC In',0 80% + * For playback, use: amixer set 'DVC Out',0 80% + */ + / { model = "Renesas SMARC EVK version 2 based on r9a09g047e57"; compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm", @@ -55,6 +86,22 @@ vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd { gpios-states = <0>; states = <3300000 0>, <1800000 1>; }; + + sound_card: sound { + compatible = "audio-graph-card"; + + label = "snd-rzg3e"; + + dais = <&rsnd_port0>; /* DA7212 */ + }; +}; + +&audio_clkb { + clock-frequency = <11289600>; +}; + +&audio_clkc { + clock-frequency = <12288000>; }; &canfd { @@ -99,6 +146,35 @@ &i2c0 { pinctrl-names = "default"; }; +&i2c1 { + da7212: codec@1a { + compatible = "dlg,da7212"; + #sound-dai-cells = <0>; + reg = <0x1a>; + + clocks = <&versa3 1>; + clock-names = "mclk"; + + dlg,micbias1-lvl = <2500>; + dlg,micbias2-lvl = <2500>; + dlg,dmic-data-sel = "lrise_rfall"; + dlg,dmic-samplephase = "between_clkedge"; + dlg,dmic-clkrate = <3000000>; + + VDDA-supply = <®_1p8v>; + VDDSP-supply = <®_3p3v>; + VDDMIC-supply = <®_3p3v>; + VDDIO-supply = <®_1p8v>; + + port { + da7212_endpoint: endpoint { + remote-endpoint = <&rsnd_endpoint0>; + mclk-fs = <256>; + }; + }; + }; +}; + &keys { pinctrl-0 = <&nmi_pins>; pinctrl-names = "default"; @@ -280,6 +356,42 @@ &sdhi1 { vqmmc-supply = <&vqmmc_sd1_pvdd>; }; +&snd_rzg3e { + pinctrl-0 = <&sound_clk_pins &sound_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* audio_clkout */ + #clock-cells = <0>; + clock-frequency = <11289600>; + + /* Multi DAI */ + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + rsnd_port0: port@0 { + reg = <0>; + rsnd_endpoint0: endpoint { + remote-endpoint = <&da7212_endpoint>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint0>; + frame-master = <&rsnd_endpoint0>; + + playback = <&ssi3>, <&src1>, <&dvc1>; + capture = <&ssi4>, <&src0>, <&dvc0>; + }; + }; + }; +}; + +&ssi4 { + shared-pin; +}; + &usb3_phy { status = "okay"; }; From 92b4465b221e4e1b38d56b6ce8290949555b72bd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 21 Jun 2026 04:50:21 +0200 Subject: [PATCH 22/29] arm64: dts: renesas: Add soc: labels to soc nodes Add soc: labels to the /soc {} nodes to align DTS with r8a77951.dtsi which already has that soc: label. The soc: label is useful in U-Boot where it is used in U-Boot extras DT fragments. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260621025052.406507-1-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-2-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-3-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-4-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-5-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-6-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-7-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-8-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-9-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 36675f5bcdea..e66d86db6e6c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -262,7 +262,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index ceef0104f75e..62c6703917db 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -146,7 +146,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 9df5f1a42400..0ae9bb72d2dd 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -326,7 +326,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index ad36aa8e7543..4f9989b5e77a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -311,7 +311,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 9d76e39eab72..ad4491ba948f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -311,7 +311,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 611a9335c63a..70708f5cf746 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -182,7 +182,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 1f6676e2795a..f7f1f280fa0b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -91,7 +91,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 86b7792d68fa..514dafe34478 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -120,7 +120,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 5f3fcef7560c..522a49db0258 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -85,7 +85,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; From 7589467672a86ae29f2f62715166f88a054f4b54 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 22 Jun 2026 18:07:33 +0100 Subject: [PATCH 23/29] arm64: dts: renesas: rzt2h-n2h-evk-common: Add memory nodes Add memory nodes for the RZ/T2H and RZ/N2H EVK boards. These boards populate 8GiB of DDR memory, which is exposed through two address ranges. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260622170733.1703585-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index ceccddb92d40..ffcc0960903b 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -29,6 +29,17 @@ chosen { stdout-path = "serial0:115200n8"; }; + memory@c8000000 { + device_type = "memory"; + /* first 128MiB is reserved for secure area. */ + reg = <0x0 0xc8000000 0x0 0x38000000>; + }; + + memory@240000000 { + device_type = "memory"; + reg = <0x2 0x40000000 0x1 0xc0000000>; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; From a91b23a9d0ea08ed20df34bf2d9e9b10eb8da4c1 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 26 Jun 2026 20:03:24 +0200 Subject: [PATCH 24/29] ARM: dts: renesas: r9a06g032: Describe SPI controllers Add nodes for the 6 SPI controllers of the Renesas RZ/N1D SoC. The first 4 can only be controllers, the latter 2 can only be targets. DMA nodes are not added yet because DMA needs some extra code in the drivers and cannot be tested yet. Basic FIFO mode works reliably, though. Signed-off-by: Wolfram Sang Tested-by: Herve Codina Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260626180326.9593-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 84 ++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 442ea26b40f5..19c9bce0a26d 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -563,6 +563,90 @@ gic: interrupt-controller@44101000 { ; }; + /* Controller only */ + spi1: spi@50005000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x50005000 0x200>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_SPI0>, <&sysctrl R9A06G032_HCLK_SPI0>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + num-cs = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* Controller only */ + spi2: spi@50006000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x50006000 0x200>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_SPI1>, <&sysctrl R9A06G032_HCLK_SPI1>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + num-cs = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* Controller only */ + spi3: spi@50007000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x50007000 0x200>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_SPI2>, <&sysctrl R9A06G032_HCLK_SPI2>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + num-cs = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* Controller only */ + spi4: spi@50008000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x50008000 0x200>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_SPI3>, <&sysctrl R9A06G032_HCLK_SPI3>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + num-cs = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* Target only */ + spi5: spi@50009000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x50009000 0x200>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_SPI4>, <&sysctrl R9A06G032_HCLK_SPI4>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + spi-slave; + #address-cells = <0>; + #size-cells = <0>; + status = "disabled"; + }; + + /* Target only */ + spi6: spi@5000a000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x5000a000 0x200>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_SPI5>, <&sysctrl R9A06G032_HCLK_SPI5>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + spi-slave; + #address-cells = <0>; + #size-cells = <0>; + status = "disabled"; + }; + /* * The GPIO mapping to the corresponding pins is not obvious. * See the hardware documentation for details. From f4f9b372a8a6aeb9b95e9ca4d9542b384ebb983c Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 26 Jun 2026 20:03:25 +0200 Subject: [PATCH 25/29] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI-FRAM Activate the FRAM and the SPI bus which it is attached to. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260626180326.9593-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a06g032-rzn1d400-eb.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts index 97a339b30d76..ead379988fb1 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts @@ -53,6 +53,10 @@ led@1 { }; }; +&gpio2 { + status = "okay"; +}; + &i2c2 { /* Sensors are different across revisions. All are LM75B compatible */ sensor@49 { @@ -152,6 +156,13 @@ pins_sdio1_clk: pins-sdio1-clk { drive-strength = <12>; }; + pins_spi1: pins-spi1 { + pinmux = , + , + , + ; + }; + pins_uart2: pins-uart2 { pinmux = , , @@ -168,6 +179,20 @@ &sdio1 { status = "okay"; }; +&spi1 { + pinctrl-0 = <&pins_spi1>; + pinctrl-names = "default"; + status = "okay"; + + cs-gpios = <&gpio2a 31 GPIO_ACTIVE_LOW>; + + fram: fram@0 { + compatible = "cypress,fm25", "atmel,at25"; + reg = <0>; + spi-max-frequency = <12500000>; + }; +}; + &switch { pinctrl-0 = <&pins_eth1>, <&pins_eth2>, <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>; From c73b080d1d1bf89775d69f2e249820e3e242814b Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 8 Jul 2026 17:33:10 +0100 Subject: [PATCH 26/29] arm64: dts: renesas: r9a09g057: Add PCIe nodes Add PCIe nodes to Renesas RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260708163311.222176-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 140 +++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 8af0f0f2f2f7..639693d464a7 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -1041,6 +1041,146 @@ rsci9: serial@12803000 { status = "disabled"; }; + pcie0: pcie@13400000 { + compatible = "renesas,r9a09g057-pcie"; + reg = <0 0x13400000 0 0x10000>; + ranges = <0x02000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, + <0x43000000 0x4 0x40000000 0x4 0x40000000 0x6 0x00000000>; + dma-ranges = <0x43000000 0x0 0x40000000 0x0 0x40000000 0x4 0x00000000>; + bus-range = <0x0 0xff>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all", + "link_equalization_request", + "turn_off_event", "pmu_poweroff", + "d3_event_f0", "d3_event_f1", + "cfg_pmcsr_writeclear_f0", + "cfg_pmcsr_writeclear_f1"; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie0 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie0 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie0 0 0 0 3>; /* INTD */ + clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>; + clock-names = "aclk", "pmu"; + resets = <&cpg 0xb2>; + reset-names = "aresetn"; + power-domains = <&cpg>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + num-lanes = <2>; + renesas,sysc = <&sys 0>; + status = "disabled"; + + pcie_port0: pcie@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type = "pci"; + vendor-id = <0x1912>; + device-id = <0x003b>; + #address-cells = <3>; + #size-cells = <2>; + }; + }; + + pcie1: pcie@13410000 { + compatible = "renesas,r9a09g057-pcie"; + reg = <0 0x13410000 0 0x10000>; + ranges = <0x02000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, + <0x43000000 0xa 0x40000000 0xa 0x40000000 0x5 0xc0000000>; + dma-ranges = <0x43000000 0x0 0x40000000 0x0 0x40000000 0x4 0x00000000>; + bus-range = <0x0 0xff>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all", + "link_equalization_request", + "turn_off_event", "pmu_poweroff", + "d3_event_f0", "d3_event_f1", + "cfg_pmcsr_writeclear_f0", + "cfg_pmcsr_writeclear_f1"; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie1 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie1 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie1 0 0 0 3>; /* INTD */ + clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>; + clock-names = "aclk", "pmu"; + resets = <&cpg 0xb2>; + reset-names = "aresetn"; + power-domains = <&cpg>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + num-lanes = <2>; + renesas,sysc = <&sys 1>; + status = "disabled"; + + pcie_port1: pcie@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type = "pci"; + vendor-id = <0x1912>; + device-id = <0x003b>; + #address-cells = <3>; + #size-cells = <2>; + }; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; From 90a9d595f36ba11d95568acfda641a7e371f627d Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 8 Jul 2026 17:33:11 +0100 Subject: [PATCH 27/29] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable PCIe Enable the PCIE1 slot which is connected to PCIe0 channel. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260708163311.222176-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 3c1ddacc0944..637fc92dcc26 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -384,6 +384,18 @@ &ostm7 { status = "okay"; }; +&pcie0 { + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + num-lanes = <4>; + status = "okay"; +}; + +&pcie_port0 { + clocks = <&versa3 5>; + clock-names = "ref"; +}; + &pinctrl { eth0_pins: eth0 { pins = "ET0_TXC_TXCLK"; @@ -430,6 +442,12 @@ i2c8_pins: i2c8 { ; /* I2C8_SCL */ }; + pcie0_pins: pcie0 { + pins = "PCIE0_RSTOUTB"; + slew-rate = <0>; + renesas,output-impedance = <2>; + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; From 3e7259fb8a31c8b784628cfc417998447b0e5629 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 8 Jul 2026 18:28:48 +0100 Subject: [PATCH 28/29] arm64: dts: renesas: r9a09g056: Fix PCIe dma-ranges memory space code The RZ/V2N SoC supports up to 8 GiB of memory. Update the PCIe dma-ranges property to use the 64-bit prefetchable memory space code. Fixes: 4c443296ff17 ("arm64: dts: renesas: r9a09g056: Add PCIe node") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260708172849.227915-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 3a308dbf733c..76fa34ff3d07 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -1065,7 +1065,7 @@ pcie: pcie@13400000 { reg = <0 0x13400000 0 0x10000>; ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>, <0x43000000 4 0x40000000 4 0x40000000 6 0x00000000>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 2 0x00000000>; + dma-ranges = <0x43000000 0 0x40000000 0 0x40000000 2 0x00000000>; bus-range = <0x0 0xff>; interrupts = , , From 24afcb87e6aca1ff3face276223eeea0012f8e2b Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 8 Jul 2026 18:28:49 +0100 Subject: [PATCH 29/29] arm64: dts: renesas: r9a09g047: Fix PCIe dma-ranges memory space code The RZ/G3E SoC supports up to 8 GiB of memory. Update the PCIe dma-ranges property to use the 64-bit prefetchable memory space code. Fixes: 1ac57c9830cb ("arm64: dts: renesas: r9a09g047: Add PCIe node") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260708172849.227915-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 310f988a63c4..73757e8e2197 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -1447,7 +1447,7 @@ pcie: pcie@13400000 { reg = <0 0x13400000 0 0x10000>; ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x43000000 4 0x40000000 4 0x40000000 6 0x00000000>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 2 0x00000000>; + dma-ranges = <0x43000000 0 0x40000000 0 0x40000000 2 0x00000000>; bus-range = <0x0 0xff>; interrupts = , ,