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arm64: dts: imx8qm-var-som: Add support for Variscite Symphony board
Add device tree support for the Variscite Symphony carrier board with the VAR-SOM-MX8 QuadMax system on module. The Symphony board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart, SPI and I2C interfaces - GPIO Expanders - RTC module - TPM module - CAN peripherals - PCIE support Link: https://variscite.com/carrier-boards/symphony-board/ Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Stefano Radaelli
Frank Li
parent
868ced4df4
commit
a40fdbf706
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@ -543,6 +543,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8qm-tqma8qm-mba8x.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8qm-var-som-symphony.dtb
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imx8qm-mek-ov5640-csi0-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo
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dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-csi0.dtb
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490
arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts
Normal file
490
arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts
Normal file
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@ -0,0 +1,490 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Variscite Symphony carrier board for VAR-SOM-MX8 QuadMax
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*
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* Link: https://variscite.com/carrier-boards/symphony-board/
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*
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* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
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*
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include "imx8qm-var-som.dtsi"
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/ {
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model = "Variscite VAR-SOM-MX8 on Symphony evaluation board";
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compatible = "variscite,var-som-imx8qm-symphony",
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"variscite,var-som-imx8qm", "fsl,imx8qm";
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chosen {
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stdout-path = &lpuart0;
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};
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gpio-keys {
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compatible = "gpio-keys";
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button-back {
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label = "Back";
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gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_BACK>;
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};
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button-home {
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label = "Home";
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gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_HOME>;
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};
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button-menu {
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label = "Menu";
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gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_MENU>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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led-heartbeat {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "heartbeat";
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};
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};
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reg_fec_phy: regulator-fec-phy {
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compatible = "regulator-fixed";
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regulator-name = "fec-phy";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <20000>;
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vin-supply = <®_vselect>;
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gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&lsio_gpio0 18 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
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compatible = "regulator-fixed";
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regulator-name = "sw-3p3-sd1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_vselect: regulator-vselect {
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compatible = "regulator-fixed";
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regulator-name = "reg_vselect";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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gpio = <&pca9534 6 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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ðphy0 {
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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linux,default-trigger = "netdev";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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linux,default-trigger = "netdev";
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};
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};
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};
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&fec1 {
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mdio {
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ethphy1: ethernet-phy@5 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <5>;
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vddio-supply = <®_phy_vddio>;
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reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <100000>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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linux,default-trigger = "netdev";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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linux,default-trigger = "netdev";
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};
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};
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};
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};
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec2>;
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/*
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* The required RGMII TX and RX 2ns delays are implemented directly
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* in hardware via passive delay elements on the SOM PCB.
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* No delay configuration is needed in software via PHY driver.
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*/
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phy-mode = "rgmii";
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phy-handle = <ðphy1>;
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phy-supply = <®_fec_phy>;
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status = "okay";
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "okay";
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};
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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status = "okay";
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};
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&hsio_phy {
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fsl,hsio-cfg = "pciea-pcieb-sata";
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fsl,refclk-pad-mode = "input";
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pca9534: gpio@20 {
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compatible = "nxp,pca9534";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pca9534>;
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interrupt-parent = <&lsio_gpio1>;
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interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
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};
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/* USB Type-C Controller */
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typec_ptn5150: typec@3d {
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compatible = "nxp,ptn5150";
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reg = <0x3d>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ptn5150>;
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interrupt-parent = <&lsio_gpio3>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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port {
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typec_dr_sw: endpoint {
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remote-endpoint = <&usb3_drd_sw>;
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};
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};
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};
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};
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&i2c4 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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status = "okay";
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pca6408: gpio@21 {
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compatible = "nxp,pcal6408";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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/* RGB_SEL */
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lvds-brg-enable-hog {
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gpio-hog;
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gpios = <7 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "lvds_brg_en";
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};
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};
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st33ktpm2xi2c: tpm@2e {
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compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
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reg = <0x2e>;
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label = "tpm";
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reset-gpios = <&pca6408 4 GPIO_ACTIVE_LOW>;
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};
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/* Capacitive touch */
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ft5x06_ts: touchscreen@38 {
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compatible = "edt,edt-ft5406";
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pinctrl-names = "default";
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reg = <0x38>;
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pinctrl-0 = <&pinctrl_captouch>;
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interrupt-parent = <&lsio_gpio0>;
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interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
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touchscreen-size-x = <800>;
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touchscreen-size-y = <480>;
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touchscreen-inverted-x;
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touchscreen-inverted-y;
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wakeup-source;
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};
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rtc@68 {
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compatible = "dallas,ds1337";
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reg = <0x68>;
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};
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};
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&lpspi1 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpspi1>;
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cs-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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/* console */
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&lpuart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart0>;
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status = "okay";
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};
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/* header */
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&lpuart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart2>;
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status = "okay";
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};
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&pca9534 {
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usb3-signal-route-hog {
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gpio-hog;
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gpios = <4 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "usb3_signal_route";
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};
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};
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&pciea{
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phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
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phy-names = "pcie-phy";
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status = "okay";
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};
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&pciea_port0 {
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reset-gpios = <&pca6408 1 GPIO_ACTIVE_LOW>;
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};
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&usb3_phy {
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "host";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1>;
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vbus-supply = <®_usb_otg1_vbus>;
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srp-disable;
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hnp-disable;
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adp-disable;
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disable-over-current;
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status = "okay";
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};
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&usbotg3 {
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status = "okay";
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};
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&usbotg3_cdns3 {
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dr_mode = "otg";
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usb-role-switch;
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status = "okay";
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port {
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usb3_drd_sw: endpoint {
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remote-endpoint = <&typec_dr_sw>;
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};
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};
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};
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&usbphy1 {
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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bus-width = <4>;
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cd-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_captouch: captouchgrp {
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fsl,pins = <
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IMX8QM_GPT1_COMPARE_LSIO_GPIO0_IO19 0x06000021
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>;
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};
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pinctrl_fec2: fec2grp {
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fsl,pins = <
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IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000048
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IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000048
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IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000048
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IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000048
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IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000048
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IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000048
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IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000048
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IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000048
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IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000048
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IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000048
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IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000048
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IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000048
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>;
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};
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pinctrl_flexcan1: flexcan0grp {
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fsl,pins = <
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IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x00000021
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IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x00000021
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>;
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};
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pinctrl_flexcan2: flexcan1grp {
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fsl,pins = <
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IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x00000021
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IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x00000021
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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IMX8QM_USB_SS3_TC3_DMA_I2C1_SDA 0xc6000020
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IMX8QM_USB_SS3_TC1_DMA_I2C1_SCL 0xc6000020
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>;
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};
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pinctrl_i2c4: i2c4grp {
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fsl,pins = <
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IMX8QM_ENET1_MDC_DMA_I2C4_SCL 0xc6000020
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IMX8QM_ENET1_MDIO_DMA_I2C4_SDA 0xc6000020
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>;
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};
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pinctrl_lpspi1: lpspi1grp {
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fsl,pins = <
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IMX8QM_ADC_IN3_DMA_SPI1_SCK 0x0600004c
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IMX8QM_ADC_IN4_DMA_SPI1_SDO 0x0600004c
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IMX8QM_ADC_IN5_DMA_SPI1_SDI 0x0600004c
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IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 0x00000021
|
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>;
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};
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020
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IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020
|
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>;
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};
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pinctrl_lpuart2: lpuart2grp {
|
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fsl,pins = <
|
||||
IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020
|
||||
IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020
|
||||
>;
|
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};
|
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|
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pinctrl_pca9534: pca9534grp {
|
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fsl,pins = <
|
||||
IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 0x00000021
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ptn5150: ptn5150grp {
|
||||
fsl,pins = <
|
||||
IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg1: otg1grp {
|
||||
fsl,pins = <
|
||||
IMX8QM_GPT1_CAPTURE_LSIO_GPIO0_IO18 0x06000048
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
|
||||
IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
|
||||
IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
|
||||
IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
|
||||
IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
|
||||
IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
|
||||
IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||||
fsl,pins = <
|
||||
IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
|
||||
IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
|
||||
IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
|
||||
IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
|
||||
IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
|
||||
IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
|
||||
IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins = <
|
||||
IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
|
||||
IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
|
||||
IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
|
||||
IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
|
||||
IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
|
||||
IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
|
||||
IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
|
||||
fsl,pins = <
|
||||
IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0x00000021
|
||||
>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user