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arm64: dts: freescale: Add support for Variscite VAR-SOM-MX8 QuadMax
Add device tree support for the Variscite VAR-SOM-MX8 QuadMax system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX8 QuadMax MPU processor - Up to 8GB of LPDDR4 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8-quadmax-quadplus/var-som-mx8/ Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Stefano Radaelli
Frank Li
parent
4a3f4d08f5
commit
868ced4df4
531
arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi
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531
arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Common dtsi for Variscite VAR-SOM-MX8
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*
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* Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8-quadmax-quadplus/var-som-mx8/
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*
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* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
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*
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*/
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/dts-v1/;
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#include "imx8qm.dtsi"
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/ {
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model = "Variscite i.MX8QM VAR-SOM-MX8 Module";
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compatible = "variscite,var-som-imx8qm", "fsl,imx8qm";
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x40000000>;
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};
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reg_audio_supply: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "wm8904-supply";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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reg_phy_vddio: regulator-phy-vddio {
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compatible = "regulator-fixed";
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regulator-name = "vddio-1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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vdev0vring0: memory@90000000 {
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reg = <0 0x90000000 0 0x8000>;
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no-map;
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};
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vdev0vring1: memory@90008000 {
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reg = <0 0x90008000 0 0x8000>;
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no-map;
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};
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vdev1vring0: memory@90010000 {
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reg = <0 0x90010000 0 0x8000>;
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no-map;
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};
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vdev1vring1: memory@90018000 {
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reg = <0 0x90018000 0 0x8000>;
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no-map;
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};
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rsc_table0: memory@900ff000 {
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reg = <0 0x900ff000 0 0x1000>;
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no-map;
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};
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vdev2vring0: memory@90100000 {
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reg = <0 0x90100000 0 0x8000>;
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no-map;
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};
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vdev2vring1: memory@90108000 {
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reg = <0 0x90108000 0 0x8000>;
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no-map;
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};
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vdev3vring0: memory@90110000 {
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reg = <0 0x90110000 0 0x8000>;
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no-map;
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};
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vdev3vring1: memory@90118000 {
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reg = <0 0x90118000 0 0x8000>;
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no-map;
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};
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rsc_table1: memory@901ff000 {
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reg = <0 0x901ff000 0 0x1000>;
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no-map;
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};
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vdevbuffer: memory@90400000 {
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compatible = "shared-dma-pool";
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reg = <0 0x90400000 0 0x100000>;
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no-map;
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};
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dsp_reserved: memory@92400000 {
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reg = <0 0x92400000 0 0x1000000>;
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no-map;
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};
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dsp_vdev0vring0: memory@942f0000 {
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reg = <0 0x942f0000 0 0x8000>;
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no-map;
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};
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dsp_vdev0vring1: memory@942f8000 {
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reg = <0 0x942f8000 0 0x8000>;
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no-map;
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};
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dsp_vdev0buffer: memory@94300000 {
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compatible = "shared-dma-pool";
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reg = <0 0x94300000 0 0x100000>;
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no-map;
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};
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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/* VAR-SOM-MX8QM doesn't have 1GB variant */
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alloc-ranges = <0 0xc0000000 0 0x3c000000>;
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size = <0 0x3c000000>;
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linux,cma-default;
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reusable;
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};
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};
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sound-wm8904 {
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compatible = "simple-audio-card";
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simple-audio-card,bitclock-master = <&codec_dai>;
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simple-audio-card,format = "i2s";
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simple-audio-card,frame-master = <&codec_dai>;
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simple-audio-card,mclk-fs = <256>;
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simple-audio-card,name = "wm8904-audio";
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simple-audio-card,routing =
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"Headphone Jack", "HPOUTL",
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"Headphone Jack", "HPOUTR",
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"IN2L", "Line In Jack",
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"IN2R", "Line In Jack",
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"IN1L", "Microphone Jack",
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"IN1R", "Microphone Jack";
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simple-audio-card,widgets =
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"Microphone", "Microphone Jack",
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"Headphone", "Headphone Jack",
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"Line", "Line In Jack";
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codec_dai: simple-audio-card,codec {
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sound-dai = <&wm8904>;
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};
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simple-audio-card,cpu {
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sound-dai = <&esai0>;
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};
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};
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};
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&acm {
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status = "okay";
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};
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&asrc0 {
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fsl,asrc-rate = <48000>;
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status = "okay";
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};
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&asrc1 {
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fsl,asrc-rate = <48000>;
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status = "okay";
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};
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&cm41_intmux {
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status = "okay";
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};
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&esai0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esai0>;
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assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
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<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
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<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
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<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
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<&esai0_lpcg IMX_LPCG_CLK_4>;
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assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>;
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assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;
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#sound-dai-cells = <0>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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/*
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* The required RGMII TX and RX 2ns delays are implemented directly
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* in hardware via passive delay elements on the SOM PCB.
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* No delay configuration is needed in software via PHY driver.
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*/
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <4>;
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reset-gpios = <&lsio_gpio2 28 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <20000>;
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vddio-supply = <®_phy_vddio>;
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};
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};
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};
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&gpio0_mipi_csi0 {
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status = "disabled";
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};
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&gpio0_mipi_csi1 {
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status = "disabled";
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};
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&i2c0 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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status = "okay";
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wm8904: codec@1a {
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compatible = "wlf,wm8904";
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reg = <0x1a>;
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#sound-dai-cells = <0>;
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clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
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clock-names = "mclk";
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assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
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<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
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<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
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<&mclkout0_lpcg IMX_LPCG_CLK_0>;
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assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
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AVDD-supply = <®_audio_supply>;
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CPVDD-supply = <®_audio_supply>;
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DBVDD-supply = <®_audio_supply>;
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DCVDD-supply = <®_audio_supply>;
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MICVDD-supply = <®_audio_supply>;
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wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
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"soft", "music";
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/*
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* Config registers per name, respectively:
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* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
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* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
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* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
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* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
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* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
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*/
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wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
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/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
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/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
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/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
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/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
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/* GPIO1 = DMIC_CLK, don't touch others */
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wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
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};
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};
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/* Bluetooth */
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&lpuart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart1>;
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uart-has-rtscts;
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status = "okay";
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};
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&mu_m0{
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status = "okay";
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};
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&mu1_m0{
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status = "okay";
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};
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&mu2_m0{
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status = "okay";
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};
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&rtc {
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status = "disabled";
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};
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&sai6 {
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assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
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<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
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<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
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<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
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<&sai6_lpcg IMX_LPCG_CLK_4>;
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assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
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assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
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fsl,sai-asynchronous;
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status = "okay";
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};
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&sai7 {
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assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>,
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<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
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<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
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<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
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<&sai7_lpcg IMX_LPCG_CLK_4>;
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assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
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assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
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fsl,sai-asynchronous;
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status = "okay";
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};
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&thermal_zones {
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pmic-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
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trips {
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pmic_alert0: trip0 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "passive";
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};
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pmic_crit0: trip1 {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&pmic_alert0>;
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cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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/* eMMC */
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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/* WIFI */
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&usdhc3 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi>;
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bus-width = <4>;
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non-removable;
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status = "okay";
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brcmf: wifi@1 {
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compatible = "brcm,bcm4329-fmac";
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reg = <1>;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_esai0: esai0grp {
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fsl,pins = <
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IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040
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IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040
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IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040
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IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040
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IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040
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IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040
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IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc600004c
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000048
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IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048
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IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048
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IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048
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IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048
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IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048
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IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048
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IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048
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IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048
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IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048
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IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048
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IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048
|
||||
IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048
|
||||
IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048
|
||||
IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x06000028
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000041
|
||||
IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 0x00000041
|
||||
IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06 0x00000041
|
||||
IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000041
|
||||
IMX8QM_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 0x00000041
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c0: i2c0grp {
|
||||
fsl,pins = <
|
||||
IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc6000020
|
||||
IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc6000020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lpuart1: lpuart1grp {
|
||||
fsl,pins = <
|
||||
IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020
|
||||
IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020
|
||||
IMX8QM_UART1_CTS_B_DMA_UART1_RTS_B 0x06000020
|
||||
IMX8QM_UART1_RTS_B_DMA_UART1_CTS_B 0x06000020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
|
||||
IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
|
||||
IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
|
||||
IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
|
||||
IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
|
||||
IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
|
||||
IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
|
||||
IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
|
||||
IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
|
||||
IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
|
||||
IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
|
||||
IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
||||
fsl,pins = <
|
||||
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
|
||||
IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
|
||||
IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
|
||||
IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
|
||||
IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
|
||||
IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
|
||||
IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
|
||||
IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
|
||||
IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
|
||||
IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
|
||||
IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
|
||||
IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||||
fsl,pins = <
|
||||
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
|
||||
IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
|
||||
IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
|
||||
IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
|
||||
IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
|
||||
IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
|
||||
IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
|
||||
IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
|
||||
IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
|
||||
IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
|
||||
IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
|
||||
IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
|
||||
IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
|
||||
IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
|
||||
IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
|
||||
IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
|
||||
IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
|
||||
fsl,pins = <
|
||||
IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
|
||||
IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
|
||||
IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
|
||||
IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
|
||||
IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
|
||||
IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||||
fsl,pins = <
|
||||
IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
|
||||
IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
|
||||
IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
|
||||
IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
|
||||
IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
|
||||
IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wifi: wifigrp {
|
||||
fsl,pins = <
|
||||
/* GPIOs used by user space WiFi init */
|
||||
IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0xc600004c
|
||||
IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x06000021
|
||||
IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 0x00000021
|
||||
IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021
|
||||
>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user