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arm64: dts: renesas: r9a08g046: Add GBETH nodes
Renesas RZ/G3L SoC is equipped with 2x Synopsys DesignWare Ethernet (10/100/1000 BASE) with TSN, IP block version 5.30. Add GBETH nodes to R9A08G046 RZ/G3L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260326111953.31024-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das
Geert Uytterhoeven
parent
fc326550eb
commit
a357a31c34
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@ -171,6 +171,240 @@ sdhi1: mmc@11c10000 {
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/* placeholder */
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};
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eth0: ethernet@11c30000 {
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compatible = "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a";
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reg = <0 0x11c30000 0 0x10000>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 85 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 87 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 88 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 81 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 82 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 83 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 84 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 90 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 91 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
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"rx-queue-0", "rx-queue-1", "rx-queue-2",
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"rx-queue-3", "tx-queue-0", "tx-queue-1",
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"tx-queue-2", "tx-queue-3", "ptp-pps-0",
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"ptp-pps-1", "ptp-pps-2", "ptp-pps-3";
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clocks = <&cpg CPG_MOD R9A08G046_ETH0_CLK_AXI>,
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<&cpg CPG_MOD R9A08G046_ETH0_CLK_CHI>,
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<&cpg CPG_MOD R9A08G046_ETH0_CLK_PTP_REF_I>,
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<&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I>,
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<&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I>,
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<&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_180_I>,
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<&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_180_I>,
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<&cpg CPG_MOD R9A08G046_ETH0_CLK_RMII_I>,
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<&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I_RMII>,
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<&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I_RMII>;
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clock-names = "stmmaceth", "pclk", "ptp_ref",
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"tx", "rx", "tx-180", "rx-180",
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"rmii", "rmii_tx", "rmii_rx";
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resets = <&cpg R9A08G046_ETH0_ARESET_N>;
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power-domains = <&cpg>;
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snps,multicast-filter-bins = <256>;
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snps,perfect-filter-entries = <128>;
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rx-fifo-depth = <8192>;
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tx-fifo-depth = <8192>;
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snps,fixed-burst;
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snps,no-pbl-x8;
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snps,force_thresh_dma_mode;
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snps,axi-config = <&stmmac_axi_setup>;
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snps,mtl-rx-config = <&mtl_rx_setup0>;
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snps,mtl-tx-config = <&mtl_tx_setup0>;
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snps,txpbl = <32>;
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snps,rxpbl = <32>;
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status = "disabled";
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mdio0: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mtl_rx_setup0: rx-queues-config {
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snps,rx-queues-to-use = <4>;
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snps,rx-sched-sp;
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queue0 {
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snps,dcb-algorithm;
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snps,priority = <0x1>;
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snps,map-to-dma-channel = <0>;
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};
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queue1 {
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snps,dcb-algorithm;
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snps,priority = <0x2>;
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snps,map-to-dma-channel = <1>;
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};
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queue2 {
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snps,dcb-algorithm;
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snps,priority = <0x4>;
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snps,map-to-dma-channel = <2>;
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};
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queue3 {
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snps,dcb-algorithm;
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snps,priority = <0x8>;
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snps,map-to-dma-channel = <3>;
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};
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};
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mtl_tx_setup0: tx-queues-config {
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snps,tx-queues-to-use = <4>;
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snps,tx-sched-wrr;
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queue0 {
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snps,weight = <0x10>;
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snps,dcb-algorithm;
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snps,priority = <0x1>;
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};
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queue1 {
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snps,weight = <0x12>;
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snps,dcb-algorithm;
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snps,priority = <0x2>;
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};
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queue2 {
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snps,weight = <0x14>;
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snps,dcb-algorithm;
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snps,priority = <0x4>;
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};
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queue3 {
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snps,weight = <0x18>;
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snps,dcb-algorithm;
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snps,priority = <0x8>;
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};
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};
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};
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eth1: ethernet@11c40000 {
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compatible = "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a";
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reg = <0 0x11c40000 0 0x10000>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 102 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 96 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 97 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 98 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 99 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 104 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 105 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 106 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 107 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
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"rx-queue-0", "rx-queue-1", "rx-queue-2",
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"rx-queue-3", "tx-queue-0", "tx-queue-1",
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"tx-queue-2", "tx-queue-3", "ptp-pps-0",
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"ptp-pps-1", "ptp-pps-2", "ptp-pps-3";
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clocks = <&cpg CPG_MOD R9A08G046_ETH1_CLK_AXI>,
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<&cpg CPG_MOD R9A08G046_ETH1_CLK_CHI>,
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<&cpg CPG_MOD R9A08G046_ETH1_CLK_PTP_REF_I>,
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<&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I>,
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<&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I>,
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<&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_180_I>,
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<&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_180_I>,
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<&cpg CPG_MOD R9A08G046_ETH1_CLK_RMII_I>,
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<&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I_RMII>,
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<&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I_RMII>;
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clock-names = "stmmaceth", "pclk", "ptp_ref",
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"tx", "rx", "tx-180", "rx-180",
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"rmii", "rmii_tx", "rmii_rx";
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resets = <&cpg R9A08G046_ETH1_ARESET_N>;
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power-domains = <&cpg>;
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snps,multicast-filter-bins = <256>;
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snps,perfect-filter-entries = <128>;
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rx-fifo-depth = <8192>;
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tx-fifo-depth = <8192>;
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snps,fixed-burst;
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snps,no-pbl-x8;
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snps,force_thresh_dma_mode;
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snps,axi-config = <&stmmac_axi_setup>;
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snps,mtl-rx-config = <&mtl_rx_setup1>;
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snps,mtl-tx-config = <&mtl_tx_setup1>;
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snps,txpbl = <32>;
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snps,rxpbl = <32>;
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status = "disabled";
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mdio1: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mtl_rx_setup1: rx-queues-config {
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snps,rx-queues-to-use = <4>;
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snps,rx-sched-sp;
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queue0 {
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snps,dcb-algorithm;
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snps,priority = <0x1>;
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snps,map-to-dma-channel = <0>;
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};
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queue1 {
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snps,dcb-algorithm;
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snps,priority = <0x2>;
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snps,map-to-dma-channel = <1>;
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};
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queue2 {
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snps,dcb-algorithm;
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snps,priority = <0x4>;
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snps,map-to-dma-channel = <2>;
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};
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queue3 {
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snps,dcb-algorithm;
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snps,priority = <0x8>;
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snps,map-to-dma-channel = <3>;
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};
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};
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mtl_tx_setup1: tx-queues-config {
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snps,tx-queues-to-use = <4>;
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snps,tx-sched-wrr;
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queue0 {
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snps,weight = <0x10>;
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snps,dcb-algorithm;
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snps,priority = <0x1>;
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};
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queue1 {
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snps,weight = <0x12>;
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snps,dcb-algorithm;
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snps,priority = <0x2>;
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};
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queue2 {
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snps,weight = <0x14>;
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snps,dcb-algorithm;
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snps,priority = <0x4>;
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};
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queue3 {
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snps,weight = <0x18>;
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snps,dcb-algorithm;
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snps,priority = <0x8>;
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};
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};
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};
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pcie: pcie@11e40000 {
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reg = <0 0x11e40000 0 0x10000>;
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ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
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@ -200,6 +434,13 @@ gic: interrupt-controller@12400000 {
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};
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};
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stmmac_axi_setup: stmmac-axi-config {
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snps,lpi_en;
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snps,wr_osr_lmt = <0xf>;
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snps,rd_osr_lmt = <0xf>;
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snps,blen = <16 8 4 0 0 0 0>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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