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Renesas fixes for v7.1
- Fix SCIF (serial port) clocks on R-Car X5H, - Fix various dtc and dtbs_check warnings. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCafiV0QAKCRCKwlD9ZEnx cBBZAP9Lk2y6SWp/ixcey1J/GHtQ2iriuzDCrXeRkkg6P+OXTgEA3SgOuAi/ucSr eV6I/nw1mNKfIohw5gYPgvClZcC+UgM= =W0b8 -----END PGP SIGNATURE----- Merge tag 'renesas-fixes-for-v7.1-tag1' into renesas-dts-for-v7.2 Renesas fixes for v7.1 - Fix SCIF (serial port) clocks on R-Car X5H, - Fix various dtc and dtbs_check warnings.
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commit
fc326550eb
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@ -34,9 +34,6 @@ flash@18000000 {
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clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>;
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power-domains = <&cpg_clocks>;
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#address-cells = <1>;
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#size-cells = <1>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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@ -36,8 +36,6 @@ flash@18000000 {
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power-domains = <&cpg_clocks>;
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bank-width = <4>;
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device-width = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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partitions {
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compatible = "fixed-partitions";
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@ -37,7 +37,7 @@ b_clk: b {
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clock-div = <3>;
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};
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bsc: bus {
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bsc: bus@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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@ -40,7 +40,7 @@ aliases {
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spi2 = &hspi2;
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};
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lbsc: bus {
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lbsc: bus@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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@ -704,7 +704,7 @@ R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
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};
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};
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lbsc: bus {
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lbsc: bus@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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@ -86,7 +86,7 @@ extal_clk: extal {
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bootph-all;
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};
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lbsc: bus {
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lbsc: bus@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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@ -27,7 +27,12 @@ &lvds1 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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lvds1_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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@ -699,7 +699,7 @@ scif0: serial@c0700000 {
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"renesas,rcar-gen5-scif", "renesas,scif";
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reg = <0 0xc0700000 0 0x40>;
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interrupts = <GIC_ESPI 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
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clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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status = "disabled";
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};
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@ -709,7 +709,7 @@ scif1: serial@c0704000 {
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"renesas,rcar-gen5-scif", "renesas,scif";
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reg = <0 0xc0704000 0 0x40>;
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interrupts = <GIC_ESPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
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clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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status = "disabled";
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};
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@ -719,7 +719,7 @@ scif3: serial@c0708000 {
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"renesas,rcar-gen5-scif", "renesas,scif";
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reg = <0 0xc0708000 0 0x40>;
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interrupts = <GIC_ESPI 12 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
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clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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status = "disabled";
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};
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@ -729,7 +729,7 @@ scif4: serial@c070c000 {
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"renesas,rcar-gen5-scif", "renesas,scif";
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reg = <0 0xc070c000 0 0x40>;
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interrupts = <GIC_ESPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
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clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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status = "disabled";
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};
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@ -1327,6 +1327,7 @@ usb20phyrst: usb20phy-reset@15830000 {
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resets = <&cpg 0xaf>;
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power-domains = <&cpg>;
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#reset-cells = <0>;
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#mux-state-cells = <1>;
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status = "disabled";
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};
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@ -1345,6 +1345,7 @@ usb20phyrst: usb20phy-reset@15830000 {
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resets = <&cpg 0xaf>;
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power-domains = <&cpg>;
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#reset-cells = <0>;
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#mux-state-cells = <1>;
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status = "disabled";
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};
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@ -1355,6 +1356,7 @@ usb21phyrst: usb21phy-reset@15840000 {
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resets = <&cpg 0xaf>;
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power-domains = <&cpg>;
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#reset-cells = <0>;
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#mux-state-cells = <1>;
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status = "disabled";
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};
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@ -46,7 +46,12 @@ &csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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csi2_in: endpoint {
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clock-lanes = <0>;
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data-lanes = <1 2>;
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@ -26,7 +26,12 @@ &du {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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du_out_rgb: endpoint {
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remote-endpoint = <&adv7513_in>;
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};
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@ -27,7 +27,12 @@ &lvds0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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lvds0_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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