github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-11-06 21:58:01 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

clk: clocking-wizard: Fix overflow in clockout0 divisor calculation

Browse Source 
On 32-bit platforms (e.g., Zynq 7000 series), parent_rate * 1000
may overflow, leading to incorrect divisor calculation.

The issue was first found on Zynq7020 with "parent_rate=1GHz"
and "xlnx,nr-outputs=2".

Cast parent_rate to u64 and use the ULL version of DIV_ROUND*
instead.

Signed-off-by: Peijie Shao <shaopeijie@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
This commit is contained in:
Peijie Shao 2026-09-09 21:14:12 +08:00 committed by Brian Masney
parent b424385039
commit a1d0465f02
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
View File

@ -881,10 +881,10 @@ static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate,
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
void __iomem *div_addr = divider->base + divider->offset;
rate_div = DIV_ROUND_DOWN_ULL(parent_rate * 1000, rate);
rate_div = DIV_ROUND_DOWN_ULL((u64)parent_rate * 1000, rate);
clockout0_div = rate_div / 1000;
pre = DIV_ROUND_CLOSEST((parent_rate * 1000), rate);
pre = DIV_ROUND_CLOSEST_ULL((u64)parent_rate * 1000, rate);
f = (u32)(pre - (clockout0_div * 1000));
f = f & WZRD_CLKOUT_FRAC_MASK;
f = f << WZRD_CLKOUT_DIVIDE_WIDTH;