From a1d0465f027d341c6855324a5c63e54780ce20f3 Mon Sep 17 00:00:00 2001 From: Peijie Shao Date: Wed, 9 Sep 2026 21:14:12 +0800 Subject: [PATCH] clk: clocking-wizard: Fix overflow in clockout0 divisor calculation On 32-bit platforms (e.g., Zynq 7000 series), parent_rate * 1000 may overflow, leading to incorrect divisor calculation. The issue was first found on Zynq7020 with "parent_rate=1GHz" and "xlnx,nr-outputs=2". Cast parent_rate to u64 and use the ULL version of DIV_ROUND* instead. Signed-off-by: Peijie Shao Signed-off-by: Brian Masney --- drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c index 25bd71822dd6..71abd46b3593 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -881,10 +881,10 @@ static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate, struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); void __iomem *div_addr = divider->base + divider->offset; - rate_div = DIV_ROUND_DOWN_ULL(parent_rate * 1000, rate); + rate_div = DIV_ROUND_DOWN_ULL((u64)parent_rate * 1000, rate); clockout0_div = rate_div / 1000; - pre = DIV_ROUND_CLOSEST((parent_rate * 1000), rate); + pre = DIV_ROUND_CLOSEST_ULL((u64)parent_rate * 1000, rate); f = (u32)(pre - (clockout0_div * 1000)); f = f & WZRD_CLKOUT_FRAC_MASK; f = f << WZRD_CLKOUT_DIVIDE_WIDTH;