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clk: qcom: dispcc-sm6125: Add missing MDSS resets

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The MDSS resets were left undescribed. Add them to allow resetting the
display subsystem, which is necessary to avoid issues caused by state
left over from the bootloader on various platforms.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260303034847.13870-5-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Val Packett 2026-03-03 00:41:23 -03:00 committed by Bjorn Andersson
parent 67d41a9237
commit a09a80b44b
1 changed files with 7 additions and 0 deletions
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7
drivers/clk/qcom/dispcc-sm6125.c
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@ -17,6 +17,7 @@
#include "clk-regmap.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
@ -607,6 +608,10 @@ static struct clk_branch disp_cc_xo_clk = {
},
};
static const struct qcom_reset_map disp_cc_sm6125_resets[] = {
[DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x3000,
.pd = {
@ -663,6 +668,8 @@ static const struct qcom_cc_desc disp_cc_sm6125_desc = {
.config = &disp_cc_sm6125_regmap_config,
.clks = disp_cc_sm6125_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm6125_clocks),
.resets = disp_cc_sm6125_resets,
.num_resets = ARRAY_SIZE(disp_cc_sm6125_resets),
.gdscs = disp_cc_sm6125_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sm6125_gdscs),
};