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drm/amd/display: Remove Mall, SubVP and MCLK from DCN42

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[Why&How]
Remove MALL, SubVP and MCLK features from DCN42 resource file since it is
an APU and does not support them.

Assisted-by: Claude:opus-4.6
Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ivan Lipski 2026-04-16 21:43:26 -04:00 committed by Alex Deucher
parent 5f6937c1af
commit 9bed715da7
1 changed files with 0 additions and 42 deletions
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42
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
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@ -1807,8 +1807,6 @@ static struct resource_funcs dcn42_res_pool_funcs = {
.get_panel_config_defaults = dcn42_get_panel_config_defaults,
.get_preferred_eng_id_dpia = dcn42_get_preferred_eng_id_dpia,
.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
.add_phantom_pipes = dcn32_add_phantom_pipes,
.calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
.prepare_mcache_programming = dcn42_prepare_mcache_programming,
.build_pipe_pix_clk_params = dcn42_build_pipe_pix_clk_params,
.get_power_profile = dcn401_get_power_profile,
@ -1898,27 +1896,7 @@ static bool dcn42_resource_construct(
dc->caps.cursor_not_scaled = true;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dmdata_alloc_size = 2048;
dc->caps.mall_size_per_mem_channel = 4;
/* total size = mall per channel * num channels * 1024 * 1024 */
dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel *
dc->ctx->dc_bios->vram_info.num_chans * 1048576;
dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
dc->caps.cache_line_size = 64;
dc->caps.cache_num_ways = 16;
/* Calculate the available MALL space */
dc->caps.max_cab_allocation_bytes =
dcn32_calc_num_avail_chans_for_mall(dc, dc->ctx->dc_bios->vram_info.num_chans) *
dc->caps.mall_size_per_mem_channel * 1024 * 1024;
dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
dc->caps.subvp_fw_processing_delay_us = 15;
dc->caps.subvp_drr_max_vblank_margin_us = 40;
dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
dc->caps.subvp_swath_height_margin_lines = 16;
dc->caps.subvp_pstate_allow_width_us = 20;
dc->caps.subvp_vertical_int_margin_us = 30;
dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
dc->caps.max_slave_planes = 2;
dc->caps.max_slave_yuv_planes = 2;
@ -2304,26 +2282,6 @@ static bool dcn42_resource_construct(
resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch =
&dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes =
pool->base.funcs->calculate_mall_ways_from_bytes;
dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
dc->dml2_options.mall_cfg.max_cab_allocation_bytes =
dc->caps.max_cab_allocation_bytes;
dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
dc->dml2_options.max_segments_per_hubp = 24;
dc->dml2_options.det_segment_size = DCN42_CRB_SEGMENT_SIZE_KB;