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drm/amd/display: Unify fast update classification paths

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[Why]
The dc_fast_update intermediate struct created code duplication and
complexity with multiple classification paths (populate_fast_updates,
fast_nonaddr_updates_exist, full_update_required). This refactoring
simplifies the update classification system by consolidating to a
single path while maintaining compatibility and adding comprehensive
test coverage for fast sequence functionality.

[How]
Remove entire dc_fast_update struct and associated helper functions:
- populate_fast_updates
- fast_nonaddr_updates_exist
- full_update_required
and
- Refactor check_update_surfaces_for_stream as the
  single classification path with explicit handling for func_shaper,
  lut3d_func, cursor_csc_color_matrix_change and
  scaler_sharpener_update.
- Add reserved bitfields to surface_update_flags and
  stream_update_flags unions for completeness guards.
- Extract dc_check_address_only_update and
  dc_check_update_surfaces_for_stream as public.
- Add comprehensive test coverage with parameterized tests for all
  FAST flags, update classification tests for MED/FULL paths,
  and completeness guard tests.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rafal Ostrowski 2026-04-07 08:33:56 +02:00 committed by Alex Deucher
parent 1547752eea
commit 5f6937c1af
4 changed files with 39 additions and 264 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

252
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -3005,7 +3005,8 @@ static struct surface_update_descriptor det_surface_update(
update_flags->bits.gamut_remap_change ||
update_flags->bits.input_csc_change ||
update_flags->bits.cm_hist_change ||
update_flags->bits.coeff_reduction_change)) {
update_flags->bits.coeff_reduction_change ||
update_flags->bits.cursor_csc_color_matrix_change)) {
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
return overall_type;
@ -3095,8 +3096,10 @@ static struct surface_update_descriptor check_update_surfaces_for_stream(
stream_update->vrr_active_variable || stream_update->vrr_active_fixed))
su_flags->bits.fams_changed = 1;
if (stream_update->scaler_sharpener_update)
if (stream_update->scaler_sharpener_update) {
su_flags->bits.scaler_sharpener = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM);
}
if (stream_update->sharpening_required)
su_flags->bits.sharpening_required = 1;
@ -3161,6 +3164,16 @@ static struct surface_update_descriptor check_update_surfaces_for_stream(
su_flags->bits.cursor_pos = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if (stream_update->func_shaper) {
su_flags->bits.func_shaper = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM);
}
if (stream_update->lut3d_func) {
su_flags->bits.lut3d_func = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM);
}
}
for (int i = 0 ; i < surface_count; i++) {
@ -4085,7 +4098,7 @@ static void build_dmub_update_dirty_rect(
}
}
static bool check_address_only_update(union surface_update_flags update_flags)
bool dc_check_address_only_update(union surface_update_flags update_flags)
{
union surface_update_flags addr_only_update_flags;
addr_only_update_flags.raw = 0;
@ -4189,7 +4202,7 @@ static void commit_planes_for_stream_fast(struct dc *dc,
for (i = 0; i < surface_count; i++) {
if (srf_updates[i].surface &&
srf_updates[i].surface->update_flags.raw &&
!check_address_only_update(srf_updates[i].surface->update_flags)) {
!dc_check_address_only_update(srf_updates[i].surface->update_flags)) {
/* more than address update, need to acquire FAMS2 lock */
should_offload_fams2_flip = false;
break;
@ -5154,133 +5167,6 @@ static bool commit_minimal_transition_state(struct dc *dc,
return true;
}
void populate_fast_updates(struct dc_fast_update *fast_update,
struct dc_surface_update *srf_updates,
int surface_count,
struct dc_stream_update *stream_update)
{
int i = 0;
if (stream_update) {
fast_update[0].out_transfer_func = stream_update->out_transfer_func;
fast_update[0].output_csc_transform = stream_update->output_csc_transform;
fast_update[0].cursor_attributes = stream_update->cursor_attributes;
fast_update[0].cursor_position = stream_update->cursor_position;
fast_update[0].periodic_interrupt = stream_update->periodic_interrupt;
fast_update[0].dither_option = stream_update->dither_option;
fast_update[0].gamut_remap = stream_update->gamut_remap;
fast_update[0].vrr_infopacket = stream_update->vrr_infopacket;
fast_update[0].vsc_infopacket = stream_update->vsc_infopacket;
fast_update[0].vsp_infopacket = stream_update->vsp_infopacket;
fast_update[0].hfvsif_infopacket = stream_update->hfvsif_infopacket;
fast_update[0].vtem_infopacket = stream_update->vtem_infopacket;
fast_update[0].adaptive_sync_infopacket = stream_update->adaptive_sync_infopacket;
fast_update[0].avi_infopacket = stream_update->avi_infopacket;
fast_update[0].hdr_static_metadata = stream_update->hdr_static_metadata;
} else {
fast_update[0].out_transfer_func = NULL;
fast_update[0].output_csc_transform = NULL;
fast_update[0].cursor_attributes = NULL;
fast_update[0].cursor_position = NULL;
fast_update[0].periodic_interrupt = NULL;
fast_update[0].dither_option = NULL;
fast_update[0].gamut_remap = NULL;
fast_update[0].vrr_infopacket = NULL;
fast_update[0].vsc_infopacket = NULL;
fast_update[0].vsp_infopacket = NULL;
fast_update[0].hfvsif_infopacket = NULL;
fast_update[0].vtem_infopacket = NULL;
fast_update[0].adaptive_sync_infopacket = NULL;
fast_update[0].avi_infopacket = NULL;
fast_update[0].hdr_static_metadata = NULL;
}
for (i = 0; i < surface_count; i++) {
fast_update[i].flip_addr = srf_updates[i].flip_addr;
fast_update[i].gamma = srf_updates[i].gamma;
fast_update[i].gamut_remap_matrix = srf_updates[i].gamut_remap_matrix;
fast_update[i].input_csc_color_matrix = srf_updates[i].input_csc_color_matrix;
fast_update[i].coeff_reduction_factor = srf_updates[i].coeff_reduction_factor;
fast_update[i].cursor_csc_color_matrix = srf_updates[i].cursor_csc_color_matrix;
#if defined(CONFIG_DRM_AMD_DC_DCN4_2)
fast_update[i].cm_hist_control = srf_updates[i].cm_hist_control;
#endif
}
}
static bool fast_updates_exist(const struct dc_fast_update *fast_update, int surface_count)
{
int i;
if (fast_update[0].out_transfer_func ||
fast_update[0].output_csc_transform ||
fast_update[0].gamut_remap ||
fast_update[0].cursor_attributes ||
fast_update[0].cursor_position ||
fast_update[0].periodic_interrupt ||
fast_update[0].dither_option ||
fast_update[0].vrr_infopacket ||
fast_update[0].vsc_infopacket ||
fast_update[0].vsp_infopacket ||
fast_update[0].hfvsif_infopacket ||
fast_update[0].vtem_infopacket ||
fast_update[0].adaptive_sync_infopacket ||
fast_update[0].avi_infopacket ||
fast_update[0].hdr_static_metadata)
return true;
for (i = 0; i < surface_count; i++) {
if (fast_update[i].flip_addr ||
fast_update[i].gamma ||
fast_update[i].gamut_remap_matrix ||
fast_update[i].input_csc_color_matrix ||
fast_update[i].cursor_csc_color_matrix ||
#if defined(CONFIG_DRM_AMD_DC_DCN4_2)
fast_update[i].cm_hist_control ||
#endif
fast_update[i].coeff_reduction_factor)
return true;
}
return false;
}
bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count)
{
int i;
if (fast_update[0].out_transfer_func ||
fast_update[0].output_csc_transform ||
fast_update[0].cursor_attributes ||
fast_update[0].cursor_position ||
fast_update[0].periodic_interrupt ||
fast_update[0].dither_option ||
fast_update[0].gamut_remap ||
fast_update[0].vrr_infopacket ||
fast_update[0].vsc_infopacket ||
fast_update[0].vsp_infopacket ||
fast_update[0].hfvsif_infopacket ||
fast_update[0].vtem_infopacket ||
fast_update[0].adaptive_sync_infopacket ||
fast_update[0].avi_infopacket ||
fast_update[0].hdr_static_metadata)
return true;
for (i = 0; i < surface_count; i++) {
if (fast_update[i].input_csc_color_matrix ||
fast_update[i].gamma ||
fast_update[i].gamut_remap_matrix ||
fast_update[i].coeff_reduction_factor ||
#if defined(CONFIG_DRM_AMD_DC_DCN4_2)
fast_update[i].cm_hist_control ||
#endif
fast_update[i].cursor_csc_color_matrix)
return true;
}
return false;
}
static bool full_update_required_weak(
const struct dc *dc,
const struct dc_surface_update *srf_updates,
@ -5309,76 +5195,6 @@ static bool full_update_required_weak(
return false;
}
static bool full_update_required(
const struct dc *dc,
const struct dc_surface_update *srf_updates,
int surface_count,
const struct dc_stream_update *stream_update,
const struct dc_stream_state *stream)
{
const union dc_plane_cm_flags blend_only_flags = {
.bits = {
.blend_enable = 1,
}
};
if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream))
return true;
for (int i = 0; i < surface_count; i++) {
if (srf_updates &&
(srf_updates[i].plane_info ||
srf_updates[i].scaling_info ||
(srf_updates[i].hdr_mult.value &&
srf_updates[i].hdr_mult.value != srf_updates->surface->hdr_mult.value) ||
(srf_updates[i].sdr_white_level_nits &&
srf_updates[i].sdr_white_level_nits != srf_updates->surface->sdr_white_level_nits) ||
srf_updates[i].in_transfer_func ||
srf_updates[i].surface->force_full_update ||
(srf_updates[i].flip_addr &&
srf_updates[i].flip_addr->address.tmz_surface != srf_updates[i].surface->address.tmz_surface) ||
(srf_updates[i].cm &&
((srf_updates[i].cm->flags.all != blend_only_flags.all && srf_updates[i].cm->flags.all != 0) ||
(srf_updates[i].surface->cm.flags.all != blend_only_flags.all && srf_updates[i].surface->cm.flags.all != 0)))))
return true;
}
if (stream_update &&
(((stream_update->src.height != 0 && stream_update->src.width != 0) ||
(stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
stream_update->integer_scaling_update) ||
stream_update->abm_level ||
stream_update->dpms_off ||
stream_update->allow_freesync ||
stream_update->vrr_active_variable ||
stream_update->vrr_active_fixed ||
stream_update->output_color_space ||
stream_update->wb_update ||
stream_update->dsc_config ||
stream_update->mst_bw_update ||
stream_update->func_shaper ||
stream_update->lut3d_func ||
stream_update->pending_test_pattern ||
stream_update->crtc_timing_adjust ||
stream_update->scaler_sharpener_update ||
stream_update->hw_cursor_req))
return true;
return false;
}
static bool fast_update_only(
const struct dc *dc,
const struct dc_fast_update *fast_update,
const struct dc_surface_update *srf_updates,
int surface_count,
const struct dc_stream_update *stream_update,
const struct dc_stream_state *stream)
{
return fast_updates_exist(fast_update, surface_count)
&& !full_update_required(dc, srf_updates, surface_count, stream_update, stream);
}
static bool update_planes_and_stream_v2(struct dc *dc,
struct dc_surface_update *srf_updates, int surface_count,
struct dc_stream_state *stream,
@ -5386,7 +5202,6 @@ static bool update_planes_and_stream_v2(struct dc *dc,
{
struct dc_state *context;
enum surface_update_type update_type;
struct dc_fast_update fast_update[MAX_SURFACES] = {0};
/* In cases where MPO and split or ODM are used transitions can
* cause underflow. Apply stream configuration with minimal pipe
@ -5394,11 +5209,7 @@ static bool update_planes_and_stream_v2(struct dc *dc,
*/
bool force_minimal_pipe_splitting = 0;
bool is_plane_addition = 0;
bool is_fast_update_only;
populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);
is_fast_update_only = fast_update_only(dc, fast_update, srf_updates,
surface_count, stream_update, stream);
force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes(
dc,
stream,
@ -5436,7 +5247,7 @@ static bool update_planes_and_stream_v2(struct dc *dc,
commit_minimal_transition_state_in_dc_update(dc, context, stream,
srf_updates, surface_count);
if (is_fast_update_only && !dc->check_config.enable_legacy_fast_update) {
if (update_type == UPDATE_TYPE_FAST && !dc->check_config.enable_legacy_fast_update) {
commit_planes_for_stream_fast(dc,
srf_updates,
surface_count,
@ -5472,13 +5283,8 @@ static void commit_planes_and_stream_update_on_current_context(struct dc *dc,
struct dc_stream_update *stream_update,
enum surface_update_type update_type)
{
struct dc_fast_update fast_update[MAX_SURFACES] = {0};
ASSERT(update_type < UPDATE_TYPE_FULL);
populate_fast_updates(fast_update, srf_updates, surface_count,
stream_update);
if (fast_update_only(dc, fast_update, srf_updates, surface_count,
stream_update, stream) &&
if (update_type == UPDATE_TYPE_FAST &&
!dc->check_config.enable_legacy_fast_update)
commit_planes_for_stream_fast(dc,
srf_updates,
@ -7456,23 +7262,6 @@ static bool update_planes_and_stream_prepare_v3(
ASSERT(scratch->flow == UPDATE_V3_FLOW_INVALID);
dc_exit_ips_for_hw_access(scratch->dc);
/* HWSS path determination needs to be done prior to updating the surface and stream states. */
struct dc_fast_update fast_update[MAX_SURFACES] = { 0 };
populate_fast_updates(fast_update,
scratch->surface_updates,
scratch->surface_count,
scratch->stream_update);
const bool is_hwss_fast_path_only =
fast_update_only(scratch->dc,
fast_update,
scratch->surface_updates,
scratch->surface_count,
scratch->stream_update,
scratch->stream) &&
!scratch->dc->check_config.enable_legacy_fast_update;
if (!update_planes_and_stream_state(
scratch->dc,
scratch->surface_updates,
@ -7488,7 +7277,8 @@ static bool update_planes_and_stream_prepare_v3(
if (scratch->new_context == scratch->dc->current_state) {
ASSERT(scratch->update_type < UPDATE_TYPE_FULL);
scratch->flow = is_hwss_fast_path_only
scratch->flow = (scratch->update_type == UPDATE_TYPE_FAST &&
!scratch->dc->check_config.enable_legacy_fast_update)
? UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST
: UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FULL;
return true;

12
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
View File

@ -1059,6 +1059,18 @@ void hwss_build_fast_sequence(struct dc *dc,
(*num_steps)++;
}
if (current_mpc_pipe->plane_state->update_flags.bits.lut_3d &&
current_mpc_pipe->plane_state->mcm_luts.lut3d_data.lut3d_src ==
DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM &&
current_mpc_pipe->plane_state->mcm_shaper_3dlut_setting ==
DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT &&
current_mpc_pipe->plane_res.hubp->funcs->hubp_enable_3dlut_fl) {
block_sequence[*num_steps].params.hubp_enable_3dlut_fl_params.hubp =
current_mpc_pipe->plane_res.hubp;
block_sequence[*num_steps].func = HUBP_ENABLE_3DLUT_FL;
(*num_steps)++;
}
if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) {
block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;
block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;

36
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -1500,11 +1500,14 @@ union surface_update_flags {
uint32_t full_update:1;
uint32_t sdr_white_level_nits:1;
uint32_t cm_hist_change:1;
uint32_t reserved:2; /* adjust when adding new flags */
} bits;
uint32_t raw;
};
bool dc_check_address_only_update(union surface_update_flags update_flags);
#define DC_REMOVE_PLANE_POINTERS 1
struct dc_plane_state {
@ -1883,34 +1886,6 @@ struct dc_scaling_info {
struct scaling_taps scaling_quality;
};
struct dc_fast_update {
const struct dc_flip_addrs *flip_addr;
const struct dc_gamma *gamma;
const struct colorspace_transform *gamut_remap_matrix;
const struct dc_csc_transform *input_csc_color_matrix;
const struct fixed31_32 *coeff_reduction_factor;
struct dc_transfer_func *out_transfer_func;
struct dc_csc_transform *output_csc_transform;
const struct dc_csc_transform *cursor_csc_color_matrix;
#if defined(CONFIG_DRM_AMD_DC_DCN4_2)
struct cm_hist_control *cm_hist_control;
#endif
/* stream-level fast updates */
const struct colorspace_transform *gamut_remap;
const struct dc_cursor_attributes *cursor_attributes;
const struct dc_cursor_position *cursor_position;
const struct periodic_interrupt_config *periodic_interrupt;
const enum dc_dither_option *dither_option;
struct dc_info_packet *vrr_infopacket;
struct dc_info_packet *vsc_infopacket;
struct dc_info_packet *vsp_infopacket;
struct dc_info_packet *hfvsif_infopacket;
struct dc_info_packet *vtem_infopacket;
struct dc_info_packet *adaptive_sync_infopacket;
struct dc_info_packet *avi_infopacket;
struct dc_info_packet *hdr_static_metadata;
};
struct dc_surface_update {
struct dc_plane_state *surface;
@ -2049,11 +2024,6 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
void get_audio_check(struct audio_info *aud_modes,
struct audio_check *aud_chk);
bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count);
void populate_fast_updates(struct dc_fast_update *fast_update,
struct dc_surface_update *srf_updates,
int surface_count,
struct dc_stream_update *stream_update);
/*
* Set up streams and links associated to drive sinks
* The streams parameter is an absolute set of all active streams.

3
drivers/gpu/drm/amd/display/dc/dc_stream.h
View File

@ -123,6 +123,9 @@ union stream_update_flags {
uint32_t info_frame : 1;
uint32_t dmdata : 1;
uint32_t dither : 1;
uint32_t func_shaper : 1;
uint32_t lut3d_func : 1;
uint32_t reserved : 11; /* adjust when adding new flags */
} bits;
uint32_t raw;