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arm64: dts: renesas: r8a779g0: Add CA76 operating points

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Add operating points for running the Cortex-A76 CPU cores on R-Car V4H
at various speeds, up to the Normal (1.7 GHz) performance mode.

Based on a patch in the BSP by Tho Vu.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/8afb32f5dc123ebf2b941703483152ff0992191d.1668429870.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2022-11-14 13:49:04 +01:00
parent ee8ce199c7
commit 9a0e630655
1 changed files with 31 additions and 0 deletions
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31
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
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@ -14,6 +14,33 @@ / {
#address-cells = <2>;
#size-cells = <2>;
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <825000>;
clock-latency-ns = <500000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <825000>;
clock-latency-ns = <500000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <825000>;
clock-latency-ns = <500000>;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <825000>;
clock-latency-ns = <500000>;
opp-suspend;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -47,6 +74,7 @@ a76_0: cpu@0 {
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
operating-points-v2 = <&cluster0_opp>;
};
a76_1: cpu@100 {
@ -58,6 +86,7 @@ a76_1: cpu@100 {
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
operating-points-v2 = <&cluster0_opp>;
};
a76_2: cpu@10000 {
@ -69,6 +98,7 @@ a76_2: cpu@10000 {
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
operating-points-v2 = <&cluster0_opp>;
};
a76_3: cpu@10100 {
@ -80,6 +110,7 @@ a76_3: cpu@10100 {
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
operating-points-v2 = <&cluster0_opp>;
};
idle-states {