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arm64: dts: mediatek: mt7981b: Add Ethernet and WiFi offload support
Add device tree nodes for the Ethernet subsystem on MT7981B SoC, including: - Ethernet MAC controller with dual GMAC support - Wireless Ethernet Dispatch (WED) - SGMII PHY controllers for high-speed Ethernet interfaces - Reserved memory regions for WiFi offload processor Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> [Angelo: Removed useless address/size cells from main eth node] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
Sjoerd Simons
AngeloGioacchino Del Regno
parent
8f350dbb2e
commit
9846a8c603
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@ -2,6 +2,7 @@
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#include <dt-bindings/clock/mediatek,mt7981-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/mt7986-resets.h>
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@ -47,11 +48,36 @@ reserved-memory {
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#size-cells = <2>;
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ranges;
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wo_boot: wo-boot@15194000 {
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reg = <0 0x15194000 0 0x1000>;
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no-map;
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};
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wo_ilm0: wo-ilm@151e0000 {
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reg = <0 0x151e0000 0 0x8000>;
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no-map;
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};
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wo_dlm0: wo-dlm@151e8000 {
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reg = <0 0x151e8000 0 0x2000>;
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no-map;
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};
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/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
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secmon_reserved: secmon@43000000 {
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reg = <0 0x43000000 0 0x30000>;
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no-map;
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};
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wo_emi0: wo-emi@47d80000 {
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reg = <0 0x47d80000 0 0x40000>;
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no-map;
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};
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wo_data: wo-data@47dc0000 {
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reg = <0 0x47dc0000 0 0x240000>;
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no-map;
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};
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};
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soc {
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@ -107,6 +133,18 @@ pwm: pwm@10048000 {
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#pwm-cells = <2>;
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};
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sgmiisys0: syscon@10060000 {
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compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
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reg = <0 0x10060000 0 0x1000>;
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#clock-cells = <1>;
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};
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sgmiisys1: syscon@10070000 {
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compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
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reg = <0 0x10070000 0 0x1000>;
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#clock-cells = <1>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x100>;
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@ -345,15 +383,106 @@ soc-uuid@140 {
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thermal_calibration: thermal-calib@274 {
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reg = <0x274 0xc>;
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};
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phy_calibration: phy-calib@8dc {
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reg = <0x8dc 0x10>;
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};
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};
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clock-controller@15000000 {
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ethsys: clock-controller@15000000 {
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compatible = "mediatek,mt7981-ethsys", "syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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wed: wed@15010000 {
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compatible = "mediatek,mt7981-wed",
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"syscon";
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reg = <0 0x15010000 0 0x1000>;
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interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
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memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
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<&wo_data>, <&wo_boot>;
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memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
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"wo-data", "wo-boot";
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mediatek,wo-ccif = <&wo_ccif0>;
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};
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eth: ethernet@15100000 {
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compatible = "mediatek,mt7981-eth";
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reg = <0 0x15100000 0 0x40000>;
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assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
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<&topckgen CLK_TOP_SGM_325M_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
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<&topckgen CLK_TOP_CB_SGM_325M>;
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clocks = <ðsys CLK_ETH_FE_EN>,
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<ðsys CLK_ETH_GP2_EN>,
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<ðsys CLK_ETH_GP1_EN>,
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<ðsys CLK_ETH_WOCPU0_EN>,
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<&topckgen CLK_TOP_SGM_REG>,
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<&sgmiisys0 CLK_SGM0_TX_EN>,
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<&sgmiisys0 CLK_SGM0_RX_EN>,
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<&sgmiisys0 CLK_SGM0_CK0_EN>,
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<&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
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<&sgmiisys1 CLK_SGM1_TX_EN>,
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<&sgmiisys1 CLK_SGM1_RX_EN>,
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<&sgmiisys1 CLK_SGM1_CK1_EN>,
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<&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
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<&topckgen CLK_TOP_NETSYS_SEL>,
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<&topckgen CLK_TOP_NETSYS_500M_SEL>;
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clock-names = "fe", "gp2", "gp1", "wocpu0",
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"sgmii_ck",
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"sgmii_tx250m", "sgmii_rx250m",
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"sgmii_cdr_ref", "sgmii_cdr_fb",
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"sgmii2_tx250m", "sgmii2_rx250m",
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"sgmii2_cdr_ref", "sgmii2_cdr_fb",
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"netsys0", "netsys1";
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0",
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"pdma1", "pdma2", "pdma3";
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sram = <ð_sram>;
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mediatek,ethsys = <ðsys>;
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mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
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mediatek,infracfg = <&topmisc>;
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mediatek,wed = <&wed>;
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status = "disabled";
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mdio_bus: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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int_gbe_phy: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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phy-mode = "gmii";
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phy-is-integrated;
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nvmem-cells = <&phy_calibration>;
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nvmem-cell-names = "phy-cal-data";
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};
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};
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};
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eth_sram: sram@15140000 {
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compatible = "mmio-sram";
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reg = <0 0x15140000 0 0x40000>;
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ranges = <0 0x15140000 0 0x40000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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wo_ccif0: syscon@151a5000 {
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compatible = "mediatek,mt7986-wo-ccif", "syscon";
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reg = <0 0x151a5000 0 0x1000>;
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interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
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};
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wifi@18000000 {
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compatible = "mediatek,mt7981-wmac";
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reg = <0 0x18000000 0 0x1000000>,
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