mirror of
https://github.com/torvalds/linux.git
synced 2026-05-27 00:22:00 +02:00
Renesas DTS updates for v6.19 (take two)
- Add Imagination Technologies PowerVR Series 7XE GE7800 GPU support
for the R-Car M3-N and V3U SoCs,
- Add Ethernet support for the RZ/T2H and RZ/N2H SoCs and their
evaluation boards,
- Add ADC support for the RZ/N1D SoC,
- Add thermal, NMI pushbutton, and RTC support for the RZ/V2H SoC and
the RZ/V2H EVK development board,
- Add USB2.0 support for the RZ/G3S SoC and the RZ/G3S SMARC Carrier
II board.
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCaRcAkgAKCRCKwlD9ZEnx
cF89AP9Vkd0D3KNWvaGX8aKc7D0PQSPfhiE5YSLhmalIYd/HkwEAzEJTbBE6mOdB
HdSO2CdHQNRJ0ApFcEfwU4Pvr+dLYgA=
=lnh0
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgiVwACgkQmmx57+YA
GNmc4Q/9ExdOkSXZFzD9AiAOFb/aQjhLg/GQrGucG01a8OiWDIvSy9r2nk+40JwS
Vs27cy1ondJ06YIj52pV1rnlfpOb6UUuLVJ3ClvNOFmfL+BRURnpyhV+kkBR+EI7
T4aMb9azwyIFYSiAjMna0sIG+0lvVVI8rHsF8uEILrcfbiIqMY8U3ra5Y4XJQZIL
liBFUfzXxL6nOMuq/UnXzrtHRYjSqrRKHA3HHBO+qMYibF4ha478/dqiSA3HJfKf
8c/jhbLCp0WXMpaGzA+sJxN5dajqxe69JAbuJly/ssGNlQQmpe9GQ1AEbHCayVor
BQcFTBQvQ8efhNvcuh4pE43uS4EY69YD5hRBKSH9TaYtJ8qwi4HXGuEcO78TklSk
hAkT22iQcBhz0tWn3tUgy1JaL+6siy+6gqj+Xt9xHlk1Is1BOCiKgQAvSDAIxoxY
Y52vejdOt9xyZCQEgBBPS1LkVq8ui6217IQRUZXAUcmF4qGEL1Jrvyk5VolR7f35
dU1slby7J27TNSxzoG0OD9gmPxeWkEJynZMXPgXRuHwQvLi+3HvVMXllna/kJUV3
Lgr+Jvl8WapDX8+l7REOSwUjKPZI4CNQOl+ChjgumhhFl9ryKx+wrkXS7m+fm0XP
dT8KYocDYIZ2B527hl5Ys7Q2JLE44kxCaJ3rYcHM+sk+HWGAWC0=
=Ioc1
-----END PGP SIGNATURE-----
Merge tag 'renesas-dts-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.19 (take two)
- Add Imagination Technologies PowerVR Series 7XE GE7800 GPU support
for the R-Car M3-N and V3U SoCs,
- Add Ethernet support for the RZ/T2H and RZ/N2H SoCs and their
evaluation boards,
- Add ADC support for the RZ/N1D SoC,
- Add thermal, NMI pushbutton, and RTC support for the RZ/V2H SoC and
the RZ/V2H EVK development board,
- Add USB2.0 support for the RZ/G3S SoC and the RZ/G3S SMARC Carrier
II board.
* tag 'renesas-dts-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable RTC
arm64: dts: renesas: r9a09g057: Add RTC node
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add NMI pushbutton support
arm64: dts: renesas: rzg3s-smarc: Enable USB support
arm64: dts: renesas: r9a08g045: Add USB support
arm64: dts: renesas: r9a09g057: Add TSU nodes
ARM: dts: renesas: r9a06g032: Add the ADC device
arm64: dts: renesas: r9a09g087: Add GMAC nodes
arm64: dts: renesas: r9a09g077: Add GMAC nodes
arm64: dts: renesas: r9a09g087: Add ETHSS node
arm64: dts: renesas: r9a09g077: Add ETHSS node
arm64: dts: renesas: r8a779a0: Add GE7800 GPU node
arm64: dts: renesas: r8a77965: Add GE7800 GPU node
dt-bindings: clock: r8a779a0: Add ZG core clock
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
9481f1ce9b
|
|
@ -290,6 +290,16 @@ i2c2: i2c@40064000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
adc: adc@40065000 {
|
||||
compatible = "renesas,r9a06g032-adc", "renesas,rzn1-adc";
|
||||
reg = <0x40065000 0x200>;
|
||||
clocks = <&sysctrl R9A06G032_HCLK_ADC>, <&sysctrl R9A06G032_CLK_ADC>;
|
||||
clock-names = "pclk", "adc";
|
||||
power-domains = <&sysctrl>;
|
||||
#io-channel-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@40067000 {
|
||||
compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
|
||||
reg = <0x40067000 0x1000>, <0x51000000 0x480>;
|
||||
|
|
|
|||
|
|
@ -2450,6 +2450,23 @@ gic: interrupt-controller@f1010000 {
|
|||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
gpu: gpu@fd000000 {
|
||||
compatible = "renesas,r8a77965-gpu",
|
||||
"img,img-ge7800",
|
||||
"img,img-rogue";
|
||||
reg = <0 0xfd000000 0 0x40000>;
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_CORE R8A77965_CLK_ZG>,
|
||||
<&cpg CPG_CORE R8A77965_CLK_S2D1>,
|
||||
<&cpg CPG_MOD 112>;
|
||||
clock-names = "core", "mem", "sys";
|
||||
power-domains = <&sysc R8A77965_PD_3DG_A>,
|
||||
<&sysc R8A77965_PD_3DG_B>;
|
||||
power-domain-names = "a", "b";
|
||||
resets = <&cpg 112>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec0: pcie@fe000000 {
|
||||
compatible = "renesas,pcie-r8a77965",
|
||||
"renesas,pcie-rcar-gen3";
|
||||
|
|
|
|||
|
|
@ -2337,6 +2337,23 @@ gic: interrupt-controller@f1000000 {
|
|||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpu: gpu@fd000000 {
|
||||
compatible = "renesas,r8a779a0-gpu",
|
||||
"img,img-ge7800",
|
||||
"img,img-rogue";
|
||||
reg = <0 0xfd000000 0 0x40000>;
|
||||
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_CORE R8A779A0_CLK_ZG>,
|
||||
<&cpg CPG_CORE R8A779A0_CLK_S3D1>,
|
||||
<&cpg CPG_MOD 0>;
|
||||
clock-names = "core", "mem", "sys";
|
||||
power-domains = <&sysc R8A779A0_PD_3DG_A>,
|
||||
<&sysc R8A779A0_PD_3DG_B>;
|
||||
power-domain-names = "a", "b";
|
||||
resets = <&cpg 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fcpvd0: fcp@fea10000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea10000 0 0x200>;
|
||||
|
|
|
|||
|
|
@ -727,6 +727,124 @@ eth1: ethernet@11c40000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
phyrst: usbphy-ctrl@11e00000 {
|
||||
compatible = "renesas,r9a08g045-usbphy-ctrl";
|
||||
reg = <0 0x11e00000 0 0x10000>;
|
||||
clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>;
|
||||
resets = <&cpg R9A08G045_USB_PRESETN>;
|
||||
power-domains = <&cpg>;
|
||||
#reset-cells = <1>;
|
||||
renesas,sysc-pwrrdy = <&sysc 0xd70 0x1>;
|
||||
status = "disabled";
|
||||
|
||||
usb0_vbus_otg: regulator-vbus {
|
||||
regulator-name = "vbus";
|
||||
};
|
||||
};
|
||||
|
||||
ohci0: usb@11e10000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0x11e10000 0 0x100>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
|
||||
<&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>;
|
||||
resets = <&phyrst 0>,
|
||||
<&cpg R9A08G045_USB_U2H0_HRESETN>;
|
||||
phys = <&usb2_phy0 1>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci1: usb@11e30000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0x11e30000 0 0x100>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
|
||||
<&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>;
|
||||
resets = <&phyrst 1>,
|
||||
<&cpg R9A08G045_USB_U2H1_HRESETN>;
|
||||
phys = <&usb2_phy1 1>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@11e10100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0x11e10100 0 0x100>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
|
||||
<&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>;
|
||||
resets = <&phyrst 0>,
|
||||
<&cpg R9A08G045_USB_U2H0_HRESETN>;
|
||||
phys = <&usb2_phy0 2>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci0>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci1: usb@11e30100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0x11e30100 0 0x100>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
|
||||
<&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>;
|
||||
resets = <&phyrst 1>,
|
||||
<&cpg R9A08G045_USB_U2H1_HRESETN>;
|
||||
phys = <&usb2_phy1 2>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci1>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_phy0: usb-phy@11e10200 {
|
||||
compatible = "renesas,usb2-phy-r9a08g045";
|
||||
reg = <0 0x11e10200 0 0x700>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
|
||||
<&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>;
|
||||
resets = <&phyrst 0>,
|
||||
<&cpg R9A08G045_USB_U2H0_HRESETN>;
|
||||
#phy-cells = <1>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_phy1: usb-phy@11e30200 {
|
||||
compatible = "renesas,usb2-phy-r9a08g045";
|
||||
reg = <0 0x11e30200 0 0x700>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
|
||||
<&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>;
|
||||
resets = <&phyrst 1>,
|
||||
<&cpg R9A08G045_USB_U2H1_HRESETN>;
|
||||
#phy-cells = <1>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsusb: usb@11e20000 {
|
||||
compatible = "renesas,usbhs-r9a08g045",
|
||||
"renesas,rzg2l-usbhs";
|
||||
reg = <0 0x11e20000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
|
||||
<&cpg CPG_MOD R9A08G045_USB_U2P_EXR_CPUCLK>;
|
||||
resets = <&phyrst 0>,
|
||||
<&cpg R9A08G045_USB_U2P_EXL_SYSRST>;
|
||||
renesas,buswait = <7>;
|
||||
phys = <&usb2_phy0 3>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@12400000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
|
|||
|
|
@ -65,6 +65,7 @@ cpu0: cpu@0 {
|
|||
next-level-cache = <&L3_CA55>;
|
||||
enable-method = "psci";
|
||||
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>;
|
||||
#cooling-cells = <2>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
|
|
@ -75,6 +76,7 @@ cpu1: cpu@100 {
|
|||
next-level-cache = <&L3_CA55>;
|
||||
enable-method = "psci";
|
||||
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>;
|
||||
#cooling-cells = <2>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
|
|
@ -85,6 +87,7 @@ cpu2: cpu@200 {
|
|||
next-level-cache = <&L3_CA55>;
|
||||
enable-method = "psci";
|
||||
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>;
|
||||
#cooling-cells = <2>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
|
|
@ -95,6 +98,7 @@ cpu3: cpu@300 {
|
|||
next-level-cache = <&L3_CA55>;
|
||||
enable-method = "psci";
|
||||
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>;
|
||||
#cooling-cells = <2>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
|
|
@ -285,6 +289,32 @@ sys: system-controller@10430000 {
|
|||
resets = <&cpg 0x30>;
|
||||
};
|
||||
|
||||
tsu0: thermal@11000000 {
|
||||
compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu";
|
||||
reg = <0 0x11000000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "adi", "adcmpi";
|
||||
clocks = <&cpg CPG_MOD 0x109>;
|
||||
resets = <&cpg 0xf7>;
|
||||
power-domains = <&cpg>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
renesas,tsu-trim = <&sys 0x320>;
|
||||
};
|
||||
|
||||
tsu1: thermal@14002000 {
|
||||
compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu";
|
||||
reg = <0 0x14002000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "adi", "adcmpi";
|
||||
clocks = <&cpg CPG_MOD 0x10a>;
|
||||
resets = <&cpg 0xf8>;
|
||||
power-domains = <&cpg>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
renesas,tsu-trim = <&sys 0x330>;
|
||||
};
|
||||
|
||||
xspi: spi@11030000 {
|
||||
compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi";
|
||||
reg = <0 0x11030000 0 0x10000>,
|
||||
|
|
@ -591,6 +621,21 @@ wdt3: watchdog@13000400 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc: rtc@11c00800 {
|
||||
compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3";
|
||||
reg = <0 0x11c00800 0 0x400>;
|
||||
interrupts = <GIC_SPI 524 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 525 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 526 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "alarm", "period", "carry";
|
||||
clocks = <&cpg CPG_MOD 0x53>, <&rtxin_clk>;
|
||||
clock-names = "bus", "counter";
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg 0x79>, <&cpg 0x7a>;
|
||||
reset-names = "rtc", "rtest";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif: serial@11c01400 {
|
||||
compatible = "renesas,scif-r9a09g057";
|
||||
reg = <0 0x11c01400 0 0x400>;
|
||||
|
|
@ -1312,6 +1357,51 @@ stmmac_axi_setup: stmmac-axi-config {
|
|||
snps,blen = <16 8 4 0 0 0 0>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
sensor1_thermal: sensor1-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&tsu0>;
|
||||
|
||||
trips {
|
||||
sensor1_crit: sensor1-crit {
|
||||
temperature = <120000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sensor2_thermal: sensor2-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&tsu1>;
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&sensor2_target>;
|
||||
cooling-device = <&cpu0 0 3>, <&cpu1 0 3>,
|
||||
<&cpu2 0 3>, <&cpu3 0 3>;
|
||||
contribution = <1024>;
|
||||
};
|
||||
};
|
||||
|
||||
trips {
|
||||
sensor2_target: trip-point {
|
||||
temperature = <95000>;
|
||||
hysteresis = <1000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
sensor2_crit: sensor2-crit {
|
||||
temperature = <120000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
|
||||
#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "r9a09g057.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
@ -34,6 +35,18 @@ chosen {
|
|||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
keys: keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
key-wakeup {
|
||||
interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>;
|
||||
linux,code = <KEY_WAKEUP>;
|
||||
label = "NMI_SW";
|
||||
debounce-interval = <20>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
|
|
@ -388,6 +401,10 @@ &qextal_clk {
|
|||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtxin_clk {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -270,6 +270,481 @@ i2c2: i2c@81008000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac0: ethernet@80100000 {
|
||||
compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20";
|
||||
reg = <0 0x80100000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
|
||||
"rx-queue-0", "rx-queue-1", "rx-queue-2",
|
||||
"rx-queue-3", "rx-queue-4", "rx-queue-5",
|
||||
"rx-queue-6", "rx-queue-7", "tx-queue-0",
|
||||
"tx-queue-1", "tx-queue-2", "tx-queue-3",
|
||||
"tx-queue-4", "tx-queue-5", "tx-queue-6",
|
||||
"tx-queue-7";
|
||||
clocks = <&cpg CPG_MOD 400>,
|
||||
<&cpg CPG_CORE R9A09G077_CLK_PCLKH>,
|
||||
<&cpg CPG_CORE R9A09G077_ETCLKB>;
|
||||
clock-names = "stmmaceth", "pclk", "tx";
|
||||
resets = <&cpg 400>, <&cpg 401>;
|
||||
reset-names = "stmmaceth", "ahb";
|
||||
power-domains = <&cpg>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <32>;
|
||||
rx-fifo-depth = <8192>;
|
||||
tx-fifo-depth = <8192>;
|
||||
snps,fixed-burst;
|
||||
snps,no-pbl-x8;
|
||||
snps,force_thresh_dma_mode;
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup0>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup0>;
|
||||
snps,txpbl = <16>;
|
||||
snps,rxpbl = <16>;
|
||||
status = "disabled";
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup0: rx-queues-config {
|
||||
snps,rx-queues-to-use = <8>;
|
||||
snps,rx-sched-sp;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
snps,map-to-dma-channel = <0>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
snps,map-to-dma-channel = <1>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
snps,map-to-dma-channel = <2>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
snps,map-to-dma-channel = <3>;
|
||||
};
|
||||
|
||||
queue4 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x10>;
|
||||
snps,map-to-dma-channel = <4>;
|
||||
};
|
||||
|
||||
queue5 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x20>;
|
||||
snps,map-to-dma-channel = <5>;
|
||||
};
|
||||
|
||||
queue6 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x40>;
|
||||
snps,map-to-dma-channel = <6>;
|
||||
};
|
||||
|
||||
queue7 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x80>;
|
||||
snps,map-to-dma-channel = <7>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_tx_setup0: tx-queues-config {
|
||||
snps,tx-queues-to-use = <8>;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue4 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue5 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue6 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue7 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: ethernet@92000000 {
|
||||
compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20";
|
||||
reg = <0 0x92000000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
|
||||
"rx-queue-0", "rx-queue-1", "rx-queue-2",
|
||||
"rx-queue-3", "rx-queue-4", "rx-queue-5",
|
||||
"rx-queue-6", "rx-queue-7", "tx-queue-0",
|
||||
"tx-queue-1", "tx-queue-2", "tx-queue-3",
|
||||
"tx-queue-4", "tx-queue-5", "tx-queue-6",
|
||||
"tx-queue-7";
|
||||
clocks = <&cpg CPG_MOD 416>,
|
||||
<&cpg CPG_CORE R9A09G077_CLK_PCLKAH>,
|
||||
<&cpg CPG_CORE R9A09G077_ETCLKB>;
|
||||
clock-names = "stmmaceth", "pclk", "tx";
|
||||
resets = <&cpg 416>, <&cpg 417>;
|
||||
reset-names = "stmmaceth", "ahb";
|
||||
power-domains = <&cpg>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <32>;
|
||||
rx-fifo-depth = <8192>;
|
||||
tx-fifo-depth = <8192>;
|
||||
snps,fixed-burst;
|
||||
snps,no-pbl-x8;
|
||||
snps,force_thresh_dma_mode;
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup1>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup1>;
|
||||
snps,txpbl = <16>;
|
||||
snps,rxpbl = <16>;
|
||||
status = "disabled";
|
||||
|
||||
mdio1: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup1: rx-queues-config {
|
||||
snps,rx-queues-to-use = <8>;
|
||||
snps,rx-sched-sp;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
snps,map-to-dma-channel = <0>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
snps,map-to-dma-channel = <1>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
snps,map-to-dma-channel = <2>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
snps,map-to-dma-channel = <3>;
|
||||
};
|
||||
|
||||
queue4 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x10>;
|
||||
snps,map-to-dma-channel = <4>;
|
||||
};
|
||||
|
||||
queue5 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x20>;
|
||||
snps,map-to-dma-channel = <5>;
|
||||
};
|
||||
|
||||
queue6 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x40>;
|
||||
snps,map-to-dma-channel = <6>;
|
||||
};
|
||||
|
||||
queue7 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x80>;
|
||||
snps,map-to-dma-channel = <7>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_tx_setup1: tx-queues-config {
|
||||
snps,tx-queues-to-use = <8>;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue4 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue5 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue6 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue7 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmac2: ethernet@92010000 {
|
||||
compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20";
|
||||
reg = <0 0x92010000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
|
||||
"rx-queue-0", "rx-queue-1", "rx-queue-2",
|
||||
"rx-queue-3", "rx-queue-4", "rx-queue-5",
|
||||
"rx-queue-6", "rx-queue-7", "tx-queue-0",
|
||||
"tx-queue-1", "tx-queue-2", "tx-queue-3",
|
||||
"tx-queue-4", "tx-queue-5", "tx-queue-6",
|
||||
"tx-queue-7";
|
||||
clocks = <&cpg CPG_MOD 417>,
|
||||
<&cpg CPG_CORE R9A09G077_CLK_PCLKAH>,
|
||||
<&cpg CPG_CORE R9A09G077_ETCLKB>;
|
||||
clock-names = "stmmaceth", "pclk", "tx";
|
||||
resets = <&cpg 418>, <&cpg 419>;
|
||||
reset-names = "stmmaceth", "ahb";
|
||||
power-domains = <&cpg>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <32>;
|
||||
rx-fifo-depth = <8192>;
|
||||
tx-fifo-depth = <8192>;
|
||||
snps,fixed-burst;
|
||||
snps,no-pbl-x8;
|
||||
snps,force_thresh_dma_mode;
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup2>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup2>;
|
||||
snps,txpbl = <16>;
|
||||
snps,rxpbl = <16>;
|
||||
status = "disabled";
|
||||
|
||||
mdio2: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup2: rx-queues-config {
|
||||
snps,rx-queues-to-use = <8>;
|
||||
snps,rx-sched-sp;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
snps,map-to-dma-channel = <0>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
snps,map-to-dma-channel = <1>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
snps,map-to-dma-channel = <2>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
snps,map-to-dma-channel = <3>;
|
||||
};
|
||||
|
||||
queue4 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x10>;
|
||||
snps,map-to-dma-channel = <4>;
|
||||
};
|
||||
|
||||
queue5 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x20>;
|
||||
snps,map-to-dma-channel = <5>;
|
||||
};
|
||||
|
||||
queue6 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x40>;
|
||||
snps,map-to-dma-channel = <6>;
|
||||
};
|
||||
|
||||
queue7 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x80>;
|
||||
snps,map-to-dma-channel = <7>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_tx_setup2: tx-queues-config {
|
||||
snps,tx-queues-to-use = <8>;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue4 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue5 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue6 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue7 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethss: ethss@80110000 {
|
||||
compatible = "renesas,r9a09g077-miic";
|
||||
reg = <0 0x80110000 0 0x10000>;
|
||||
clocks = <&cpg CPG_CORE R9A09G077_ETCLKE>,
|
||||
<&cpg CPG_CORE R9A09G077_ETCLKB>,
|
||||
<&cpg CPG_CORE R9A09G077_ETCLKD>,
|
||||
<&cpg CPG_MOD 403>;
|
||||
clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
|
||||
resets = <&cpg 405>, <&cpg 406>;
|
||||
reset-names = "rst", "crst";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mii_conv0: mii-conv@0 {
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mii_conv1: mii-conv@1 {
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mii_conv2: mii-conv@2 {
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mii_conv3: mii-conv@3 {
|
||||
reg = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
cpg: clock-controller@80280000 {
|
||||
compatible = "renesas,r9a09g077-cpg-mssr";
|
||||
reg = <0 0x80280000 0 0x1000>,
|
||||
|
|
@ -458,6 +933,13 @@ sdhi1_vqmmc: vqmmc-regulator {
|
|||
};
|
||||
};
|
||||
|
||||
stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,lpi_en;
|
||||
snps,wr_osr_lmt = <0xf>;
|
||||
snps,rd_osr_lmt = <0xf>;
|
||||
snps,blen = <16 8 4 0 0 0 0>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
|
|
|
|||
|
|
@ -149,7 +149,77 @@ &i2c1 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio1_phy {
|
||||
reset-gpios = <&pinctrl RZT2H_GPIO(32, 3) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&mdio2_phy {
|
||||
/*
|
||||
* PHY2 Reset Configuration:
|
||||
*
|
||||
* SW6[1] OFF; SW6[2] ON; SW6[3] OFF - use pin P17_5 for GMAC_RESETOUT2#
|
||||
*/
|
||||
reset-gpios = <&pinctrl RZT2H_GPIO(17, 5) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
/*
|
||||
* GMAC2 Pin Configuration:
|
||||
*
|
||||
* SW2[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2
|
||||
* SW2[7] ON - use pins P29_1-P29_7, P30_0-P30_4, and P31_2-P31_5
|
||||
* for Ethernet port 2
|
||||
*/
|
||||
gmac2_pins: gmac2-pins {
|
||||
pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
|
||||
<RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD0 */
|
||||
<RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD1 */
|
||||
<RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD2 */
|
||||
<RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD3 */
|
||||
<RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
|
||||
<RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
|
||||
<RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD0 */
|
||||
<RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD1 */
|
||||
<RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD2 */
|
||||
<RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD3 */
|
||||
<RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
|
||||
<RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
|
||||
<RZT2H_PORT_PINMUX(31, 3, 0xf)>, /* ETH2_RXER */
|
||||
<RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
|
||||
<RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
|
||||
<RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
|
||||
<RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */
|
||||
<RZT2H_PORT_PINMUX(31, 0, 0x2)>; /* ETH2_REFCLK */
|
||||
};
|
||||
|
||||
/*
|
||||
* GMAC1 Pin Configuration:
|
||||
*
|
||||
* SW2[8] ON - use pins P33_2-P33_7, P34_0-P34_5, P34_7 and
|
||||
* P35_0-P35_2 for Ethernet port 3
|
||||
*/
|
||||
gmac1_pins: gmac1-pins {
|
||||
pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
|
||||
<RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD0 */
|
||||
<RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD1 */
|
||||
<RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD2 */
|
||||
<RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD3 */
|
||||
<RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
|
||||
<RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
|
||||
<RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD0 */
|
||||
<RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD1 */
|
||||
<RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2 */
|
||||
<RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3 */
|
||||
<RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
|
||||
<RZT2H_PORT_PINMUX(34, 7, 0xf)>, /* ETH3_TXER */
|
||||
<RZT2H_PORT_PINMUX(35, 0, 0xf)>, /* ETH3_RXER */
|
||||
<RZT2H_PORT_PINMUX(35, 1, 0xf)>, /* ETH3_CRS */
|
||||
<RZT2H_PORT_PINMUX(35, 2, 0xf)>, /* ETH3_COL */
|
||||
<RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
|
||||
<RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */
|
||||
<RZT2H_PORT_PINMUX(34, 6, 0x2)>; /* ETH3_REFCLK */
|
||||
};
|
||||
|
||||
/*
|
||||
* I2C0 Pin Configuration:
|
||||
* ------------------------
|
||||
|
|
|
|||
|
|
@ -270,6 +270,484 @@ i2c2: i2c@81008000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac0: ethernet@80100000 {
|
||||
compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth",
|
||||
"snps,dwmac-5.20";
|
||||
reg = <0 0x80100000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
|
||||
"rx-queue-0", "rx-queue-1", "rx-queue-2",
|
||||
"rx-queue-3", "rx-queue-4", "rx-queue-5",
|
||||
"rx-queue-6", "rx-queue-7", "tx-queue-0",
|
||||
"tx-queue-1", "tx-queue-2", "tx-queue-3",
|
||||
"tx-queue-4", "tx-queue-5", "tx-queue-6",
|
||||
"tx-queue-7";
|
||||
clocks = <&cpg CPG_MOD 400>,
|
||||
<&cpg CPG_CORE R9A09G087_CLK_PCLKH>,
|
||||
<&cpg CPG_CORE R9A09G087_ETCLKB>;
|
||||
clock-names = "stmmaceth", "pclk", "tx";
|
||||
resets = <&cpg 400>, <&cpg 401>;
|
||||
reset-names = "stmmaceth", "ahb";
|
||||
power-domains = <&cpg>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <32>;
|
||||
rx-fifo-depth = <8192>;
|
||||
tx-fifo-depth = <8192>;
|
||||
snps,fixed-burst;
|
||||
snps,no-pbl-x8;
|
||||
snps,force_thresh_dma_mode;
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup0>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup0>;
|
||||
snps,txpbl = <16>;
|
||||
snps,rxpbl = <16>;
|
||||
status = "disabled";
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup0: rx-queues-config {
|
||||
snps,rx-queues-to-use = <8>;
|
||||
snps,rx-sched-sp;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
snps,map-to-dma-channel = <0>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
snps,map-to-dma-channel = <1>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
snps,map-to-dma-channel = <2>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
snps,map-to-dma-channel = <3>;
|
||||
};
|
||||
|
||||
queue4 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x10>;
|
||||
snps,map-to-dma-channel = <4>;
|
||||
};
|
||||
|
||||
queue5 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x20>;
|
||||
snps,map-to-dma-channel = <5>;
|
||||
};
|
||||
|
||||
queue6 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x40>;
|
||||
snps,map-to-dma-channel = <6>;
|
||||
};
|
||||
|
||||
queue7 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x80>;
|
||||
snps,map-to-dma-channel = <7>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_tx_setup0: tx-queues-config {
|
||||
snps,tx-queues-to-use = <8>;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue4 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue5 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue6 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue7 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: ethernet@92000000 {
|
||||
compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth",
|
||||
"snps,dwmac-5.20";
|
||||
reg = <0 0x92000000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
|
||||
"rx-queue-0", "rx-queue-1", "rx-queue-2",
|
||||
"rx-queue-3", "rx-queue-4", "rx-queue-5",
|
||||
"rx-queue-6", "rx-queue-7", "tx-queue-0",
|
||||
"tx-queue-1", "tx-queue-2", "tx-queue-3",
|
||||
"tx-queue-4", "tx-queue-5", "tx-queue-6",
|
||||
"tx-queue-7";
|
||||
clocks = <&cpg CPG_MOD 416>,
|
||||
<&cpg CPG_CORE R9A09G087_CLK_PCLKAH>,
|
||||
<&cpg CPG_CORE R9A09G087_ETCLKB>;
|
||||
clock-names = "stmmaceth", "pclk", "tx";
|
||||
resets = <&cpg 416>, <&cpg 417>;
|
||||
reset-names = "stmmaceth", "ahb";
|
||||
power-domains = <&cpg>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <32>;
|
||||
rx-fifo-depth = <8192>;
|
||||
tx-fifo-depth = <8192>;
|
||||
snps,fixed-burst;
|
||||
snps,no-pbl-x8;
|
||||
snps,force_thresh_dma_mode;
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup1>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup1>;
|
||||
snps,txpbl = <16>;
|
||||
snps,rxpbl = <16>;
|
||||
status = "disabled";
|
||||
|
||||
mdio1: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup1: rx-queues-config {
|
||||
snps,rx-queues-to-use = <8>;
|
||||
snps,rx-sched-sp;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
snps,map-to-dma-channel = <0>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
snps,map-to-dma-channel = <1>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
snps,map-to-dma-channel = <2>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
snps,map-to-dma-channel = <3>;
|
||||
};
|
||||
|
||||
queue4 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x10>;
|
||||
snps,map-to-dma-channel = <4>;
|
||||
};
|
||||
|
||||
queue5 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x20>;
|
||||
snps,map-to-dma-channel = <5>;
|
||||
};
|
||||
|
||||
queue6 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x40>;
|
||||
snps,map-to-dma-channel = <6>;
|
||||
};
|
||||
|
||||
queue7 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x80>;
|
||||
snps,map-to-dma-channel = <7>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_tx_setup1: tx-queues-config {
|
||||
snps,tx-queues-to-use = <8>;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue4 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue5 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue6 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue7 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmac2: ethernet@92010000 {
|
||||
compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth",
|
||||
"snps,dwmac-5.20";
|
||||
reg = <0 0x92010000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
|
||||
"rx-queue-0", "rx-queue-1", "rx-queue-2",
|
||||
"rx-queue-3", "rx-queue-4", "rx-queue-5",
|
||||
"rx-queue-6", "rx-queue-7", "tx-queue-0",
|
||||
"tx-queue-1", "tx-queue-2", "tx-queue-3",
|
||||
"tx-queue-4", "tx-queue-5", "tx-queue-6",
|
||||
"tx-queue-7";
|
||||
clocks = <&cpg CPG_MOD 417>,
|
||||
<&cpg CPG_CORE R9A09G087_CLK_PCLKAH>,
|
||||
<&cpg CPG_CORE R9A09G087_ETCLKB>;
|
||||
clock-names = "stmmaceth", "pclk", "tx";
|
||||
resets = <&cpg 418>, <&cpg 419>;
|
||||
reset-names = "stmmaceth", "ahb";
|
||||
power-domains = <&cpg>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <32>;
|
||||
rx-fifo-depth = <8192>;
|
||||
tx-fifo-depth = <8192>;
|
||||
snps,fixed-burst;
|
||||
snps,no-pbl-x8;
|
||||
snps,force_thresh_dma_mode;
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup2>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup2>;
|
||||
snps,txpbl = <16>;
|
||||
snps,rxpbl = <16>;
|
||||
status = "disabled";
|
||||
|
||||
mdio2: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup2: rx-queues-config {
|
||||
snps,rx-queues-to-use = <8>;
|
||||
snps,rx-sched-sp;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
snps,map-to-dma-channel = <0>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
snps,map-to-dma-channel = <1>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
snps,map-to-dma-channel = <2>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
snps,map-to-dma-channel = <3>;
|
||||
};
|
||||
|
||||
queue4 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x10>;
|
||||
snps,map-to-dma-channel = <4>;
|
||||
};
|
||||
|
||||
queue5 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x20>;
|
||||
snps,map-to-dma-channel = <5>;
|
||||
};
|
||||
|
||||
queue6 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x40>;
|
||||
snps,map-to-dma-channel = <6>;
|
||||
};
|
||||
|
||||
queue7 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x80>;
|
||||
snps,map-to-dma-channel = <7>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_tx_setup2: tx-queues-config {
|
||||
snps,tx-queues-to-use = <8>;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue4 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue5 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue6 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue7 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethss: ethss@80110000 {
|
||||
compatible = "renesas,r9a09g087-miic", "renesas,r9a09g077-miic";
|
||||
reg = <0 0x80110000 0 0x10000>;
|
||||
clocks = <&cpg CPG_CORE R9A09G087_ETCLKE>,
|
||||
<&cpg CPG_CORE R9A09G087_ETCLKB>,
|
||||
<&cpg CPG_CORE R9A09G087_ETCLKD>,
|
||||
<&cpg CPG_MOD 403>;
|
||||
clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
|
||||
resets = <&cpg 405>, <&cpg 406>;
|
||||
reset-names = "rst", "crst";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mii_conv0: mii-conv@0 {
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mii_conv1: mii-conv@1 {
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mii_conv2: mii-conv@2 {
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mii_conv3: mii-conv@3 {
|
||||
reg = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
cpg: clock-controller@80280000 {
|
||||
compatible = "renesas,r9a09g087-cpg-mssr";
|
||||
reg = <0 0x80280000 0 0x1000>,
|
||||
|
|
@ -458,6 +936,13 @@ sdhi1_vqmmc: vqmmc-regulator {
|
|||
};
|
||||
};
|
||||
|
||||
stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,lpi_en;
|
||||
snps,wr_osr_lmt = <0xf>;
|
||||
snps,rd_osr_lmt = <0xf>;
|
||||
snps,blen = <16 8 4 0 0 0 0>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
|
|
|
|||
|
|
@ -186,7 +186,85 @@ &i2c1 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio1_phy {
|
||||
/*
|
||||
* PHY3 Reset Configuration:
|
||||
*
|
||||
* DSW12[5] OFF; DSW12[6] ON - use pin P03_2 for GMAC_RESETOUT3#
|
||||
*/
|
||||
reset-gpios = <&pinctrl RZT2H_GPIO(3, 2) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&mdio2_phy {
|
||||
/*
|
||||
* PHY2 Reset Configuration:
|
||||
*
|
||||
* DSW8[1] ON; DSW8[2] OFF; DSW12[7] OFF; DSW12[8] ON - use pin
|
||||
* P03_1 for GMAC_RESETOUT2#
|
||||
*/
|
||||
reset-gpios = <&pinctrl RZT2H_GPIO(3, 1) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
/*
|
||||
* GMAC2 Pin Configuration:
|
||||
*
|
||||
* DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2
|
||||
* DSW5[7] ON - use pins P29_1-P29_7, P30_0-P30_4, P30_7,
|
||||
* P31_2, P31_4 and P31_5 are used for Ethernet port 2
|
||||
*/
|
||||
gmac2_pins: gmac2-pins {
|
||||
pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
|
||||
<RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD0 */
|
||||
<RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD1 */
|
||||
<RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD2 */
|
||||
<RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD3 */
|
||||
<RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
|
||||
<RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
|
||||
<RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD0 */
|
||||
<RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD1 */
|
||||
<RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD2 */
|
||||
<RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD3 */
|
||||
<RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
|
||||
<RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
|
||||
<RZT2H_PORT_PINMUX(31, 1, 0xf)>, /* ETH2_RXER */
|
||||
<RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
|
||||
<RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
|
||||
<RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
|
||||
<RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */
|
||||
<RZT2H_PORT_PINMUX(31, 0, 0x2)>; /* ETH2_REFCLK */
|
||||
|
||||
};
|
||||
|
||||
/*
|
||||
* GMAC2 Pin Configuration:
|
||||
*
|
||||
* DSW5[8] ON - use pins P00_0-P00_2, P33_2-P33_7, P34_0-P34_6
|
||||
* for Ethernet port 3
|
||||
* DSW12[1] OFF; DSW12[2] ON - use pin P00_3 for Ethernet port 3
|
||||
*/
|
||||
gmac1_pins: gmac1-pins {
|
||||
pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
|
||||
<RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD0 */
|
||||
<RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD0 */
|
||||
<RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD2 */
|
||||
<RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD3 */
|
||||
<RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
|
||||
<RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
|
||||
<RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD0 */
|
||||
<RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD1 */
|
||||
<RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2 */
|
||||
<RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3 */
|
||||
<RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
|
||||
<RZT2H_PORT_PINMUX(0, 0, 0xf)>, /* ETH3_TXER */
|
||||
<RZT2H_PORT_PINMUX(0, 1, 0xf)>, /* ETH3_RXER */
|
||||
<RZT2H_PORT_PINMUX(0, 2, 0xf)>, /* ETH3_CRS */
|
||||
<RZT2H_PORT_PINMUX(0, 3, 0xf)>, /* ETH3_COL */
|
||||
<RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
|
||||
<RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */
|
||||
<RZT2H_PORT_PINMUX(34, 6, 0x2)>; /* ETH3_REFCLK */
|
||||
};
|
||||
|
||||
/*
|
||||
* I2C0 Pin Configuration:
|
||||
* ------------------------
|
||||
|
|
|
|||
|
|
@ -92,6 +92,20 @@ &audio_clk2 {
|
|||
clock-frequency = <12288000>;
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -132,6 +146,19 @@ power-monitor@44 {
|
|||
};
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&phyrst {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
audio_clock_pins: audio-clock {
|
||||
pins = "AUDIO_CLK1", "AUDIO_CLK2";
|
||||
|
|
@ -207,6 +234,23 @@ ssi3_pins: ssi3 {
|
|||
<RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */
|
||||
<RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
peri {
|
||||
pinmux = <RZG2L_PORT_PINMUX(5, 0, 1)>, /* VBUS */
|
||||
<RZG2L_PORT_PINMUX(5, 2, 1)>; /* OVC */
|
||||
};
|
||||
|
||||
otg {
|
||||
pinmux = <RZG2L_PORT_PINMUX(5, 3, 1)>; /* OTG_ID */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(5, 4, 5)>, /* OVC */
|
||||
<RZG2L_PORT_PINMUX(6, 0, 1)>; /* VBUS */
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
|
|
@ -242,3 +286,16 @@ &ssi3 {
|
|||
pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
vbus-supply = <&usb0_vbus_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -7,10 +7,14 @@
|
|||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/net/mscc-phy-vsc8531.h>
|
||||
#include <dt-bindings/net/renesas,r9a09g077-pcs-miic.h>
|
||||
#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
ethernet3 = &gmac1;
|
||||
ethernet2 = &gmac2;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhi0;
|
||||
|
|
@ -70,10 +74,34 @@ &ehci {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
ðss {
|
||||
status = "okay";
|
||||
|
||||
renesas,miic-switch-portin = <ETHSS_GMAC0_PORT>;
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
pinctrl-0 = <&gmac1_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&mdio1_phy>;
|
||||
phy-mode = "rgmii-id";
|
||||
pcs-handle = <&mii_conv3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac2 {
|
||||
pinctrl-0 = <&gmac2_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&mdio2_phy>;
|
||||
phy-mode = "rgmii-id";
|
||||
pcs-handle = <&mii_conv2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
|
|
@ -87,6 +115,48 @@ eeprom: eeprom@50 {
|
|||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
mdio1_phy: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <3>;
|
||||
vsc8531,led-0-mode = <VSC8531_ACTIVITY>;
|
||||
vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
|
||||
reset-assert-us = <2000>;
|
||||
reset-deassert-us = <15000>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio2 {
|
||||
mdio2_phy: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <2>;
|
||||
vsc8531,led-0-mode = <VSC8531_ACTIVITY>;
|
||||
vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
|
||||
reset-assert-us = <2000>;
|
||||
reset-deassert-us = <15000>;
|
||||
};
|
||||
};
|
||||
|
||||
&mii_conv0 {
|
||||
renesas,miic-input = <ETHSS_ETHSW_PORT0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mii_conv1 {
|
||||
renesas,miic-input = <ETHSS_ETHSW_PORT1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mii_conv2 {
|
||||
renesas,miic-input = <ETHSS_GMAC2_PORT>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mii_conv3 {
|
||||
renesas,miic-input = <ETHSS_GMAC1_PORT>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -51,5 +51,6 @@
|
|||
#define R8A779A0_CLK_CBFUSA 40
|
||||
#define R8A779A0_CLK_R 41
|
||||
#define R8A779A0_CLK_OSC 42
|
||||
#define R8A779A0_CLK_ZG 43
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user