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arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support
Enable Ethernet support on the RZ/T2H and RZ/N2H EVKs. Configure the MIIC converter in mode 0x6: Port 0 <-> ETHSW Port 0 Port 1 <-> ETHSW Port 1 Port 2 <-> GMAC2 Port 3 <-> GMAC1 Enable the ETHSS, GMAC1 and GMAC2 nodes. ETHSW support will be added once the switch driver is available. Configure the MIIC converters to map ports according to the selected switching mode, with converters 0 and 1 mapped to switch ports and converters 2 and 3 mapped to GMAC ports. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251110203926.692242-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar
Geert Uytterhoeven
parent
1eb61aa4d8
commit
b272b94fd2
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@ -149,7 +149,77 @@ &i2c1 {
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status = "okay";
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};
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&mdio1_phy {
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reset-gpios = <&pinctrl RZT2H_GPIO(32, 3) GPIO_ACTIVE_LOW>;
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};
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&mdio2_phy {
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/*
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* PHY2 Reset Configuration:
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*
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* SW6[1] OFF; SW6[2] ON; SW6[3] OFF - use pin P17_5 for GMAC_RESETOUT2#
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*/
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reset-gpios = <&pinctrl RZT2H_GPIO(17, 5) GPIO_ACTIVE_LOW>;
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};
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&pinctrl {
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/*
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* GMAC2 Pin Configuration:
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*
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* SW2[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2
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* SW2[7] ON - use pins P29_1-P29_7, P30_0-P30_4, and P31_2-P31_5
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* for Ethernet port 2
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*/
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gmac2_pins: gmac2-pins {
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pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
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<RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD0 */
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<RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD1 */
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<RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD2 */
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<RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD3 */
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<RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
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<RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
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<RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD0 */
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<RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD1 */
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<RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD2 */
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<RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD3 */
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<RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
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<RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
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<RZT2H_PORT_PINMUX(31, 3, 0xf)>, /* ETH2_RXER */
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<RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
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<RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
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<RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
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<RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */
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<RZT2H_PORT_PINMUX(31, 0, 0x2)>; /* ETH2_REFCLK */
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};
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/*
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* GMAC1 Pin Configuration:
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*
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* SW2[8] ON - use pins P33_2-P33_7, P34_0-P34_5, P34_7 and
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* P35_0-P35_2 for Ethernet port 3
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*/
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gmac1_pins: gmac1-pins {
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pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
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<RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD0 */
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<RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD1 */
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<RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD2 */
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<RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD3 */
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<RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
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<RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
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<RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD0 */
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<RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD1 */
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<RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2 */
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<RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3 */
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<RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
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<RZT2H_PORT_PINMUX(34, 7, 0xf)>, /* ETH3_TXER */
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<RZT2H_PORT_PINMUX(35, 0, 0xf)>, /* ETH3_RXER */
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<RZT2H_PORT_PINMUX(35, 1, 0xf)>, /* ETH3_CRS */
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<RZT2H_PORT_PINMUX(35, 2, 0xf)>, /* ETH3_COL */
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<RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
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<RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */
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<RZT2H_PORT_PINMUX(34, 6, 0x2)>; /* ETH3_REFCLK */
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};
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/*
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* I2C0 Pin Configuration:
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* ------------------------
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@ -186,7 +186,85 @@ &i2c1 {
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status = "okay";
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};
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&mdio1_phy {
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/*
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* PHY3 Reset Configuration:
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*
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* DSW12[5] OFF; DSW12[6] ON - use pin P03_2 for GMAC_RESETOUT3#
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*/
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reset-gpios = <&pinctrl RZT2H_GPIO(3, 2) GPIO_ACTIVE_LOW>;
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};
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&mdio2_phy {
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/*
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* PHY2 Reset Configuration:
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*
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* DSW8[1] ON; DSW8[2] OFF; DSW12[7] OFF; DSW12[8] ON - use pin
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* P03_1 for GMAC_RESETOUT2#
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*/
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reset-gpios = <&pinctrl RZT2H_GPIO(3, 1) GPIO_ACTIVE_LOW>;
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};
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&pinctrl {
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/*
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* GMAC2 Pin Configuration:
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*
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* DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2
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* DSW5[7] ON - use pins P29_1-P29_7, P30_0-P30_4, P30_7,
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* P31_2, P31_4 and P31_5 are used for Ethernet port 2
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*/
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gmac2_pins: gmac2-pins {
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pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
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<RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD0 */
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<RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD1 */
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<RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD2 */
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<RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD3 */
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<RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
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<RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
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<RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD0 */
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<RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD1 */
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<RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD2 */
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<RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD3 */
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<RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
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<RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
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<RZT2H_PORT_PINMUX(31, 1, 0xf)>, /* ETH2_RXER */
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<RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
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<RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
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<RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
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<RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */
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<RZT2H_PORT_PINMUX(31, 0, 0x2)>; /* ETH2_REFCLK */
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};
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/*
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* GMAC2 Pin Configuration:
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*
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* DSW5[8] ON - use pins P00_0-P00_2, P33_2-P33_7, P34_0-P34_6
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* for Ethernet port 3
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* DSW12[1] OFF; DSW12[2] ON - use pin P00_3 for Ethernet port 3
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*/
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gmac1_pins: gmac1-pins {
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pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
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<RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD0 */
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<RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD0 */
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<RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD2 */
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<RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD3 */
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<RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
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<RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
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<RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD0 */
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<RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD1 */
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<RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2 */
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<RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3 */
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<RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
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<RZT2H_PORT_PINMUX(0, 0, 0xf)>, /* ETH3_TXER */
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<RZT2H_PORT_PINMUX(0, 1, 0xf)>, /* ETH3_RXER */
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<RZT2H_PORT_PINMUX(0, 2, 0xf)>, /* ETH3_CRS */
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<RZT2H_PORT_PINMUX(0, 3, 0xf)>, /* ETH3_COL */
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<RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
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<RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */
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<RZT2H_PORT_PINMUX(34, 6, 0x2)>; /* ETH3_REFCLK */
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};
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/*
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* I2C0 Pin Configuration:
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* ------------------------
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@ -7,10 +7,14 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/net/mscc-phy-vsc8531.h>
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#include <dt-bindings/net/renesas,r9a09g077-pcs-miic.h>
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#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
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/ {
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aliases {
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ethernet3 = &gmac1;
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ethernet2 = &gmac2;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &sdhi0;
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@ -70,10 +74,34 @@ &ehci {
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status = "okay";
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};
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ðss {
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status = "okay";
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renesas,miic-switch-portin = <ETHSS_GMAC0_PORT>;
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};
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&extal_clk {
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clock-frequency = <25000000>;
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};
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&gmac1 {
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pinctrl-0 = <&gmac1_pins>;
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pinctrl-names = "default";
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phy-handle = <&mdio1_phy>;
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phy-mode = "rgmii-id";
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pcs-handle = <&mii_conv3>;
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status = "okay";
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};
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&gmac2 {
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pinctrl-0 = <&gmac2_pins>;
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pinctrl-names = "default";
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phy-handle = <&mdio2_phy>;
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phy-mode = "rgmii-id";
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pcs-handle = <&mii_conv2>;
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status = "okay";
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};
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&hsusb {
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dr_mode = "otg";
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status = "okay";
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@ -87,6 +115,48 @@ eeprom: eeprom@50 {
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};
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};
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&mdio1 {
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mdio1_phy: ethernet-phy@3 {
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compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22";
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reg = <3>;
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vsc8531,led-0-mode = <VSC8531_ACTIVITY>;
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vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
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reset-assert-us = <2000>;
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reset-deassert-us = <15000>;
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};
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};
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&mdio2 {
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mdio2_phy: ethernet-phy@2 {
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compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22";
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reg = <2>;
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vsc8531,led-0-mode = <VSC8531_ACTIVITY>;
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vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
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reset-assert-us = <2000>;
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reset-deassert-us = <15000>;
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};
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};
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&mii_conv0 {
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renesas,miic-input = <ETHSS_ETHSW_PORT0>;
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status = "okay";
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};
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&mii_conv1 {
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renesas,miic-input = <ETHSS_ETHSW_PORT1>;
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status = "okay";
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};
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&mii_conv2 {
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renesas,miic-input = <ETHSS_GMAC2_PORT>;
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status = "okay";
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};
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&mii_conv3 {
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renesas,miic-input = <ETHSS_GMAC1_PORT>;
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status = "okay";
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};
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&ohci {
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dr_mode = "otg";
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status = "okay";
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