github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-07-31 03:27:03 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

Snap for 8187536 from 174eff53b1 to android-mainline-keystone-qcom-release

Browse Source 
Change-Id: I7ed49f055c3bbcdbbb1a6cae0fa173453c1efa7c
This commit is contained in:
Android Build Coastguard Worker 2022-02-15 23:49:30 +00:00
commit 935b7f9baf
2592 changed files with 96576 additions and 53985 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.clang-format
View File

@ -216,7 +216,6 @@ ForEachMacros:
- 'for_each_migratetype_order'
- 'for_each_msi_entry'
- 'for_each_msi_entry_safe'
- 'for_each_msi_vector'
- 'for_each_net'
- 'for_each_net_continue_reverse'
- 'for_each_netdev'

2
BUILD.bazel
View File

@ -17,6 +17,6 @@ package(
],
)
load("//build/kleaf:common_kernels.bzl", "define_common_kernels")
load("//build/kernel/kleaf:common_kernels.bzl", "define_common_kernels")
define_common_kernels()

22
Documentation/ABI/obsolete/sysfs-class-dax
View File

@ -1,22 +0,0 @@
What: /sys/class/dax/
Date: May, 2016
KernelVersion: v4.7
Contact: nvdimm@lists.linux.dev
Description: Device DAX is the device-centric analogue of Filesystem
DAX (CONFIG_FS_DAX). It allows memory ranges to be
allocated and mapped without need of an intervening file
system. Device DAX is strict, precise and predictable.
Specifically this interface:
1. Guarantees fault granularity with respect to a given
page size (pte, pmd, or pud) set at configuration time.
2. Enforces deterministic behavior by being strict about
what fault scenarios are supported.
The /sys/class/dax/ interface enumerates all the
device-dax instances in the system. The ABI is
deprecated and will be removed after 2020. It is
replaced with the DAX bus interface /sys/bus/dax/ where
device-dax instances can be found under
/sys/bus/dax/devices/

23
Documentation/ABI/testing/debugfs-driver-habanalabs
View File

@ -21,11 +21,11 @@ Description: Allow the root user to disable/enable in runtime the clock
a different engine to disable/enable its clock gating feature.
The bitmask is composed of 20 bits:
======= ============
======= ============
0 - 7 DMA channels
8 - 11 MME engines
12 - 19 TPC engines
======= ============
======= ============
The bit's location of a specific engine can be determined
using (1 << GAUDI_ENGINE_ID_*). GAUDI_ENGINE_ID_* values
@ -155,6 +155,13 @@ Description: Triggers an I2C transaction that is generated by the device's
CPU. Writing to this file generates a write transaction while
reading from the file generates a read transaction
What: /sys/kernel/debug/habanalabs/hl<n>/i2c_len
Date: Dec 2021
KernelVersion: 5.17
Contact: obitton@habana.ai
Description: Sets I2C length in bytes for I2C transaction that is generated by
the device's CPU
What: /sys/kernel/debug/habanalabs/hl<n>/i2c_reg
Date: Jan 2019
KernelVersion: 5.1
@ -226,12 +233,6 @@ Description: Gets the state dump occurring on a CS timeout or failure.
Writing an integer X discards X state dumps, so that the
next read would return X+1-st newest state dump.
What: /sys/kernel/debug/habanalabs/hl<n>/timeout_locked
Date: Sep 2021
KernelVersion: 5.16
Contact: obitton@habana.ai
Description: Sets the command submission timeout value in seconds.
What: /sys/kernel/debug/habanalabs/hl<n>/stop_on_err
Date: Mar 2020
KernelVersion: 5.6
@ -239,6 +240,12 @@ Contact: ogabbay@kernel.org
Description: Sets the stop-on_error option for the device engines. Value of
"0" is for disable, otherwise enable.
What: /sys/kernel/debug/habanalabs/hl<n>/timeout_locked
Date: Sep 2021
KernelVersion: 5.16
Contact: obitton@habana.ai
Description: Sets the command submission timeout value in seconds.
What: /sys/kernel/debug/habanalabs/hl<n>/userptr
Date: Jan 2019
KernelVersion: 5.1

16
Documentation/ABI/testing/sysfs-bus-iio-filter-admv8818 Normal file
View File

@ -0,0 +1,16 @@
What: /sys/bus/iio/devices/iio:deviceX/filter_mode_available
KernelVersion:
Contact: linux-iio@vger.kernel.org
Description:
Reading this returns the valid values that can be written to the
on_altvoltage0_mode attribute:
- auto -> Adjust bandpass filter to track changes in input clock rate.
- manual -> disable/unregister the clock rate notifier / input clock tracking.
What: /sys/bus/iio/devices/iio:deviceX/filter_mode
KernelVersion:
Contact: linux-iio@vger.kernel.org
Description:
This attribute configures the filter mode.
Reading returns the actual mode.

38
Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1013 Normal file
View File

@ -0,0 +1,38 @@
What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-1_i_calibphase
KernelVersion:
Contact: linux-iio@vger.kernel.org
Description:
Read/write unscaled value for the Local Oscillatior path quadrature I phase shift.
What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-1_q_calibphase
KernelVersion:
Contact: linux-iio@vger.kernel.org
Description:
Read/write unscaled value for the Local Oscillatior path quadrature Q phase shift.
What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_i_calibbias
KernelVersion:
Contact: linux-iio@vger.kernel.org
Description:
Read/write value for the Local Oscillatior Feedthrough Offset Calibration I Positive
side.
What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_q_calibbias
KernelVersion:
Contact: linux-iio@vger.kernel.org
Description:
Read/write value for the Local Oscillatior Feedthrough Offset Calibration Q Positive side.
What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage1_i_calibbias
KernelVersion:
Contact: linux-iio@vger.kernel.org
Description:
Read/write raw value for the Local Oscillatior Feedthrough Offset Calibration I Negative
side.
What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage1_q_calibbias
KernelVersion:
Contact: linux-iio@vger.kernel.org
Description:
Read/write raw value for the Local Oscillatior Feedthrough Offset Calibration Q Negative
side.

20
Documentation/admin-guide/kernel-parameters.txt
View File

@ -612,8 +612,8 @@
clocksource.max_cswd_read_retries= [KNL]
Number of clocksource_watchdog() retries due to
external delays before the clock will be marked
unstable. Defaults to three retries, that is,
four attempts to read the clock under test.
unstable. Defaults to two retries, that is,
three attempts to read the clock under test.
clocksource.verify_n_cpus= [KNL]
Limit the number of CPUs checked for clocksources
@ -3397,7 +3397,7 @@
Disable SMAP (Supervisor Mode Access Prevention)
even if it is supported by processor.
nosmep [X86,PPC]
nosmep [X86,PPC64s]
Disable SMEP (Supervisor Mode Execution Prevention)
even if it is supported by processor.
@ -4170,6 +4170,14 @@
Override pmtimer IOPort with a hex value.
e.g. pmtmr=0x508
pmu_override= [PPC] Override the PMU.
This option takes over the PMU facility, so it is no
longer usable by perf. Setting this option starts the
PMU counters by setting MMCR0 to 0 (the FC bit is
cleared). If a number is given, then MMCR1 is set to
that number, otherwise (e.g., 'pmu_override=on'), MMCR1
remains 0.
pm_debug_messages [SUSPEND,KNL]
Enable suspend/resume debug messages during boot up.
@ -6498,6 +6506,12 @@
controller on both pseries and powernv
platforms. Only useful on POWER9 and above.
xive.store-eoi=off [PPC]
By default on POWER10 and above, the kernel will use
stores for EOI handling when the XIVE interrupt mode
is active. This option allows the XIVE driver to use
loads instead, as on POWER9.
xhci-hcd.quirks [USB,KNL]
A hex value specifying bitmask with supplemental xhci
host controller quirks. Meaning of each bit can be

4
Documentation/devicetree/bindings/Makefile
View File

@ -65,7 +65,9 @@ DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd)))
override DTC_FLAGS := \
-Wno-avoid_unnecessary_addr_size \
-Wno-graph_child_address \
-Wno-interrupt_provider
-Wno-interrupt_provider \
-Wno-unique_unit_address \
-Wunique_unit_address_if_enabled
# Disable undocumented compatible checks until warning free
override DT_CHECKER_FLAGS ?=

10
Documentation/devicetree/bindings/arm/arm,cci-400.yaml
View File

@ -166,16 +166,6 @@ examples:
};
};
dma0: dma@3000000 {
/* compatible = "arm,pl330", "arm,primecell"; */
cci-control-port = <&cci_control0>;
reg = <0x0 0x3000000 0x0 0x1000>;
interrupts = <10>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
cci@2c090000 {
compatible = "arm,cci-400";
#address-cells = <1>;

27
Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
View File

@ -1,27 +0,0 @@
* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
with a shared L3 memory system, control logic and external interfaces to
form a multicore cluster. The PMU enables to gather various statistics on
the operations of the DSU. The PMU provides independent 32bit counters that
can count any of the supported events, along with a 64bit cycle counter.
The PMU is accessed via CPU system registers and has no MMIO component.
** DSU PMU required properties:
- compatible : should be one of :
"arm,dsu-pmu"
- interrupts : Exactly 1 SPI must be listed.
- cpus : List of phandles for the CPUs connected to this DSU instance.
** Example:
dsu-pmu-0 {
compatible = "arm,dsu-pmu";
interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
cpus = <&cpu_0>, <&cpu_1>;
};

7
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@ -137,6 +137,9 @@ properties:
- arm,cortex-a75
- arm,cortex-a76
- arm,cortex-a77
- arm,cortex-a78
- arm,cortex-a510
- arm,cortex-a710
- arm,cortex-m0
- arm,cortex-m0+
- arm,cortex-m1
@ -145,8 +148,12 @@ properties:
- arm,cortex-r4
- arm,cortex-r5
- arm,cortex-r7
- arm,cortex-x1
- arm,cortex-x2
- arm,neoverse-e1
- arm,neoverse-n1
- arm,neoverse-n2
- arm,neoverse-v1
- brcm,brahma-b15
- brcm,brahma-b53
- brcm,vulcan

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
View File

@ -14,6 +14,7 @@ Required Properties:
- "mediatek,mt7622-apmixedsys"
- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
- "mediatek,mt7629-apmixedsys"
- "mediatek,mt7986-apmixedsys"
- "mediatek,mt8135-apmixedsys"
- "mediatek,mt8167-apmixedsys", "syscon"
- "mediatek,mt8173-apmixedsys"

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
View File

@ -10,6 +10,7 @@ Required Properties:
- "mediatek,mt7622-ethsys", "syscon"
- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7629-ethsys", "syscon"
- "mediatek,mt7986-ethsys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
View File

@ -15,6 +15,7 @@ Required Properties:
- "mediatek,mt7622-infracfg", "syscon"
- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
- "mediatek,mt7629-infracfg", "syscon"
- "mediatek,mt7986-infracfg", "syscon"
- "mediatek,mt8135-infracfg", "syscon"
- "mediatek,mt8167-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon"

2
Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
View File

@ -8,6 +8,8 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-sgmiisys", "syscon"
- "mediatek,mt7629-sgmiisys", "syscon"
- "mediatek,mt7986-sgmiisys_0", "syscon"
- "mediatek,mt7986-sgmiisys_1", "syscon"
- #clock-cells: Must be 1
The SGMIISYS controller uses the common clk binding from

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
View File

@ -14,6 +14,7 @@ Required Properties:
- "mediatek,mt7622-topckgen"
- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
- "mediatek,mt7629-topckgen"
- "mediatek,mt7986-topckgen", "syscon"
- "mediatek,mt8135-topckgen"
- "mediatek,mt8167-topckgen", "syscon"
- "mediatek,mt8173-topckgen"

8
Documentation/devicetree/bindings/arm/pmu.yaml
View File

@ -44,10 +44,18 @@ properties:
- arm,cortex-a76-pmu
- arm,cortex-a77-pmu
- arm,cortex-a78-pmu
- arm,cortex-a510-pmu
- arm,cortex-a710-pmu
- arm,cortex-x1-pmu
- arm,cortex-x2-pmu
- arm,neoverse-e1-pmu
- arm,neoverse-n1-pmu
- arm,neoverse-n2-pmu
- arm,neoverse-v1-pmu
- brcm,vulcan-pmu
- cavium,thunder-pmu
- nvidia,denver-pmu
- nvidia,carmel-pmu
- qcom,krait-pmu
- qcom,scorpion-pmu
- qcom,scorpion-mp-pmu

30
Documentation/devicetree/bindings/arm/ux500.yaml
View File

@ -20,6 +20,11 @@ properties:
- const: st-ericsson,mop500
- const: st-ericsson,u8500
- description: ST-Ericsson HREF520
items:
- const: st-ericsson,href520
- const: st-ericsson,u8500
- description: ST-Ericsson HREF (v60+)
items:
- const: st-ericsson,hrefv60+
@ -30,9 +35,34 @@ properties:
- const: calaosystems,snowball-a9500
- const: st-ericsson,u9500
- description: Samsung Galaxy Ace 2 (GT-I8160)
items:
- const: samsung,codina
- const: st-ericsson,u8500
- description: Samsung Galaxy Beam (GT-I8530)
items:
- const: samsung,gavini
- const: st-ericsson,u8500
- description: Samsung Galaxy S III mini (GT-I8190)
items:
- const: samsung,golden
- const: st-ericsson,u8500
- description: Samsung Galaxy S Advance (GT-I9070)
items:
- const: samsung,janice
- const: st-ericsson,u8500
- description: Samsung Galaxy Amp (SGH-I407)
items:
- const: samsung,kyle
- const: st-ericsson,u8500
- description: Samsung Galaxy XCover 2 (GT-S7710)
items:
- const: samsung,skomer
- const: st-ericsson,u8500
additionalProperties: true

14
Documentation/devicetree/bindings/arm/xen.txt
View File

@ -7,15 +7,17 @@ the following properties:
compatible = "xen,xen-<version>", "xen,xen";
where <version> is the version of the Xen ABI of the platform.
- reg: specifies the base physical address and size of a region in
memory where the grant table should be mapped to, using an
HYPERVISOR_memory_op hypercall. The memory region is large enough to map
the whole grant table (it is larger or equal to gnttab_max_grant_frames()).
This property is unnecessary when booting Dom0 using ACPI.
- reg: specifies the base physical address and size of the regions in memory
where the special resources should be mapped to, using an HYPERVISOR_memory_op
hypercall.
Region 0 is reserved for mapping grant table, it must be always present.
The memory region is large enough to map the whole grant table (it is larger
or equal to gnttab_max_grant_frames()).
Regions 1...N are extended regions (unused address space) for mapping foreign
GFNs and grants, they might be absent if there is nothing to expose.
- interrupts: the interrupt used by Xen to inject event notifications.
A GIC node is also required.
This property is unnecessary when booting Dom0 using ACPI.
To support UEFI on Xen ARM virtual platforms, Xen populates the FDT "uefi" node
under /hypervisor with following parameters:

45
Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
View File

@ -1,45 +0,0 @@
* Broadcom SATA3 AHCI Controller
SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
Required properties:
- compatible : should be one or more of
"brcm,bcm7216-ahci"
"brcm,bcm7425-ahci"
"brcm,bcm7445-ahci"
"brcm,bcm-nsp-ahci"
"brcm,sata3-ahci"
"brcm,bcm63138-ahci"
- reg : register mappings for AHCI and SATA_TOP_CTRL
- reg-names : "ahci" and "top-ctrl"
- interrupts : interrupt mapping for SATA IRQ
Optional properties:
- reset: for "brcm,bcm7216-ahci" must be a valid reset phandle
pointing to the RESCAL reset controller provider node.
- reset-names: for "brcm,bcm7216-ahci", must be "rescal".
Also see ahci-platform.txt.
Example:
sata@f045a000 {
compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>;
reg-names = "ahci", "top-ctrl";
interrupts = <0 30 0>;
#address-cells = <1>;
#size-cells = <0>;
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy 0>;
};
sata1: sata-port@1 {
reg = <1>;
phys = <&sata_phy 1>;
};
};

90
Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml Normal file
View File

@ -0,0 +1,90 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom SATA3 AHCI Controller
description:
SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
allOf:
- $ref: sata-common.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- brcm,bcm7216-ahci
- brcm,bcm7445-ahci
- brcm,bcm7425-ahci
- brcm,bcm63138-ahci
- const: brcm,sata3-ahci
- items:
- const: brcm,bcm-nsp-ahci
reg:
minItems: 2
maxItems: 2
reg-names:
items:
- const: ahci
- const: top-ctrl
interrupts:
maxItems: 1
dma-coherent: true
if:
properties:
compatible:
contains:
enum:
- brcm,bcm7216-ahci
- brcm,bcm63138-ahci
then:
properties:
resets:
maxItems: 1
reset-names:
enum:
- rescal
- ahci
required:
- compatible
- reg
- interrupts
- "#address-cells"
- "#size-cells"
unevaluatedProperties: false
examples:
- |
sata@f045a000 {
compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>;
reg-names = "ahci", "top-ctrl";
interrupts = <0 30 0>;
#address-cells = <1>;
#size-cells = <0>;
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy 0>;
};
sata1: sata-port@1 {
reg = <1>;
phys = <&sata_phy 1>;
};
};

34
Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
View File

@ -1,34 +0,0 @@
Broadcom GISB bus Arbiter controller
Required properties:
- compatible:
"brcm,bcm7278-gisb-arb" for V7 28nm chips
"brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips
"brcm,bcm7435-gisb-arb" for newer 40nm chips
"brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
"brcm,bcm7038-gisb-arb" for 130nm chips
- reg: specifies the base physical address and size of the registers
- interrupts: specifies the two interrupts (timeout and TEA) to be used from
the parent interrupt controller. A third optional interrupt may be specified
for breakpoints.
Optional properties:
- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB
masters are valid at the system level
- brcm,gisb-arb-master-names: string list of the litteral name of the GISB
masters. Should match the number of bits set in brcm,gisb-master-mask and
the order in which they appear
Example:
gisb-arb@f0400000 {
compatible = "brcm,gisb-arb";
reg = <0xf0400000 0x800>;
interrupts = <0>, <2>;
interrupt-parent = <&sun_l2_intc>;
brcm,gisb-arb-master-mask = <0x7>;
brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
};

66
Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml Normal file
View File

@ -0,0 +1,66 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom GISB bus Arbiter controller
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
properties:
compatible:
oneOf:
- items:
- enum:
- brcm,bcm7445-gisb-arb # for other 28nm chips
- const: brcm,gisb-arb
- items:
- enum:
- brcm,bcm7278-gisb-arb # for V7 28nm chips
- brcm,bcm7435-gisb-arb # for newer 40nm chips
- brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips
- brcm,bcm7038-gisb-arb # for 130nm chips
- brcm,gisb-arb # fallback compatible
reg:
maxItems: 1
interrupts:
minItems: 2
items:
- description: timeout interrupt line
- description: target abort interrupt line
- description: breakpoint interrupt line
brcm,gisb-arb-master-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
32-bits wide bitmask used to specify which GISB masters are valid at the
system level
brcm,gisb-arb-master-names:
$ref: /schemas/types.yaml#/definitions/string-array
description: >
String list of the litteral name of the GISB masters. Should match the
number of bits set in brcm,gisb-master-mask and the order in which they
appear from MSB to LSB.
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
gisb-arb@f0400000 {
compatible = "brcm,gisb-arb";
reg = <0xf0400000 0x800>;
interrupts = <0>, <2>;
interrupt-parent = <&sun_l2_intc>;
brcm,gisb-arb-master-mask = <0x7>;
brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
};

4
Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
View File

@ -34,6 +34,8 @@ properties:
- allwinner,sun8i-v3-ccu
- allwinner,sun8i-v3s-ccu
- allwinner,sun9i-a80-ccu
- allwinner,sun20i-d1-ccu
- allwinner,sun20i-d1-r-ccu
- allwinner,sun50i-a64-ccu
- allwinner,sun50i-a64-r-ccu
- allwinner,sun50i-a100-ccu
@ -79,6 +81,7 @@ if:
enum:
- allwinner,sun8i-a83t-r-ccu
- allwinner,sun8i-h3-r-ccu
- allwinner,sun20i-d1-r-ccu
- allwinner,sun50i-a64-r-ccu
- allwinner,sun50i-a100-r-ccu
- allwinner,sun50i-h6-r-ccu
@ -99,6 +102,7 @@ else:
properties:
compatible:
enum:
- allwinner,sun20i-d1-ccu
- allwinner,sun50i-a100-ccu
- allwinner,sun50i-h6-ccu
- allwinner,sun50i-h616-ccu

190
Documentation/devicetree/bindings/clock/exynos5260-clock.txt
View File

@ -1,190 +0,0 @@
* Samsung Exynos5260 Clock Controller
Exynos5260 has 13 clock controllers which are instantiated
independently from the device-tree. These clock controllers
generate and supply clocks to various hardware blocks within
the SoC.
Each clock is assigned an identifier and client nodes can use
this identifier to specify the clock which they consume. All
available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5260-clk.h header and can be used in
device tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It
is expected that they are defined using standard clock bindings
with following clock-output-names:
- "fin_pll" - PLL input clock from XXTI
- "xrtcxti" - input clock from XRTCXTI
- "ioclk_pcm_extclk" - pcm external operation clock
- "ioclk_spdif_extclk" - spdif external operation clock
- "ioclk_i2s_cdclk" - i2s0 codec clock
Phy clocks:
There are several clocks which are generated by specific PHYs.
These clocks are fed into the clock controller and then routed to
the hardware blocks. These clocks are defined as fixed clocks in the
driver with following names:
- "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
- "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
- "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
- "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
- "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
- "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
- "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
- "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
- "phyclk_dptx_phy_clk_div2"
- "phyclk_mipi_dphy_4l_m_rxclkesc0"
- "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
- "phyclk_usbhost20_phy_freeclk"
- "phyclk_usbhost20_phy_clk48mohci"
- "phyclk_usbdrd30_udrd30_pipe_pclk"
- "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
Required Properties for Clock Controller:
- compatible: should be one of the following.
1) "samsung,exynos5260-clock-top"
2) "samsung,exynos5260-clock-peri"
3) "samsung,exynos5260-clock-egl"
4) "samsung,exynos5260-clock-kfc"
5) "samsung,exynos5260-clock-g2d"
6) "samsung,exynos5260-clock-mif"
7) "samsung,exynos5260-clock-mfc"
8) "samsung,exynos5260-clock-g3d"
9) "samsung,exynos5260-clock-fsys"
10) "samsung,exynos5260-clock-aud"
11) "samsung,exynos5260-clock-isp"
12) "samsung,exynos5260-clock-gscl"
13) "samsung,exynos5260-clock-disp"
- reg: physical base address of the controller and the length of
memory mapped region.
- #clock-cells: should be 1.
- clocks: list of clock identifiers which are fed as the input to
the given clock controller. Please refer the next section to find
the input clocks for a given controller.
- clock-names: list of names of clocks which are fed as the input
to the given clock controller.
Input clocks for top clock controller:
- fin_pll
- dout_mem_pll
- dout_bus_pll
- dout_media_pll
Input clocks for peri clock controller:
- fin_pll
- ioclk_pcm_extclk
- ioclk_i2s_cdclk
- ioclk_spdif_extclk
- phyclk_hdmi_phy_ref_cko
- dout_aclk_peri_66
- dout_sclk_peri_uart0
- dout_sclk_peri_uart1
- dout_sclk_peri_uart2
- dout_sclk_peri_spi0_b
- dout_sclk_peri_spi1_b
- dout_sclk_peri_spi2_b
- dout_aclk_peri_aud
- dout_sclk_peri_spi0_b
Input clocks for egl clock controller:
- fin_pll
- dout_bus_pll
Input clocks for kfc clock controller:
- fin_pll
- dout_media_pll
Input clocks for g2d clock controller:
- fin_pll
- dout_aclk_g2d_333
Input clocks for mif clock controller:
- fin_pll
Input clocks for mfc clock controller:
- fin_pll
- dout_aclk_mfc_333
Input clocks for g3d clock controller:
- fin_pll
Input clocks for fsys clock controller:
- fin_pll
- phyclk_usbhost20_phy_phyclock
- phyclk_usbhost20_phy_freeclk
- phyclk_usbhost20_phy_clk48mohci
- phyclk_usbdrd30_udrd30_pipe_pclk
- phyclk_usbdrd30_udrd30_phyclock
- dout_aclk_fsys_200
Input clocks for aud clock controller:
- fin_pll
- fout_aud_pll
- ioclk_i2s_cdclk
- ioclk_pcm_extclk
Input clocks for isp clock controller:
- fin_pll
- dout_aclk_isp1_266
- dout_aclk_isp1_400
- mout_aclk_isp1_266
Input clocks for gscl clock controller:
- fin_pll
- dout_aclk_gscl_400
- dout_aclk_gscl_333
Input clocks for disp clock controller:
- fin_pll
- phyclk_dptx_phy_ch3_txd_clk
- phyclk_dptx_phy_ch2_txd_clk
- phyclk_dptx_phy_ch1_txd_clk
- phyclk_dptx_phy_ch0_txd_clk
- phyclk_hdmi_phy_tmds_clko
- phyclk_hdmi_phy_ref_clko
- phyclk_hdmi_phy_pixel_clko
- phyclk_hdmi_link_o_tmds_clkhi
- phyclk_mipi_dphy_4l_m_txbyte_clkhs
- phyclk_dptx_phy_o_ref_clk_24m
- phyclk_dptx_phy_clk_div2
- phyclk_mipi_dphy_4l_m_rxclkesc0
- phyclk_hdmi_phy_ref_cko
- ioclk_spdif_extclk
- dout_aclk_peri_aud
- dout_aclk_disp_222
- dout_sclk_disp_pixel
- dout_aclk_disp_333
Example 1: An example of a clock controller node is listed below.
clock_mfc: clock-controller@11090000 {
compatible = "samsung,exynos5260-clock-mfc";
clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>;
clock-names = "fin_pll", "dout_aclk_mfc_333";
reg = <0x11090000 0x10000>;
#clock-cells = <1>;
};
Example 2: UART controller node that consumes the clock generated by the
peri clock controller. Refer to the standard clock bindings for
information about 'clocks' and 'clock-names' property.
serial@12c00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <0 146 0>;
clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
};

50
Documentation/devicetree/bindings/clock/exynos5410-clock.txt
View File

@ -1,50 +0,0 @@
* Samsung Exynos5410 Clock Controller
The Exynos5410 clock controller generates and supplies clock to various
controllers within the Exynos5410 SoC.
Required Properties:
- compatible: should be "samsung,exynos5410-clock"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
- clocks: should contain an entry specifying the root clock from external
oscillator supplied through XXTI or XusbXTI pin. This clock should be
defined using standard clock bindings with "fin_pll" clock-output-name.
That clock is being passed internally to the 9 PLLs.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5410.h header and can be used in device
tree sources.
Example 1: An example of a clock controller node is listed below.
fin_pll: xxti {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "fin_pll";
#clock-cells = <0>;
};
clock: clock-controller@10010000 {
compatible = "samsung,exynos5410-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
clocks = <&fin_pll>;
};
Example 2: UART controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
serial@12c20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <0 51 0>;
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
};

507
Documentation/devicetree/bindings/clock/exynos5433-clock.txt
View File

@ -1,507 +0,0 @@
* Samsung Exynos5433 CMU (Clock Management Units)
The Exynos5433 clock controller generates and supplies clock to various
controllers within the Exynos5433 SoC.
Required Properties:
- compatible: should be one of the following.
- "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
domains and bus clocks.
- "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
which generates clocks for LLI (Low Latency Interface) IP.
- "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
which generates clocks for DRAM Memory Controller domain.
- "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
- "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
- "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
- "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
which generates clocks for G2D/MDMA IPs.
- "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
which generates clocks for Cortex-A5/BUS/AUDIO clocks.
- "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
which generates global data buses clock and global peripheral buses clock.
- "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
which generates clocks for 3D Graphics Engine IP.
- "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL
which generates clocks for GSCALER IPs.
- "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
which generates clocks for Cortex-A53 Quad-core processor.
- "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
L2 cache controller.
- "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
- "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC
which generates clocks for MFC(Multi-Format Codec) IP.
- "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
- "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
- "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
IPs.
- "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
- "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM
which generates clocks for SSS (Security SubSystem) and SlimSSS IPs.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
- clocks: list of the clock controller input clock identifiers,
from common clock bindings. Please refer the next section
to find the input clocks for a given controller.
- clock-names: list of the clock controller input clock names,
as described in clock-bindings.txt.
Input clocks for top clock controller:
- oscclk
- sclk_mphy_pll
- sclk_mfc_pll
- sclk_bus_pll
Input clocks for cpif clock controller:
- oscclk
Input clocks for mif clock controller:
- oscclk
- sclk_mphy_pll
Input clocks for fsys clock controller:
- oscclk
- sclk_ufs_mphy
- aclk_fsys_200
- sclk_pcie_100_fsys
- sclk_ufsunipro_fsys
- sclk_mmc2_fsys
- sclk_mmc1_fsys
- sclk_mmc0_fsys
- sclk_usbhost30_fsys
- sclk_usbdrd30_fsys
Input clocks for g2d clock controller:
- oscclk
- aclk_g2d_266
- aclk_g2d_400
Input clocks for disp clock controller:
- oscclk
- sclk_dsim1_disp
- sclk_dsim0_disp
- sclk_dsd_disp
- sclk_decon_tv_eclk_disp
- sclk_decon_vclk_disp
- sclk_decon_eclk_disp
- sclk_decon_tv_vclk_disp
- aclk_disp_333
Input clocks for audio clock controller:
- oscclk
- fout_aud_pll
Input clocks for bus0 clock controller:
- aclk_bus0_400
Input clocks for bus1 clock controller:
- aclk_bus1_400
Input clocks for bus2 clock controller:
- oscclk
- aclk_bus2_400
Input clocks for g3d clock controller:
- oscclk
- aclk_g3d_400
Input clocks for gscl clock controller:
- oscclk
- aclk_gscl_111
- aclk_gscl_333
Input clocks for apollo clock controller:
- oscclk
- sclk_bus_pll_apollo
Input clocks for atlas clock controller:
- oscclk
- sclk_bus_pll_atlas
Input clocks for mscl clock controller:
- oscclk
- sclk_jpeg_mscl
- aclk_mscl_400
Input clocks for mfc clock controller:
- oscclk
- aclk_mfc_400
Input clocks for hevc clock controller:
- oscclk
- aclk_hevc_400
Input clocks for isp clock controller:
- oscclk
- aclk_isp_dis_400
- aclk_isp_400
Input clocks for cam0 clock controller:
- oscclk
- aclk_cam0_333
- aclk_cam0_400
- aclk_cam0_552
Input clocks for cam1 clock controller:
- oscclk
- sclk_isp_uart_cam1
- sclk_isp_spi1_cam1
- sclk_isp_spi0_cam1
- aclk_cam1_333
- aclk_cam1_400
- aclk_cam1_552
Input clocks for imem clock controller:
- oscclk
- aclk_imem_sssx_266
- aclk_imem_266
- aclk_imem_200
Optional properties:
- power-domains: a phandle to respective power domain node as described by
generic PM domain bindings (see power/power_domain.txt for more
information).
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5433.h header and can be used in device
tree sources.
Example 1: Examples of 'oscclk' source clock node are listed below.
xxti: xxti {
compatible = "fixed-clock";
clock-output-names = "oscclk";
#clock-cells = <0>;
};
Example 2: Examples of clock controller nodes are listed below.
cmu_top: clock-controller@10030000 {
compatible = "samsung,exynos5433-cmu-top";
reg = <0x10030000 0x0c04>;
#clock-cells = <1>;
clock-names = "oscclk",
"sclk_mphy_pll",
"sclk_mfc_pll",
"sclk_bus_pll";
clocks = <&xxti>,
<&cmu_cpif CLK_SCLK_MPHY_PLL>,
<&cmu_mif CLK_SCLK_MFC_PLL>,
<&cmu_mif CLK_SCLK_BUS_PLL>;
};
cmu_cpif: clock-controller@10fc0000 {
compatible = "samsung,exynos5433-cmu-cpif";
reg = <0x10fc0000 0x0c04>;
#clock-cells = <1>;
clock-names = "oscclk";
clocks = <&xxti>;
};
cmu_mif: clock-controller@105b0000 {
compatible = "samsung,exynos5433-cmu-mif";
reg = <0x105b0000 0x100c>;
#clock-cells = <1>;
clock-names = "oscclk",
"sclk_mphy_pll";
clocks = <&xxti>,
<&cmu_cpif CLK_SCLK_MPHY_PLL>;
};
cmu_peric: clock-controller@14c80000 {
compatible = "samsung,exynos5433-cmu-peric";
reg = <0x14c80000 0x0b08>;
#clock-cells = <1>;
};
cmu_peris: clock-controller@10040000 {
compatible = "samsung,exynos5433-cmu-peris";
reg = <0x10040000 0x0b20>;
#clock-cells = <1>;
};
cmu_fsys: clock-controller@156e0000 {
compatible = "samsung,exynos5433-cmu-fsys";
reg = <0x156e0000 0x0b04>;
#clock-cells = <1>;
clock-names = "oscclk",
"sclk_ufs_mphy",
"aclk_fsys_200",
"sclk_pcie_100_fsys",
"sclk_ufsunipro_fsys",
"sclk_mmc2_fsys",
"sclk_mmc1_fsys",
"sclk_mmc0_fsys",
"sclk_usbhost30_fsys",
"sclk_usbdrd30_fsys";
clocks = <&xxti>,
<&cmu_cpif CLK_SCLK_UFS_MPHY>,
<&cmu_top CLK_ACLK_FSYS_200>,
<&cmu_top CLK_SCLK_PCIE_100_FSYS>,
<&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
<&cmu_top CLK_SCLK_MMC2_FSYS>,
<&cmu_top CLK_SCLK_MMC1_FSYS>,
<&cmu_top CLK_SCLK_MMC0_FSYS>,
<&cmu_top CLK_SCLK_USBHOST30_FSYS>,
<&cmu_top CLK_SCLK_USBDRD30_FSYS>;
};
cmu_g2d: clock-controller@12460000 {
compatible = "samsung,exynos5433-cmu-g2d";
reg = <0x12460000 0x0b08>;
#clock-cells = <1>;
clock-names = "oscclk",
"aclk_g2d_266",
"aclk_g2d_400";
clocks = <&xxti>,
<&cmu_top CLK_ACLK_G2D_266>,
<&cmu_top CLK_ACLK_G2D_400>;
power-domains = <&pd_g2d>;
};
cmu_disp: clock-controller@13b90000 {
compatible = "samsung,exynos5433-cmu-disp";
reg = <0x13b90000 0x0c04>;
#clock-cells = <1>;
clock-names = "oscclk",
"sclk_dsim1_disp",
"sclk_dsim0_disp",
"sclk_dsd_disp",
"sclk_decon_tv_eclk_disp",
"sclk_decon_vclk_disp",
"sclk_decon_eclk_disp",
"sclk_decon_tv_vclk_disp",
"aclk_disp_333";
clocks = <&xxti>,
<&cmu_mif CLK_SCLK_DSIM1_DISP>,
<&cmu_mif CLK_SCLK_DSIM0_DISP>,
<&cmu_mif CLK_SCLK_DSD_DISP>,
<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
<&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
<&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
<&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
<&cmu_mif CLK_ACLK_DISP_333>;
power-domains = <&pd_disp>;
};
cmu_aud: clock-controller@114c0000 {
compatible = "samsung,exynos5433-cmu-aud";
reg = <0x114c0000 0x0b04>;
#clock-cells = <1>;
clock-names = "oscclk", "fout_aud_pll";
clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
power-domains = <&pd_aud>;
};
cmu_bus0: clock-controller@13600000 {
compatible = "samsung,exynos5433-cmu-bus0";
reg = <0x13600000 0x0b04>;
#clock-cells = <1>;
clock-names = "aclk_bus0_400";
clocks = <&cmu_top CLK_ACLK_BUS0_400>;
};
cmu_bus1: clock-controller@14800000 {
compatible = "samsung,exynos5433-cmu-bus1";
reg = <0x14800000 0x0b04>;
#clock-cells = <1>;
clock-names = "aclk_bus1_400";
clocks = <&cmu_top CLK_ACLK_BUS1_400>;
};
cmu_bus2: clock-controller@13400000 {
compatible = "samsung,exynos5433-cmu-bus2";
reg = <0x13400000 0x0b04>;
#clock-cells = <1>;
clock-names = "oscclk", "aclk_bus2_400";
clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
};
cmu_g3d: clock-controller@14aa0000 {
compatible = "samsung,exynos5433-cmu-g3d";
reg = <0x14aa0000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk", "aclk_g3d_400";
clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
power-domains = <&pd_g3d>;
};
cmu_gscl: clock-controller@13cf0000 {
compatible = "samsung,exynos5433-cmu-gscl";
reg = <0x13cf0000 0x0b10>;
#clock-cells = <1>;
clock-names = "oscclk",
"aclk_gscl_111",
"aclk_gscl_333";
clocks = <&xxti>,
<&cmu_top CLK_ACLK_GSCL_111>,
<&cmu_top CLK_ACLK_GSCL_333>;
power-domains = <&pd_gscl>;
};
cmu_apollo: clock-controller@11900000 {
compatible = "samsung,exynos5433-cmu-apollo";
reg = <0x11900000 0x1088>;
#clock-cells = <1>;
clock-names = "oscclk", "sclk_bus_pll_apollo";
clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
};
cmu_atlas: clock-controller@11800000 {
compatible = "samsung,exynos5433-cmu-atlas";
reg = <0x11800000 0x1088>;
#clock-cells = <1>;
clock-names = "oscclk", "sclk_bus_pll_atlas";
clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
};
cmu_mscl: clock-controller@105d0000 {
compatible = "samsung,exynos5433-cmu-mscl";
reg = <0x105d0000 0x0b10>;
#clock-cells = <1>;
clock-names = "oscclk",
"sclk_jpeg_mscl",
"aclk_mscl_400";
clocks = <&xxti>,
<&cmu_top CLK_SCLK_JPEG_MSCL>,
<&cmu_top CLK_ACLK_MSCL_400>;
power-domains = <&pd_mscl>;
};
cmu_mfc: clock-controller@15280000 {
compatible = "samsung,exynos5433-cmu-mfc";
reg = <0x15280000 0x0b08>;
#clock-cells = <1>;
clock-names = "oscclk", "aclk_mfc_400";
clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
power-domains = <&pd_mfc>;
};
cmu_hevc: clock-controller@14f80000 {
compatible = "samsung,exynos5433-cmu-hevc";
reg = <0x14f80000 0x0b08>;
#clock-cells = <1>;
clock-names = "oscclk", "aclk_hevc_400";
clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
power-domains = <&pd_hevc>;
};
cmu_isp: clock-controller@146d0000 {
compatible = "samsung,exynos5433-cmu-isp";
reg = <0x146d0000 0x0b0c>;
#clock-cells = <1>;
clock-names = "oscclk",
"aclk_isp_dis_400",
"aclk_isp_400";
clocks = <&xxti>,
<&cmu_top CLK_ACLK_ISP_DIS_400>,
<&cmu_top CLK_ACLK_ISP_400>;
power-domains = <&pd_isp>;
};
cmu_cam0: clock-controller@120d0000 {
compatible = "samsung,exynos5433-cmu-cam0";
reg = <0x120d0000 0x0b0c>;
#clock-cells = <1>;
clock-names = "oscclk",
"aclk_cam0_333",
"aclk_cam0_400",
"aclk_cam0_552";
clocks = <&xxti>,
<&cmu_top CLK_ACLK_CAM0_333>,
<&cmu_top CLK_ACLK_CAM0_400>,
<&cmu_top CLK_ACLK_CAM0_552>;
power-domains = <&pd_cam0>;
};
cmu_cam1: clock-controller@145d0000 {
compatible = "samsung,exynos5433-cmu-cam1";
reg = <0x145d0000 0x0b08>;
#clock-cells = <1>;
clock-names = "oscclk",
"sclk_isp_uart_cam1",
"sclk_isp_spi1_cam1",
"sclk_isp_spi0_cam1",
"aclk_cam1_333",
"aclk_cam1_400",
"aclk_cam1_552";
clocks = <&xxti>,
<&cmu_top CLK_SCLK_ISP_UART_CAM1>,
<&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
<&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
<&cmu_top CLK_ACLK_CAM1_333>,
<&cmu_top CLK_ACLK_CAM1_400>,
<&cmu_top CLK_ACLK_CAM1_552>;
power-domains = <&pd_cam1>;
};
cmu_imem: clock-controller@11060000 {
compatible = "samsung,exynos5433-cmu-imem";
reg = <0x11060000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk",
"aclk_imem_sssx_266",
"aclk_imem_266",
"aclk_imem_200";
clocks = <&xxti>,
<&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
<&cmu_top CLK_DIV_ACLK_IMEM_266>,
<&cmu_top CLK_DIV_ACLK_IMEM_200>;
};
Example 3: UART controller node that consumes the clock generated by the clock
controller.
serial_0: serial@14c10000 {
compatible = "samsung,exynos5433-uart";
reg = <0x14C10000 0x100>;
interrupts = <0 421 0>;
clocks = <&cmu_peric CLK_PCLK_UART0>,
<&cmu_peric CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
pinctrl-0 = <&uart0_bus>;
};

108
Documentation/devicetree/bindings/clock/exynos7-clock.txt
View File

@ -1,108 +0,0 @@
* Samsung Exynos7 Clock Controller
Exynos7 clock controller has various blocks which are instantiated
independently from the device-tree. These clock controllers
generate and supply clocks to various hardware blocks within
the SoC.
Each clock is assigned an identifier and client nodes can use
this identifier to specify the clock which they consume. All
available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos7-clk.h header and can be used in
device tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It
is expected that they are defined using standard clock bindings
with following clock-output-names:
- "fin_pll" - PLL input clock from XXTI
Required Properties for Clock Controller:
- compatible: clock controllers will use one of the following
compatible strings to indicate the clock controller
functionality.
- "samsung,exynos7-clock-topc"
- "samsung,exynos7-clock-top0"
- "samsung,exynos7-clock-top1"
- "samsung,exynos7-clock-ccore"
- "samsung,exynos7-clock-peric0"
- "samsung,exynos7-clock-peric1"
- "samsung,exynos7-clock-peris"
- "samsung,exynos7-clock-fsys0"
- "samsung,exynos7-clock-fsys1"
- "samsung,exynos7-clock-mscl"
- "samsung,exynos7-clock-aud"
- reg: physical base address of the controller and the length of
memory mapped region.
- #clock-cells: should be 1.
- clocks: list of clock identifiers which are fed as the input to
the given clock controller. Please refer the next section to
find the input clocks for a given controller.
- clock-names: list of names of clocks which are fed as the input
to the given clock controller.
Input clocks for top0 clock controller:
- fin_pll
- dout_sclk_bus0_pll
- dout_sclk_bus1_pll
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
- dout_sclk_aud_pll
Input clocks for top1 clock controller:
- fin_pll
- dout_sclk_bus0_pll
- dout_sclk_bus1_pll
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
Input clocks for ccore clock controller:
- fin_pll
- dout_aclk_ccore_133
Input clocks for peric0 clock controller:
- fin_pll
- dout_aclk_peric0_66
- sclk_uart0
Input clocks for peric1 clock controller:
- fin_pll
- dout_aclk_peric1_66
- sclk_uart1
- sclk_uart2
- sclk_uart3
- sclk_spi0
- sclk_spi1
- sclk_spi2
- sclk_spi3
- sclk_spi4
- sclk_i2s1
- sclk_pcm1
- sclk_spdif
Input clocks for peris clock controller:
- fin_pll
- dout_aclk_peris_66
Input clocks for fsys0 clock controller:
- fin_pll
- dout_aclk_fsys0_200
- dout_sclk_mmc2
Input clocks for fsys1 clock controller:
- fin_pll
- dout_aclk_fsys1_200
- dout_sclk_mmc0
- dout_sclk_mmc1
Input clocks for aud clock controller:
- fin_pll
- fout_aud_pll

9
Documentation/devicetree/bindings/clock/imx5-clock.yaml
View File

@ -55,11 +55,4 @@ examples:
<0 72 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
};
can@53fc8000 {
compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
reg = <0x53fc8000 0x4000>;
interrupts = <82>;
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
clock-names = "ipg", "per";
};
...

60
Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml Normal file
View File

@ -0,0 +1,60 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip LAN966X Generic Clock Controller
maintainers:
- Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
description: |
The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
ddr_clk and sys_clk. This clock controller generates and supplies
clock to various peripherals within the SoC.
properties:
compatible:
const: microchip,lan966x-gck
reg:
minItems: 1
items:
- description: Generic clock registers
- description: Optional gate clock registers
clocks:
items:
- description: CPU clock source
- description: DDR clock source
- description: System clock source
clock-names:
items:
- const: cpu
- const: ddr
- const: sys
'#clock-cells':
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
- |
clks: clock-controller@e00c00a8 {
compatible = "microchip,lan966x-gck";
#clock-cells = <1>;
clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
clock-names = "cpu", "ddr", "sys";
reg = <0xe00c00a8 0x38>;
};
...

97
Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml Normal file
View File

@ -0,0 +1,97 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8976
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8976.
See also:
- dt-bindings/clock/qcom,gcc-msm8976.h
properties:
compatible:
enum:
- qcom,gcc-msm8976
- qcom,gcc-msm8976-v1.1
clocks:
items:
- description: XO source
- description: Always-on XO source
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY1
- description: Byte clock from DSI PHY1
clock-names:
items:
- const: xo
- const: xo_a
- const: dsi0pll
- const: dsi0pllbyte
- const: dsi1pll
- const: dsi1pllbyte
vdd_gfx-supply:
description:
Phandle to voltage regulator providing power to the GX domain.
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- vdd_gfx-supply
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
clock-controller@1800000 {
compatible = "qcom,gcc-msm8976";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x1800000 0x80000>;
clocks = <&xo_board>,
<&xo_board>,
<&dsi0_phy 1>,
<&dsi0_phy 0>,
<&dsi1_phy 1>,
<&dsi1_phy 0>;
clock-names = "xo",
"xo_a",
"dsi0pll",
"dsi0pllbyte",
"dsi1pll",
"dsi1pllbyte";
vdd_gfx-supply = <&pm8004_s5>;
};
...

2
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
View File

@ -22,10 +22,12 @@ properties:
- qcom,sc8180x-rpmh-clk
- qcom,sdm845-rpmh-clk
- qcom,sdx55-rpmh-clk
- qcom,sdx65-rpmh-clk
- qcom,sm6350-rpmh-clk
- qcom,sm8150-rpmh-clk
- qcom,sm8250-rpmh-clk
- qcom,sm8350-rpmh-clk
- qcom,sm8450-rpmh-clk
clocks:
maxItems: 1

1
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
View File

@ -48,6 +48,7 @@ properties:
- renesas,r8a77990-cpg-mssr # R-Car E3
- renesas,r8a77995-cpg-mssr # R-Car D3
- renesas,r8a779a0-cpg-mssr # R-Car V3U
- renesas,r8a779f0-cpg-mssr # R-Car S4-8
reg:
maxItems: 1

382
Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml Normal file
View File

@ -0,0 +1,382 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos5260 SoC clock controller
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>
description: |
Expected external clocks, defined in DTS as fixed-rate clocks with a matching
name::
- "fin_pll" - PLL input clock from XXTI
- "xrtcxti" - input clock from XRTCXTI
- "ioclk_pcm_extclk" - pcm external operation clock
- "ioclk_spdif_extclk" - spdif external operation clock
- "ioclk_i2s_cdclk" - i2s0 codec clock
Phy clocks::
There are several clocks which are generated by specific PHYs. These clocks
are fed into the clock controller and then routed to the hardware blocks.
These clocks are defined as fixed clocks in the driver with following names::
- "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
- "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
- "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
- "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
- "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
- "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
- "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
- "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
- "phyclk_dptx_phy_clk_div2"
- "phyclk_mipi_dphy_4l_m_rxclkesc0"
- "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
- "phyclk_usbhost20_phy_freeclk"
- "phyclk_usbhost20_phy_clk48mohci"
- "phyclk_usbdrd30_udrd30_pipe_pclk"
- "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
All available clocks are defined as preprocessor macros in
include/dt-bindings/clock/exynos5260-clk.h header.
properties:
compatible:
enum:
- samsung,exynos5260-clock-top
- samsung,exynos5260-clock-peri
- samsung,exynos5260-clock-egl
- samsung,exynos5260-clock-kfc
- samsung,exynos5260-clock-g2d
- samsung,exynos5260-clock-mif
- samsung,exynos5260-clock-mfc
- samsung,exynos5260-clock-g3d
- samsung,exynos5260-clock-fsys
- samsung,exynos5260-clock-aud
- samsung,exynos5260-clock-isp
- samsung,exynos5260-clock-gscl
- samsung,exynos5260-clock-disp
clocks:
minItems: 1
maxItems: 19
clock-names:
minItems: 1
maxItems: 19
"#clock-cells":
const: 1
reg:
maxItems: 1
required:
- compatible
- "#clock-cells"
- reg
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos5260-clock-top
then:
properties:
clocks:
minItems: 4
maxItems: 4
clock-names:
items:
- const: fin_pll
- const: dout_mem_pll
- const: dout_bus_pll
- const: dout_media_pll
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5260-clock-peri
then:
properties:
clocks:
minItems: 13
maxItems: 13
clock-names:
items:
- const: fin_pll
- const: ioclk_pcm_extclk
- const: ioclk_i2s_cdclk
- const: ioclk_spdif_extclk
- const: phyclk_hdmi_phy_ref_cko
- const: dout_aclk_peri_66
- const: dout_sclk_peri_uart0
- const: dout_sclk_peri_uart1
- const: dout_sclk_peri_uart2
- const: dout_sclk_peri_spi0_b
- const: dout_sclk_peri_spi1_b
- const: dout_sclk_peri_spi2_b
- const: dout_aclk_peri_aud
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5260-clock-egl
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: fin_pll
- const: dout_bus_pll
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5260-clock-kfc
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: fin_pll
- const: dout_media_pll
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5260-clock-g2d
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: fin_pll
- const: dout_aclk_g2d_333
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5260-clock-mif
then:
properties:
clocks:
minItems: 1
maxItems: 1
clock-names:
items:
- const: fin_pll
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5260-clock-mfc
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: fin_pll
- const: dout_aclk_mfc_333
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5260-clock-g3d
then:
properties:
clocks:
minItems: 1
maxItems: 1
clock-names:
items:
- const: fin_pll
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5260-clock-fsys
then:
properties:
clocks:
minItems: 7
maxItems: 7
clock-names:
items:
- const: fin_pll
- const: phyclk_usbhost20_phy_phyclock
- const: phyclk_usbhost20_phy_freeclk
- const: phyclk_usbhost20_phy_clk48mohci
- const: phyclk_usbdrd30_udrd30_pipe_pclk
- const: phyclk_usbdrd30_udrd30_phyclock
- const: dout_aclk_fsys_200
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5260-clock-aud
then:
properties:
clocks:
minItems: 4
maxItems: 4
clock-names:
items:
- const: fin_pll
- const: fout_aud_pll
- const: ioclk_i2s_cdclk
- const: ioclk_pcm_extclk
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5260-clock-isp
then:
properties:
clocks:
minItems: 4
maxItems: 4
clock-names:
items:
- const: fin_pll
- const: dout_aclk_isp1_266
- const: dout_aclk_isp1_400
- const: mout_aclk_isp1_266
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5260-clock-gscl
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: fin_pll
- const: dout_aclk_gscl_400
- const: dout_aclk_gscl_333
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5260-clock-disp
then:
properties:
clocks:
minItems: 19
maxItems: 19
clock-names:
items:
- const: fin_pll
- const: phyclk_dptx_phy_ch3_txd_clk
- const: phyclk_dptx_phy_ch2_txd_clk
- const: phyclk_dptx_phy_ch1_txd_clk
- const: phyclk_dptx_phy_ch0_txd_clk
- const: phyclk_hdmi_phy_tmds_clko
- const: phyclk_hdmi_phy_ref_clko
- const: phyclk_hdmi_phy_pixel_clko
- const: phyclk_hdmi_link_o_tmds_clkhi
- const: phyclk_mipi_dphy_4l_m_txbyte_clkhs
- const: phyclk_dptx_phy_o_ref_clk_24m
- const: phyclk_dptx_phy_clk_div2
- const: phyclk_mipi_dphy_4l_m_rxclkesc0
- const: phyclk_hdmi_phy_ref_cko
- const: ioclk_spdif_extclk
- const: dout_aclk_peri_aud
- const: dout_aclk_disp_222
- const: dout_sclk_disp_pixel
- const: dout_aclk_disp_333
required:
- clock-names
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5260-clk.h>
fin_pll: clock {
compatible = "fixed-clock";
clock-output-names = "fin_pll";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
clock-controller@10010000 {
compatible = "samsung,exynos5260-clock-top";
reg = <0x10010000 0x10000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&clock_mif MIF_DOUT_MEM_PLL>,
<&clock_mif MIF_DOUT_BUS_PLL>,
<&clock_mif MIF_DOUT_MEDIA_PLL>;
clock-names = "fin_pll",
"dout_mem_pll",
"dout_bus_pll",
"dout_media_pll";
};

66
Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml Normal file
View File

@ -0,0 +1,66 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos5410 SoC clock controller
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>
description: |
Expected external clocks, defined in DTS as fixed-rate clocks with a matching
name::
- "fin_pll" - PLL input clock from XXTI
All available clocks are defined as preprocessor macros in
include/dt-bindings/clock/exynos5410.h header.
properties:
compatible:
oneOf:
- enum:
- samsung,exynos5410-clock
clocks:
description:
Should contain an entry specifying the root clock from external
oscillator supplied through XXTI or XusbXTI pin. This clock should be
defined using standard clock bindings with "fin_pll" clock-output-name.
That clock is being passed internally to the 9 PLLs.
maxItems: 1
"#clock-cells":
const: 1
reg:
maxItems: 1
required:
- compatible
- "#clock-cells"
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5410.h>
fin_pll: osc-clock {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "fin_pll";
#clock-cells = <0>;
};
clock-controller@10010000 {
compatible = "samsung,exynos5410-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
clocks = <&fin_pll>;
};

524
Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml Normal file
View File

@ -0,0 +1,524 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos5433 SoC clock controller
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>
description: |
Expected external clocks, defined in DTS as fixed-rate clocks with a matching
name::
- "oscclk" - PLL input clock from XXTI
All available clocks are defined as preprocessor macros in
include/dt-bindings/clock/exynos5433.h header.
properties:
compatible:
enum:
# CMU_TOP which generates clocks for
# IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS domains and bus
# clocks
- samsung,exynos5433-cmu-top
# CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP
- samsung,exynos5433-cmu-cpif
# CMU_MIF which generates clocks for DRAM Memory Controller domain
- samsung,exynos5433-cmu-mif
# CMU_PERIC which generates clocks for
# UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs
- samsung,exynos5433-cmu-peric
# CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs
- samsung,exynos5433-cmu-peris
# CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
- samsung,exynos5433-cmu-fsys
- samsung,exynos5433-cmu-g2d
# CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs
- samsung,exynos5433-cmu-disp
- samsung,exynos5433-cmu-aud
- samsung,exynos5433-cmu-bus0
- samsung,exynos5433-cmu-bus1
- samsung,exynos5433-cmu-bus2
- samsung,exynos5433-cmu-g3d
- samsung,exynos5433-cmu-gscl
- samsung,exynos5433-cmu-apollo
# CMU_ATLAS which generates clocks for Cortex-A57 Quad-core processor,
# CoreSight and L2 cache controller
- samsung,exynos5433-cmu-atlas
# CMU_MSCL which generates clocks for M2M (Memory to Memory) scaler and
# JPEG IPs
- samsung,exynos5433-cmu-mscl
- samsung,exynos5433-cmu-mfc
- samsung,exynos5433-cmu-hevc
# CMU_ISP which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs
- samsung,exynos5433-cmu-isp
# CMU_CAM0 which generates clocks for
# MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs
- samsung,exynos5433-cmu-cam0
# CMU_CAM1 which generates clocks for
# Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs
- samsung,exynos5433-cmu-cam1
# CMU_IMEM which generates clocks for SSS (Security SubSystem) and
# SlimSSS IPs
- samsung,exynos5433-cmu-imem
clocks:
minItems: 1
maxItems: 10
clock-names:
minItems: 1
maxItems: 10
"#clock-cells":
const: 1
power-domains:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- "#clock-cells"
- reg
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-top
then:
properties:
clocks:
minItems: 4
maxItems: 4
clock-names:
items:
- const: oscclk
- const: sclk_mphy_pll
- const: sclk_mfc_pll
- const: sclk_bus_pll
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-cpif
then:
properties:
clocks:
minItems: 1
maxItems: 1
clock-names:
items:
- const: oscclk
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-mif
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: oscclk
- const: sclk_mphy_pll
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-fsys
then:
properties:
clocks:
minItems: 10
maxItems: 10
clock-names:
items:
- const: oscclk
- const: sclk_ufs_mphy
- const: aclk_fsys_200
- const: sclk_pcie_100_fsys
- const: sclk_ufsunipro_fsys
- const: sclk_mmc2_fsys
- const: sclk_mmc1_fsys
- const: sclk_mmc0_fsys
- const: sclk_usbhost30_fsys
- const: sclk_usbdrd30_fsys
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-g2d
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: oscclk
- const: aclk_g2d_266
- const: aclk_g2d_400
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-disp
then:
properties:
clocks:
minItems: 9
maxItems: 9
clock-names:
items:
- const: oscclk
- const: sclk_dsim1_disp
- const: sclk_dsim0_disp
- const: sclk_dsd_disp
- const: sclk_decon_tv_eclk_disp
- const: sclk_decon_vclk_disp
- const: sclk_decon_eclk_disp
- const: sclk_decon_tv_vclk_disp
- const: aclk_disp_333
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-aud
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: oscclk
- const: fout_aud_pll
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-bus0
then:
properties:
clocks:
minItems: 1
maxItems: 1
clock-names:
items:
- const: aclk_bus0_400
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-bus1
then:
properties:
clocks:
minItems: 1
maxItems: 1
clock-names:
items:
- const: aclk_bus1_400
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-bus2
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: oscclk
- const: aclk_bus2_400
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-g3d
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: oscclk
- const: aclk_g3d_400
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-gscl
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: oscclk
- const: aclk_gscl_111
- const: aclk_gscl_333
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-apollo
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: oscclk
- const: sclk_bus_pll_apollo
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-atlas
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: oscclk
- const: sclk_bus_pll_atlas
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-mscl
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: oscclk
- const: sclk_jpeg_mscl
- const: aclk_mscl_400
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-mfc
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: oscclk
- const: aclk_mfc_400
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-hevc
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: oscclk
- const: aclk_hevc_400
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-isp
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: oscclk
- const: aclk_isp_dis_400
- const: aclk_isp_400
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-cam0
then:
properties:
clocks:
minItems: 4
maxItems: 4
clock-names:
items:
- const: oscclk
- const: aclk_cam0_333
- const: aclk_cam0_400
- const: aclk_cam0_552
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-cam1
then:
properties:
clocks:
minItems: 7
maxItems: 7
clock-names:
items:
- const: oscclk
- const: sclk_isp_uart_cam1
- const: sclk_isp_spi1_cam1
- const: sclk_isp_spi0_cam1
- const: aclk_cam1_333
- const: aclk_cam1_400
- const: aclk_cam1_552
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-cmu-imem
then:
properties:
clocks:
minItems: 4
maxItems: 4
clock-names:
items:
- const: oscclk
- const: aclk_imem_sssx_266
- const: aclk_imem_266
- const: aclk_imem_200
required:
- clock-names
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5433.h>
xxti: clock {
compatible = "fixed-clock";
clock-output-names = "oscclk";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
clock-controller@10030000 {
compatible = "samsung,exynos5433-cmu-top";
reg = <0x10030000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk",
"sclk_mphy_pll",
"sclk_mfc_pll",
"sclk_bus_pll";
clocks = <&xxti>,
<&cmu_cpif CLK_SCLK_MPHY_PLL>,
<&cmu_mif CLK_SCLK_MFC_PLL>,
<&cmu_mif CLK_SCLK_BUS_PLL>;
};

272
Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml Normal file
View File

@ -0,0 +1,272 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos7 SoC clock controller
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>
description: |
Expected external clocks, defined in DTS as fixed-rate clocks with a matching
name::
- "fin_pll" - PLL input clock from XXTI
All available clocks are defined as preprocessor macros in
include/dt-bindings/clock/exynos7-clk.h header.
properties:
compatible:
enum:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
- samsung,exynos7-clock-top1
- samsung,exynos7-clock-ccore
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
- samsung,exynos7-clock-peris
- samsung,exynos7-clock-fsys0
- samsung,exynos7-clock-fsys1
- samsung,exynos7-clock-mscl
- samsung,exynos7-clock-aud
clocks:
minItems: 1
maxItems: 13
clock-names:
minItems: 1
maxItems: 13
"#clock-cells":
const: 1
reg:
maxItems: 1
required:
- compatible
- "#clock-cells"
- reg
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos7-clock-top0
then:
properties:
clocks:
minItems: 6
maxItems: 6
clock-names:
items:
- const: fin_pll
- const: dout_sclk_bus0_pll
- const: dout_sclk_bus1_pll
- const: dout_sclk_cc_pll
- const: dout_sclk_mfc_pll
- const: dout_sclk_aud_pll
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos7-clock-top1
then:
properties:
clocks:
minItems: 5
maxItems: 5
clock-names:
items:
- const: fin_pll
- const: dout_sclk_bus0_pll
- const: dout_sclk_bus1_pll
- const: dout_sclk_cc_pll
- const: dout_sclk_mfc_pll
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos7-clock-ccore
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: fin_pll
- const: dout_aclk_ccore_133
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos7-clock-peric0
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: fin_pll
- const: dout_aclk_peric0_66
- const: sclk_uart0
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos7-clock-peric1
then:
properties:
clocks:
minItems: 13
maxItems: 13
clock-names:
items:
- const: fin_pll
- const: dout_aclk_peric1_66
- const: sclk_uart1
- const: sclk_uart2
- const: sclk_uart3
- const: sclk_spi0
- const: sclk_spi1
- const: sclk_spi2
- const: sclk_spi3
- const: sclk_spi4
- const: sclk_i2s1
- const: sclk_pcm1
- const: sclk_spdif
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos7-clock-peris
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: fin_pll
- const: dout_aclk_peris_66
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos7-clock-fsys0
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: fin_pll
- const: dout_aclk_fsys0_200
- const: dout_sclk_mmc2
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos7-clock-fsys1
then:
properties:
clocks:
minItems: 7
maxItems: 7
clock-names:
items:
- const: fin_pll
- const: dout_aclk_fsys1_200
- const: dout_sclk_mmc0
- const: dout_sclk_mmc1
- const: dout_sclk_ufsunipro20
- const: dout_sclk_phy_fsys1
- const: dout_sclk_phy_fsys1_26m
required:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
const: samsung,exynos7-clock-aud
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: fin_pll
- const: fout_aud_pll
required:
- clock-names
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos7-clk.h>
fin_pll: clock {
compatible = "fixed-clock";
clock-output-names = "fin_pll";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
clock-controller@105e0000 {
compatible = "samsung,exynos7-clock-top1";
reg = <0x105e0000 0xb000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&clock_topc DOUT_SCLK_BUS0_PLL>,
<&clock_topc DOUT_SCLK_BUS1_PLL>,
<&clock_topc DOUT_SCLK_CC_PLL>,
<&clock_topc DOUT_SCLK_MFC_PLL>;
clock-names = "fin_pll",
"dout_sclk_bus0_pll",
"dout_sclk_bus1_pll",
"dout_sclk_cc_pll",
"dout_sclk_mfc_pll";
};

166
Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml Normal file
View File

@ -0,0 +1,166 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos7885 SoC clock controller
maintainers:
- Dávid Virág <virag.david003@gmail.com>
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>
description: |
Exynos7885 clock controller is comprised of several CMU units, generating
clocks for different domains. Those CMU units are modeled as separate device
tree nodes, and might depend on each other. The root clock in that root tree
is an external clock: OSCCLK (26 MHz). This external clock must be defined
as a fixed-rate clock in dts.
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All clocks available for usage
in clock consumer nodes are defined as preprocessor macros in
'dt-bindings/clock/exynos7885.h' header.
properties:
compatible:
enum:
- samsung,exynos7885-cmu-top
- samsung,exynos7885-cmu-core
- samsung,exynos7885-cmu-peri
clocks:
minItems: 1
maxItems: 10
clock-names:
minItems: 1
maxItems: 10
"#clock-cells":
const: 1
reg:
maxItems: 1
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos7885-cmu-top
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
clock-names:
items:
- const: oscclk
- if:
properties:
compatible:
contains:
const: samsung,exynos7885-cmu-core
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_CORE bus clock (from CMU_TOP)
- description: CCI clock (from CMU_TOP)
- description: G3D clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_core_bus
- const: dout_core_cci
- const: dout_core_g3d
- if:
properties:
compatible:
contains:
const: samsung,exynos7885-cmu-peri
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_PERI bus clock (from CMU_TOP)
- description: SPI0 clock (from CMU_TOP)
- description: SPI1 clock (from CMU_TOP)
- description: UART0 clock (from CMU_TOP)
- description: UART1 clock (from CMU_TOP)
- description: UART2 clock (from CMU_TOP)
- description: USI0 clock (from CMU_TOP)
- description: USI1 clock (from CMU_TOP)
- description: USI2 clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_peri_bus
- const: dout_peri_spi0
- const: dout_peri_spi1
- const: dout_peri_uart0
- const: dout_peri_uart1
- const: dout_peri_uart2
- const: dout_peri_usi0
- const: dout_peri_usi1
- const: dout_peri_usi2
required:
- compatible
- "#clock-cells"
- clocks
- clock-names
- reg
additionalProperties: false
examples:
# Clock controller node for CMU_PERI
- |
#include <dt-bindings/clock/exynos7885.h>
cmu_peri: clock-controller@10010000 {
compatible = "samsung,exynos7885-cmu-peri";
reg = <0x10010000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>,
<&cmu_top CLK_DOUT_PERI_BUS>,
<&cmu_top CLK_DOUT_PERI_SPI0>,
<&cmu_top CLK_DOUT_PERI_SPI1>,
<&cmu_top CLK_DOUT_PERI_UART0>,
<&cmu_top CLK_DOUT_PERI_UART1>,
<&cmu_top CLK_DOUT_PERI_UART2>,
<&cmu_top CLK_DOUT_PERI_USI0>,
<&cmu_top CLK_DOUT_PERI_USI1>,
<&cmu_top CLK_DOUT_PERI_USI2>;
clock-names = "oscclk",
"dout_peri_bus",
"dout_peri_spi0",
"dout_peri_spi1",
"dout_peri_uart0",
"dout_peri_uart1",
"dout_peri_uart2",
"dout_peri_usi0",
"dout_peri_usi1",
"dout_peri_usi2";
};
...

38
Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
View File

@ -32,6 +32,8 @@ properties:
compatible:
enum:
- samsung,exynos850-cmu-top
- samsung,exynos850-cmu-apm
- samsung,exynos850-cmu-cmgp
- samsung,exynos850-cmu-core
- samsung,exynos850-cmu-dpu
- samsung,exynos850-cmu-hsi
@ -68,6 +70,42 @@ allOf:
items:
- const: oscclk
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-apm
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_APM bus clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_apm_bus
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-cmgp
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_CMGP bus clock (from CMU_APM)
clock-names:
items:
- const: oscclk
- const: gout_clkcmu_cmgp_bus
- if:
properties:
compatible:

77
Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
View File

@ -1,77 +0,0 @@
* Samsung S5P6442/S5PC110/S5PV210 Clock Controller
Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
controller, which generates and supplies clock to various controllers
within the SoC.
Required Properties:
- compatible: should be one of following:
- "samsung,s5pv210-clock" : for clock controller of Samsung
S5PC110/S5PV210 SoCs,
- "samsung,s5p6442-clock" : for clock controller of Samsung
S5P6442 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xxti": external crystal oscillator connected to XXTI and XXTO pins of
the SoC,
- "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO
pins of the SoC,
A subset of above clocks available on given board shall be specified in
board device tree, including the system base clock, as selected by XOM[0]
pin of the SoC. Refer to generic fixed rate clock bindings
documentation[1] for more information how to specify these clocks.
[1] Documentation/devicetree/bindings/clock/fixed-clock.yaml
Example: Clock controller node:
clock: clock-controller@7e00f000 {
compatible = "samsung,s5pv210-clock";
reg = <0x7e00f000 0x1000>;
#clock-cells = <1>;
};
Example: Required external clocks:
xxti: clock-xxti {
compatible = "fixed-clock";
clock-output-names = "xxti";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
xusbxti: clock-xusbxti {
compatible = "fixed-clock";
clock-output-names = "xusbxti";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
uart0: serial@e2900000 {
compatible = "samsung,s5pv210-uart";
reg = <0xe2900000 0x400>;
interrupt-parent = <&vic1>;
interrupts = <10>;
clock-names = "uart", "clk_uart_baud0",
"clk_uart_baud1";
clocks = <&clocks UART0>, <&clocks UART0>,
<&clocks SCLK_UART0>;
};

79
Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml Normal file
View File

@ -0,0 +1,79 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>
description: |
Expected external clocks, defined in DTS as fixed-rate clocks with a matching
name::
- "xxti" - external crystal oscillator connected to XXTI and XXTO pins of
the SoC,
- "xusbxti" - external crystal oscillator connected to XUSBXTI and XUSBXTO
pins of the SoC,
All available clocks are defined as preprocessor macros in
include/dt-bindings/clock/s5pv210.h header.
properties:
compatible:
enum:
- samsung,s5pv210-clock
- samsung,s5p6442-clock
clocks:
items:
- description: xxti clock
- description: xusbxti clock
clock-names:
items:
- const: xxti
- const: xusbxti
"#clock-cells":
const: 1
reg:
maxItems: 1
required:
- compatible
- "#clock-cells"
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/s5pv210.h>
xxti: clock-0 {
compatible = "fixed-clock";
clock-frequency = <0>;
clock-output-names = "xxti";
#clock-cells = <0>;
};
xusbxti: clock-1 {
compatible = "fixed-clock";
clock-frequency = <0>;
clock-output-names = "xusbxti";
#clock-cells = <0>;
};
clock-controller@e0100000 {
compatible = "samsung,s5pv210-clock";
reg = <0xe0100000 0x10000>;
clock-names = "xxti", "xusbxti";
clocks = <&xxti>, <&xusbxti>;
#clock-cells = <1>;
};

57
Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml Normal file
View File

@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pipllct.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Toshiba Visconti5 TMPV770X PLL Controller Device Tree Bindings
maintainers:
- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
description:
Toshia Visconti5 PLL controller which supports the PLLs on TMPV770X.
properties:
compatible:
const: toshiba,tmpv7708-pipllct
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
description: External reference clock (OSC2)
maxItems: 1
required:
- compatible
- reg
- "#clock-cells"
- clocks
additionalProperties: false
examples:
- |
osc2_clk: osc2-clk {
compatible = "fixed-clock";
clock-frequency = <20000000>;
#clock-cells = <0>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
pipllct: clock-controller@24220000 {
compatible = "toshiba,tmpv7708-pipllct";
reg = <0 0x24220000 0 0x820>;
#clock-cells = <1>;
clocks = <&osc2_clk>;
};
};
...

52
Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml Normal file
View File

@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pismu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Toshiba Visconti5 TMPV770x SMU controller Device Tree Bindings
maintainers:
- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
description:
Toshia Visconti5 SMU (System Management Unit) which supports the clock
and resets on TMPV770x.
properties:
compatible:
items:
- const: toshiba,tmpv7708-pismu
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- "#clock-cells"
- "#reset-cells"
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pismu: syscon@24200000 {
compatible = "toshiba,tmpv7708-pismu", "syscon";
reg = <0 0x24200000 0 0x2140>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};
...

19
Documentation/devicetree/bindings/crypto/qcom,prng.txt
View File

@ -1,19 +0,0 @@
Qualcomm MSM pseudo random number generator.
Required properties:
- compatible : should be "qcom,prng" for 8916 etc
: should be "qcom,prng-ee" for 8996 and later using EE
(Execution Environment) slice of prng
- reg : specifies base physical address and size of the registers map
- clocks : phandle to clock-controller plus clock-specifier pair
- clock-names : "core" clocks all registers, FIFO and circuits in PRNG IP block
Example:
rng@f9bff000 {
compatible = "qcom,prng";
reg = <0xf9bff000 0x200>;
clocks = <&clock GCC_PRNG_AHB_CLK>;
clock-names = "core";
};

43
Documentation/devicetree/bindings/crypto/qcom,prng.yaml Normal file
View File

@ -0,0 +1,43 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/qcom,prng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Pseudo Random Number Generator
maintainers:
- Vinod Koul <vkoul@kernel.org>
properties:
compatible:
enum:
- qcom,prng # 8916 etc.
- qcom,prng-ee # 8996 and later using EE
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: core
required:
- compatible
- reg
- clocks
- clock-names
additionalProperties: false
examples:
- |
rng@f9bff000 {
compatible = "qcom,prng";
reg = <0xf9bff000 0x200>;
clocks = <&clk 125>;
clock-names = "core";
};

5
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
View File

@ -31,13 +31,11 @@ properties:
clocks:
items:
- description: Display AHB clock from gcc
- description: Display AXI clock
- description: Display core clock
clock-names:
items:
- const: iface
- const: bus
- const: core
interrupts:
@ -160,9 +158,8 @@ examples:
power-domains = <&dispcc MDSS_GDSC>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_DISP_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "bus", "core";
clock-names = "iface", "core";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;

2
Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.yaml
View File

@ -35,6 +35,8 @@ properties:
phandle of the gpio for power ic line
Power IC supply enable, High active
port: true
required:
- compatible
- reg

4
Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml
View File

@ -34,7 +34,7 @@ properties:
description: phandle of gpio for reset line - This should be 8mA, gpio
can be configured using mux, pinctrl, pinctrl-names (active high)
vddio-supply:
vddi0-supply:
description: phandle of the regulator that provides the supply voltage
Power IC supply
@ -75,8 +75,6 @@ examples:
reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
port {
tianma_nt36672a_in_0: endpoint {
remote-endpoint = <&dsi0_out>;

12
Documentation/devicetree/bindings/display/simple-framebuffer.yaml
View File

@ -83,13 +83,25 @@ properties:
format:
description: >
Format of the framebuffer:
* `a1r5g5b5` - 16-bit pixels, d[15]=a, d[14:10]=r, d[9:5]=g, d[4:0]=b
* `a2r10g10b10` - 32-bit pixels, d[31:30]=a, d[29:20]=r, d[19:10]=g, d[9:0]=b
* `a8b8g8r8` - 32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r
* `a8r8g8b8` - 32-bit pixels, d[31:24]=a, d[23:16]=r, d[15:8]=g, d[7:0]=b
* `r5g6b5` - 16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b
* `r5g5b5a1` - 16-bit pixels, d[15:11]=r, d[10:6]=g, d[5:1]=b d[1:0]=a
* `r8g8b8` - 24-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b
* `x1r5g5b5` - 16-bit pixels, d[14:10]=r, d[9:5]=g, d[4:0]=b
* `x2r10g10b10` - 32-bit pixels, d[29:20]=r, d[19:10]=g, d[9:0]=b
* `x8r8g8b8` - 32-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b
enum:
- a1r5g5b5
- a2r10g10b10
- a8b8g8r8
- a8r8g8b8
- r5g6b5
- r5g5b5a1
- r8g8b8
- x1r5g5b5
- x2r10g10b10
- x8r8g8b8

3
Documentation/devicetree/bindings/display/st,stm32-dsi.yaml
View File

@ -110,7 +110,7 @@ examples:
};
};
panel-dsi@0 {
panel@0 {
compatible = "orisetech,otm8009a";
reg = <0>;
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
@ -125,4 +125,3 @@ examples:
};
...

2
Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
View File

@ -50,7 +50,7 @@ examples:
dma@3000000 {
compatible = "sifive,fu540-c000-pdma";
reg = <0x3000000 0x8000>;
interrupts = <23 24 25 26 27 28 29 30>;
interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
#dma-cells = <1>;
};

29
Documentation/devicetree/bindings/eeprom/at24.yaml
View File

@ -86,6 +86,10 @@ properties:
pattern: c1024$
- items:
pattern: cs1024$
- items:
pattern: c1025$
- items:
pattern: cs1025$
- items:
pattern: c2048$
- items:
@ -95,17 +99,20 @@ properties:
# These are special cases that don't conform to the above pattern.
# Each requires a standard at24 model as fallback.
- items:
- const: nxp,se97b
- enum:
- rohm,br24g01
- rohm,br24t01
- const: atmel,24c01
- items:
- enum:
- nxp,se97b
- renesas,r1ex24002
- const: atmel,24c02
- items:
- const: onnn,cat24c04
- enum:
- onnn,cat24c04
- onnn,cat24c05
- const: atmel,24c04
- items:
- const: onnn,cat24c05
- const: atmel,24c04
- items:
- const: renesas,r1ex24002
- const: atmel,24c02
- items:
- const: renesas,r1ex24016
- const: atmel,24c16
@ -115,12 +122,6 @@ properties:
- items:
- const: renesas,r1ex24128
- const: atmel,24c128
- items:
- const: rohm,br24g01
- const: atmel,24c01
- items:
- const: rohm,br24t01
- const: atmel,24c01
label:
description: Descriptive name of the EEPROM.

83
Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
View File

@ -1,83 +0,0 @@
Broadcom STB "UPG GIO" GPIO controller
The controller's registers are organized as sets of eight 32-bit
registers with each set controlling a bank of up to 32 pins. A single
interrupt is shared for all of the banks handled by the controller.
Required properties:
- compatible:
Must be "brcm,brcmstb-gpio"
- reg:
Define the base and range of the I/O address space containing
the brcmstb GPIO controller registers
- #gpio-cells:
Should be <2>. The first cell is the pin number (within the controller's
pin space), and the second is used for the following:
bit[0]: polarity (0 for active-high, 1 for active-low)
- gpio-controller:
Specifies that the node is a GPIO controller.
- brcm,gpio-bank-widths:
Number of GPIO lines for each bank. Number of elements must
correspond to number of banks suggested by the 'reg' property.
Optional properties:
- interrupts:
The interrupt shared by all GPIO lines for this controller.
- interrupts-extended:
Alternate form of specifying interrupts and parents that allows for
multiple parents. This takes precedence over 'interrupts' and
'interrupt-parent'. Wakeup-capable GPIO controllers often route their
wakeup interrupt lines through a different interrupt controller than the
primary interrupt line, making this property necessary.
- #interrupt-cells:
Should be <2>. The first cell is the GPIO number, the second should specify
flags. The following subset of flags is supported:
- bits[3:0] trigger type and level flags
1 = low-to-high edge triggered
2 = high-to-low edge triggered
4 = active high level-sensitive
8 = active low level-sensitive
Valid combinations are 1, 2, 3, 4, 8.
See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- interrupt-controller:
Marks the device node as an interrupt controller
- wakeup-source:
GPIOs for this controller can be used as a wakeup source
Example:
upg_gio: gpio@f040a700 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
gpio-controller;
interrupt-controller;
reg = <0xf040a700 0x80>;
interrupt-parent = <&irq0_intc>;
interrupts = <0x6>;
brcm,gpio-bank-widths = <32 32 32 24>;
};
upg_gio_aon: gpio@f04172c0 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
gpio-controller;
interrupt-controller;
reg = <0xf04172c0 0x40>;
interrupt-parent = <&irq0_aon_intc>;
interrupts = <0x6>;
interrupts-extended = <&irq0_aon_intc 0x6>,
<&aon_pm_l2_intc 0x5>;
wakeup-source;
brcm,gpio-bank-widths = <18 4>;
};

104
Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml Normal file
View File

@ -0,0 +1,104 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom STB "UPG GIO" GPIO controller
description: >
The controller's registers are organized as sets of eight 32-bit
registers with each set controlling a bank of up to 32 pins. A single
interrupt is shared for all of the banks handled by the controller.
maintainers:
- Doug Berger <opendmb@gmail.com>
- Florian Fainelli <f.fainelli@gmail.com>
properties:
compatible:
items:
- enum:
- brcm,bcm7445-gpio
- const: brcm,brcmstb-gpio
reg:
maxItems: 1
description: >
Define the base and range of the I/O address space containing
the brcmstb GPIO controller registers
"#gpio-cells":
const: 2
description: >
The first cell is the pin number (within the controller's
pin space), and the second is used for the following:
bit[0]: polarity (0 for active-high, 1 for active-low)
gpio-controller: true
brcm,gpio-bank-widths:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: >
Number of GPIO lines for each bank. Number of elements must
correspond to number of banks suggested by the 'reg' property.
interrupts:
maxItems: 1
description: >
The interrupt shared by all GPIO lines for this controller.
"#interrupt-cells":
const: 2
description: |
The first cell is the GPIO number, the second should specify
flags. The following subset of flags is supported:
- bits[3:0] trigger type and level flags
1 = low-to-high edge triggered
2 = high-to-low edge triggered
4 = active high level-sensitive
8 = active low level-sensitive
Valid combinations are 1, 2, 3, 4, 8.
interrupt-controller: true
wakeup-source:
type: boolean
description: >
GPIOs for this controller can be used as a wakeup source
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
- "brcm,gpio-bank-widths"
additionalProperties: false
examples:
- |
upg_gio: gpio@f040a700 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
gpio-controller;
interrupt-controller;
reg = <0xf040a700 0x80>;
interrupt-parent = <&irq0_intc>;
interrupts = <0x6>;
brcm,gpio-bank-widths = <32 32 32 24>;
};
upg_gio_aon: gpio@f04172c0 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
gpio-controller;
interrupt-controller;
reg = <0xf04172c0 0x40>;
interrupt-parent = <&irq0_aon_intc>;
interrupts = <0x6>;
wakeup-source;
brcm,gpio-bank-widths = <18 4>;
};

1
Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml
View File

@ -43,7 +43,6 @@ required:
- gpio-controller
- interrupt-controller
- "#interrupt-cells"
- interrupt-parent
additionalProperties: false

45
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
View File

@ -19,6 +19,7 @@ properties:
- amlogic,meson-g12a-mali
- mediatek,mt8183-mali
- realtek,rtd1619-mali
- renesas,r9a07g044-mali
- rockchip,px30-mali
- rockchip,rk3568-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
@ -27,19 +28,26 @@ properties:
maxItems: 1
interrupts:
minItems: 3
items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
- description: Event interrupt
interrupt-names:
minItems: 3
items:
- const: job
- const: mmu
- const: gpu
- const: event
clocks:
maxItems: 1
minItems: 1
maxItems: 3
clock-names: true
mali-supply: true
@ -52,7 +60,10 @@ properties:
maxItems: 3
resets:
maxItems: 2
minItems: 1
maxItems: 3
reset-names: true
"#cooling-cells":
const: 2
@ -94,6 +105,36 @@ allOf:
then:
required:
- resets
- if:
properties:
compatible:
contains:
const: renesas,r9a07g044-mali
then:
properties:
interrupts:
minItems: 4
interrupt-names:
minItems: 4
clocks:
minItems: 3
clock-names:
items:
- const: gpu
- const: bus
- const: bus_ace
resets:
minItems: 3
reset-names:
items:
- const: rst
- const: axi_rst
- const: ace_rst
required:
- clock-names
- power-domains
- resets
- reset-names
- if:
properties:
compatible:

1
Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
View File

@ -63,7 +63,6 @@ examples:
i2c0: i2c-bus@40 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
compatible = "aspeed,ast2500-i2c-bus";
reg = <0x40 0x40>;
clocks = <&syscon ASPEED_CLK_APB>;

22
Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.txt
View File

@ -1,22 +0,0 @@
Broadcom BCM2835 I2C controller
Required properties:
- compatible : Should be one of:
"brcm,bcm2711-i2c"
"brcm,bcm2835-i2c"
- reg: Should contain register location and length.
- interrupts: Should contain interrupt.
- clocks : The clock feeding the I2C controller.
Recommended properties:
- clock-frequency : desired I2C bus clock frequency in Hz.
Example:
i2c@7e205000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e205000 0x1000>;
interrupts = <2 21>;
clocks = <&clk_i2c>;
clock-frequency = <100000>;
};

54
Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.yaml Normal file
View File

@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/brcm,bcm2835-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM2835 I2C controller
maintainers:
- Stephen Warren <swarren@wwwdotorg.org>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
properties:
compatible:
oneOf:
- enum:
- brcm,bcm2835-i2c
- items:
- const: brcm,bcm2711-i2c
- const: brcm,bcm2835-i2c
reg:
maxItems: 1
interrupts:
maxItems: 1
clock-names:
maxItems: 1
clocks:
maxItems: 1
clock-frequency: true
required:
- compatible
- reg
- interrupts
- clocks
unevaluatedProperties: false
examples:
- |
i2c@7e205000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e205000 0x1000>;
interrupts = <2 21>;
clocks = <&clk_i2c>;
clock-frequency = <100000>;
};

53
Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
View File

@ -1,53 +0,0 @@
* Samsung's High Speed I2C controller
The Samsung's High Speed I2C controller is used to interface with I2C devices
at various speeds ranging from 100khz to 3.4Mhz.
Required properties:
- compatible: value should be.
-> "samsung,exynos5-hsi2c", (DEPRECATED)
for i2c compatible with HSI2C available
on Exynos5250 and Exynos5420 SoCs.
-> "samsung,exynos5250-hsi2c", for i2c compatible with HSI2C available
on Exynos5250 and Exynos5420 SoCs.
-> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available
on Exynos5260 SoCs.
-> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available
on Exynos7 SoCs.
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- #address-cells: always 1 (for i2c addresses)
- #size-cells: always 0
- Pinctrl:
- pinctrl-0: Pin control group to be used for this controller.
- pinctrl-names: Should contain only one value - "default".
Optional properties:
- clock-frequency: Desired operating frequency in Hz of the bus.
-> If not specified, the bus operates in fast-speed mode at
at 100khz.
-> If specified, the bus operates in high-speed mode only if the
clock-frequency is >= 1Mhz.
Example:
hsi2c@12ca0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12ca0000 0x100>;
interrupts = <56>;
clock-frequency = <100000>;
pinctrl-0 = <&i2c4_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
s2mps11_pmic@66 {
compatible = "samsung,s2mps11-pmic";
reg = <0x66>;
};
};

133
Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml Normal file
View File

@ -0,0 +1,133 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-exynos5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung's High Speed I2C controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
description: |
The Samsung's High Speed I2C controller is used to interface with I2C devices
at various speeds ranging from 100kHz to 3.4MHz.
In case the HSI2C controller is encapsulated within USI block (it's the case
e.g. for Exynos850 and Exynos Auto V9 SoCs), it might be also necessary to
define USI node in device tree file, choosing "i2c" configuration. Please see
Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml for details.
properties:
compatible:
oneOf:
- enum:
- samsung,exynos5250-hsi2c # Exynos5250 and Exynos5420
- samsung,exynos5260-hsi2c # Exynos5260
- samsung,exynos7-hsi2c # Exynos7
- samsung,exynosautov9-hsi2c # ExynosAutoV9 and Exynos850
- const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420
deprecated: true
reg:
maxItems: 1
interrupts:
maxItems: 1
clock-frequency:
default: 100000
description:
Desired operating frequency in Hz of the bus.
If not specified, the bus operates in fast-speed mode at 100kHz.
If specified, the bus operates in high-speed mode only if the
clock-frequency is >= 1MHz.
clocks:
minItems: 1
items:
- description: I2C operating clock
- description: Bus clock (APB)
clock-names:
minItems: 1
items:
- const: hsi2c
- const: hsi2c_pclk
required:
- compatible
- reg
- interrupts
- clocks
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
- if:
properties:
compatible:
contains:
enum:
- samsung,exynosautov9-hsi2c
then:
properties:
clocks:
minItems: 2
clock-names:
minItems: 2
required:
- clock-names
else:
properties:
clocks:
maxItems: 1
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5420.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
hsi2c_8: i2c@12e00000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12e00000 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
clocks = <&clock CLK_USI4>;
clock-names = "hsi2c";
pmic@66 {
/* compatible = "samsung,s2mps11-pmic"; */
reg = <0x66>;
};
};
- |
#include <dt-bindings/clock/exynos850.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
hsi2c_2: i2c@138c0000 {
compatible = "samsung,exynosautov9-hsi2c";
reg = <0x138c0000 0xc0>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>,
<&cmu_peri CLK_GOUT_HSI2C2_PCLK>;
clock-names = "hsi2c", "hsi2c_pclk";
pmic@66 {
/* compatible = "samsung,s2mps11-pmic"; */
reg = <0x66>;
};
};

2
Documentation/devicetree/bindings/i2c/i2c-gate.yaml
View File

@ -31,7 +31,7 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
ak8975@c {
compatible = "ak,ak8975";
compatible = "asahi-kasei,ak8975";
reg = <0x0c>;
};
};

2
Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
View File

@ -20,7 +20,9 @@ properties:
- items:
- enum:
- fsl,imx8qxp-lpi2c
- fsl,imx8dxl-lpi2c
- fsl,imx8qm-lpi2c
- fsl,imx8ulp-lpi2c
- const: fsl,imx7ulp-lpi2c
reg:

80
Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt
View File

@ -1,80 +0,0 @@
GPIO-based I2C Bus Mux
This binding describes an I2C bus multiplexer that uses GPIOs to
route the I2C signals.
+-----+ +-----+
| dev | | dev |
+------------+ +-----+ +-----+
| SoC | | |
| | /--------+--------+
| +------+ | +------+ child bus A, on GPIO value set to 0
| | I2C |-|--| Mux |
| +------+ | +--+---+ child bus B, on GPIO value set to 1
| | | \----------+--------+--------+
| +------+ | | | | |
| | GPIO |-|-----+ +-----+ +-----+ +-----+
| +------+ | | dev | | dev | | dev |
+------------+ +-----+ +-----+ +-----+
Required properties:
- compatible: i2c-mux-gpio
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
port is connected to.
- mux-gpios: list of gpios used to control the muxer
* Standard I2C mux properties. See i2c-mux.yaml in this directory.
* I2C child bus nodes. See i2c-mux.yaml in this directory.
Optional properties:
- idle-state: value to set the muxer to when idle. When no value is
given, it defaults to the last value used.
For each i2c child node, an I2C child bus will be created. They will
be numbered based on their order in the device tree.
Whenever an access is made to a device on a child bus, the value set
in the relevant node's reg property will be output using the list of
GPIOs, the first in the list holding the least-significant value.
If an idle state is defined, using the idle-state (optional) property,
whenever an access is not being made to a device on a child bus, the
GPIOs will be set according to the idle value.
If an idle state is not defined, the most recently used value will be
left programmed into hardware whenever no access is being made to a
device on a child bus.
Example:
i2cmux {
compatible = "i2c-mux-gpio";
#address-cells = <1>;
#size-cells = <0>;
mux-gpios = <&gpio1 22 0 &gpio1 23 0>;
i2c-parent = <&i2c1>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
ssd1307: oled@3c {
compatible = "solomon,ssd1307fb-i2c";
reg = <0x3c>;
pwms = <&pwm 4 3000>;
reset-gpios = <&gpio2 7 1>;
};
};
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
pca9555: pca9555@20 {
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
};
};
};

104
Documentation/devicetree/bindings/i2c/i2c-mux-gpio.yaml Normal file
View File

@ -0,0 +1,104 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-mux-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: GPIO-based I2C Bus Mux
maintainers:
- Wolfram Sang <wsa@kernel.org>
description: |
This binding describes an I2C bus multiplexer that uses GPIOs to route the I2C signals.
+-----+ +-----+
| dev | | dev |
+------------+ +-----+ +-----+
| SoC | | |
| | /--------+--------+
| +------+ | +------+ child bus A, on GPIO value set to 0
| | I2C |-|--| Mux |
| +------+ | +--+---+ child bus B, on GPIO value set to 1
| | | \----------+--------+--------+
| +------+ | | | | |
| | GPIO |-|-----+ +-----+ +-----+ +-----+
| +------+ | | dev | | dev | | dev |
+------------+ +-----+ +-----+ +-----+
For each I2C child node, an I2C child bus will be created. They will be numbered based on their
order in the device tree.
Whenever an access is made to a device on a child bus, the value set in the relevant node's reg
property will be output using the list of GPIOs, the first in the list holding the least-
significant value.
If an idle state is defined, using the idle-state (optional) property, whenever an access is not
being made to a device on a child bus, the GPIOs will be set according to the idle value.
If an idle state is not defined, the most recently used value will be left programmed into
hardware whenever no access is being made to a device on a child bus.
properties:
compatible:
const: i2c-mux-gpio
i2c-parent:
description: phandle of the I2C bus that this multiplexer's master-side port is connected to
$ref: "/schemas/types.yaml#/definitions/phandle"
mux-gpios:
description: list of GPIOs used to control the muxer
minItems: 1
maxItems: 4 # Should be enough
idle-state:
description: Value to set the muxer to when idle. When no value is given, it defaults to the
last value used.
$ref: "/schemas/types.yaml#/definitions/uint32"
allOf:
- $ref: i2c-mux.yaml
unevaluatedProperties: false
required:
- compatible
- i2c-parent
- mux-gpios
examples:
- |
i2cmux {
compatible = "i2c-mux-gpio";
#address-cells = <1>;
#size-cells = <0>;
mux-gpios = <&gpio1 22 0>, <&gpio1 23 0>;
i2c-parent = <&i2c1>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
ssd1307: oled@3c {
compatible = "solomon,ssd1307fb-i2c";
reg = <0x3c>;
pwms = <&pwm 4 3000>;
reset-gpios = <&gpio2 7 1>;
};
};
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
pca9555: pca9555@20 {
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
};
};
};

93
Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt
View File

@ -1,93 +0,0 @@
Pinctrl-based I2C Bus Mux
This binding describes an I2C bus multiplexer that uses pin multiplexing to
route the I2C signals, and represents the pin multiplexing configuration
using the pinctrl device tree bindings.
+-----+ +-----+
| dev | | dev |
+------------------------+ +-----+ +-----+
| SoC | | |
| /----|------+--------+
| +---+ +------+ | child bus A, on first set of pins
| |I2C|---|Pinmux| |
| +---+ +------+ | child bus B, on second set of pins
| \----|------+--------+--------+
| | | | |
+------------------------+ +-----+ +-----+ +-----+
| dev | | dev | | dev |
+-----+ +-----+ +-----+
Required properties:
- compatible: i2c-mux-pinctrl
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
port is connected to.
Also required are:
* Standard pinctrl properties that specify the pin mux state for each child
bus. See ../pinctrl/pinctrl-bindings.txt.
* Standard I2C mux properties. See i2c-mux.yaml in this directory.
* I2C child bus nodes. See i2c-mux.yaml in this directory.
For each named state defined in the pinctrl-names property, an I2C child bus
will be created. I2C child bus numbers are assigned based on the index into
the pinctrl-names property.
The only exception is that no bus will be created for a state named "idle". If
such a state is defined, it must be the last entry in pinctrl-names. For
example:
pinctrl-names = "ddc", "pta", "idle" -> ddc = bus 0, pta = bus 1
pinctrl-names = "ddc", "idle", "pta" -> Invalid ("idle" not last)
pinctrl-names = "idle", "ddc", "pta" -> Invalid ("idle" not last)
Whenever an access is made to a device on a child bus, the relevant pinctrl
state will be programmed into hardware.
If an idle state is defined, whenever an access is not being made to a device
on a child bus, the idle pinctrl state will be programmed into hardware.
If an idle state is not defined, the most recently used pinctrl state will be
left programmed into hardware whenever no access is being made of a device on
a child bus.
Example:
i2cmux {
compatible = "i2c-mux-pinctrl";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c1>;
pinctrl-names = "ddc", "pta", "idle";
pinctrl-0 = <&state_i2cmux_ddc>;
pinctrl-1 = <&state_i2cmux_pta>;
pinctrl-2 = <&state_i2cmux_idle>;
i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom {
compatible = "eeprom";
reg = <0x50>;
};
};
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
eeprom {
compatible = "eeprom";
reg = <0x50>;
};
};
};

103
Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.yaml Normal file
View File

@ -0,0 +1,103 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-mux-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Pinctrl-based I2C Bus Mux
maintainers:
- Wolfram Sang <wsa@kernel.org>
description: |
This binding describes an I2C bus multiplexer that uses pin multiplexing to route the I2C
signals, and represents the pin multiplexing configuration using the pinctrl device tree
bindings.
+-----+ +-----+
| dev | | dev |
+------------------------+ +-----+ +-----+
| SoC | | |
| /----|------+--------+
| +---+ +------+ | child bus A, on first set of pins
| |I2C|---|Pinmux| |
| +---+ +------+ | child bus B, on second set of pins
| \----|------+--------+--------+
| | | | |
+------------------------+ +-----+ +-----+ +-----+
| dev | | dev | | dev |
+-----+ +-----+ +-----+
For each named state defined in the pinctrl-names property, an I2C child bus will be created.
I2C child bus numbers are assigned based on the index into the pinctrl-names property.
The only exception is that no bus will be created for a state named "idle". If such a state is
defined, it must be the last entry in pinctrl-names. For example:
pinctrl-names = "ddc", "pta", "idle" -> ddc = bus 0, pta = bus 1
pinctrl-names = "ddc", "idle", "pta" -> Invalid ("idle" not last)
pinctrl-names = "idle", "ddc", "pta" -> Invalid ("idle" not last)
Whenever an access is made to a device on a child bus, the relevant pinctrl state will be
programmed into hardware.
If an idle state is defined, whenever an access is not being made to a device on a child bus,
the idle pinctrl state will be programmed into hardware.
If an idle state is not defined, the most recently used pinctrl state will be left programmed
into hardware whenever no access is being made of a device on a child bus.
properties:
compatible:
const: i2c-mux-pinctrl
i2c-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: The phandle of the I2C bus that this multiplexer's master-side port is connected
to.
allOf:
- $ref: i2c-mux.yaml
unevaluatedProperties: false
required:
- compatible
- i2c-parent
examples:
- |
i2cmux {
compatible = "i2c-mux-pinctrl";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c1>;
pinctrl-names = "ddc", "pta", "idle";
pinctrl-0 = <&state_i2cmux_ddc>;
pinctrl-1 = <&state_i2cmux_pta>;
pinctrl-2 = <&state_i2cmux_idle>;
i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
};
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
};
};

42
Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
View File

@ -1,42 +0,0 @@
NVIDIA Tegra186 BPMP I2C controller
In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
devices, such as the I2C controller for the power management I2C bus. Software
running on other CPUs must perform IPC to the BPMP in order to execute
transactions on that I2C bus. This binding describes an I2C bus that is
accessed in such a fashion.
The BPMP I2C node must be located directly inside the main BPMP node. See
../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
This node represents an I2C controller. See ../i2c/i2c.txt for details of the
core I2C binding.
Required properties:
- compatible:
Array of strings.
One of:
- "nvidia,tegra186-bpmp-i2c".
- #address-cells: Address cells for I2C device address.
Single-cell integer.
Must be <1>.
- #size-cells:
Single-cell integer.
Must be <0>.
- nvidia,bpmp-bus-id:
Single-cell integer.
Indicates the I2C bus number this DT node represent, as defined by the
BPMP firmware.
Example:
bpmp {
...
i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
#address-cells = <1>;
#size-cells = <0>;
nvidia,bpmp-bus-id = <5>;
};
};

45
Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml Normal file
View File

@ -0,0 +1,45 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra186 (and later) BPMP I2C controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: |
In Tegra186 and later, the BPMP (Boot and Power Management Processor)
owns certain HW devices, such as the I2C controller for the power
management I2C bus. Software running on other CPUs must perform IPC to
the BPMP in order to execute transactions on that I2C bus. This
binding describes an I2C bus that is accessed in such a fashion.
The BPMP I2C node must be located directly inside the main BPMP node.
See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
binding.
This node represents an I2C controller. See ../i2c/i2c.txt for details
of the core I2C binding.
properties:
compatible:
const: nvidia,tegra186-bpmp-i2c
nvidia,bpmp-bus-id:
$ref: /schemas/types.yaml#/definitions/uint32
description: Indicates the I2C bus number this DT node represents,
as defined by the BPMP firmware.
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml
unevaluatedProperties: false
required:
- compatible
- "#address-cells"
- "#size-cells"
- nvidia,bpmp-bus-id

87
Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
View File

@ -1,87 +0,0 @@
NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver.
Required properties:
- compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
"nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c".
For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be
"nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
tegra124, tegra132, or tegra210.
Details of compatible are as follows:
nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
controller. This only support master mode of I2C communication. Register
interface/offset and interrupts handling are different than generic I2C
controller. Driver of DVC I2C controller is only compatible with
"nvidia,tegra20-i2c-dvc".
nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
master and slave mode of I2C communication. The i2c-tegra driver only
support master mode of I2C communication. Driver of I2C controller is
only compatible with "nvidia,tegra20-i2c".
nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
very much similar to Tegra20 I2C controller with additional feature:
Continue Transfer Support. This feature helps to implement M_NO_START
as per I2C core API transfer flags. Driver of I2C controller is
compatible with "nvidia,tegra30-i2c" to enable the continue transfer
support. This is also compatible with "nvidia,tegra20-i2c" without
continue transfer support.
nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is
very much similar to Tegra30 I2C controller with some hardware
modification:
- Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and
fast-clk. Tegra114 has only one clock source called as div-clk and
hence clock mechanism is changed in I2C controller.
- Tegra30/Tegra20 I2C controller has enabled per packet transfer by
default and there is no way to disable it. Tegra114 has this
interrupt disable by default and SW need to enable explicitly.
Due to above changes, Tegra114 I2C driver makes incompatible with
previous hardware driver. Hence, tegra114 I2C controller is compatible
with "nvidia,tegra114-i2c".
nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is on host1x bus
and is part of VE power domain and typically used for camera use-cases.
This VI I2C controller is mostly compatible with the programming model
of the regular I2C controllers with a few exceptions. The I2C registers
start at an offset of 0xc00 (instead of 0), registers are 16 bytes
apart (rather than 4) and the controller does not support slave mode.
- reg: Should contain I2C controller registers physical address and length.
- interrupts: Should contain I2C controller interrupts.
- address-cells: Address cells for I2C device address.
- size-cells: Size of the I2C device address.
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
Tegra20/Tegra30:
- div-clk
- fast-clk
Tegra114:
- div-clk
Tegra210:
- div-clk
- slow (only for nvidia,tegra210-i2c-vi compatible node)
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- i2c
- power-domains: Only for nvidia,tegra210-i2c-vi compatible node and must
include venc powergate node as vi i2c is part of VE power domain.
tegra210-i2c-vi:
- pd_venc
- dmas: Must contain an entry for each entry in clock-names.
See ../dma/dma.txt for details.
- dma-names: Must include the following entries:
- rx
- tx
Example:
i2c@7000c000 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>, <&tegra_car 124>;
clock-names = "div-clk", "fast-clk";
resets = <&tegra_car 12>;
reset-names = "i2c";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
};

192
Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml Normal file
View File

@ -0,0 +1,192 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
title: NVIDIA Tegra I2C controller driver
properties:
compatible:
oneOf:
- description: Tegra20 has 4 generic I2C controller. This can support
master and slave mode of I2C communication. The i2c-tegra driver
only support master mode of I2C communication. Driver of I2C
controller is only compatible with "nvidia,tegra20-i2c".
const: nvidia,tegra20-i2c
- description: Tegra20 has specific I2C controller called as DVC I2C
controller. This only support master mode of I2C communication.
Register interface/offset and interrupts handling are different than
generic I2C controller. Driver of DVC I2C controller is only
compatible with "nvidia,tegra20-i2c-dvc".
const: nvidia,tegra20-i2c-dvc
- description: |
Tegra30 has 5 generic I2C controller. This controller is very much
similar to Tegra20 I2C controller with additional feature: Continue
Transfer Support. This feature helps to implement M_NO_START as per
I2C core API transfer flags. Driver of I2C controller is compatible
with "nvidia,tegra30-i2c" to enable the continue transfer support.
This is also compatible with "nvidia,tegra20-i2c" without continue
transfer support.
items:
- const: nvidia,tegra30-i2c
- const: nvidia,tegra20-i2c
- description: |
Tegra114 has 5 generic I2C controllers. This controller is very much
similar to Tegra30 I2C controller with some hardware modification:
- Tegra30/Tegra20 I2C controller has 2 clock source called div-clk
and fast-clk. Tegra114 has only one clock source called as
div-clk and hence clock mechanism is changed in I2C controller.
- Tegra30/Tegra20 I2C controller has enabled per packet transfer
by default and there is no way to disable it. Tegra114 has this
interrupt disable by default and SW need to enable explicitly.
Due to above changes, Tegra114 I2C driver makes incompatible with
previous hardware driver. Hence, Tegra114 I2C controller is
compatible with "nvidia,tegra114-i2c".
const: nvidia,tegra114-i2c
- description: |
Tegra124 has 6 generic I2C controllers. These controllers are very
similar to those found on Tegra114 but also contain several hardware
improvements and new registers.
const: nvidia,tegra124-i2c
- description: |
Tegra210 has 6 generic I2C controllers. These controllers are very
similar to those found on Tegra124.
items:
- const: nvidia,tegra210-i2c
- const: nvidia,tegra124-i2c
- description: |
Tegra210 has one I2C controller that is on host1x bus and is part of
the VE power domain and typically used for camera use-cases. This VI
I2C controller is mostly compatible with the programming model of
the regular I2C controllers with a few exceptions. The I2C registers
start at an offset of 0xc00 (instead of 0), registers are 16 bytes
apart (rather than 4) and the controller does not support slave
mode.
const: nvidia,tegra210-i2c-vi
- description: |
Tegra186 has 9 generic I2C controllers, two of which are in the AON
(always-on) partition of the SoC. All of these controllers are very
similar to those found on Tegra210.
const: nvidia,tegra186-i2c
- description: |
Tegra194 has 8 generic I2C controllers, two of which are in the AON
(always-on) partition of the SoC. All of these controllers are very
similar to those found on Tegra186. However, these controllers have
support for 64 KiB transactions whereas earlier chips supported no
more than 4 KiB per transactions.
const: nvidia,tegra194-i2c
reg:
maxItems: 1
interrupts:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
maxItems: 2
resets:
items:
- description: module reset
reset-names:
items:
- const: i2c
dmas:
items:
- description: DMA channel for the reception FIFO
- description: DMA channel for the transmission FIFO
dma-names:
items:
- const: rx
- const: tx
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra20-i2c
- nvidia,tegra30-i2c
then:
properties:
clock-names:
items:
- const: div-clk
- const: fast-clk
- if:
properties:
compatible:
contains:
const: nvidia,tegra114-i2c
then:
properties:
clock-names:
items:
- const: div-clk
- if:
properties:
compatible:
contains:
const: nvidia,tegra210-i2c
then:
properties:
clock-names:
items:
- const: div-clk
- if:
properties:
compatible:
contains:
const: nvidia,tegra210-i2c-vi
then:
properties:
clock-names:
items:
- const: div-clk
- const: slow
power-domains:
items:
- description: phandle to the VENC power domain
unevaluatedProperties: false
examples:
- |
i2c@7000c000 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>;
clocks = <&tegra_car 12>, <&tegra_car 124>;
clock-names = "div-clk", "fast-clk";
resets = <&tegra_car 12>;
reset-names = "i2c";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
};

6
Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
View File

@ -112,6 +112,9 @@ examples:
clocks = <&rcc 0 149>;
};
- |
#include <dt-bindings/mfd/stm32f7-rcc.h>
#include <dt-bindings/clock/stm32fx-clock.h>
//Example 2 (with st,stm32f7-i2c compatible)
i2c@40005800 {
compatible = "st,stm32f7-i2c";
@ -124,6 +127,9 @@ examples:
clocks = <&rcc 1 CLK_I2C1>;
};
- |
#include <dt-bindings/mfd/stm32f7-rcc.h>
#include <dt-bindings/clock/stm32fx-clock.h>
//Example 3 (with st,stm32mp15-i2c compatible on stm32mp)
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>

2
Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ADC found on Freescale vf610 and similar SoCs
maintainers:
- Fugang Duan <fugang.duan@nxp.com>
- Haibo Chen <haibo.chen@nxp.com>
description:
ADCs found on vf610/i.MX6slx and upward SoCs from Freescale.

3
Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml
View File

@ -27,6 +27,7 @@ description: |
8 | batt_v
9 | batt_chrg_i
10 | batt_dischrg_i
11 | ts_v
AXP22x
------
@ -34,6 +35,7 @@ description: |
1 | batt_v
2 | batt_chrg_i
3 | batt_dischrg_i
4 | ts_v
AXP813
------
@ -42,6 +44,7 @@ description: |
2 | batt_v
3 | batt_chrg_i
4 | batt_dischrg_i
5 | ts_v
properties:

227
Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml Normal file
View File

@ -0,0 +1,227 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/xlnx,zynqmp-ams.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Ultrascale AMS controller
maintainers:
- Anand Ashok Dumbre <anand.ashok.dumbre@xilinx.com>
description: |
The AMS (Analog Monitoring System) includes an ADC as well as on-chip sensors
that can be used to sample external voltages and monitor on-die operating
conditions, such as temperature and supply voltage levels.
The AMS has two SYSMON blocks which are PL (Programmable Logic) SYSMON and
PS (Processing System) SYSMON.
All designs should have AMS registers, but PS and PL are optional. The
AMS controller can work with only PS, only PL and both PS and PL
configurations. Please specify registers according to your design. Devicetree
should always have AMS module property. Providing PS & PL module is optional.
AMS Channel Details
```````````````````
Sysmon Block |Channel| Details |Measurement
|Number | |Type
---------------------------------------------------------------------------------------------------------
AMS CTRL |0 |System PLLs voltage measurement, VCC_PSPLL. |Voltage
|1 |Battery voltage measurement, VCC_PSBATT. |Voltage
|2 |PL Internal voltage measurement, VCCINT. |Voltage
|3 |Block RAM voltage measurement, VCCBRAM. |Voltage
|4 |PL Aux voltage measurement, VCCAUX. |Voltage
|5 |Voltage measurement for six DDR I/O PLLs, VCC_PSDDR_PLL. |Voltage
|6 |VCC_PSINTFP_DDR voltage measurement. |Voltage
---------------------------------------------------------------------------------------------------------
PS Sysmon |7 |LPD temperature measurement. |Temperature
|8 |FPD temperature measurement (REMOTE). |Temperature
|9 |VCC PS LPD voltage measurement (supply1). |Voltage
|10 |VCC PS FPD voltage measurement (supply2). |Voltage
|11 |PS Aux voltage reference (supply3). |Voltage
|12 |DDR I/O VCC voltage measurement. |Voltage
|13 |PS IO Bank 503 voltage measurement (supply5). |Voltage
|14 |PS IO Bank 500 voltage measurement (supply6). |Voltage
|15 |VCCO_PSIO1 voltage measurement. |Voltage
|16 |VCCO_PSIO2 voltage measurement. |Voltage
|17 |VCC_PS_GTR voltage measurement (VPS_MGTRAVCC). |Voltage
|18 |VTT_PS_GTR voltage measurement (VPS_MGTRAVTT). |Voltage
|19 |VCC_PSADC voltage measurement. |Voltage
---------------------------------------------------------------------------------------------------------
PL Sysmon |20 |PL temperature measurement. |Temperature
|21 |PL Internal voltage measurement, VCCINT. |Voltage
|22 |PL Auxiliary voltage measurement, VCCAUX. |Voltage
|23 |ADC Reference P+ voltage measurement. |Voltage
|24 |ADC Reference N- voltage measurement. |Voltage
|25 |PL Block RAM voltage measurement, VCCBRAM. |Voltage
|26 |LPD Internal voltage measurement, VCC_PSINTLP (supply4). |Voltage
|27 |FPD Internal voltage measurement, VCC_PSINTFP (supply5). |Voltage
|28 |PS Auxiliary voltage measurement (supply6). |Voltage
|29 |PL VCCADC voltage measurement (vccams). |Voltage
|30 |Differential analog input signal voltage measurment. |Voltage
|31 |VUser0 voltage measurement (supply7). |Voltage
|32 |VUser1 voltage measurement (supply8). |Voltage
|33 |VUser2 voltage measurement (supply9). |Voltage
|34 |VUser3 voltage measurement (supply10). |Voltage
|35 |Auxiliary ch 0 voltage measurement (VAux0). |Voltage
|36 |Auxiliary ch 1 voltage measurement (VAux1). |Voltage
|37 |Auxiliary ch 2 voltage measurement (VAux2). |Voltage
|38 |Auxiliary ch 3 voltage measurement (VAux3). |Voltage
|39 |Auxiliary ch 4 voltage measurement (VAux4). |Voltage
|40 |Auxiliary ch 5 voltage measurement (VAux5). |Voltage
|41 |Auxiliary ch 6 voltage measurement (VAux6). |Voltage
|42 |Auxiliary ch 7 voltage measurement (VAux7). |Voltage
|43 |Auxiliary ch 8 voltage measurement (VAux8). |Voltage
|44 |Auxiliary ch 9 voltage measurement (VAux9). |Voltage
|45 |Auxiliary ch 10 voltage measurement (VAux10). |Voltage
|46 |Auxiliary ch 11 voltage measurement (VAux11). |Voltage
|47 |Auxiliary ch 12 voltage measurement (VAux12). |Voltage
|48 |Auxiliary ch 13 voltage measurement (VAux13). |Voltage
|49 |Auxiliary ch 14 voltage measurement (VAux14). |Voltage
|50 |Auxiliary ch 15 voltage measurement (VAux15). |Voltage
--------------------------------------------------------------------------------------------------------
properties:
compatible:
enum:
- xlnx,zynqmp-ams
interrupts:
maxItems: 1
reg:
description: AMS Controller register space
maxItems: 1
ranges:
description:
Maps the child address space for PS and/or PL.
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 1
'#io-channel-cells':
const: 1
ams-ps@0:
type: object
description: |
PS (Processing System) SYSMON is memory mapped to PS. This block has
built-in alarm generation logic that is used to interrupt the processor
based on condition set.
properties:
compatible:
enum:
- xlnx,zynqmp-ams-ps
reg:
description: Register Space for PS-SYSMON
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
ams-pl@400:
type: object
description:
PL-SYSMON is capable of monitoring off chip voltage and temperature.
PL-SYSMON block has DRP, JTAG and I2C interface to enable monitoring
from external master. Out of this interface currently only DRP is
supported. This block has alarm generation logic that is used to
interrupt the processor based on condition set.
properties:
compatible:
items:
- enum:
- xlnx,zynqmp-ams-pl
reg:
description: Register Space for PL-SYSMON.
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
"^channel@([2-4][0-9]|50)$":
type: object
description:
Describes the external channels connected.
properties:
reg:
description:
Pair of pins the channel is connected to. This value is
same as Channel Number for a particular channel.
minimum: 20
maximum: 50
xlnx,bipolar:
$ref: /schemas/types.yaml#/definitions/flag
type: boolean
description:
If the set channel is used in bipolar mode.
required:
- reg
additionalProperties: false
required:
- compatible
- reg
- ranges
additionalProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
xilinx_ams: ams@ffa50000 {
compatible = "xlnx,zynqmp-ams";
interrupt-parent = <&gic>;
interrupts = <0 56 4>;
reg = <0x0 0xffa50000 0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
#io-channel-cells = <1>;
ranges = <0 0 0xffa50800 0x800>;
ams_ps: ams-ps@0 {
compatible = "xlnx,zynqmp-ams-ps";
reg = <0 0x400>;
};
ams_pl: ams-pl@400 {
compatible = "xlnx,zynqmp-ams-pl";
reg = <0x400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
channel@30 {
reg = <30>;
xlnx,bipolar;
};
channel@31 {
reg = <31>;
};
channel@38 {
reg = <38>;
xlnx,bipolar;
};
};
};
};

158
Documentation/devicetree/bindings/iio/addac/adi,ad74413r.yaml Normal file
View File

@ -0,0 +1,158 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/addac/adi,ad74413r.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD74412R/AD74413R device
maintainers:
- Cosmin Tanislav <cosmin.tanislav@analog.com>
description: |
The AD74412R and AD74413R are quad-channel software configurable input/output
solutions for building and process control applications. They contain
functionality for analog output, analog input, digital input, resistance
temperature detector, and thermocouple measurements integrated
into a single chip solution with an SPI interface.
The devices feature a 16-bit ADC and four configurable 13-bit DACs to provide
four configurable input/output channels and a suite of diagnostic functions.
The AD74413R differentiates itself from the AD74412R by being HART-compatible.
https://www.analog.com/en/products/ad74412r.html
https://www.analog.com/en/products/ad74413r.html
properties:
compatible:
enum:
- adi,ad74412r
- adi,ad74413r
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
spi-max-frequency:
maximum: 1000000
spi-cpol: true
interrupts:
maxItems: 1
refin-supply: true
shunt-resistor-micro-ohms:
description:
Shunt (sense) resistor value in micro-Ohms.
default: 100000000
required:
- compatible
- reg
- spi-max-frequency
- spi-cpol
- refin-supply
additionalProperties: false
patternProperties:
"^channel@[0-3]$":
type: object
description: Represents the external channels which are connected to the device.
properties:
reg:
description: |
The channel number. It can have up to 4 channels numbered from 0 to 3.
minimum: 0
maximum: 3
adi,ch-func:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Channel function.
HART functions are not supported on AD74412R.
0 - CH_FUNC_HIGH_IMPEDANCE
1 - CH_FUNC_VOLTAGE_OUTPUT
2 - CH_FUNC_CURRENT_OUTPUT
3 - CH_FUNC_VOLTAGE_INPUT
4 - CH_FUNC_CURRENT_INPUT_EXT_POWER
5 - CH_FUNC_CURRENT_INPUT_LOOP_POWER
6 - CH_FUNC_RESISTANCE_INPUT
7 - CH_FUNC_DIGITAL_INPUT_LOGIC
8 - CH_FUNC_DIGITAL_INPUT_LOOP_POWER
9 - CH_FUNC_CURRENT_INPUT_EXT_POWER_HART
10 - CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART
minimum: 0
maximum: 10
default: 0
adi,gpo-comparator:
type: boolean
description: |
Whether to configure GPO as a comparator or not.
When not configured as a comparator, the GPO will be treated as an
output-only GPIO.
required:
- reg
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/iio/addac/adi,ad74413r.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
cs-gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
status = "okay";
ad74413r@0 {
compatible = "adi,ad74413r";
reg = <0>;
spi-max-frequency = <1000000>;
spi-cpol;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&gpio>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
refin-supply = <&ad74413r_refin>;
channel@0 {
reg = <0>;
adi,ch-func = <CH_FUNC_VOLTAGE_OUTPUT>;
};
channel@1 {
reg = <1>;
adi,ch-func = <CH_FUNC_CURRENT_OUTPUT>;
};
channel@2 {
reg = <2>;
adi,ch-func = <CH_FUNC_DIGITAL_INPUT_LOGIC>;
adi,gpo-comparator;
};
channel@3 {
reg = <3>;
adi,ch-func = <CH_FUNC_CURRENT_INPUT_EXT_POWER>;
};
};
};
...

217
Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml Normal file
View File

@ -0,0 +1,217 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020 Analog Devices Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,ad3552r.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD2552R DAC device driver
maintainers:
- Mihail Chindris <mihail.chindris@analog.com>
description: |
Bindings for the Analog Devices AD3552R DAC device and similar.
Datasheet can be found here:
https://www.analog.com/media/en/technical-documentation/data-sheets/ad3542r.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/ad3552r.pdf
properties:
compatible:
enum:
- adi,ad3542r
- adi,ad3552r
reg:
maxItems: 1
spi-max-frequency:
maximum: 30000000
reset-gpios:
maxItems: 1
ldac-gpios:
description: |
LDAC pin to be used as a hardware trigger to update the DAC channels.
maxItems: 1
vref-supply:
description:
The regulator to use as an external reference. If it does not exists the
internal reference will be used. External reference must be 2.5V
adi,vref-out-en:
description: Vref I/O driven by internal vref to 2.5V. If not set, Vref pin
will be floating.
type: boolean
adi,sdo-drive-strength:
description: |
Configure SDIO0 and SDIO1 strength levels:
- 0: low SDO drive strength.
- 1: medium low SDO drive strength.
- 2: medium high SDO drive strength.
- 3: high SDO drive strength
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
"^channel@([0-1])$":
type: object
description: Configurations of the DAC Channels
additionalProperties: false
properties:
reg:
description: Channel number
enum: [0, 1]
adi,output-range-microvolt: true
custom-output-range-config:
type: object
description: Configuration of custom range when
adi,output-range-microvolt is not present.
The formulas for calculation the output voltages are
Vout_fs = 2.5 + [(GainN + Offset/1024) * 2.5 * Rfbx * 1.03]
Vout_zs = 2.5 - [(GainP + Offset/1024) * 2.5 * Rfbx * 1.03]
properties:
adi,gain-offset:
description: Gain offset used in the above formula
$ref: /schemas/types.yaml#/definitions/int32
maximum: 511
minimum: -511
adi,gain-scaling-p-inv-log2:
description: GainP = 1 / ( 2 ^ adi,gain-scaling-p-inv-log2)
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
adi,gain-scaling-n-inv-log2:
description: GainN = 1 / ( 2 ^ adi,gain-scaling-n-inv-log2)
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
adi,rfb-ohms:
description: Feedback Resistor
required:
- adi,gain-offset
- adi,gain-scaling-p-inv-log2
- adi,gain-scaling-n-inv-log2
- adi,rfb-ohms
required:
- reg
oneOf:
# If adi,output-range-microvolt is missing,
# custom-output-range-config must be used
- required:
- adi,output-range-microvolt
- required:
- custom-output-range-config
allOf:
- if:
properties:
compatible:
contains:
const: adi,ad3542r
then:
patternProperties:
"^channel@([0-1])$":
type: object
properties:
adi,output-range-microvolt:
description: |
Voltage output range of the channel as <minimum, maximum>
Required connections:
Rfb1x for: 0 to 2.5 V; 0 to 3V; 0 to 5 V;
Rfb2x for: 0 to 10 V; 2.5 to 7.5V; -5 to 5 V;
oneOf:
- items:
- const: 0
- enum: [2500000, 3000000, 5000000, 10000000]
- items:
- const: -2500000
- const: 7500000
- items:
- const: -5000000
- const: 5000000
required:
- adi,output-range-microvolt
- if:
properties:
compatible:
contains:
const: adi,ad3552r
then:
patternProperties:
"^channel@([0-1])$":
type: object
properties:
adi,output-range-microvolt:
description: |
Voltage output range of the channel as <minimum, maximum>
Required connections:
Rfb1x for: 0 to 2.5 V; 0 to 5 V;
Rfb2x for: 0 to 10 V; -5 to 5 V;
Rfb4x for: -10 to 10V
oneOf:
- items:
- const: 0
- enum: [2500000, 5000000, 10000000]
- items:
- const: -5000000
- const: 5000000
- items:
- const: -10000000
- const: 10000000
required:
- compatible
- reg
- spi-max-frequency
additionalProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
ad3552r@0 {
compatible = "adi,ad3552r";
reg = <0>;
spi-max-frequency = <20000000>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
adi,output-range-microvolt = <0 10000000>;
};
channel@1 {
reg = <1>;
custom-output-range-config {
adi,gain-offset = <5>;
adi,gain-scaling-p-inv-log2 = <1>;
adi,gain-scaling-n-inv-log2 = <2>;
adi,rfb-ohms = <1>;
};
};
};
};
...

1
Documentation/devicetree/bindings/iio/dac/adi,ad5755.yaml
View File

@ -125,7 +125,6 @@ oneOf:
examples:
- |
#include <dt-bindings/iio/adi,ad5592r.h>
spi {
#address-cells = <1>;
#size-cells = <0>;

61
Documentation/devicetree/bindings/iio/dac/adi,ad7293.yaml Normal file
View File

@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,ad7293.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: AD7293 12-Bit Power Amplifier Current Controller with ADC,
DACs, Temperature and Current Sensors
maintainers:
- Antoniu Miclaus <antoniu.miclaus@analog.com>
description: |
Power Amplifier drain current controller containing functionality
for general-purpose monitoring and control of current, voltage,
and temperature, integrated into a single chip solution with an
SPI-compatible interface.
https://www.analog.com/en/products/ad7293.html
properties:
compatible:
enum:
- adi,ad7293
avdd-supply: true
vdrive-supply: true
reset-gpios:
maxItems: 1
reg:
maxItems: 1
spi-max-frequency:
maximum: 1000000
required:
- compatible
- reg
- avdd-supply
- vdrive-supply
additionalProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
ad7293@0 {
compatible = "adi,ad7293";
reg = <0>;
spi-max-frequency = <1000000>;
avdd-supply = <&avdd>;
vdrive-supply = <&vdrive>;
reset-gpios = <&gpio 10 0>;
};
};
...

66
Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml Normal file
View File

@ -0,0 +1,66 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/filter/adi,admv8818.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ADMV8818 Digitally Tunable, High-Pass and Low-Pass Filter
maintainers:
- Antoniu Miclaus <antoniu.miclaus@analog.com>
description: |
Fully monolithic microwave integrated circuit (MMIC) that
features a digitally selectable frequency of operation.
The device features four independently controlled high-pass
filters (HPFs) and four independently controlled low-pass filters
(LPFs) that span the 2 GHz to 18 GHz frequency range.
https://www.analog.com/en/products/admv8818.html
properties:
compatible:
enum:
- adi,admv8818
reg:
maxItems: 1
spi-max-frequency:
maximum: 10000000
clocks:
description:
Definition of the external clock.
minItems: 1
clock-names:
items:
- const: rf_in
clock-output-names:
maxItems: 1
'#clock-cells':
const: 0
required:
- compatible
- reg
additionalProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
admv8818@0 {
compatible = "adi,admv8818";
reg = <0>;
spi-max-frequency = <10000000>;
clocks = <&admv8818_rfin>;
clock-names = "rf_in";
};
};
...

91
Documentation/devicetree/bindings/iio/frequency/adi,admv1013.yaml Normal file
View File

@ -0,0 +1,91 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/frequency/adi,admv1013.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ADMV1013 Microwave Upconverter
maintainers:
- Antoniu Miclaus <antoniu.miclaus@analog.com>
description: |
Wideband, microwave upconverter optimized for point to point microwave
radio designs operating in the 24 GHz to 44 GHz frequency range.
https://www.analog.com/en/products/admv1013.html
properties:
compatible:
enum:
- adi,admv1013
reg:
maxItems: 1
spi-max-frequency:
maximum: 1000000
clocks:
description:
Definition of the external clock.
minItems: 1
clock-names:
items:
- const: lo_in
vcm-supply:
description:
Analog voltage regulator.
adi,detector-enable:
description:
Enable the Envelope Detector available at output pins VENV_P and
VENV_N. Disable to reduce power consumption.
type: boolean
adi,input-mode:
description:
Select the input mode.
iq - in-phase quadrature (I/Q) input
if - complex intermediate frequency (IF) input
enum: [iq, if]
adi,quad-se-mode:
description:
Switch the LO path from differential to single-ended operation.
se-neg - Single-Ended Mode, Negative Side Disabled.
se-pos - Single-Ended Mode, Positive Side Disabled.
diff - Differential Mode.
enum: [se-neg, se-pos, diff]
'#clock-cells':
const: 0
required:
- compatible
- reg
- clocks
- clock-names
- vcm-supply
additionalProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
admv1013@0{
compatible = "adi,admv1013";
reg = <0>;
spi-max-frequency = <1000000>;
clocks = <&admv1013_lo>;
clock-names = "lo_in";
vcm-supply = <&vcm>;
adi,quad-se-mode = "diff";
adi,detector-enable;
};
};
...

2
Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.yaml
View File

@ -61,7 +61,7 @@ examples:
#size-cells = <0>;
magnetometer@c {
compatible = "ak,ak8975";
compatible = "asahi-kasei,ak8975";
reg = <0x0c>;
};
};

2
Documentation/devicetree/bindings/iio/imu/invensense,mpu6050.yaml
View File

@ -95,7 +95,7 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
magnetometer@c {
compatible = "ak,ak8975";
compatible = "asahi-kasei,ak8975";
reg = <0x0c>;
};
};

7
Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml
View File

@ -61,6 +61,13 @@ properties:
type: boolean
description: enable/disable internal i2c controller pullup resistors.
st,disable-sensor-hub:
type: boolean
description:
Enable/disable internal i2c controller slave autoprobing at bootstrap.
Disable sensor-hub is useful if i2c controller clock/data lines are
connected through a pull-up with other chip lines (e.g. SDO/SA0).
drive-open-drain:
type: boolean
description:

7
Documentation/devicetree/bindings/iio/light/liteon,ltr501.yaml
View File

@ -9,6 +9,9 @@ title: LiteON LTR501 I2C Proximity and Light sensor
maintainers:
- Nikita Travkin <nikita@trvn.ru>
allOf:
- $ref: ../common.yaml#
properties:
compatible:
enum:
@ -25,6 +28,8 @@ properties:
interrupts:
maxItems: 1
proximity-near-level: true
additionalProperties: false
required:
@ -42,6 +47,8 @@ examples:
light-sensor@23 {
compatible = "liteon,ltr559";
reg = <0x23>;
proximity-near-level = <75>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l6>;

2
Documentation/devicetree/bindings/iio/magnetometer/yamaha,yas530.yaml
View File

@ -96,7 +96,7 @@ examples:
vdd-supply = <&ldo1_reg>;
iovdd-supply = <&ldo2_reg>;
reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
interrupts = <&gpio6 13 IRQ_TYPE_EDGE_RISING>;
interrupts = <13 IRQ_TYPE_EDGE_RISING>;
};
};

22
Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml
View File

@ -448,17 +448,17 @@ examples:
reg = <20>;
adi,sensor-type = <9>; //custom thermocouple
adi,single-ended;
adi,custom-thermocouple = /bits/ 64
<(-50220000) 0>,
<(-30200000) 99100000>,
<(-5300000) 135400000>,
<0 273150000>,
<40200000 361200000>,
<55300000 522100000>,
<88300000 720300000>,
<132200000 811200000>,
<188700000 922500000>,
<460400000 1000000000>; //10 pairs
adi,custom-thermocouple =
/bits/ 64 <(-50220000) 0>,
/bits/ 64 <(-30200000) 99100000>,
/bits/ 64 <(-5300000) 135400000>,
/bits/ 64 <0 273150000>,
/bits/ 64 <40200000 361200000>,
/bits/ 64 <55300000 522100000>,
/bits/ 64 <88300000 720300000>,
/bits/ 64 <132200000 811200000>,
/bits/ 64 <188700000 922500000>,
/bits/ 64 <460400000 1000000000>; //10 pairs
};
};

66
Documentation/devicetree/bindings/input/pwm-vibrator.txt
View File

@ -1,66 +0,0 @@
* PWM vibrator device tree bindings
Registers a PWM device as vibrator. It is expected, that the vibrator's
strength increases based on the duty cycle of the enable PWM channel
(100% duty cycle meaning strongest vibration, 0% meaning no vibration).
The binding supports an optional direction PWM channel, that can be
driven at fixed duty cycle. If available this is can be used to increase
the vibration effect of some devices.
Required properties:
- compatible: should contain "pwm-vibrator"
- pwm-names: Should contain "enable" and optionally "direction"
- pwms: Should contain a PWM handle for each entry in pwm-names
Optional properties:
- vcc-supply: Phandle for the regulator supplying power
- direction-duty-cycle-ns: Duty cycle of the direction PWM channel in
nanoseconds, defaults to 50% of the channel's
period.
Example from Motorola Droid 4:
&omap4_pmx_core {
vibrator_direction_pin: pinmux_vibrator_direction_pin {
pinctrl-single,pins = <
OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */
>;
};
vibrator_enable_pin: pinmux_vibrator_enable_pin {
pinctrl-single,pins = <
OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */
>;
};
};
/ {
pwm8: dmtimer-pwm {
pinctrl-names = "default";
pinctrl-0 = <&vibrator_direction_pin>;
compatible = "ti,omap-dmtimer-pwm";
#pwm-cells = <3>;
ti,timers = <&timer8>;
ti,clock-source = <0x01>;
};
pwm9: dmtimer-pwm {
pinctrl-names = "default";
pinctrl-0 = <&vibrator_enable_pin>;
compatible = "ti,omap-dmtimer-pwm";
#pwm-cells = <3>;
ti,timers = <&timer9>;
ti,clock-source = <0x01>;
};
vibrator {
compatible = "pwm-vibrator";
pwms = <&pwm9 0 1000000000 0>,
<&pwm8 0 1000000000 0>;
pwm-names = "enable", "direction";
direction-duty-cycle-ns = <1000000000>;
};
};

57
Documentation/devicetree/bindings/input/pwm-vibrator.yaml Normal file
View File

@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/input/pwm-vibrator.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: PWM vibrator
maintainers:
- Sebastian Reichel <sre@kernel.org>
description: >
Registers a PWM device as vibrator. It is expected, that the vibrator's
strength increases based on the duty cycle of the enable PWM channel
(100% duty cycle meaning strongest vibration, 0% meaning no vibration).
The binding supports an optional direction PWM channel, that can be
driven at fixed duty cycle. If available this is can be used to increase
the vibration effect of some devices.
properties:
compatible:
const: pwm-vibrator
pwm-names:
items:
- const: enable
- const: direction
minItems: 1
pwms:
minItems: 1
maxItems: 2
vcc-supply: true
direction-duty-cycle-ns:
description: >
Duty cycle of the direction PWM channel in nanoseconds,
defaults to 50% of the channel's period.
required:
- compatible
- pwm-names
- pwms
additionalProperties: false
examples:
- |
vibrator {
compatible = "pwm-vibrator";
pwms = <&pwm9 0 1000000000 0>,
<&pwm8 0 1000000000 0>;
pwm-names = "enable", "direction";
direction-duty-cycle-ns = <1000000000>;
};

1
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
View File

@ -18,6 +18,7 @@ properties:
compatible:
enum:
- qcom,sc7180-osm-l3
- qcom,sc7280-epss-l3
- qcom,sc8180x-osm-l3
- qcom,sdm845-osm-l3
- qcom,sm8150-osm-l3

137
Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml Normal file
View File

@ -0,0 +1,137 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,qcm2290.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm QCM2290 Network-On-Chip interconnect
maintainers:
- Shawn Guo <shawn.guo@linaro.org>
description: |
The Qualcomm QCM2290 interconnect providers support adjusting the
bandwidth requirements between the various NoC fabrics.
properties:
reg:
maxItems: 1
compatible:
enum:
- qcom,qcm2290-bimc
- qcom,qcm2290-cnoc
- qcom,qcm2290-snoc
'#interconnect-cells':
const: 1
clock-names:
items:
- const: bus
- const: bus_a
clocks:
items:
- description: Bus Clock
- description: Bus A Clock
# Child node's properties
patternProperties:
'^interconnect-[a-z0-9]+$':
type: object
description:
The interconnect providers do not have a separate QoS register space,
but share parent's space.
properties:
compatible:
enum:
- qcom,qcm2290-qup-virt
- qcom,qcm2290-mmrt-virt
- qcom,qcm2290-mmnrt-virt
'#interconnect-cells':
const: 1
clock-names:
items:
- const: bus
- const: bus_a
clocks:
items:
- description: Bus Clock
- description: Bus A Clock
required:
- compatible
- '#interconnect-cells'
- clock-names
- clocks
additionalProperties: false
required:
- compatible
- reg
- '#interconnect-cells'
- clock-names
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
snoc: interconnect@1880000 {
compatible = "qcom,qcm2290-snoc";
reg = <0x01880000 0x60200>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>;
qup_virt: interconnect-qup {
compatible = "qcom,qcm2290-qup-virt";
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_QUP_CLK>,
<&rpmcc RPM_SMD_QUP_A_CLK>;
};
mmnrt_virt: interconnect-mmnrt {
compatible = "qcom,qcm2290-mmnrt-virt";
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_MMNRT_CLK>,
<&rpmcc RPM_SMD_MMNRT_A_CLK>;
};
mmrt_virt: interconnect-mmrt {
compatible = "qcom,qcm2290-mmrt-virt";
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_MMRT_CLK>,
<&rpmcc RPM_SMD_MMRT_A_CLK>;
};
};
cnoc: interconnect@1900000 {
compatible = "qcom,qcm2290-cnoc";
reg = <0x01900000 0x8200>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
<&rpmcc RPM_SMD_CNOC_A_CLK>;
};
bimc: interconnect@4480000 {
compatible = "qcom,qcm2290-bimc";
reg = <0x04480000 0x80000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
<&rpmcc RPM_SMD_BIMC_A_CLK>;
};

145
Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
View File

@ -27,22 +27,37 @@ properties:
- qcom,msm8939-pcnoc
- qcom,msm8939-snoc
- qcom,msm8939-snoc-mm
- qcom,msm8996-a0noc
- qcom,msm8996-a1noc
- qcom,msm8996-a2noc
- qcom,msm8996-bimc
- qcom,msm8996-cnoc
- qcom,msm8996-mnoc
- qcom,msm8996-pnoc
- qcom,msm8996-snoc
- qcom,qcs404-bimc
- qcom,qcs404-pcnoc
- qcom,qcs404-snoc
- qcom,sdm660-a2noc
- qcom,sdm660-bimc
- qcom,sdm660-cnoc
- qcom,sdm660-gnoc
- qcom,sdm660-mnoc
- qcom,sdm660-snoc
'#interconnect-cells':
const: 1
clock-names:
items:
- const: bus
- const: bus_a
clocks:
items:
- description: Bus Clock
- description: Bus A Clock
minItems: 2
maxItems: 7
clock-names:
minItems: 2
maxItems: 7
power-domains:
maxItems: 1
required:
- compatible
@ -53,6 +68,120 @@ required:
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8916-bimc
- qcom,msm8916-pcnoc
- qcom,msm8916-snoc
- qcom,msm8939-bimc
- qcom,msm8939-pcnoc
- qcom,msm8939-snoc
- qcom,msm8939-snoc-mm
- qcom,msm8996-a1noc
- qcom,msm8996-a2noc
- qcom,msm8996-bimc
- qcom,msm8996-cnoc
- qcom,msm8996-pnoc
- qcom,msm8996-snoc
- qcom,qcs404-bimc
- qcom,qcs404-pcnoc
- qcom,qcs404-snoc
- qcom,sdm660-bimc
- qcom,sdm660-cnoc
- qcom,sdm660-gnoc
- qcom,sdm660-snoc
then:
properties:
clock-names:
items:
- const: bus
- const: bus_a
clocks:
items:
- description: Bus Clock
- description: Bus A Clock
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8996-mnoc
- qcom,sdm660-mnoc
then:
properties:
clock-names:
items:
- const: bus
- const: bus_a
- const: iface
clocks:
items:
- description: Bus Clock.
- description: Bus A Clock.
- description: CPU-NoC High-performance Bus Clock.
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8996-a0noc
then:
properties:
clock-names:
items:
- const: aggre0_snoc_axi
- const: aggre0_cnoc_ahb
- const: aggre0_noc_mpu_cfg
clocks:
items:
- description: Aggregate0 System NoC AXI Clock.
- description: Aggregate0 Config NoC AHB Clock.
- description: Aggregate0 NoC MPU Clock.
required:
- power-domains
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm660-a2noc
then:
properties:
clock-names:
items:
- const: bus
- const: bus_a
- const: ipa
- const: ufs_axi
- const: aggre2_ufs_axi
- const: aggre2_usb3_axi
- const: cfg_noc_usb2_axi
clocks:
items:
- description: Bus Clock.
- description: Bus A Clock.
- description: IPA Clock.
- description: UFS AXI Clock.
- description: Aggregate2 UFS AXI Clock.
- description: Aggregate2 USB3 AXI Clock.
- description: Config NoC USB2 AXI Clock.
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>

11
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
View File

@ -104,6 +104,17 @@ properties:
- qcom,sm8350-mmss-noc
- qcom,sm8350-compute-noc
- qcom,sm8350-system-noc
- qcom,sm8450-aggre1-noc
- qcom,sm8450-aggre2-noc
- qcom,sm8450-clk-virt
- qcom,sm8450-config-noc
- qcom,sm8450-gem-noc
- qcom,sm8450-lpass-ag-noc
- qcom,sm8450-mc-virt
- qcom,sm8450-mmss-noc
- qcom,sm8450-nsp-noc
- qcom,sm8450-pcie-anoc
- qcom,sm8450-system-noc
'#interconnect-cells':
enum: [ 1, 2 ]

185
Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml
View File

@ -1,185 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sdm660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDM660 Network-On-Chip interconnect
maintainers:
- AngeloGioacchino Del Regno <kholk11@gmail.com>
description: |
The Qualcomm SDM660 interconnect providers support adjusting the
bandwidth requirements between the various NoC fabrics.
properties:
reg:
maxItems: 1
compatible:
enum:
- qcom,sdm660-a2noc
- qcom,sdm660-bimc
- qcom,sdm660-cnoc
- qcom,sdm660-gnoc
- qcom,sdm660-mnoc
- qcom,sdm660-snoc
'#interconnect-cells':
const: 1
clocks:
minItems: 1
maxItems: 7
clock-names:
minItems: 1
maxItems: 7
required:
- compatible
- reg
- '#interconnect-cells'
- clock-names
- clocks
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm660-mnoc
then:
properties:
clocks:
items:
- description: Bus Clock.
- description: Bus A Clock.
- description: CPU-NoC High-performance Bus Clock.
clock-names:
items:
- const: bus
- const: bus_a
- const: iface
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm660-a2noc
then:
properties:
clocks:
items:
- description: Bus Clock.
- description: Bus A Clock.
- description: IPA Clock.
- description: UFS AXI Clock.
- description: Aggregate2 UFS AXI Clock.
- description: Aggregate2 USB3 AXI Clock.
- description: Config NoC USB2 AXI Clock.
clock-names:
items:
- const: bus
- const: bus_a
- const: ipa
- const: ufs_axi
- const: aggre2_ufs_axi
- const: aggre2_usb3_axi
- const: cfg_noc_usb2_axi
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm660-bimc
- qcom,sdm660-cnoc
- qcom,sdm660-gnoc
- qcom,sdm660-snoc
then:
properties:
clocks:
items:
- description: Bus Clock.
- description: Bus A Clock.
clock-names:
items:
- const: bus
- const: bus_a
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
#include <dt-bindings/clock/qcom,gcc-sdm660.h>
bimc: interconnect@1008000 {
compatible = "qcom,sdm660-bimc";
reg = <0x01008000 0x78000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
<&rpmcc RPM_SMD_BIMC_A_CLK>;
};
cnoc: interconnect@1500000 {
compatible = "qcom,sdm660-cnoc";
reg = <0x01500000 0x10000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
<&rpmcc RPM_SMD_CNOC_A_CLK>;
};
snoc: interconnect@1626000 {
compatible = "qcom,sdm660-snoc";
reg = <0x01626000 0x7090>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>;
};
a2noc: interconnect@1704000 {
compatible = "qcom,sdm660-a2noc";
reg = <0x01704000 0xc100>;
#interconnect-cells = <1>;
clock-names = "bus",
"bus_a",
"ipa",
"ufs_axi",
"aggre2_ufs_axi",
"aggre2_usb3_axi",
"cfg_noc_usb2_axi";
clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
<&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
<&rpmcc RPM_SMD_IPA_CLK>,
<&gcc GCC_UFS_AXI_CLK>,
<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
<&gcc GCC_CFG_NOC_USB2_AXI_CLK>;
};
mnoc: interconnect@1745000 {
compatible = "qcom,sdm660-mnoc";
reg = <0x01745000 0xa010>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a", "iface";
clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
<&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
<&mmcc AHB_CLK_SRC>;
};
gnoc: interconnect@17900000 {
compatible = "qcom,sdm660-gnoc";
reg = <0x17900000 0xe000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&xo_board>, <&xo_board>;
};

3
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
View File

@ -239,6 +239,7 @@ examples:
};
};
- |
interrupt-controller@2c010000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
@ -254,7 +255,7 @@ examples:
<0x2c040000 0x2000>, // GICC
<0x2c060000 0x2000>, // GICH
<0x2c080000 0x2000>; // GICV
interrupts = <1 9 4>;
interrupts = <1 9 4 0>;
msi-controller@2c200000 {
compatible = "arm,gic-v3-its";

39
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
View File

@ -1,39 +0,0 @@
Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
This interrupt controller shows up in various forms on many BCM338x/BCM63xx
chipsets. It has the following properties:
- outputs a single interrupt signal to its interrupt controller parent
- contains one or more enable/status word pairs, which often appear at
different offsets in different blocks
- no atomic set/clear operations
Required properties:
- compatible: should be "brcm,bcm3380-l2-intc"
- reg: specifies one or more enable/status pairs, in the following format:
<enable_reg 0x4 status_reg 0x4>...
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
source, should be 1.
- interrupts: specifies the interrupt line in the interrupt-parent controller
node, valid values depend on the type of parent interrupt controller
Optional properties:
- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
wakeup source for system suspend/resume.
Example:
irq0_intc: interrupt-controller@10000020 {
compatible = "brcm,bcm3380-l2-intc";
reg = <0x10000024 0x4 0x1000002c 0x4>,
<0x10000020 0x4 0x10000028 0x4>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>;
};

61
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
View File

@ -1,61 +0,0 @@
Broadcom BCM7038-style Level 1 interrupt controller
This block is a first level interrupt controller that is typically connected
directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
since BCM7038 has contained this hardware.
Key elements of the hardware design include:
- 64, 96, 128, or 160 incoming level IRQ lines
- Most onchip peripherals are wired directly to an L1 input
- A separate instance of the register set for each CPU, allowing individual
peripheral IRQs to be routed to any CPU
- Atomic mask/unmask operations
- No polarity/level/edge settings
- No FIFO or priority encoder logic; software is expected to read all
2-5 status words to determine which IRQs are pending
Required properties:
- compatible: should be "brcm,bcm7038-l1-intc"
- reg: specifies the base physical address and size of the registers;
the number of supported IRQs is inferred from the size argument
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
source, should be 1.
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
node; valid values depend on the type of parent interrupt controller
Optional properties:
- brcm,irq-can-wake: If present, this means the L1 controller can be used as a
wakeup source for system suspend/resume.
Optional properties:
- brcm,int-fwd-mask: if present, a bit mask to indicate which interrupts
have already been configured by the firmware and should be left unmanaged.
This should have one 32-bit word per status/set/clear/mask group.
If multiple reg ranges and interrupt-parent entries are present on an SMP
system, the driver will allow IRQ SMP affinity to be set up through the
/proc/irq/ interface. In the simplest possible configuration, only one
reg range and one interrupt-parent is needed.
Example:
periph_intc: periph_intc@1041a400 {
compatible = "brcm,bcm7038-l1-intc";
reg = <0x1041a400 0x30 0x1041a600 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>, <3>;
};

91
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.yaml Normal file
View File

@ -0,0 +1,91 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM7038-style Level 1 interrupt controller
description: >
This block is a first level interrupt controller that is typically connected
directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
since BCM7038 has contained this hardware.
Key elements of the hardware design include:
- 64, 96, 128, or 160 incoming level IRQ lines
- Most onchip peripherals are wired directly to an L1 input
- A separate instance of the register set for each CPU, allowing individual
peripheral IRQs to be routed to any CPU
- Atomic mask/unmask operations
- No polarity/level/edge settings
- No FIFO or priority encoder logic; software is expected to read all
2-5 status words to determine which IRQs are pending
If multiple reg ranges and interrupt-parent entries are present on an SMP
system, the driver will allow IRQ SMP affinity to be set up through the
/proc/irq/ interface. In the simplest possible configuration, only one
reg range and one interrupt-parent is needed.
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
const: brcm,bcm7038-l1-intc
reg:
description: >
Specifies the base physical address and size of the registers
the number of supported IRQs is inferred from the size argument
interrupt-controller: true
"#interrupt-cells":
const: 1
interrupts:
description: >
Specifies the interrupt line(s) in the interrupt-parent controller node;
valid values depend on the type of parent interrupt controller
brcm,irq-can-wake:
type: boolean
description: >
If present, this means the L1 controller can be used as a
wakeup source for system suspend/resume.
brcm,int-fwd-mask:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
If present, a bit mask to indicate which interrupts have already been
configured by the firmware and should be left unmanaged. This should
have one 32-bit word per status/set/clear/mask group.
required:
- compatible
- reg
- interrupt-controller
- "#interrupt-cells"
- interrupts
additionalProperties: false
examples:
- |
periph_intc: interrupt-controller@1041a400 {
compatible = "brcm,bcm7038-l1-intc";
reg = <0x1041a400 0x30>, <0x1041a600 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>, <3>;
};

88
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
View File

@ -1,88 +0,0 @@
Broadcom BCM7120-style Level 2 interrupt controller
This interrupt controller hardware is a second level interrupt controller that
is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
platforms. It can be found on BCM7xxx products starting with BCM7120.
Such an interrupt controller has the following hardware design:
- outputs multiple interrupts signals towards its interrupt controller parent
- controls how some of the interrupts will be flowing, whether they will
directly output an interrupt signal towards the interrupt controller parent,
or if they will output an interrupt signal at this 2nd level interrupt
controller, in particular for UARTs
- has one 32-bit enable word and one 32-bit status word
- no atomic set/clear operations
- not all bits within the interrupt controller actually map to an interrupt
The typical hardware layout for this controller is represented below:
2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
0 -----[ MUX ] ------------|==========> GIC interrupt 75
\-----------\
|
1 -----[ MUX ] --------)---|==========> GIC interrupt 76
\------------|
|
2 -----[ MUX ] --------)---|==========> GIC interrupt 77
\------------|
|
3 ---------------------|
4 ---------------------|
5 ---------------------|
7 ---------------------|---|===========> GIC interrupt 66
9 ---------------------|
10 --------------------|
11 --------------------/
6 ------------------------\
|===========> GIC interrupt 64
8 ------------------------/
12 ........................ X
13 ........................ X (not connected)
..
31 ........................ X
Required properties:
- compatible: should be "brcm,bcm7120-l2-intc"
- reg: specifies the base physical address and size of the registers
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
source, should be 1.
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
node, valid values depend on the type of parent interrupt controller
- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
are wired to this 2nd level interrupt controller, and how they match their
respective interrupt parents. Should match exactly the number of interrupts
specified in the 'interrupts' property.
Optional properties:
- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
wakeup source for system suspend/resume.
- brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which
have a mux gate, typically UARTs. Setting these bits will make their
respective interrupt outputs bypass this 2nd level interrupt controller
completely; it is completely transparent for the interrupt controller
parent. This should have one 32-bit word per enable/status pair.
Example:
irq0_intc: interrupt-controller@f0406800 {
compatible = "brcm,bcm7120-l2-intc";
interrupt-parent = <&intc>;
#interrupt-cells = <1>;
reg = <0xf0406800 0x8>;
interrupt-controller;
interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
brcm,int-map-mask = <0xeb8>, <0x140>;
brcm,int-fwd-mask = <0x7>;
};

151
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml Normal file
View File

@ -0,0 +1,151 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
description: >
This interrupt controller hardware is a second level interrupt controller that
is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
platforms. It can be found on BCM7xxx products starting with BCM7120.
Such an interrupt controller has the following hardware design:
- outputs multiple interrupts signals towards its interrupt controller parent
- controls how some of the interrupts will be flowing, whether they will
directly output an interrupt signal towards the interrupt controller parent,
or if they will output an interrupt signal at this 2nd level interrupt
controller, in particular for UARTs
- has one 32-bit enable word and one 32-bit status word
- no atomic set/clear operations
- not all bits within the interrupt controller actually map to an interrupt
The typical hardware layout for this controller is represented below:
2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
0 -----[ MUX ] ------------|==========> GIC interrupt 75
\-----------\
|
1 -----[ MUX ] --------)---|==========> GIC interrupt 76
\------------|
|
2 -----[ MUX ] --------)---|==========> GIC interrupt 77
\------------|
|
3 ---------------------|
4 ---------------------|
5 ---------------------|
7 ---------------------|---|===========> GIC interrupt 66
9 ---------------------|
10 --------------------|
11 --------------------/
6 ------------------------\
|===========> GIC interrupt 64
8 ------------------------/
12 ........................ X
13 ........................ X (not connected)
..
31 ........................ X
The BCM3380 Level 1 / Level 2 interrrupt controller shows up in various forms
on many BCM338x/BCM63xx chipsets. It has the following properties:
- outputs a single interrupt signal to its interrupt controller parent
- contains one or more enable/status word pairs, which often appear at
different offsets in different blocks
- no atomic set/clear operations
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
items:
- enum:
- brcm,bcm7120-l2-intc
- brcm,bcm3380-l2-intc
reg:
minItems: 1
maxItems: 4
description: >
Specifies the base physical address and size of the registers
interrupt-controller: true
"#interrupt-cells":
const: 1
interrupts:
minItems: 1
maxItems: 32
brcm,int-map-mask:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: >
32-bits bit mask describing how many and which interrupts are wired to
this 2nd level interrupt controller, and how they match their respective
interrupt parents. Should match exactly the number of interrupts
specified in the 'interrupts' property.
brcm,irq-can-wake:
type: boolean
description: >
If present, this means the L2 controller can be used as a wakeup source
for system suspend/resume.
brcm,int-fwd-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
if present, a bit mask to configure the interrupts which have a mux gate,
typically UARTs. Setting these bits will make their respective interrupt
outputs bypass this 2nd level interrupt controller completely; it is
completely transparent for the interrupt controller parent. This should
have one 32-bit word per enable/status pair.
additionalProperties: false
required:
- compatible
- reg
- interrupt-controller
- "#interrupt-cells"
- interrupts
examples:
- |
irq0_intc: interrupt-controller@f0406800 {
compatible = "brcm,bcm7120-l2-intc";
interrupt-parent = <&intc>;
#interrupt-cells = <1>;
reg = <0xf0406800 0x8>;
interrupt-controller;
interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
brcm,int-map-mask = <0xeb8>, <0x140>;
brcm,int-fwd-mask = <0x7>;
};
- |
irq1_intc: interrupt-controller@10000020 {
compatible = "brcm,bcm3380-l2-intc";
reg = <0x10000024 0x4>, <0x1000002c 0x4>,
<0x10000020 0x4>, <0x10000028 0x4>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>;
};

Some files were not shown because too many files have changed in this diff Show More