Merge keystone/mirror-android-mainline into keystone/android-mainline-keystone-qcom-dev

* keystone/mirror-android-mainline: ANDROID: GKI: Enable CONFIG_SERIAL_8250_RUNTIME_UARTS=0 ANDROID: clang: update to 14.0.2 Revert "ANDROID: GKI: defconfig: enable BTF debug info" Revert "clk: Emit a stern warning with writable debugfs enabled" UPSTREAM: lib/crypto: blake2s: avoid indirect calls to compression function for Clang CFI ANDROID: kleaf: build/kleaf -> build/kernel/kleaf ANDROID: Revert "perf/core: Use static_call to optimize perf_guest_info_callbacks" ANDROID: build/build-tools -> build/kernel/build-tools. Revert "ANDROID: GKI: enable test_stackinit kernel module" ANDROID: incremental-fs: populate userns before calling vfs_rename ANDROID: incremental-fs: remove index and incomplete dir on umount Revert "ANDROID: Support CONFIG_CMDLINE_EXTEND" ANDROID: fs/fuse: Use extended init flags for FUSE_PASSTHROUGH FROMLIST: kbuild: install the modules.order for external modules Revert "FROMLIST: kbuild: install the modules.order for external modules" ANDROID: Re-apply vendor hooks for rt_mutex information of blocked tasks ANDROID: Re-apply vendor hooks for information of blocked tasks mm/memremap: add ZONE_DEVICE support for compound pages mm/page_alloc: refactor memmap_init_zone_device() page init mm/page_alloc: split prep_compound_page into head and tail subparts mm: defer kmemleak object creation of module_alloc() mm: kmemleak: alloc gray object for reserved region with direct map kmemleak: fix kmemleak false positive report with HW tag-based kasan enable mm: slab: make slab iterator functions static mm/slab_common: use WARN() if cache still has objects on destroy fs/ioctl: remove unnecessary __user annotation ocfs2: remove redundant assignment to variable free_space ocfs2: use BUG_ON instead of if condition followed by BUG. squashfs: provide backing_dev_info in order to disable read-ahead fs/ntfs/attrib.c: fix one kernel-doc comment scripts/spelling.txt: add "oveflow" ocfs2: cluster: use default_groups in kobj_type ia64: topology: use default_groups in kobj_type ocfs2: remove redundant assignment to pointer root_bh ia64: fix typo in a comment ocfs2: use default_groups in kobj_type arch/ia64/kernel/setup.c: use swap() to make code cleaner ocfs2: clearly handle ocfs2_grab_pages_for_write() return value ia64: module: use swap() to make code cleaner trace/hwlat: make use of the helper function kthread_run_on_cpu() trace/osnoise: make use of the helper function kthread_run_on_cpu() rcutorture: make use of the helper function kthread_run_on_cpu() ring-buffer: make use of the helper function kthread_run_on_cpu() RDMA/siw: make use of the helper function kthread_run_on_cpu() kthread: add the helper function kthread_run_on_cpu() ALSA: hda: intel-dsp-config: reorder the config table ALSA: hda: intel-dsp-config: add JasperLake support leds: lp55xx: initialise output direction from dts ARM: dts: omap3-n900: Fix lp5523 for multi color leds: ktd2692: Drop calling dev_of_node() in ktd2692_parse_dt leds: lgm-sso: Get rid of duplicate of_node assignment leds: tca6507: Get rid of duplicate of_node assignment leds: leds-fsg: Drop FSG3 LED driver leds: lp50xx: remove unused variable dt-bindings: leds: Replace moonlight with indicator in mt6360 example leds: led-core: Update fwnode with device_set_node leds: tca6507: use swap() to make code cleaner leds: Add mt6360 driver xfs: fix online fsck handling of v5 feature bits on secondary supers dt-bindings: net: mdio: Drop resets/reset-names child properties x86/entry_32: Fix segment exceptions dt-bindings: mailbox: Add more protocol and client ID mailbox: qcom-ipcc: Support interrupt wake up from suspend mailbox: qcom-ipcc: Support more IPCC instance mailbox: qcom-ipcc: Dynamic alloc for channel arrangement mailbox: change mailbox-mpfs compatible string mailbox: pcc: Handle all PCC subtypes correctly in pcc_mbox_irq mailbox: pcc: Avoid using the uninitialized variable 'dev' mailbox: mtk: add missing of_node_put before return mailbox: zynq: add missing of_node_put before return mailbox: imx: Fix an IS_ERR() vs NULL bug mailbox: hi3660: convert struct comments to kernel-doc notation mailbox: add control_by_sw for mt8195 mailbox: mtk-cmdq: Silent EPROBE_DEFER errors for clks mailbox: fix gce_num of mt8192 driver data mailbox: apple: Bind to generic compatibles dt-bindings: mailbox: apple,mailbox: Add generic and t6000 compatibles xfs: take the ILOCK when readdir inspects directory mapping data 9p, afs, ceph, nfs: Use current_is_kswapd() rather than gfpflags_allow_blocking() fscache: Add a tracepoint for cookie use/unuse fscache: Rewrite documentation ceph: add fscache writeback support ceph: conversion to new fscache API openrisc: init: Add support for common clk i2c: sh_mobile: remove unneeded semicolon dt-bindings: clock: samsung: convert S5Pv210 to dtschema dt-bindings: clock: samsung: convert Exynos5410 to dtschema dt-bindings: clock: samsung: convert Exynos5260 to dtschema dt-bindings: clock: samsung: extend Exynos7 bindings with UFS dt-bindings: clock: samsung: convert Exynos7 to dtschema dt-bindings: clock: samsung: convert Exynos5433 to dtschema dt-bindings: i2c: maxim,max96712: Add bindings for Maxim Integrated MAX96712 dt-bindings: iio: adi,ltc2983: Fix 64-bit property sizes dt-bindings: power: maxim,max17040: Fix incorrect type for 'maxim,rcomp' dt-bindings: interrupt-controller: arm,gic-v3: Fix 'interrupts' cell size in example dt-bindings: iio/magnetometer: yamaha,yas530: Fix invalid 'interrupts' in example dt-bindings: clock: imx5: Drop clock consumer node from example dt-bindings: Drop required 'interrupt-parent' dt-bindings: net: ti,dp83869: Drop value on boolean 'ti,max-output-impedance' dt-bindings: net: wireless: mt76: Fix 8-bit property sizes dt-bindings: PCI: snps,dw-pcie-ep: Drop conflicting 'max-functions' schema dt-bindings: i2c: st,stm32-i2c: Make each example a separate entry dt-bindings: net: stm32-dwmac: Make each example a separate entry dt-bindings: net: Cleanup MDIO node schemas ALSA: hda: cs35l41: fix double free on error in probe() MIPS: ath79: drop _machine_restart again PCI: brcmstb: Augment driver for MIPs SOCs MIPS: bmips: Remove obsolete DMA mapping support MIPS: bmips: Add support PCIe controller device nodes dt-bindings: PCI: Add compatible string for Brcmstb 74[23]5 MIPs SOCs genirq/msi: Populate sysfs entry only once RDMA/irdma: Remove the redundant return nfs: Implement cache I/O by accessing the cache directly nfs: Convert to new fscache volume/cookie API 9p: Copy local writes to the cache when writing to the server 9p: Use fscache indexing rewrite and reenable caching dt-bindings: net: Add missing properties used in examples dt-bindings: net: snps,dwmac: Enable burst length properties for more compatibles dt-bindings: net: mdio: Allow any child node name dt-bindings: vendor-prefixes: Add Sunplus MIPS: compressed: Fix build with ZSTD compression MIPS: BCM47XX: Add support for Netgear WN2500RP v1 & v2 MIPS: BCM47XX: Add support for Netgear R6300 v1 MIPS: BCM47XX: Add LEDs and buttons for Asus RTN-10U MIPS: BCM47XX: Add board entry for Linksys WRT320N v1 MIPS: BCM47XX: Define Linksys WRT310N V2 buttons MIPS: Remove duplicated include in local.h ALSA: hda: Fix dependencies of CS35L41 on SPI/I2C buses of/fdt: Don't worry about non-memory region overlap for no-map of: unittest: remove unneeded semicolon of: base: Improve argument length mismatch error of: base: Fix phandle argument length mismatch error message ALSA: hda: Fix dependency on ASoC cs35l41 codec clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup() RDMA/rxe: Use the standard method to produce udp source port RDMA/irdma: Make the source udp port vary RDMA/hns: Replace get_udp_sport with rdma_get_udp_sport RDMA/core: Calculate UDP source port based on flow label or lqpn/rqpn ASoC: cs35l41: Add support for hibernate memory retention mode ASoC: cs35l41: Update handling of test key registers IB/qib: Fix typos RDMA/rtrs-clt: Rename rtrs_clt to rtrs_clt_sess RDMA/rtrs-srv: Rename rtrs_srv to rtrs_srv_sess RDMA/rtrs-clt: Rename rtrs_clt_sess to rtrs_clt_path RDMA/rtrs-srv: Rename rtrs_srv_sess to rtrs_srv_path RDMA/rtrs: Rename rtrs_sess to rtrs_path RDMA/hns: Modify the hop num of HIP09 EQ to 1 afs: Skip truncation on the server of data we haven't written yet afs: Copy local writes to the cache when writing to the server afs: Convert afs to use the new fscache API fscache, cachefiles: Display stat of culling events fscache, cachefiles: Display stats of no-space events cachefiles: Allow cachefiles to actually function fscache, cachefiles: Store the volume coherency data cachefiles: Implement the I/O routines cachefiles: Implement cookie resize for truncate cachefiles: Implement begin and end I/O operation cachefiles: Implement backing file wrangling cachefiles: Implement culling daemon commands cachefiles: Mark a backing file in use with an inode flag cachefiles: Implement metadata/coherency data storage in xattrs cachefiles: Implement key to filename encoding cachefiles: Implement object lifecycle funcs cachefiles: Add tracepoints for calls to the VFS cachefiles: Implement volume support cachefiles: Implement cache registration and withdrawal cachefiles: Implement a function to get/create a directory in the cache vfs, cachefiles: Mark a backing file in use with an inode flag cachefiles: Provide a function to check how much space there is cachefiles: Register a miscdev and parse commands over it cachefiles: Add security derivation cachefiles: Add cache error reporting macro cachefiles: Add a couple of tracepoints for logging errors cachefiles: Add some error injection support cachefiles: Define structs cachefiles: Introduce rewritten driver fscache: Provide a function to resize a cookie fscache: Provide a function to note the release of a page vfs, fscache: Implement pinning of cache usage for writeback fscache: Implement higher-level write I/O interface fscache: Implement raw I/O interface netfs: Pass more information on how to deal with a hole in the cache fscache: Provide a function to let the netfs update its coherency data fscache: Provide read/write stat counters for the cache fscache: Count data storage objects in a cache fscache: Provide a means to begin an operation fscache: Implement cookie invalidation fscache: Implement cookie user counting and resource pinning fscache: Implement simple cookie state machine fscache: Add a function for a cache backend to note an I/O error fscache: Provide and use cache methods to lookup/create/free a volume fscache: Implement functions add/remove a cache fscache: Implement cookie-level access helpers fscache: Implement volume-level access helpers fscache: Implement cache-level access helpers fscache: Implement cookie registration fscache: Implement volume registration fscache: Implement cache registration fscache: Implement a hash function fscache: Introduce new driver netfs: Pass a flag to ->prepare_write() to say if there's no alloc'd space netfs: Display the netfs inode number in the netfs_read tracepoint fscache: Remove the contents of the fscache driver, pending rewrite cachefiles: Delete the cachefiles driver pending rewrite fscache, cachefiles: Disable configuration ALSA: intel_hdmi: Check for error num after setting mask clk: mediatek: add mt7986 clock support clk: mediatek: add mt7986 clock IDs dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpers clk: mediatek: clk-gate: Shrink by adding clockgating bit check helper clk: x86: Fix clk_gate_flags for RV_CLK_GATE clk: x86: Use dynamic con_id string during clk registration ACPI: APD: Add a fmw property clk-name drivers: acpi: acpi_apd: Remove unused device property "is-rv" x86: clk: clk-fch: Add support for newer family of AMD's SOC clk: ingenic: Add MDMA and BDMA clocks dt-bindings: clk/ingenic: Add MDMA and BDMA clocks clk: bm1880: remove kfrees on static allocations IB/iser: Align coding style across driver ASoC: wcd9335: Keep a RX port value for each SLIM RX mux ASoC: amd: acp: acp-mach: Change default RT1019 amp dev id ALSA: virmidi: Remove duplicated code ALSA: seq: virmidi: Add a drain operation counter: 104-quad-8: Fix use-after-free by quad8_irq_handler ASoC: topology: Fix typo ASoC: fsl_asrc: refine the check of available clock divider ASoC: Intel: bytcr_rt5640: Add support for external GPIO jack-detect ASoC: Intel: bytcr_rt5640: Support retrieving the codec IRQ from the AMCR0F28 ACPI dev ASoC: rt5640: Add support for boards with an external jack-detect GPIO ASoC: rt5640: Allow snd_soc_component_set_jack() to override the codec IRQ ASoC: rt5640: Change jack_work to a delayed_work ASoC: rt5640: Fix possible NULL pointer deref on resume ASoC: imx-card: improve the sound quality for low rate ASoC: imx-card: Fix mclk calculation issue for akcodec ASoC: imx-card: Need special setting for ak4497 on i.MX8MQ powerpc/xmon: Dump XIVE information for online-only processors. dt-bindings: xen: Clarify "reg" purpose arm/xen: Read extended regions from DT and init Xen resource xen/unpopulated-alloc: Add mechanism to use Xen resource xen/balloon: Bring alloc(free)_xenballooned_pages helpers back arm/xen: Switch to use gnttab_setup_auto_xlat_frames() for DT xen/unpopulated-alloc: Drop check for virt_addr_valid() in fill_list() xen/x86: obtain upper 32 bits of video frame buffer address for Dom0 xen/gntdev: fix unmap notification order clk: Drop unused COMMON_CLK_STM32MP157_SCMI config clk: st: clkgen-mux: search reg within node or parent clk: st: clkgen-fsyn: search reg within node or parent clk: Enable/Disable runtime PM for clk_summary MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller clk: visconti: Add support common clock driver and reset driver dt-bindings: clock: Add DT bindings for SMU of Toshiba Visconti TMPV770x SoC dt-bindings: clock: Add DT bindings for PLL of Toshiba Visconti TMPV770x SoC clk: socfpga: s10: Make use of the helper function devm_platform_ioremap_resource() clk: socfpga: agilex: Make use of the helper function devm_platform_ioremap_resource() clk: socfpga: remove redundant assignment after a mask operation clk: socfpga: remove redundant assignment on division clk: qcom: gcc-sc7280: Mark gcc_cfg_noc_lpass_clk always enabled clk: qcom: clk-alpha-pll: Increase PLL lock detect poll time IB/iser: Remove un-needed casting to/from void pointer IB/iser: Don't suppress send completions IB/iser: Rename ib_ret local variable IB/iser: Fix RNR errors IB/iser: Remove deprecated pi_guard module param IB/mlx5: Expose NDR speed through MAD RDMA/cxgb4: Set queue pair state when being queried RDMA/hns: Remove support for HIP06 RDMA/rxe: Delete deprecated module parameters interface RDMA/mad: Delete duplicated init_query_mad functions RDMA/rxe: Fix indentations and operators sytle RDMA: Use default_groups in kobj_type RDMA/mlx5: Print wc status on CQE error and dump needed RDMA/rxe: Fix a typo in opcode name RDMA/rxe: Remove the unused xmit_errors member RDMA/rxe: Remove redundant err variable RDMA/ocrdma: Remove unneeded variable dt-bindings: display: novatek,nt36672a: Fix unevaluated properties warning ALSA: hda: ALC287: Add Lenovo IdeaPad Slim 9i 14ITL5 speaker quirk ASoC: ak4375: Fix unused function error ALSA: hda/realtek: Add CS35L41 support for Thinkpad laptops ALSA: hda/realtek: Add support for Legion 7 16ACHg6 laptop ALSA: hda: cs35l41: Add support for CS35L41 in HDA systems ALSA: hda/realtek: Re-order quirk entries for Lenovo ALSA: hda/realtek: Add quirk for Legion Y9000X 2020 ASoC: cs4265: Add a remove() function ASoC: wm_adsp: Add support for "toggle" preloaders firmware: cs_dsp: Clear core reset for cache ASoC: cs35l41: Correct handling of some registers in the cache ASoC: cs35l41: Correct DSP power down ASoC: cs35l41: Remove incorrect comment ASoC: cs35l41: Add cs35l51/53 IDs dt-bindings: rng: timeriomem_rng: convert TimerIO RNG to dtschema dt-bindings: rng: st,rng: convert ST RNG to dtschema dt-bindings: rng: ti,omap-rom-rng: convert OMAP ROM RNG to dtschema dt-bindings: rng: nuvoton,npcm-rng: convert Nuvoton NPCM RNG to dtschema dt-bindings: rng: ti,keystone-rng: convert TI Keystone RNG to dtschema dt-bindings: rng: atmel,at91-trng: document sama7g5 TRNG dt-bindings: rng: atmel,at91-trng: convert Atmel TRNG to dtschema dt-bindings: rng: apm,x-gene-rng: convert APM RNG to dtschema MIPS: retire "asm/llsc.h" MIPS: rework local_t operation on MIPS64 MIPS: fix local_{add,sub}_return on MIPS64 mips/pci: remove redundant ret variable MIPS: Loongson64: Add missing of_node_put() in ls2k_reset_init() cxl/core: Remove cxld_const_init in cxl_decoder_alloc() of: unittest: re-implement overlay tracking of: unittest: change references to obsolete overlay id dt-bindings: display: enable port jdi,lt070me05000 dt-bindings: vendor-prefixes: add OnePlus dt-bindings: display: st,stm32-dsi: Fix panel node name in example dt-bindings: memory: Document Tegra210 EMC table powerpc/opal: use default_groups in kobj_type powerpc/cacheinfo: use default_groups in kobj_type ALSA: hda/cs8409: Fix Jack detection after resume ALSA: hda/cs8409: Increase delay during jack detection ASoC: fsl_mqs: fix MODULE_ALIAS powerpc/sched: Remove unused TASK_SIZE_OF powerpc/xive: Add missing null check after calling kmalloc powerpc/floppy: Remove usage of the deprecated "pci-dma-compat.h" API ALSA: hda/realtek - Fix silent output on Gigabyte X570 Aorus Master after reboot from Windows dt-bindings: mux: Document mux-states property dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC i2c: riic: Use platform_get_irq() to get the interrupt i2c: sh_mobile: Use platform_get_irq_optional() to get the interrupt i2c: bcm2835: Use platform_get_irq() to get the interrupt MIPS: new Kconfig option ZBOOT_LOAD_ADDRESS MIPS: enable both vmlinux.gz.itb and vmlinuz for generic MIPS: signal: Return immediately if call fails MIPS: signal: Protect against sigaltstack wraparound mips: bcm63xx: add support for clk_set_parent() mips: lantiq: add support for clk_set_parent() dt-bindings: mips: Add Loongson-2K1000 reset support MIPS: Loongson64: DTS: Add pm block node for Loongson-2K1000 MIPS: Loongson64: Add Loongson-2K1000 reset platform driver MIPS: TXX9: Remove TX4939 SoC support MIPS: TXX9: Remove rbtx4939 board support arm64: tegra: Remove non existent Tegra194 reset dt-bindings: sound: tegra: Add minItems for resets ALSA: hda/tegra: Fix Tegra194 HDA reset failure ASoC: cs35l41: Create shared function for boost configuration ASoC: cs35l41: Create shared function for setting channels ASoC: cs35l41: Create shared function for errata patches ASoC: cs35l41: Move power initializations to reg_sequence ASoC: cs35l41: Move cs35l41_otp_unpack to shared code ASoC: cs35l41: Convert tables to shared source code ASoC: mediatek: mt8195: add playback support to PCM1_BE dai_link ASoC: mediatek: mt8195: correct pcmif BE dai control flow counter: remove old and now unused registration API counter: ti-eqep: Convert to new counter registration counter: stm32-lptimer-cnt: Convert to new counter registration counter: stm32-timer-cnt: Convert to new counter registration counter: microchip-tcb-capture: Convert to new counter registration counter: ftm-quaddec: Convert to new counter registration counter: intel-qep: Convert to new counter registration counter: interrupt-cnt: Convert to new counter registration counter: 104-quad-8: Convert to new counter registration counter: Update documentation for new counter registration functions counter: Provide alternative counter registration functions counter: stm32-timer-cnt: Convert to counter_priv() wrapper counter: stm32-lptimer-cnt: Convert to counter_priv() wrapper counter: ti-eqep: Convert to counter_priv() wrapper counter: ftm-quaddec: Convert to counter_priv() wrapper counter: intel-qep: Convert to counter_priv() wrapper counter: microchip-tcb-capture: Convert to counter_priv() wrapper counter: interrupt-cnt: Convert to counter_priv() wrapper counter: 104-quad-8: Convert to counter_priv() wrapper counter: Provide a wrapper to access device private data counter: microchip-tcb-capture: Drop unused platform_set_drvdata() counter: ftm-quaddec: Drop unused platform_set_drvdata() counter: Use container_of instead of drvdata to track counter_device mei: hbm: fix client dma reply status misc: lattice-ecp3-config: Fix task hung when firmware load failed ASoC: rt5682: Register wclk with its parent_hws instead of parent_data ASoC: mediatek: mt8195: update control for RT5682 series ASoC: samsung: idma: Check of ioremap return value ASoC: mediatek: use of_device_get_match_data() ASoC: cs4265: Fix part number ID error message cxl: use default_groups in kobj_type UIO: use default_groups in kobj_type iio: chemical: sunrise_co2: set val parameter only on success phy: cadence: Sierra: Add support for derived reference clock output dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration phy: cadence: Sierra: Add support for PHY multilink configurations phy: cadence: Sierra: Fix to get correct parent for mux clocks phy: cadence: Sierra: Update single link PCIe register configuration phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation phy: cadence: Sierra: Check cmn_ready assertion during PHY power on phy: cadence: Sierra: Add PHY PCS common register configurations phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation phy: cadence: Sierra: Add support to get SSC type from device tree dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names phy: cadence: Sierra: Prepare driver to add support for multilink configurations phy: cadence: Sierra: Use of_device_get_match_data() to get driver data phy: mediatek: Fix missing check in mtk_mipi_tx_probe mei: cleanup status before client dma setup call mei: add POWERING_DOWN into device state print habanalabs: support hard-reset scheduling during soft-reset habanalabs: add a lock to protect multiple reset variables habanalabs: refactor reset information variables habanalabs: handle skip multi-CS if handling not done habanalabs: add CPU-CP packet for engine core ASID cfg habanalabs: replace some -ENOTTY with -EINVAL habanalabs: fix comments according to kernel-doc habanalabs: fix endianness when reading cpld version habanalabs: change wait_for_interrupt implementation habanalabs: prevent wait if CS in multi-CS list completed habanalabs: modify cpu boot status error print habanalabs: clean MMU headers definitions habanalabs: expose soft reset sysfs nodes for inference ASIC habanalabs: sysfs support for two infineon versions habanalabs: keep control device alive during hard reset habanalabs: fix hwmon handling for legacy f/w habanalabs: add current PI value to cpu packets habanalabs: remove in_debug check in device open habanalabs: return correct clock throttling period habanalabs: wait again for multi-CS if no CS completed habanalabs: remove compute context pointer habanalabs: add helper to get compute context habanalabs: fix etr asid configuration habanalabs: save ctx inside encaps signal habanalabs: remove redundant check on ctx_fini habanalabs: free signal handle on failure habanalabs: add missing kernel-doc comments for hl_device fields habanalabs: pass reset flags to reset thread habanalabs: enable access to info ioctl during hard reset habanalabs: add SOB information to signal submission uAPI habanalabs: skip read fw errors if dynamic descriptor invalid habanalabs: handle events during soft-reset habanalabs: change misleading IRQ warning during reset habanalabs: add power information type to POWER_GET packet habanalabs: add more info ioctls support during reset habanalabs: fix race condition in multi CS completion habanalabs: move device boot warnings to the correct location habanalabs/gaudi: return EPERM on non hard-reset habanalabs: rename late init after reset function habanalabs: fix soft reset accounting habanalabs: Move frequency change thread to goya_late_init habanalabs: abort reset on invalid request habanalabs: fix possible deadlock in cache invl failure habanalabs: skip PLL freq fetch habanalabs: align debugfs documentation to alphabetical order habanalabs: prevent false heartbeat message habanalabs: add support for fetching historic errors habanalabs: handle device TPM boot error as warning habanalabs: debugfs support for larger I2C transactions habanalabs: make hdev creation code more readable habanalabs: add new opcodes for INFO IOCTL habanalabs: refactor wait-for-user-interrupt function habanalabs/gaudi: Fix collective wait bug habanalabs: expand clock throttling information uAPI habanalabs: change wait for interrupt timeout to 64 bit habanalabs: rename reset flags habanalabs: add dedicated message towards f/w to set power habanalabs: handle abort scenario for user interrupt habanalabs: don't clear previous f/w indications habanalabs: use variable poll interval for fw loading habanalabs: adding indication of boot fit loaded habanalabs: partly skip cache flush when in PMMU map flow habanalabs: add enum mmu_op_flags habanalabs: make last_mask an MMU property habanalabs: wrong VA size calculation habanalabs/gaudi: fix debugfs dma channel selection habanalabs: revise and document use of boot status flags habanalabs: print va_range in vm node debugfs habanalabs/gaudi: recover from CPU WD event habanalabs: modify wait for boot fit in dynamic FW load ALSA: hda/realtek: Use ALC285_FIXUP_HP_GPIO_LED on another HP laptop ALSA: hda/realtek: Add speaker fixup for some Yoga 15ITL5 devices ALSA: hda: Add new AlderLake-P variant PCI ID ALSA: hda: Add AlderLake-N PCI ID ALSA: hda/hdmi: Disable silent stream on GLK ALSA: hda: use swap() to make code cleaner kselftest: alsa: Validate values read from enumerations kselftest: alsa: Factor out check that values meet constraints ALSA: HDA: hdac_ext_stream: use consistent prefixes for variables ALSA/ASoC: hda: move/rename snd_hdac_ext_stop_streams to hdac_stream.c selftests/powerpc: Add a test of sigreturning to an unaligned address powerpc/64s: Use EMIT_WARN_ENTRY for SRR debug warnings powerpc/64s: Mask NIP before checking against SRR0 ASoC: amd: acp: Power on/off the speaker enable gpio pin based on DAPM callback. ASoC: remove unneeded variable ASoC: mediatek: Check for error clk pointer ASoC: mediatek: mt8195: release device_node after snd_soc_register_card ASoC: mediatek: mt8173: reduce log verbosity in probe() ASoC: mediatek: mt8183: fix device_node leak ASoC: mediatek: mt8173: fix device_node leak soundwire: intel: remove PDM support soundwire: intel: remove unnecessary init ASoC: Intel/SOF: use set_stream() instead of set_tdm_slots() for HDAudio ASoC/SoundWire: dai: expand 'stream' concept beyond SoundWire soundwire: intel: improve suspend flows ASoC/soundwire: intel: simplify callbacks for params/hw_free ASOC: SOF: Intel: use snd_soc_dai_get_widget() extcon: Deduplicate code in extcon_set_state_sync() extcon: usb-gpio: fix a non-kernel-doc comment phy: uniphier-usb3ss: fix unintended writing zeros to PHY register phy: phy-mtk-tphy: use new io helpers to access register phy: phy-mtk-xsphy: use new io helpers to access register phy: mediatek: add helpers to update bits of registers phy: phy-mtk-tphy: add support efuse setting dt-bindings: phy: mediatek: tphy: support software efuse load phy: qcom-qmp: Add SM8450 PCIe1 PHY support dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings iomap: Fix error handling in iomap_zero_iter() ASoC: msm8916-wcd-analog: Use separate outputs for HPH_L/HPH_R ASoC: qcom: common: Parse "pin-switches" and "widgets" from DT ASoC: dt-bindings: qcom: sm8250: Document "pin-switches" and "widgets" ASoC: core: Add snd_soc_of_parse_pin_switches() from simple-card-utils ASoC: mediatek: mt8192-mt6359: fix device_node leak dt-bindings: crypto: convert Qualcomm PRNG to yaml dt-bindings: msm: disp: remove bus from dpu bindings dt-binding: soc: qcom: convert Qualcomm Command DB documentation to yaml dt-binding: soc: qcom: convert rmtfs documentation to yaml ASoC: codec: tlv320adc3xxx: Fix missing clk_disable_unprepare() on error in adc3xxx_i2c_probe() ASoC: dt-bindings: aiu: spdif-dit: add missing sound-name-prefix property ASoC: dt-bindings: spdif-dit: add missing sound-name-prefix property ASoC: SOF: Intel: hda: Use DEBUG log level for optional prints ASoC: SOF: debug: Use DEBUG log level for optional prints ASoC: SOF: Add clarifying comments for sof_core_debug and DSP dump flags ASoC: SOF: Rename snd_sof_get_status() and add kernel log level parameter ASoC: SOF: dsp_arch_ops: add kernel log level parameter for oops and stack ASoC: SOF: ops: Always print DSP Panic message but use different message ASoc: SOF: core: Update the FW boot state transition diagram ASoC: SOF: pm: Force DSP off on suspend in BOOT_FAILED state also ASoC: SOF: Set SOF_FW_BOOT_FAILED in case we have failure during boot ASoC: SOF: ipc: Only allow sending of an IPC in SOF_FW_BOOT_COMPLETE state ASoC: SOF: Rename 'enum snd_sof_fw_state' to 'enum sof_fw_state' ASoC: SOF: Move the definition of enum snd_sof_fw_state to global header ASoC: SOF: Introduce new firmware state: SOF_FW_BOOT_READY_OK ASoC: SOF: Introduce new firmware state: SOF_FW_CRASHED ASoC: SOF: Add a 'message' parameter to snd_sof_dsp_dbg_dump() ASoC: SOF: Add 'non_recoverable' parameter to snd_sof_dsp_panic() ASoC: SOF: Use sof_debug_check_flag() instead of sof_core_debug directly ASoC: SOF: core: Add simple wrapper to check flags in sof_core_debug ASoC: SOF: Intel: hda-loader: Avoid re-defining the HDA_FW_BOOT_ATTEMPTS ASoC: SOF: ops: Use dev_warn() if the panic offsets differ dt-bindings:iio:adc: update the maintainer of vf610-adc MAINTAINERS: add imx7d/imx6sx/imx6ul/imx8qxp and vf610 adc maintainer Documentation:ABI:testing:admv1013: add ABI docs dt-bindings: iio: frequency: add admv1013 doc iio: frequency: admv1013: add support for ADMV1013 powerpc/perf: Fix spelling of "its" powerpc/32: Fix boot failure with GCC latent entropy plugin powerpc/code-patching: Replace patch_instruction() by ppc_inst_write() in selftests powerpc/code-patching: Move code patching selftests in its own file powerpc/code-patching: Move instr_is_branch_{i/b}form() in code-patching.h powerpc/code-patching: Move patch_exception() outside code-patching.c powerpc/code-patching: Use test_trampoline for prefixed patch test powerpc/code-patching: Fix patch_branch() return on out-of-range failure powerpc/code-patching: Reorganise do_patch_instruction() to ease error handling powerpc/code-patching: Fix unmap_patch_area() error handling powerpc/code-patching: Fix error handling in do_patch_instruction() powerpc/code-patching: Remove init_mem_is_free powerpc/code-patching: Remove pr_debug()/pr_devel() messages and fix check() powerpc/mm/book3s64/hash: Switch pre 2.06 tlbiel to .long powerpc/mm: Switch obsolete dssall to .long powerpc/64/asm: Do not reassign labels powerpc/64/asm: Inline BRANCH_TO_C000 powerpc: check for support for -Wa,-m{power4,any} powerpc/toc: Future proof kernel toc cuda/pmu: Make find_via_cuda/pmu init functions powerpc/512x: Add __init attribute to eligible functions powerpc/85xx: Add __init attribute to eligible functions powerpc/83xx: Add __init attribute to eligible functions powerpc/embedded6xx: Add __init attribute to eligible functions powerpc/44x: Add __init attribute to eligible functions powerpc/4xx: Add __init attribute to eligible functions powerpc/ps3: Add __init attribute to eligible functions powerpc/pseries: Add __init attribute to eligible functions powerpc/powernv: Add __init attribute to eligible functions powerpc/powermac: Add __init attribute to eligible functions powerpc/pasemi: Add __init attribute to eligible functions powerpc/chrp: Add __init attribute to eligible functions powerpc/cell: Add __init attribute to eligible functions powerpc/xmon: Add __init attribute to eligible functions powerpc/sysdev: Add __init attribute to eligible functions powerpc/perf: Add __init attribute to eligible functions powerpc/mm: Add __init attribute to eligible functions powerpc/lib: Add __init attribute to eligible functions powerpc/kernel: Add __init attribute to eligible functions phy: phy-rockchip-inno-usb2: add rk3568 support phy: phy-rockchip-inno-usb2: support muxed interrupts phy: phy-rockchip-inno-usb2: support standalone phy nodes phy: phy-rockchip-inno-usb2: support #address_cells = 2 dt-bindings: phy: phy-rockchip-inno-usb2: add rk3568 documentation scsi: mpi3mr: Bump driver version to 8.0.0.61.0 scsi: mpi3mr: Fixes around reply request queues scsi: mpi3mr: Enhanced Task Management Support Reply handling scsi: mpi3mr: Use TM response codes from MPI3 headers scsi: mpi3mr: Add io_uring interface support in I/O-polled mode scsi: mpi3mr: Print cable mngnt and temp threshold events scsi: mpi3mr: Support Prepare for Reset event scsi: mpi3mr: Add Event acknowledgment logic scsi: mpi3mr: Gracefully handle online FW update operation scsi: mpi3mr: Detect async reset that occurred in firmware scsi: mpi3mr: Add IOC reinit function scsi: mpi3mr: Handle offline FW activation in graceful manner scsi: mpi3mr: Code refactor of IOC init - part2 scsi: mpi3mr: Code refactor of IOC init - part1 scsi: mpi3mr: Fault IOC when internal command gets timeout scsi: mpi3mr: Display IOC firmware package version scsi: mpi3mr: Handle unaligned PLL in unmap cmnds scsi: mpi3mr: Increase internal cmnds timeout to 60s scsi: mpi3mr: Do access status validation before adding devices scsi: mpi3mr: Add support for PCIe Managed Switch SES device scsi: mpi3mr: Update MPI3 headers - part2 scsi: mpi3mr: Update MPI3 headers - part1 scsi: mpi3mr: Don't reset IOC if cmnds flush with reset status scsi: mpi3mr: Replace spin_lock() with spin_lock_irqsave() scsi: mpi3mr: Add debug APIs based on logging_level bits scsi: pmcraid: Don't use GFP_DMA in pmcraid_alloc_sglist() scsi: snic: Don't use GFP_DMA in snic_queue_report_tgt_req() scsi: myrs: Don't use GFP_DMA scsi: myrb: Don't use GFP_DMA in myrb_pdev_slave_alloc() scsi: initio: Don't use GFP_DMA in initio_probe_one() scsi: sr: Don't use GFP_DMA scsi: ch: Don't use GFP_DMA scsi: hisi_sas: Use autosuspend for the host controller scsi: libsas: Keep host active while processing events scsi: hisi_sas: Keep controller active between ISR of phyup and the event being processed scsi: libsas: Defer works of new phys during suspend scsi: libsas: Refactor sas_queue_deferred_work() scsi: libsas: Add flag SAS_HA_RESUMING scsi: libsas: Resume host while sending SMP I/Os scsi: hisi_sas: Add more logs for runtime suspend/resume scsi: libsas: Insert PORTE_BROADCAST_RCVD event for resuming host scsi: mvsas: Add spin_lock/unlock() to protect asd_sas_port->phy_list scsi: hisi_sas: Fix some issues related to asd_sas_port->phy_list scsi: libsas: Add spin_lock/unlock() to protect asd_sas_port->phy_list scsi: block: pm: Always set request queue runtime active in blk_post_runtime_resume() scsi: Revert "scsi: hisi_sas: Filter out new PHY up events during suspend" scsi: libsas: Don't always drain event workqueue for HA resume ASoC: codecs: ak4375: Change invert controls to a stereo switch gnss: usb: add support for Sierra Wireless XM1210 gnss: add USB support efi: apply memblock cap after memblock_add() of: fdt: Aggregate the processing of "linux,usable-memory-range" ASoC: meson: g12a: add missing sound-name-prefix property ASoC: meson: t9015: add missing sound-name-prefix property ASoC: dt-bindings: Use name-prefix schema dt-bindings: arm,cci-400: Drop the PL330 from example dt-bindings: arm: ux500: Document missing compatibles dt-bindings: power: reset: gpio-restart: Convert to json-schema ASoC: Add AK4375 support ASoC: dt-bindings: codecs: Add bindings for ak4375 ASoC: bcm: Use platform_get_irq() to get the interrupt ASoC: xlnx: Use platform_get_irq() to get the interrupt ASoC: amd: acp: Remove duplicate dependency in Kconfig ASoC: qdsp6: fix a use after free bug in open() ASoC: SOF: AMD: simplify return status handling ASoC: tegra-audio-rt5677: Correct example ASoC: amd: acp-config: Update sof_tplg_filename for SOF machines ASoC: amd: acp-config: Enable SOF audio for Google chrome boards. iio: adc: ti-adc081c: Partial revert of removal of ACPI IDs iio:addac:ad74413r: Fix uninitialized ret in a path that won't be hit. MAINTAINERS: Add maintainer for xilinx-ams dt-bindings: iio: adc: Add Xilinx AMS binding documentation iio: adc: Add Xilinx AMS driver device property: Add fwnode_iomap() iio:accel:kxcjk-1013: Mark struct __maybe_unused to avoid warning. iio:accel:bmc150: Mark structure __maybe_unused as only needed with for pm ops. iio:dummy: Drop set but unused variable len. iio:magn:ak8975: Suppress clang W=1 warning about pointer to enum conversion. iio:imu:inv_mpu6050: Suppress clang W=1 warning about pointer to enum conversion. iio:imu:inv_icm42600: Suppress clang W=1 warning about pointer to enum conversion. iio:dac:mcp4725: Suppress clang W=1 warning about pointer to enum conversion. iio:amplifiers:hmc425a: Suppress clang W=1 warning about pointer to enum conversion. iio:adc:ti-ads1015: Suppress clang W=1 warning about pointer to enum conversion. iio:adc:rcar: Suppress clang W=1 warning about pointer to enum conversion. iio:adc:ina2xx-adc: Suppress clang W=1 warning about pointer to enum conversion. MIPS: generic: enable SMP on SMVP systems MIPS: only register MT SMP ops if MT is supported MIPS: Octeon: Fix build errors using clang w1: w1_therm: use swap() to make code cleaner counter: 104-quad-8: Fix persistent enabled events bug counter: ti-eqep: Use container_of instead of struct counter_device::priv counter: Add the necessary colons and indents to the comments of counter_compi dt-bindings: nvmem: Add missing 'reg' property nvmem: mtk-efuse: support minimum one byte access stride and granularity dt-bindings: nvmem: mediatek: add support for mt8195 dt-bindings: nvmem: mediatek: add support bits property drivers/misc/ocxl: remove redundant rc variable misc: vmw_vmci: Switch to kvfree_rcu() API paride: fix up build warning on mips platforms rapidio: remove not used code about RIO_VID_TUNDRA rapidio: remove not used macro definition in rio_ids.h selftests/powerpc: Add a test of sigreturning to the kernel powerpc/dts: Remove "spidev" nodes firmware: qemu_fw_cfg: remove sysfs entries explicitly firmware: qemu_fw_cfg: fix sysfs information leak firmware: qemu_fw_cfg: fix kobject leak in probe error path firmware: qemu_fw_cfg: fix NULL-pointer deref on duplicate entries applicom: unneed to initialise statics to 0 uacce: use sysfs_emit instead of sprintf greybus: es2: fix typo in a comment firmware: Update Kconfig help text for Google firmware binder: use proper cacheflush header file clk: qcom: turingcc-qcs404: explicitly include clk-provider.h clk: qcom: q6sstop-qcs404: explicitly include clk-provider.h clk: qcom: mmcc-apq8084: explicitly include clk-provider.h clk: qcom: lpasscc-sdm845: explicitly include clk-provider.h clk: qcom: lpasscc-sc7280: explicitly include clk-provider.h clk: qcom: gcc-sm6350: explicitly include clk-provider.h clk: qcom: gcc-msm8994: explicitly include clk-provider.h clk: qcom: gcc-sm8350: explicitly include clk-provider.h ASoC: mediatek: mt8195-mt6359: reduce log verbosity in probe() iommu/iova: Temporarily include dma-mapping.h from iova.h ASoC: codec: tlv320adc3xxx: New codec driver ASoC: tlv320adc3xxx: New codec bindings ASoC: sunxi: Use dev_err_probe() helper ASoC: stm: Use dev_err_probe() helper ASoC: samsung: Use dev_err_probe() helper ASoC: rockchip: Use dev_err_probe() helper ASoC: qcom: Use dev_err_probe() helper ASoC: mxs: Use dev_err_probe() helper ASoC: meson: Use dev_err_probe() helper ASoC: img: Use dev_err_probe() helper ASoC: generic: Use dev_err_probe() helper ASoC: fsl: Use dev_err_probe() helper ASoC: ti: Use dev_err_probe() helper ASoC: ateml: Use dev_err_probe() helper ASoC: codecs: tlv320aic31xx: Use dev_err_probe() helper ASoC: codecs: ssm2305: Use dev_err_probe() helper ASoC: codecs: simple-mux: Use dev_err_probe() helper ASoC: codecs: simple-amplifier: Use dev_err_probe() helper ASoC: codecs: sgtl5000: Use dev_err_probe() helper ASoC: codecs: pcm3168a: Use dev_err_probe() helper ASoC: codecs: max9860: Use dev_err_probe() helper ASoC: codecs: max9759: Use dev_err_probe() helper ASoC: codecs: es7241: Use dev_err_probe() helper ASoC: codecs: ak4118: Use dev_err_probe() helper ASoC: mediatek: mt8195: correct default value dt-bindings: timer: Add Mstar MSC313e timer devicetree bindings documentation clocksource/drivers/msc313e: Add support for ssd20xd-based platforms clocksource/drivers: Add MStar MSC313e timer support irqchip/renesas-intc-irqpin: Use platform_get_irq_optional() to get the interrupt irqchip/renesas-irqc: Use platform_get_irq_optional() to get the interrupt iommu: Move flush queue data into iommu_dma_cookie iommu/iova: Move flush queue code to iommu-dma iommu/iova: Consolidate flush queue code iommu/vt-d: Use put_pages_list iommu/amd: Use put_pages_list iommu/amd: Simplify pagetable freeing iommu/iova: Squash flush_cb abstraction iommu/iova: Squash entry_dtor abstraction iommu/iova: Fix race between FQ timeout and teardown iommu/amd: Fix typo in *glues … together* in comment ocxl: remove redundant rc variable powerpc/64s/radix: Fix huge vmap false positive powerpc: use swap() to make code cleaner powerpc/mpic: Use bitmap_zalloc() when applicable clk: samsung: Add initial Exynos7885 clock driver clk: samsung: clk-pll: Add support for pll1417x clk: samsung: Make exynos850_register_cmu shared dt-bindings: clock: Document Exynos7885 CMU bindings dt-bindings: clock: Add bindings definitions for Exynos7885 CMU clk: samsung: exynos850: Add missing sysreg clocks dt-bindings: clock: Add bindings for Exynos850 sysreg clocks PCI/MSI: Unbreak pci_irq_get_affinity() ACPI: NFIT: Import GUID before use dax: remove the copy_from_iter and copy_to_iter methods dax: remove the DAXDEV_F_SYNC flag dax: simplify dax_synchronous and set_dax_synchronous uio: remove copy_from_iter_flushcache() and copy_mc_to_iter() phy: qcom-qmp: Add SM8450 PCIe0 PHY support dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings dt-bindings: i2c: i2c-mux-gpio: Convert to json-schema dt-bindings: i2c: i2c-mux-pinctrl: Convert to json-schema dt-bindings: i2c: tegra: Convert to json-schema dt-bindings: interrupt-controller: Merge BCM3380 with BCM7120 dt-bindings: interrupt-controller: Convert BCM7120 L2 to YAML ASoC: sh: rz-ssi: Check return value of pm_runtime_resume_and_get() ASoC: Intel: catpt: Streamline locals declaration for PCM-functions ASoC: Intel: catpt: Reduce size of catpt_component_open() ASoC: Intel: catpt: Test dmaengine_submit() result before moving on spmi: spmi-pmic-arb: fix irq_set_type race condition spmi: mediatek: Add support for MT8195 spmi: mediatek: Add support for MT6873/8192 dt-bindings: spmi: document binding for the Mediatek SPMI controller dt-bindings: spmi: remove the constraint of reg property spmi: pmic-arb: Add sid and address to error messages bus: mhi: pci_generic: Introduce Sierra EM919X support bus: mhi: core: Use correctly sized arguments for bit field bus: mhi: core: Add an API for auto queueing buffers for DL channel bus: mhi: core: Fix race while handling SYS_ERR at power up bus: mhi: core: Fix reading wake_capable channel configuration bus: mhi: pci_generic: Simplify code and axe the use of a deprecated API bus: mhi: core: Minor style and comment fixes bus: mhi: core: Use macros for execution environment features bus: mhi: pci_generic: Graceful shutdown on freeze bus: mhi: pci_generic: Add new device ID support for T99W175 dt-bindings: usb: Convert BDC to YAML dt-bindings: bus: Convert GISB arbiter to YAML dt-bindings: ata: Convert Broadcom SATA to YAML ASoC: tegra20: i2s: Filter out unsupported rates ASoC: tegra20: spdif: Filter out unsupported rates ASoC: tegra20: spdif: Support system suspend ASoC: tegra20: spdif: Reset hardware ASoC: tegra20: spdif: Use more resource-managed helpers ASoC: tegra20: spdif: Improve driver's code ASoC: tegra20: spdif: Support device-tree ASoC: tegra20: spdif: Set FIFO trigger level ASoC: dt-bindings: tegra20-i2s: Document new nvidia,fixed-parent-rate property ASoC: dt-bindings: tegra20-i2s: Convert to schema ASoC: dt-bindings: Add binding for Tegra20 S/PDIF ASoC: SOF: Kconfig: Make the SOF_DEVELOPER_SUPPORT depend on SND_SOC_SOF ASoC: dt-bindings: audio-graph-port: enable both flag/phandle for bitclock/frame-master ipc: debug: Add shared memory heap to memory scan ASoC: SOF: ipc: Add null pointer check for substream->runtime ASoC: SOF: avoid casting "const" attribute away ASoC: SOF: Intel: hda: remove support for RESUME in platform trigger ASoC: SOF: Intel: hda: remove support for RESUME trigger ASoC: SOF: pcm: remove support for RESUME trigger iommu/vt-d: Remove unused dma_to_mm_pfn function iommu/vt-d: Drop duplicate check in dma_pte_free_pagetable() iommu/vt-d: Use bitmap_zalloc() when applicable iommu/amd: Remove useless irq affinity notifier iommu/amd: X2apic mode: mask/unmask interrupts on suspend/resume iommu/amd: X2apic mode: setup the INTX registers on mask/unmask iommu/amd: X2apic mode: re-enable after resume iommu/amd: Restore GA log/tail pointer on host resume iommu/iova: Move fast alloc size roundup into alloc_iova_fast() iommu/virtio: Fix typo in a comment iommu/vt-d: Remove unused macros iommu/vt-d: Use correctly sized arguments for bit field dmaengine: remove slave_id config field dmaengine: xilinx_dpdma: stop using slave_id field dmaengine: qcom-adm: stop abusing slave_id config dmaengine: sprd: stop referencing config->slave_id dmaengine: pxa/mmp: stop referencing config->slave_id dmaengine: shdma: remove legacy slave_id parsing mmc: bcm2835: stop setting chan_config->slave_id spi: pic32: stop setting dma_config->slave_id ASoC: dai_dma: remove slave_id field dmaengine: tegra20-apb: stop checking config->slave_id ASoC: tegra20-spdif: stop setting slave_id scsi: libsas: Decode SAM status and host byte codes scsi: hisi_sas: Fix phyup timeout on FPGA scsi: hisi_sas: Prevent parallel FLR and controller reset scsi: hisi_sas: Prevent parallel controller reset and control phy command scsi: hisi_sas: Factor out task prep and delivery code scsi: hisi_sas: Pass abort structure for internal abort scsi: hisi_sas: Make internal abort have no task proto scsi: hisi_sas: Start delivery hisi_sas_task_exec() directly scsi: efct: Don't pass GFP_DMA to dma_alloc_coherent() scsi: ufs: core: Fix deadlock issue in ufshcd_wait_for_doorbell_clr() scsi: qla2xxx: Synchronize rport dev_loss_tmo setting selftest/lkdtm: Skip stack-entropy test if lkdtm is not available lkdtm: Fix content of section containing lkdtm_rodata_do_nothing() lkdtm: avoid printk() in recursive_loop() lkdtm: Note that lkdtm_kernel_info should be removed in the future of/fdt: Rework early_init_dt_scan_memory() to call directly of/fdt: Rework early_init_dt_scan_root() to call directly of/fdt: Rework early_init_dt_scan_chosen() to call directly i2c: aspeed: Remove unused includes dt-bindings: i2c: aspeed: Drop stray '#interrupt-cells' i2c: sh_mobile: update to new DMAENGINE API when terminating i2c: rcar: update to new DMAENGINE API when terminating genirq/msi: Convert storage to xarray genirq/msi: Simplify sysfs handling genirq/msi: Add abuse prevention comment to msi header genirq/msi: Mop up old interfaces genirq/msi: Convert to new functions genirq/msi: Make interrupt allocation less convoluted platform-msi: Simplify platform device MSI code platform-msi: Let core code handle MSI descriptors bus: fsl-mc-msi: Simplify MSI descriptor handling soc: ti: ti_sci_inta_msi: Remove ti_sci_inta_msi_domain_free_irqs() soc: ti: ti_sci_inta_msi: Rework MSI descriptor allocation NTB/msi: Convert to msi_on_each_desc() PCI: hv: Rework MSI handling powerpc/mpic_u3msi: Use msi_for_each-desc() powerpc/fsl_msi: Use msi_for_each_desc() powerpc/pasemi/msi: Convert to msi_on_each_dec() powerpc/cell/axon_msi: Convert to msi_on_each_desc() powerpc/4xx/hsta: Rework MSI handling s390/pci: Rework MSI descriptor walk xen/pcifront: Rework MSI handling x86/pci/xen: Use msi_for_each_desc() PCI/MSI: Use msi_on_each_desc() PCI/MSI: Let core code free MSI descriptors PCI/MSI: Use msi_add_msi_desc() PCI/MSI: Protect MSI operations genirq/msi: Provide domain flags to allocate/free MSI descriptors automatically genirq/msi: Provide msi_alloc_msi_desc() and a simple allocator genirq/msi: Provide a set of advanced MSI accessors and iterators genirq/msi: Provide msi_domain_alloc/free_irqs_descs_locked() genirq/msi: Add mutex for MSI list protection genirq/msi: Move descriptor list to struct msi_device_data i2c: exynos5: Fix getting the optional clock i2c: designware-pci: Convert to use dev_err_probe() i2c: designware-pci: use __maybe_unused for PM functions i2c: designware-pci: Group MODULE_*() macros dmaengine: qcom_hidma: Cleanup MSI handling soc: ti: ti_sci_inta_msi: Get rid of ti_sci_inta_msi_get_virq() bus: fsl-mc: fsl-mc-allocator: Rework MSI handling mailbox: bcm-flexrm-mailbox: Rework MSI interrupt handling iommu/arm-smmu-v3: Use msi_get_virq() perf/smmuv3: Use msi_get_virq() dmaengine: mv_xor_v2: Get rid of msi_desc abuse PCI/MSI: Simplify pci_irq_get_affinity() PCI/MSI: Use msi_get_virq() in pci_get_vector() genirq/msi: Provide interface to retrieve Linux interrupt number powerpc/pseries/msi: Let core code check for contiguous entries PCI/MSI: Provide MSI_FLAG_MSIX_CONTIGUOUS PCI/MSI: Use msi_desc::msi_index soc: ti: ti_sci_inta_msi: Use msi_desc::msi_index bus: fsl-mc-msi: Use msi_desc::msi_index platform-msi: Use msi_desc::msi_index genirq/msi: Consolidate MSI descriptor data platform-msi: Store platform private data pointer in msi_device_data platform-msi: Rename functions and clarify comments genirq/msi: Remove the original sysfs interfaces platform-msi: Let the core code handle sysfs groups PCI/MSI: Let the irq code handle sysfs groups genirq/msi: Provide msi_device_populate/destroy_sysfs() soc: ti: ti_sci_inta_msi: Allocate MSI device data on first use bus: fsl-mc-msi: Allocate MSI device data on first use platform-msi: Allocate MSI device data on first use PCI/MSI: Allocate MSI device data on first use PCI/MSI: Decouple MSI[-X] disable from pcim_release() device: Add device:: Msi_data pointer and struct msi_device_data device: Move MSI related data into a struct powerpc/pseries/msi: Use PCI device properties powerpc/cell/axon_msi: Use PCI device property genirq/msi: Use PCI device property x86/apic/msi: Use PCI device MSI property x86/pci/XEN: Use PCI device property PCI/MSI: Set pci_dev::msi[x]_enabled early i2c: designware-pci: Add a note about struct dw_scl_sda_cfg usage i2c: designware-pci: Fix to change data types of hcnt and lcnt parameters i2c: designware: Do not complete i2c read without RX_FULL interrupt clk: qcom: Add MSM8976/56 Global Clock Controller (GCC) driver dt-bindings: clk: qcom: Document MSM8976 Global Clock Controller clk: qcom: Add clock driver for SM8450 clk: qcom: Add SDX65 GCC support clk: qcom: Add LUCID_EVO PLL type for SDX65 iio:accel:bma180: Suppress clang W=1 warning about pointer to enum conversion. drivers:iio:dac: Add AD3552R driver support dt-bindings: iio: dac: Add adi,ad3552r.yaml iio:filter:admv8818: Add sysfs ABI documentation dt-bindings:iio:filter: add admv8818 doc iio:filter:admv8818: add support for ADMV8818 iio: add filter subfolder iio: vz89x: Remove unnecessary cast iio: in2xx-adc: Remove unnecessary cast iio: as3935: Remove unnecessary cast irqchip/gic-v4: Disable redistributors' view of the VPE table at boot time irqchip/ingenic-tcu: Use correctly sized arguments for bit field irqchip/gic-v2m: Add const to of_device_id irqchip/imx-gpcv2: Mark imx_gpcv2_instance with __ro_after_init MIPS: OCTEON: add put_device() after of_find_device_by_node() MIPS: BCM47XX: Replace strlcpy with strscpy mips: fix Kconfig reference to PHYS_ADDR_T_64BIT mips: txx9: remove left-over for removed TXX9_ACLC configs mips: alchemy: remove historic comment on gpio build constraints mips: remove obsolete selection of CPU_HAS_LOAD_STORE_LR mips: kgdb: adjust the comment to the actual ifdef condition mips: dec: provide the correctly capitalized config CPU_R4X00 in init error message mips: drop selecting non-existing config NR_CPUS_DEFAULT_2 mips: add SYS_HAS_CPU_MIPS64_R5 config for MIPS Release 5 support MIPS: drop selected EARLY_PRINTK configs for MACH_REALTEK_RTL irqchip/spear-shirq: Add support for IRQ 0..6 irqchip/gic-v3-its: Limit memreserve cpuhp state lifetime irqchip/gic-v3-its: Postpone LPI pending table freeing and memreserve irqchip/gic-v3-its: Give the percpu rdist struct its own flags field iio: stmpe-adc: Use correctly sized arguments for bit field iio:adc:ti-ads8688:: remove redundant ret variable iio: addac: ad74413r: fix off by one in ad74413r_parse_channel_config() iio: adc: ad7606: Fix syntax errors in comments iio: event_monitor: Flush output on event iio: iio_device_alloc(): Remove unnecessary self drvdata selftests/powerpc: skip tests for unavailable mitigations. powerpc/pseries: use slab context cpumask allocation in CPU hotplug init powerpc/64s/interrupt: avoid saving CFAR in some asynchronous interrupts powerpc/64/interrupt: reduce expensive debug tests powerpc/64s/interrupt: Don't enable MSR[EE] in irq handlers unless perf is in use powerpc/64s/perf: add power_pmu_wants_prompt_pmi to say whether perf wants PMIs to be soft-NMI powerpc/64s/interrupt: handle MSR EE and RI in interrupt entry wrapper powerpc/64/interrupt: make normal synchronous interrupts enable MSR[EE] if possible powerpc/pseries/vas: Don't print an error when VAS is unavailable powerpc/perf: Add data source encodings for power10 platform powerpc/perf: Add encodings to represent data based on newer composite PERF_MEM_LVLNUM* fields perf: Add new macros for mem_hops field clk: stm32mp1: remove redundant assignment to pointer data clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after system enter shell phy: qcom-qmp: Add SM8450 USB QMP PHYs dt-bindings: phy: qcom,qmp: Add SM8450 USB3 PHY dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for SM8450 clk: Introduce clk-tps68470 driver of: unittest: 64 bit dma address test requires arch support of: unittest: fix warning on PowerPC frame size warning dt-bindings: input: pwm-vibrator: Convert txt bindings to yaml ASoC: AMD: fix depend/select mistake on SND_AMD_ACP_CONFIG ASoC: nvidia,tegra-audio: Convert multiple txt bindings to yaml ASoC: SOF: topology: read back control data from DSP ASoC: SOF: Drop ctrl_type parameter for snd_sof_ipc_set_get_comp_data() ASoC: SOF: control: Do not handle control notification with component type ASoC: SOF: sof-audio: Drop the `cmd` member from struct snd_sof_control ASoC: SOF: Drop ctrl_cmd parameter for snd_sof_ipc_set_get_comp_data() ASoC: SOF: topology: Set control_data->cmd alongside scontrol->cmd ASoC: SOF: Drop ipc_cmd parameter for snd_sof_ipc_set_get_comp_data() ASoC: SOF: ipc: Rename send parameter in snd_sof_ipc_set_get_comp_data() clk: tegra: Support runtime PM and power domain clk: tegra: Make vde a child of pll_p on tegra114 phy: freescale: pcie: explicitly add bitfield.h x86/xen: Use correct #ifdef guard for xen_initdom_restore_msi() ASoC: rt5663: Handle device_property_read_u32_array error codes ASoC: SOF: OF: Avoid reverse module dependency Revert "iommu/arm-smmu-v3: Decrease the queue size of evtq and priq" interconnect: qcom: Add QCM2290 driver support dt-bindings: interconnect: Add Qualcomm QCM2290 NoC support interconnect: icc-rpm: Support child NoC device probe interconnect: icc-rpm: Add QNOC type QoS support interconnect: icc-rpm: Define ICC device type IB/mthca: Use memset_startat() for clearing mpt_entry iw_cxgb4: Use memset_startat() for cpl_t5_pass_accept_rpl RDMA/mlx5: Use memset_after() to zero struct mlx5_ib_mr RDMA/cma: Let cma_resolve_ib_dev() continue search even after empty entry RDMA/core: Let ib_find_gid() continue search even after empty entry RDMA/core: Modify rdma_query_gid() to return accurate error codes RDMA/hns: Support direct wqe of userspace dt-bindings: PCI: designware: Fix 'unevaluatedProperties' warnings dt-bindings: PCI: cdns-ep: Fix 'unevaluatedProperties' warnings dt-bindings: PCI: Fix 'unevaluatedProperties' warnings dt-bindings: memory-controllers: ti,gpmc: Drop incorrect unevaluatedProperties dt-bindings: usb: Add missing properties used in examples dt-bindings: watchdog: atmel: Add missing 'interrupts' property dt-bindings: watchdog: ti,rti-wdt: Fix assigned-clock-parents dt-bindings: i2c: aspeed: Drop stray '#interrupt-cells' interconnect: qcom: Add SM8450 interconnect provider driver dt-bindings: interconnect: Add Qualcomm SM8450 DT bindings dt-bindings: perf: Add compatible for Arm DSU-110 dt-bindings: perf: Convert Arm DSU to schema dt-bindings: gpu: mali-bifrost: Document RZ/G2L support dt-bindings: thermal: Convert Broadcom TMON to YAML dt-bindings: rng: Convert iProc RNG200 to YAML dt-bindings: interrupt-controller: Convert Broadcom STB L2 to YAML dt-binding: interrupt-controller: Convert BCM7038 L1 intc to YAML dt-bindings: gpio: Convert Broadcom STB GPIO to YAML dt-bindings: rtc: Convert Broadcom STB waketimer to YAML dt-bindings: pwm: Convert BCM7038 PWM binding to YAML dt-bindings: reset: Convert Broadcom STB reset to YAML dt-bindings: pci: Convert iProc PCIe to YAML dt-bindings: phy: Convert Cygnus PCIe PHY to YAML ASoC: qdsp6: Fix an IS_ERR() vs NULL bug ASoC: qcom: Distinguish headset codec by codec_dai->name ASoC: soc-pcm: fix BE handling of PAUSE_RELEASE ASoC: soc-pcm: test refcount before triggering ASoC: soc-pcm: serialize BE triggers ASoC: soc-pcm: Fix and cleanup DPCM locking ASoC: soc-pcm: align BE 'atomicity' with that of the FE ASoC: soc-pcm: use GFP_ATOMIC for dpcm structure iommu/io-pgtable-arm-v7s: Add error handle for page table allocation failure iommu/arm-smmu-v3: Constify arm_smmu_mmu_notifier_ops iommu: arm-smmu-impl: Add SM8450 qcom iommu implementation dt-bindings: arm-smmu: Add compatible for SM8450 SoC iommu/arm-smmu-qcom: Fix TTBR0 read dt-bindings: arm-smmu: Add compatible for the SDX55 SoC phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver dt-bindings: phy: Add imx8 pcie phy driver support dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phy ASoC: mediatek: assign correct type to argument ASoC: SOF: sof-probes: Constify sof_probe_compr_ops ASoC: SOF: Remove pm_runtime_put_autosuspend() for SOF OF device KVM: PPC: Book3S HV P9: Use kvm_arch_vcpu_get_wait() to get rcuwait object Documentation/filesystem/dax: DAX on virtiofs fuse: mark inode DONT_CACHE when per inode DAX hint changes fuse: negotiate per inode DAX in FUSE_INIT fuse: enable per inode DAX fuse: support per inode DAX in fuse protocol fuse: make DAX mount option a tri-state fuse: add fuse_should_enable_dax() helper clocksource/drivers/pistachio: Fix -Wunused-but-set-variable warning clocksource/drivers/timer-imx-sysctr: Set cpumask to cpu_possible_mask phy: rockchip-inno-usb2: remove redundant assignment to variable delay mips: ralink: add missing of_node_put() call in ill_acc_of_setup() MIPS: fix typo in a comment MIPS: lantiq: Fix typo in a comment MIPS: Fix typo in a comment MIPS: Makefile: Remove "ifdef need-compiler" for Kbuild.platforms MIPS: SGI-IP22: Remove unnecessary check of GCC option phy: lan966x: Remove set_speed function phy: ti: Use IS_ERR_OR_NULL() to clean code dt-bindings: phy: qcom,qusb2: Add SM6350 compatible phy: tegra: xusb: Fix return value of tegra_xusb_find_port_node function scsi: hpsa: Remove an unused variable in hpsa_update_scsi_devices() scsi: lpfc: Use struct_group to isolate cast to larger object scsi: lpfc: Use struct_group() to initialize struct lpfc_cgn_info ASoC: qcom: apq8016_sbc: Allow routing audio through QDSP6 ASoC: dt-bindings: qcom: Document qcom,msm8916-qdsp6-sndcard compatible ASoC: dt-bindings: qcom: apq8016-sbc: Move to qcom,sm8250 DT schema ASoC: dt-bindings: qcom: sm8250: Document "aux-devs" ASoC: dt-bindings: qcom: sm8250: Drop redundant MultiMedia routes ASoC: SOF: Intel: add comment on JasperLake support ASoC: SOF: Intel: hda-dai: remove unused fields ASoC: SOF: Intel: hda: add quirks for HDAudio DMA position information ASoC: SOF: hda-stream: only enable DPIB if needed ASoC: SOF: Intel: hda-ctrl: apply symmetry for DPIB ASoC: SOF: Intel: hda-stream: limit PROCEN workaround ASoC: SOF: Intel: ICL: move ICL-specific ops to icl.c coresight: core: Fix typo in a comment ALSA: gus: Fix memory leaks at memory allocator error paths ALSA: gus: Fix erroneous memory allocation eeprom: at24: Add support for 24c1025 EEPROM dt-bindings: at24: add at24c1025 ALSA: sound/isa/gus: check the return value of kstrdup() ALSA: uapi: use C90 comment style instead of C99 style ALSA: pcm: comment about relation between msbits hw parameter and [S|U]32 formats dt-bindings: iio: dac: adi,ad5755: drop unrelated included. iio:adc/dac:Kconfig: Update to drop OF dependencies. iio:adc:ti-ads124s08: Drop dependency on OF. iio:adc:envelope-detector: Switch from of headers to mod_devicetable.h iio:adc:ti-adc12138: Switch to generic firmware properties and drop of_match_ptr iio:adc:mcp3911: Switch to generic firmware properties. iio:adc:max9611: Switch to generic firmware properties. iio:light:cm3605: Switch to generic firmware properties. iio:pot:mcp41010: Switch to generic firmware properties. iio:dac:lpc18xx_dac: Swap from of* to mod_devicetable.h iio:dac:dpot-dac: Swap of.h for mod_devicetable.h iio:dac:ad5758: Drop unused of specific headers. iio:dac:ad5755: Switch to generic firmware properties and drop pdata iio: trigger: Fix a scheduling whilst atomic issue seen on tsc2046 iio: addac: add AD74413R driver dt-bindings: iio: add AD74413R iio: add addac subdirectory MAINTAINERS: Update i.MX 8QXP ADC info dt-bindings:iio:dac: add ad7293 doc kselftest: alsa: Use private alsa-lib configuration in mixer test kselftest: alsa: optimization for SNDRV_CTL_ELEM_ACCESS_VOLATILE kselftest: alsa: Add simplistic test for ALSA mixer controls kselftest ALSA: sparc: no need to initialise statics to 0 objtool: Remove .fixup handling x86: Remove .fixup section x86/word-at-a-time: Remove .fixup usage x86/usercopy: Remove .fixup usage x86/usercopy_32: Simplify __copy_user_intel_nocache() x86/sgx: Remove .fixup usage x86/checksum_32: Remove .fixup usage x86/vmx: Remove .fixup usage x86/kvm: Remove .fixup usage x86/segment: Remove .fixup usage x86/fpu: Remove .fixup usage x86/xen: Remove .fixup usage x86/uaccess: Remove .fixup usage x86/futex: Remove .fixup usage x86/msr: Remove .fixup usage x86/extable: Extend extable functionality x86/entry_32: Remove .fixup usage x86/entry_64: Remove .fixup usage x86/copy_mc_64: Remove .fixup usage x86/copy_user_64: Remove .fixup usage x86/mmx_32: Remove X86_USE_3DNOW bitfield.h: Fix "type of reg too small for mask" test clk: Emit a stern warning with writable debugfs enabled i2c: tegra: use i2c_timings for bus clock freq net/mlx4: Use irq_update_affinity_hint() net/mlx5: Use irq_set_affinity_and_hint() hinic: Use irq_set_affinity_and_hint() scsi: lpfc: Use irq_set_affinity() mailbox: Use irq_update_affinity_hint() ixgbe: Use irq_update_affinity_hint() be2net: Use irq_update_affinity_hint() enic: Use irq_update_affinity_hint() RDMA/irdma: Use irq_update_affinity_hint() scsi: mpt3sas: Use irq_set_affinity_and_hint() scsi: megaraid_sas: Use irq_set_affinity_and_hint() i40e: Use irq_update_affinity_hint() iavf: Use irq_update_affinity_hint() genirq: Provide new interfaces for affinity hints dt-bindings: at24: Rework special case compatible handling fpga: region: fix kernel-doc clk: Add write operation for clk_parent debugfs node clk: __clk_core_init() never takes NULL clk: clk_core_get() can also return NULL clk/ti/adpll: Make const pointer error a static const array MIPS: DTS: Ingenic: adjust register size to available registers MIPS: defconfig: CI20: configure for DRM_DW_HDMI_JZ4780 MIPS: DTS: CI20: Add DT nodes for HDMI setup MIPS: DTS: jz4780: Account for Synopsys HDMI driver and LCD controllers i2c: i801: Don't clear status flags twice in interrupt mode i2c: i801: Don't read back cleared status in i801_check_pre() i2c: exynos5: Mention Exynos850 and ExynosAutoV9 in Kconfig i2c: exynos5: Add bus clock support clocksource/drivers/imx-sysctr: Mark two variable with __ro_after_init clocksource/drivers/renesas,ostm: Make RENESAS_OSTM symbol visible clocksource/drivers/renesas-ostm: Add RZ/G2L OSTM support dt-bindings: timer: renesas: ostm: Document Renesas RZ/G2L OSTM x86: Add straight-line-speculation mitigation ASoC: test-component: fix null pointer dereference. ASoC: dt-bindings: tegra: Document interconnects property phy: qcom: use struct_size instead of sizeof powerpc/powermac: Add additional missing lockdep_register_key() powerpc/fadump: Fix inaccurate CPU state info in vmcore generated with panic powerpc: handle kdump appropriately with crash_kexec_post_notifiers option selftests/powerpc/spectre_v2: Return skip code when miss_percent is high powerpc/cell: Fix clang -Wimplicit-fallthrough warning macintosh: Add const to of_device_id powerpc/inst: Optimise copy_inst_from_kernel_nofault() powerpc/inst: Move ppc_inst_t definition in asm/reg.h powerpc/inst: Define ppc_inst_t as u32 on PPC32 powerpc/inst: Define ppc_inst_t powerpc/inst: Refactor ___get_user_instr() powerpc/32s: Allocate one 256k IBAT instead of two consecutives 128k IBATs powerpc: Remove CONFIG_PPC_HAVE_KUAP and CONFIG_PPC_HAVE_KUEP powerpc/kuap: Wire-up KUAP on book3e/64 powerpc/kuap: Wire-up KUAP on 85xx in 32 bits mode. powerpc/kuap: Wire-up KUAP on 40x powerpc/kuap: Wire-up KUAP on 44x powerpc: Add KUAP support for BOOKE and 40x powerpc/kuap: Make PPC_KUAP_DEBUG depend on PPC_KUAP only powerpc/kuap: Prepare for supporting KUAP on BOOK3E/64 powerpc/config: Add CONFIG_BOOKE_OR_40x powerpc/nohash: Move setup_kuap out of 8xx.c powerpc/kuap: Add kuap_lock() powerpc/kuap: Remove __kuap_assert_locked() powerpc/kuap: Check KUAP activation in generic functions powerpc/kuap: Add a generic intermediate layer powerpc/kuep: Remove 'nosmep' boot time parameter except for book3s/64 powerpc/32s: Save content of sr0 to avoid 'mfsr' powerpc/32s: Do kuep_lock() and kuep_unlock() in assembly powerpc/32s: Remove capability to disable KUEP at boottime powerpc/book3e: Activate KUEP at all time powerpc/44x: Activate KUEP at all time powerpc/8xx: Activate KUEP at all time Revert "powerpc: Inline setup_kup()" powerpc/40x: Map 32Mbytes of memory at startup powerpc/microwatt: add POWER9_CPU, clear PPC_64S_HASH_MMU powerpc/64s: Move hash MMU support code under CONFIG_PPC_64S_HASH_MMU powerpc/64s: Make hash MMU support configurable powerpc/64s: Always define arch unmapped area calls powerpc/64s: Fix radix MMU when MMU_FTR_HPTE_TABLE is clear powerpc/64e: remove mmu_linear_psize clocksource/drivers/exynos_mct: Fix silly typo resulting in checkpatch warning PCI/MSI: Move descriptor counting on allocation fail to the legacy code genirq/msi: Handle PCI/MSI allocation fail in core code PCI/MSI: Make pci_msi_domain_check_cap() static PCI/MSI: Move msi_lock to struct pci_dev PCI/MSI: Sanitize MSI-X table map handling PCI/MSI: Split out irqdomain code PCI/MSI: Split out !IRQDOMAIN code PCI/MSI: Split out CONFIG_PCI_MSI independent part PCI/MSI: Move code into a separate directory PCI/MSI: Make msix_update_entries() smarter PCI/MSI: Cleanup include zoo PCI/MSI: Make arch_restore_msi_irqs() less horrible. x86/hyperv: Refactor hv_msi_domain_free_irqs() genirq/msi, treewide: Use a named struct for PCI/MSI attributes MIPS: Octeon: Use arch_setup_msi_irq() PCI/sysfs: Use pci_irq_vector() PCI/MSI: Remove msi_desc_to_pci_sysdata() PCI/MSI: Make pci_msi_domain_write_msg() static genirq/msi: Fixup includes genirq/msi: Remove unused domain callbacks genirq/msi: Guard sysfs code PCI/MSI: Fix pci_irq_vector()/pci_irq_get_affinity() powerpc/4xx: Complete removal of MSI support powerpc/4xx: Remove MSI support which never worked x86/alternative: Relax text_poke_bp() constraint MIPS: TXX9: Remove rbtx4938 board support MIPS: Loongson64: Use three arguments for slti MIPS: Loongson2ef: Remove unnecessary {as,cc}-option calls i2c: exynos5: Add support for ExynosAutoV9 SoC dt-bindings: i2c: exynos5: Add bus clock dt-bindings: i2c: exynos5: Add exynosautov9-hsi2c compatible dt-bindings: i2c: exynos5: Convert to dtschema dt-bindings: i2c: brcm,bcm2835-i2c: convert to YAML schema dt-bindings: i2c: tegra-bpmp: Convert to json-schema dt-bindings: arm: pmu: Document Denver and Carmel PMUs dt-bindings: arm: Catch up with Cortex/Neoverse CPUs again dt-bindings: net: Convert SYSTEMPORT to YAML dt-bindings: net: Convert AMAC to YAML dt-bindings: net: Convert iProc MDIO mux to YAML dt-bindings: phy: Convert Northstar 2 PCIe PHY to YAML dt-bindings: net: Convert GENET binding to YAML dt-bindings: net: Document moca PHY interface dt-bindings: net: brcm,unimac-mdio: Update maintainers for binding dt-bindings: net: brcm,unimac-mdio: reg-names is optional dt-bindings: PCI: brcmstb: compatible is required objtool: Add straight-line-speculation validation x86: Prepare inline-asm for straight-line-speculation ASoC: amd: Convert to new style DAI format definitions binder: fix pointer cast warning ASoC: mediatek: mt8195: silence uninitialized variable warning iomap: turn the byte variable in iomap_zero_iter into a ssize_t misc: sram: Add compatible string for Tegra234 SYSRAM ASoC: AMD: acp-config: fix missing dependency on SND_SOC_ACPI ASoC: dt-bindings: rt5682s: add AMIC delay time property ASoC: Intel: sof_rt5682: Move rt1015 speaker amp to common file ASoC: rt5682s: add delay time to fix pop sound issue ASoC: Intel: boards: add 'static' qualifiers for max98390 routes x86: Prepare asm files for straight-line-speculation x86/lib/atomic64_386_32: Rename things x86: Use -mindirect-branch-cs-prefix for RETPOLINE builds x86: Move RETPOLINE*_CFLAGS to arch Makefile x86/csum: Rewrite/optimize csum_partial() clk: lan966x: Extend lan966x clock driver for clock gating support dt-bindings: clock: lan966x: Extend includes with clock gates dt-bindings: clock: lan966x: Extend for clock gate support clk: gate: Add devm_clk_hw_register_gate() clk: lan966x: Add lan966x SoC clock driver dt-bindings: clock: lan966x: Add LAN966X Clock Controller dt-bindings: clock: lan966x: Add binding includes for lan966x SoC clock IDs clk: renesas: r9a07g044: Add GPU clock and reset entries clk: renesas: r9a07g044: Add mux and divider for G clock clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro clk: renesas: cpg-mssr: Add support for R-Car S4-8 clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver RDMA/qedr: Fix reporting max_{send/recv}_wr attrs RDMA/rxe: Remove the unnecessary variable ALSA: seq: Set upper limit of processed events ALSA: mixart: Add sanity check for timer notify streams ALSA: ppc: beep: fix clang -Wimplicit-fallthrough fuse: Pass correct lend value to filemap_write_and_wait_range() phy: qcom-qmp: Add SM8450 UFS QMP Phy dt-bindings: phy: qcom,qmp: Add SM8450 UFS phy compatible scsi: ufs: dt-bindings: Add SM8450 compatible strings ALSA: mixart: Reduce size of mixart_timer_notify scsi: lpfc: Update lpfc version to 14.0.0.4 scsi: lpfc: Add additional debugfs support for CMF scsi: lpfc: Cap CMF read bytes to MBPI scsi: lpfc: Adjust CMF total bytes and rxmonitor scsi: lpfc: Trigger SLI4 firmware dump before doing driver cleanup scsi: lpfc: Fix NPIV port deletion crash scsi: lpfc: Fix lpfc_force_rscn ndlp kref imbalance scsi: lpfc: Change return code on I/Os received during link bounce scsi: lpfc: Fix leaked lpfc_dmabuf mbox allocations with NPIV scsi: ufs: Implement polling support scsi: ufs: Optimize the command queueing code scsi: ufs: Stop using the clock scaling lock in the error handler scsi: ufs: Fix a kernel crash during shutdown scsi: ufs: Improve SCSI abort handling further scsi: ufs: Introduce ufshcd_release_scsi_cmd() scsi: ufs: Remove the 'update_scaling' local variable scsi: ufs: Remove hba->cmd_queue scsi: ufs: Fix a deadlock in the error handler scsi: ufs: Rework ufshcd_change_queue_depth() scsi: ufs: Remove ufshcd_any_tag_in_use() scsi: ufs: Fix race conditions related to driver data scsi: ufs: Remove dead code scsi: ufs: Remove the sdev_rpmb member scsi: ufs: Remove is_rpmb_wlun() scsi: ufs: Rename a function argument scsi: core: Fix scsi_device_max_queue_depth() scsi: mptfusion: Remove redundant variable r scsi: be2iscsi: Remove maintainers scsi: qla4xxx: Format SYSFS_FLAG_FW_SEL_BOOT as byte scsi: qedi: Fix SYSFS_FLAG_FW_SEL_BOOT formatting scsi: hisi_sas: Use non-atomic bitmap functions when possible scsi: hisi_sas: Remove some useless code in hisi_sas_alloc() scsi: hisi_sas: Use devm_bitmap_zalloc() when applicable RDMA/bnxt_re: Fix endianness warning for req.pkey RDMA/irdma: Fix the type used to declare a bitmap IB/core: Remove redundant pointer mm RDMA/uverbs: Remove the unnecessary assignment RDMA/hns: Modify the mapping attribute of doorbell to device RDMA/siw: Use max() instead of doing it manually dt-bindings: Use correct vendor prefix for Asahi Kasei Corp. dt-bindings: Only show unique unit address warning for enabled nodes interconnect: qcom: rpm: Prevent integer overflow in rate interconnect: icc-rpm: Use NOC_QOS_MODE_INVALID for qos_mode check clk: qcom: rpmh: add support for SM8450 rpmh clocks dt-bindings: clock: Add RPMHCC bindings for SM8450 clk: qcom: smd-rpm: Drop binary value handling for buffered clock clk: qcom: smd-rpm: Drop the use of struct rpm_cc clk: qcom: smd-rpm: Drop MFD qcom-rpm reference iommu/virtio: Support identity-mapped domains iommu/virtio: Pass end address to viommu_add_mapping() iommu/virtio: Sort reserved regions iommu/virtio: Support bypass domains iommu/virtio: Add definitions for VIRTIO_IOMMU_F_BYPASS_CONFIG ASoC: mediatek: mt8195: add memory-region property ASoC: mediatek: mt8195: add adsp and dai-link property ASoC: mediatek: mt8195: add sof support on mt8195-mt6359-rt1019-rt5682 ASoC: mediatek: mt8195: add model property ASoC: amd: acp6x-pdm-dma: Constify static snd_soc_dai_ops ASoC: SOF: Intel: fix build issue related to CODEC_PROBE_ENTRIES ASoC: ti: davinci-mcasp: Remove unnecessary conditional ASoC: ti: davinci-mcasp: Get rid of duplicate of_node assignment ASoC: zl38060: Setup parent device and get rid of unnecessary of_node assignment ASoC: test-component: fix null pointer dereference. sound/soc: remove useless bool conversion to bool variable ASoC: mediatek: mt8195: add headset codec rt5682s support ASoC: fsl-asoc-card: Add missing Kconfig option for tlv320aic31xx ASoC: mediatek: mt8195: support reserved memory assignment iommu/io-pgtable-arm: Fix table descriptor paddr formatting iommu: Extend mutex lock scope in iommu_probe_device() iommu: Log iova range in map/unmap trace events ALSA: usb-audio: Drop CONFIG_PM ifdefs ALSA: oss: remove useless NULL check before kfree ALSA: Fix some typo uio: uio_dmem_genirq: Catch the Exception memremap: remove support for external pgmap refcounts fsdax: don't require CONFIG_BLOCK iomap: build the block based code conditionally dax: fix up some of the block device related ifdefs fsdax: shift partition offset handling into the file systems dax: return the partition offset from fs_dax_get_by_bdev iomap: add a IOMAP_DAX flag xfs: pass the mapping flags to xfs_bmbt_to_iomap xfs: use xfs_direct_write_iomap_ops for DAX zeroing xfs: move dax device handling into xfs_{alloc,free}_buftarg ext4: cleanup the dax handling in ext4_fill_super ext2: cleanup the dax handling in ext2_fill_super fsdax: decouple zeroing from the iomap buffered I/O code fsdax: factor out a dax_memzero helper fsdax: simplify the offset check in dax_iomap_zero xfs: add xfs_zero_range and xfs_truncate_page helpers fsdax: simplify the pgoff calculation fsdax: use a saner calling convention for copy_cow_page_dax fsdax: remove a pointless __force cast in copy_cow_page_dax dm-stripe: add a stripe_dax_pgoff helper dm-log-writes: add a log_writes_dax_pgoff helper dm-linear: add a linear_dax_pgoff helper dax: remove dax_capable xfs: factor out a xfs_setup_dax_always helper dax: move the partition alignment check into fs_dax_get_by_bdev dax: remove the pgmap sanity checks in generic_fsdax_supported dax: simplify the dax_device <-> gendisk association dax: remove CONFIG_DAX_DRIVER dm: make the DAX support depend on CONFIG_FS_DAX dm: fix alloc_dax error handling in alloc_dev iio:dac:ad7293: add support for AD7293 iio: ltr501: Export near level property for proximity sensor dt-bindings: iio: light: ltr501: Add proximity-near-level dt-bindings: iio: adc: document TS voltage in AXP PMICs iio:adc:axp20x: add support for NTC thermistor Documentation: dt: iio: st_lsm6dsx: add disable-sensor-hub property iio: imu: st_lsm6dsx: add dts property to disable sensor-hub openrisc: Add clone3 ABI wrapper openrisc: Use delay slot for clone and fork wrappers openrisc: Cleanup switch code and comments clk: qcom: Add support for SDX65 RPMh clocks dt-bindings: clock: Introduce RPMHCC bindings for SDX65 driver: soc: xilinx: register for power events in zynqmp power driver firmware: xilinx: instantiate xilinx event manager driver drivers: soc: xilinx: add xilinx event management driver nvmem: core: set size for sysfs bin file w1: Misuse of get_user()/put_user() reported by sparse binder: defer copies of pre-patched txn data binder: read pre-translated fds from sender buffer binder: avoid potential data leakage when copying txn binder: fix handling of error during copy binder: remove repeat word from comment char/mwave: Adjust io port register size mei: Remove some dead code misc: at25: Align comment style misc: at25: Replace commas by spaces in the ID tables misc: at25: Reorganize headers for better maintenance misc: at25: Factor out at_fram_to_chip() misc: at25: Switch to use BIT() instead of custom approaches misc: at25: Get rid of intermediate storage for AT25 chip data misc: at25: Get platform data via dev_get_platdata() misc: at25: Check new property ("address-width") first misc: at25: Unshadow error codes in at25_fw_to_chip() misc: at25: Use at25->chip instead of local chip everywhere in ->probe() misc: at25: Check proper value of chip length in FRAM case misc: at25: Don't copy garbage to the at25->chip in FRAM case misc: at25: Make driver OF independent again fpga: stratix10-soc: Do not use ret uninitialized in s10_probe() scsi: sd_zbc: Clean up sd_zbc_parse_report() setting of wp scsi: sd_zbc: Simplify zone full condition check MAINTAINERS: Add entry for Qualcomm clock drivers clk: Gemini: fix struct name in kernel-doc clk: zynq: pll: Fix kernel-doc warnings clk: imx: pllv1: fix kernel-doc notation for struct clk_pllv1 ASoC: cs35l41: Fix undefined reference to core functions ASoC: amd: Fix dependency for SPI master ASoC: rt5640: Fix the wrong state of the JD in the HDA header powerpc: make memremap_compat_align 64s-only powerpc/64: pcpu setup avoid reading mmu_linear_psize on 64e or radix powerpc/64s: Rename hash_hugetlbpage.c to hugetlbpage.c powerpc/64s: move page size definitions from hash specific file powerpc/64s: Make flush_and_reload_slb a no-op when radix is enabled powerpc/64s: move THP trace point creation out of hash specific file powerpc/pseries: lparcfg don't include slb_size line in radix mode powerpc/pseries: move process table registration away from hash-specific code powerpc/64s: Move and rename do_bad_slb_fault as it is not hash specific powerpc/pseries: Stop selecting PPC_HASH_MMU_NATIVE powerpc: Rename PPC_NATIVE to PPC_HASH_MMU_NATIVE powerpc: Remove unused FW_FEATURE_NATIVE references KVM: PPC: Book3S: Suppress failed alloc warning in H_COPY_TOFROM_GUEST KVM: PPC: Book3S: Suppress warnings when allocating too big memory slots ALSA: usb-audio: Drop superfluous '0' in Presonus Studio 1810c's ID ALSA: hda/hdmi: Consider ELD is invalid when no SAD is present phy: lan966x: Extend lan966x to support multiple phy interfaces. phy: intel: Remove redundant dev_err call in thunderbay_emmc_phy_probe() dt-bindings: net: cdns,macb: Convert to json-schema dt-bindings: dma: sifive,fu540-c000-pdma: Group interrupt tuples dt-bindings: net: ethernet-controller: add 2.5G and 10G speeds of: base: Skip CPU nodes with "fail"/"fail-..." status Update trivial-devices.yaml with Sensirion,sht4x dt-bindings: Add resets to the PL011 bindings dt-bindings: hwmon: add TI DC-DC converters dt-bindings: leds: convert BCM6328 controller to the json-schema KVM: PPC: Book3S HV P9: Remove unused ri_set local variable powerpc/xive: Fix compile when !CONFIG_PPC_POWERNV. powerpc/signal32: Use struct_group() to zero spe regs i2c: stm32f7: remove noisy and imprecise log messages i2c: stm32: get rid of stm32f7_i2c_release_bus return value ASoC: codecs: wcd934x: remove redundant ret variable ASoC: tegra: Add master volume/mute control support eeprom: at24: remove struct at24_client ALSA: oss: fix compile error when OSS_DEBUG is enabled clocksource: Reduce the default clocksource_watchdog() retries to 2 clocksource: Avoid accidental unstable marking of clocksources genirq/generic_chip: Constify irq_generic_chip_ops Revert "i2c: designware-pci: Add support for Fast Mode Plus and High Speed Mode" Revert "i2c: designware-pci: Set ideal timing parameters for Elkhart Lake PSE" ASoC: Intel: Skylake: Use NHLT API to search for blob ALSA: hda: Simplify DMIC-in-NHLT check ALSA: hda: Fill gaps in NHLT endpoint-interface ASoC: Intel: boards: add max98390 2/4 speakers support ASoC: mediatek: mt8195: make several arrays static const firmware: cs_dsp: Move lockdep asserts to avoid potential null pointer ASoC: intel: boards: bytcht*: Constify static snd_soc_ops ASoC: Intel: hda_dsp_common: don't multiline PCM topology warning ASoC: mediatek: mt8195: Constify static snd_soc_ops interconnect: qcom: icc-rpmh: Add BCMs to commit list in pre_aggregate powerpc/32s: Fix shift-out-of-bounds in KASAN init powerpc/powermac: Add missing lockdep_register_key() powerpc/modules: Don't WARN on first module allocation attempt powerpc/64s: Get LPID bit width from device tree MIPS: TXx9: Let MACH_TX49XX select BOOT_ELF32 clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB powerpc/perf: Fix PMU callbacks to clear pending PMI before resetting an overflown PMC scsi: Remove superfluous #include <linux/async.h> directives scsi: pmcraid: Fix a kernel-doc warning scsi: pm8001: Fix kernel-doc warnings scsi: megaraid: Fix a kernel-doc warning scsi: initio: Fix a kernel-doc warning scsi: dc395x: Fix a kernel-doc warning scsi: bfa: Declare 'bfad_im_vport_attrs' static scsi: atp870u: Fix a kernel-doc warning scsi: a100u2w: Fix a kernel-doc warning scsi: core: Show SCMD_LAST in text form scsi: core: Declare 'scsi_scan_type' static scsi: core: Suppress a kernel-doc warning scsi: qedi: Remove set but unused 'page' variable scsi: ufs: Let devices remain runtime suspended during system suspend powerpc/atomics: Remove atomic_inc()/atomic_dec() and friends powerpc/atomics: Use immediate operand when possible powerpc/bitops: Use immediate operand when possible i2c: i801: Improve handling platform data for tco device dt-bindings: arm: cpus: Add ARM Cortex-A78 dt-bindings: thermal: Fix definition of cooling-maps contribution property dt-bindings: display: sync formats with simplefb.h RDMA/bnxt_re: Use bitmap_zalloc() when applicable RDMA/pvrdma: Use non-atomic bitmap functions when possible RDMA/pvrdma: Use bitmap_zalloc() when applicable IB/hfi1: Use bitmap_zalloc() when applicable RDMA/mlx4: Use bitmap_alloc() when applicable RDMA/ocrdma: Simplify code in 'ocrdma_search_mmap()' RDMA/ocrdma: Use bitmap_zalloc() when applicable i2c: designware-pci: Set ideal timing parameters for Elkhart Lake PSE i2c: designware-pci: Add support for Fast Mode Plus and High Speed Mode i2c: enable async suspend/resume on i2c client devices i2c: enable async suspend/resume for i2c adapters i2c: designware: Enable async suspend / resume of designware devices i2c: mpc: Correct I2C reset procedure ALSA: hda: Make proper use of timecounter ASoC: sunxi: sun4i-spdif: Implement IEC958 control ASoC: qcom: Add support for ALC5682I-VS codec ASoC: sun8i-codec: Add AIF, ADC, and DAC volume controls ASoC: soc-pcm: tidyup soc_pcm_pointer()'s delay update method ASoC: intel: sst-mfld-platform-pcm: add .delay support ASoC: amd: acp-pcm-dma: add .delay support ASoC: soc-component: add snd_soc_pcm_component_delay() ASoC: soc-dai: update snd_soc_dai_delay() to snd_soc_pcm_dai_delay() powerpc: flexible GPR range save/restore macros powerpc/watchdog: help remote CPUs to flush NMI printk output powerpc: Don't bother about .data..Lubsan sections powerpc/ptdump: Fix display a BAT's size unit powerpc/ftrace: Activate HAVE_DYNAMIC_FTRACE_WITH_REGS on PPC32 powerpc/ftrace: Add module_trampoline_target() for PPC32 powerpc/ftrace: No need to read LR from stack in _mcount() powerpc: Mark probe_machine() __init and static powerpc/smp: Move setup_profiling_timer() under CONFIG_PROFILING powerpc/mm: Move tlbcam_sz() and make it static powerpc/85xx: Make c293_pcie_pic_init() static powerpc/85xx: Make mpc85xx_smp_kexec_cpu_down() static powerpc/85xx: Fix no previous prototype warning for mpc85xx_setup_pmc() powerpc: select CPUMASK_OFFSTACK if NR_CPUS >= 8192 powerpc: remove cpu_online_cores_map function MIPS: CPS: Use bitfield helpers MIPS: CPC: Use bitfield helpers MIPS: Remove a repeated word in a comment dt-bindings: timer: tpm-timer: Add imx8ulp compatible string i2c: designware: Fix the kernel doc description for struct dw_i2c_dev i2c: rk3x: enable clock before getting rate i2c: i801: Improve handling of chip-specific feature definitions i2c: i801: Remove i801_set_block_buffer_mode i2c: i801: Don't silently correct invalid transfer size i2c: tegra: Add the ACPI support dt-bindings: i2c: imx-lpi2c: Add imx8ulp compatible string dt-bindings: i2c: imx-lpi2c: Add i.MX8DXL compatible match Revert "powerpc/code-patching: Improve verification of patchability" fpga: region: Use standard dev_release for class driver fpga: bridge: Use standard dev_release for class driver fpga: mgr: Use standard dev_release for class driver iio: test: Add test for IIO_VAL_INT_64. iio: test: Add check against NULL for buffer in tests. iio: expose shared parameter in IIO_ENUM_AVAILABLE iio: buffer-dma: Use round_down() instead of rounddown() iio: buffer-dma: Remove unused iio_buffer_block struct Documentation: coresight: Update coresight configuration docs coresight: configfs: Allow configfs to activate configuration coresight: syscfg: Example CoreSight configuration loadable module coresight: syscfg: Update load API for config loadable modules coresight: configuration: Update API to permit dynamic load/unload coresight: configuration: Update API to introduce load owner concept most: usb: replace snprintf in show functions with sysfs_emit speakup: remove redundant assignment of variable i scripts/tags: add space regexs to all regex_c comedi: Move "comedi_isadma.h" to <linux/comedi/comedi_isadma.h> comedi: Move "comedi_8254.h" to <linux/comedi/comedi_8254.h> comedi: Move and rename "8255.h" to <linux/comedi/comedi_8255.h> comedi: ni_routing: tools: Update due to moved COMEDI headers comedi: Move the main COMEDI headers include/linux/byteorder/generic.h: fix index variables ASoC: SOF: mediatek: Use %pR/%pa to print resources/physical addresses ASoC: cs35l41: Fix link problem ASoC: codecs/jz4770: Add missing gain control after DAC/ADC mixer ASoC: imx-hdmi: add put_device() after of_find_device_by_node() ASoC: SOF: Intel: hda: send DAI_CONFIG IPC during pause ASoC: SOF: IPC: dai: Expand DAI_CONFIG IPC flags ASoC: SOF: align the hw_free sequence with stop ASoC: SOF: pcm: move the check for prepared flag ASoC: SOF: Add a helper for freeing PCM stream ASoC: SOF: call platform hw_free for paused streams during suspend ASoC: SOF: pcm: invoke platform hw_free for STOP/SUSPEND triggers ASoC: SOF: Intel: hda: reset stream before coupling host and link DMA's ASoC: SOF: Intel: hda: Add a helper function for stream reset ASoC: SOF: Intel: hda: clear stream before freeing the DAI widget clk: renesas: r9a07g044: Add TSU clock and reset entry mmc: renesas_sdhi: Simplify an expression mmc: renesas_sdhi: Use devm_clk_get_optional() to obtain CD clock phy: stm32: adopt dev_err_probe for regulators RDMA/bnxt_re: Remove dynamic pkey table RDMA/siw: Use helper function to set sys_image_guid RDMA/rtrs-clt: Fix the initial value of min_latency RDMA/cma: Remove open coding of overflow checking for private_data_len RDMA/cxgb4: Use non-atomic bitmap functions when possible RDMA/cxgb4: Use bitmap_set() when applicable RDMA/cxgb4: Use bitmap_zalloc() when applicable IB/mthca: Use non-atomic bitmap functions when possible in 'mthca_mr.c' IB/mthca: Use non-atomic bitmap functions when possible in 'mthca_allocator.c' IB/mthca: Use bitmap_set() when applicable IB/mthca: Use bitmap_zalloc() when applicable fuse: send security context of inode on file fuse: extend init flags ASoC: rt5640: Add the HDA header support ASoC: rt5640: Add the binding include file for the HDA header support ASoC: codecs: wcd938x: add SND_SOC_WCD938_SDW to codec list instead ASoC: uniphier: drop selecting non-existing SND_SOC_UNIPHIER_AIO_DMA ASoC: SOF: mediatek: Add missing of_node_put() in platform_parse_resource() ASoC: mediatek: remove unnecessary CONFIG_PM powerpc/watchdog: Fix wd_smp_last_reset_tb reporting phy: bcm-ns-usb2: improve printing ref clk errors dax: Kill DEV_DAX_PMEM_COMPAT powerpc/microwatt: Make microwatt_get_random_darn() static powerpc/watchdog: read TB close to where it is used powerpc/watchdog: Avoid holding wd_smp_lock over printk and smp_send_nmi_ipi powerpc/watchdog: tighten non-atomic read-modify-write access powerpc/watchdog: Fix missed watchdog reset due to memory ordering race powerpc/prom_init: Fix improper check of prom_getprop() powerpc/rtas: rtas_busy_delay_time() kernel-doc powerpc/rtas: rtas_busy_delay() improvements powerpc/pseries: delete scanlog powerpc/rtas: kernel-doc fixes powerpc/code-patching: Improve verification of patchability powerpc/tsi108: make EXPORT_SYMBOL follow its function immediately bpf ppc32: Access only if addr is kernel address bpf ppc32: Add BPF_PROBE_MEM support for JIT bpf ppc64: Access only if addr is kernel address bpf ppc64: Add BPF_PROBE_MEM support for JIT powerpc/ppc-opcode: introduce PPC_RAW_BRANCH() macro bpf powerpc: refactor JIT compiler code bpf powerpc: Remove extra_pass from bpf_jit_build_body() bpf powerpc: Remove unused SEEN_STACK powerpc/eeh: Use a goto for recovery failures powerpc/eeh: Small refactor of eeh_handle_normal_event() powerpc/xive: Add a debugfs toggle for save-restore powerpc/xive: Add a kernel parameter for StoreEOI powerpc/xive: Add a debugfs toggle for StoreEOI powerpc/xive: Add a debugfs file to dump EQs powerpc/xive: Rename the 'cpus' debugfs file to 'ipis' powerpc/xive: Change the debugfs file 'xive' into a directory powerpc/xive: Introduce xive_core_debugfs_create() powerpc/xive: Activate StoreEOI on P10 powerpc/xive: Introduce an helper to print out interrupt characteristics powerpc/xive: Replace pr_devel() by pr_debug() to ease debug powerpc/powernv: Remove POWER9 PVR version check for entry and uaccess flushes powerpc/btext: add missing of_node_put powerpc/cell: add missing of_node_put powerpc/powernv: add missing of_node_put powerpc/6xx: add missing of_node_put ASoC: SOF: handle paused streams during system suspend ASoC: SOF: topology: don't use list_for_each_entry_reverse() ASoC: SOF: sof-audio: setup sched widgets during pipeline complete step ASoC: SOF: Intel: add .ack support for HDaudio platforms ASoC: SOF: pcm: add .ack callback support ALSA: pcm: introduce INFO_NO_REWINDS flag ALSA: pcm: unconditionally check if appl_ptr is in 0..boundary range KVM: PPC: Book3S HV P9: Remove subcore HMI handling KVM: PPC: Book3S HV P9: Stop using vc->dpdes KVM: PPC: Book3S HV P9: Tidy kvmppc_create_dtl_entry KVM: PPC: Book3S HV P9: Remove most of the vcore logic KVM: PPC: Book3S HV P9: Avoid cpu_in_guest atomics on entry and exit KVM: PPC: Book3S HV P9: Add unlikely annotation for !mmu_ready KVM: PPC: Book3S HV P9: Avoid changing MSR[RI] in entry and exit KVM: PPC: Book3S HV P9: Optimise hash guest SLB saving KVM: PPC: Book3S HV P9: Improve mfmsr performance on entry KVM: PPC: Book3S HV Nested: Avoid extra mftb() in nested entry KVM: PPC: Book3S HV P9: Avoid tlbsync sequence on radix guest exit KVM: PPC: Book3S HV: Split P8 from P9 path guest vCPU TLB flushing KVM: PPC: Book3S HV P9: Don't restore PSSCR if not needed KVM: PPC: Book3S HV P9: Test dawr_enabled() before saving host DAWR SPRs KVM: PPC: Book3S HV P9: Comment and fix MMU context switching code KVM: PPC: Book3S HV P9: Use Linux SPR save/restore to manage some host SPRs KVM: PPC: Book3S HV P9: Demand fault TM facility registers KVM: PPC: Book3S HV P9: Demand fault EBB facility registers KVM: PPC: Book3S HV P9: More SPR speed improvements KVM: PPC: Book3S HV P9: Restrict DSISR canary workaround to processors that require it KVM: PPC: Book3S HV P9: Switch PMU to guest as late as possible KVM: PPC: Book3S HV P9: Implement TM fastpath for guest entry/exit KVM: PPC: Book3S HV P9: Move remaining SPR and MSR access into low level entry KVM: PPC: Book3S HV P9: Move nested guest entry into its own function KVM: PPC: Book3S HV P9: Move host OS save/restore functions to built-in KVM: PPC: Book3S HV P9: Move vcpu register save/restore into functions KVM: PPC: Book3S HV P9: Juggle SPR switching around KVM: PPC: Book3S HV P9: Only execute mtSPR if the value changed KVM: PPC: Book3S HV P9: Avoid SPR scoreboard stalls KVM: PPC: Book3S HV P9: Optimise timebase reads KVM: PPC: Book3S HV P9: Move TB updates KVM: PPC: Book3S HV: Change dec_expires to be relative to guest timebase KVM: PPC: Book3S HV P9: Add kvmppc_stop_thread to match kvmppc_start_thread KVM: PPC: Book3S HV P9: Improve mtmsrd scheduling by delaying MSR[EE] disable KVM: PPC: Book3S HV P9: Reduce mtmsrd instructions required to save host SPRs KVM: PPC: Book3S HV P9: Move SPRG restore to restore_p9_host_os_sprs KVM: PPC: Book3S HV: CTRL SPR does not require read-modify-write KVM: PPC: Book3S HV P9: Factor out yield_count increment KVM: PPC: Book3S HV P9: Demand fault PMU SPRs when marked not inuse KVM: PPC: Book3S HV P9: Factor PMU save/load into context switch functions KVM: PPC: Book3S HV P9: Implement PMU save/restore in C powerpc/64s: Implement PMU override command line option powerpc/64s: Always set PMU control registers to frozen/disabled when not in use KVM: PPC: Book3S HV: Don't always save PMU for guest capable of nesting powerpc/64s: Keep AMOR SPR a constant ~0 at runtime KVM: PPC: Book3S HV: POWER10 enable HAIL when running radix guests powerpc/time: add API for KVM to re-arm the host timer/decrementer KVM: PPC: Book3S HV P9: Reduce mftb per guest entry/exit KVM: PPC: Book3S HV P9: Use large decrementer for HDEC KVM: PPC: Book3S HV P9: Use host timer accounting to avoid decrementer read KMV: PPC: Book3S HV P9: Use set_dec to set decrementer to host powerpc/64s: guard optional TIDR SPR with CPU ftr test powerpc/64s: Remove WORT SPR from POWER9/10 (take 2) ALSA: led: Use restricted type for iface assignment soundwire: qcom: remove redundant version number read i2c: mux: gpio: Use array_size() helper i2c: mux: gpio: Don't dereference fwnode from struct device i2c: mux: gpio: Replace custom acpi_get_local_address() i2c: imx: Add timer for handling the stop condition clk: sunxi-ng: Add support for the D1 SoC clocks clk: sunxi-ng: gate: Add macros for gates with fixed dividers clk: sunxi-ng: mux: Add macros using clk_parent_data and clk_hw clk: sunxi-ng: mp: Add macros using clk_parent_data and clk_hw clk: sunxi-ng: div: Add macros using clk_parent_data and clk_hw dt-bindings: clk: Add compatibles for D1 CCUs clk: sunxi-ng: Allow the CCU core to be built as a module clk: sunxi-ng: Convert early providers to platform drivers i2c: Remove unused Netlogic/Sigma Designs XLR driver i2c: Remove Netlogic XLP variant phy: intel: Add Thunder Bay eMMC PHY support dt-bindings: phy: intel: Add Thunder Bay eMMC PHY bindings phy: Add lan966x ethernet serdes PHY driver dt-bindings: phy: Add constants for lan966x serdes dt-bindings: phy: Add lan966x-serdes binding phy: phy-can-transceiver: Make devm_gpiod_get optional phy: cadence-torrent: use swap() to make code cleaner phy: uniphier-ahci: Add support for Pro4 SoC dt-bindings: phy: uniphier-ahci: Add bindings for Pro4 SoC phy: uniphier-pcie: Add dual-phy support for NX1 SoC phy: uniphier-pcie: Set VCOPLL clamp mode in PHY register phy: uniphier-pcie: Add compatible string and SoC-dependent data for NX1 SoC dt-bindings: phy: uniphier-pcie: Add bindings for NX1 SoC phy: uniphier-usb3: Add compatible string for NX1 SoC dt-bindings: phy: uniphier-usb3: Add bindings for NX1 SoC dt-bindings: phy: Tegra194 P2U convert to YAML phy: amlogic: Add a new driver for the HDMI TX PHY on Meson8/8b/8m2 dt-bindings: phy: Add the Amlogic Meson8 HDMI TX PHY bindings phy: qcom: Introduce new eDP PHY driver dt-bindings: phy: Introduce Qualcomm eDP PHY binding phy: bcm-ns-usb2: support updated DT binding with PHY reg space clk: samsung: exynos850: Register clocks early interconnect: qcom: Add MSM8996 interconnect provider driver dt-bindings: interconnect: Add Qualcomm MSM8996 DT bindings interconnect: icc-rpm: Add support for bus power domain dt-bindings: interconnect: Combine SDM660 bindings into RPM schema ASoC: fsl-asoc-card: Support fsl,imx-audio-tlv320aic31xx codec ASoC: tlv320aic31xx: Handle BCLK set as PLL input configuration ASoC: tlv320aic31xx: Add divs for bclk as clk_in ASoC: tlv320aic31xx: Add support for pll_r coefficient ASoC: tlv320aic31xx: Fix typo in BCLK clock name ASoC: cs42l42: Report initial jack state ASoC: SOF: sof-pci-dev: use community key on all Up boards ASoC: stm32: spdifrx: add pm_runtime support ASoC: stm32: dfsdm: add pm_runtime support for audio ASoC: stm32: i2s: add pm_runtime support ASoC: SOF: Intel: hda: free DAI widget during stop and suspend ASoC: SOF: add support for dynamic pipelines with multi-core ASoC: SOF: hda: don't use the core op for power up/power down ASoC: SOF: free widgets in sof_tear_down_pipelines() for static pipelines ASoC: SOF: topology: remove sof_load_pipeline_ipc() ASoC: SOF: Intel: CNL/ICL/APL: set core_get/core_put ops ASoC: SOF: Intel: TGL: set core_get/put ops ASoC: SOF: Add ops for core_get and core_put ASoC: SOF: Introduce num_cores and ref count per core ASoC: SOF: Intel: hda: expose get_chip_info() ASoC: SOF: imx8m: Implement reset callback ASoC: SOF: imx8m: Implement DSP start ASoC: SOF: imx8m: Add runtime PM / System PM support ASoC: SOF: imx8: Add runtime PM / System PM support ASoC: SOF: imx: Add code to manage DSP related clocks clk: imx8mp: Fix the parent clk of the audio_root_clk clk: imx8mp: Remove IPG_AUDIO_ROOT from imx8mp-clock.h interconnect: qcom: Add EPSS L3 support on SC7280 dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 clk: imx8mn: Fix imx8mn_clko1_sels clk: imx: Use div64_ul instead of do_div clk: imx: imx8ulp: set suppress_bind_attrs to true clk: samsung: exynos850: Keep some crucial clocks running clk: samsung: exynos850: Implement CMU_CMGP domain dt-bindings: clock: Add bindings for Exynos850 CMU_CMGP clk: samsung: exynos850: Implement CMU_APM domain dt-bindings: clock: Add bindings for Exynos850 CMU_APM clk: sunxi-ng: Allow drivers to be built as modules clk: sunxi-ng: Export symbols used by CCU drivers iio: buffer: Use dedicated variable in iio_buffers_alloc_sysfs_and_mask() clk: samsung: Update CPU clk registration ALSA: hda: Remove redundant runtime PM calls clk: samsung: Remove meaningless __init and extern from header files clk: samsung: remove __clk_lookup() usage dt-bindings: clock: samsung: add IDs for some core clocks RDMA/hns: Remove magic number RDMA/hns: Remove macros that are no longer used RDMA/hns: Correctly initialize the members of Array[][] RDMA/hns: Correct the type of variables participating in the shift operation RDMA/hns: Replace tab with space in the right-side comments RDMA/hns: Correct the print format to be consistent with the variable type RDMA/hns: Correct the hex print format RDMA/rxe: Remove some #defines from rxe_pool.h RDMA/rxe: Remove #include "rxe_loc.h" from rxe_pool.c RDMA/rxe: Save object pointer in pool element RDMA/rxe: Copy setup parameters into rxe_pool RDMA/rxe: Cleanup rxe_pool_entry RDMA/rxe: Replace irqsave locks with bh locks RDMA/usnic: Clean up usnic_ib_alloc_pd() RDMA/cxgb4: Use helper function to set GUIDs reset: Add of_reset_control_get_optional_exclusive() dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0 clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple() clk: renesas: cpg-mssr: Check return value of pm_genpd_init() clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple() clk: renesas: rzg2l: Check return value of pm_genpd_init() clk: renesas: r9a07g044: Add RSPI clock and reset entries clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV clk: renesas: rzg2l: Add CPG_PL1_DDIV macro mmc: renesas_sdhi: Parse DT for SDnH mmc: renesas_sdhi: Use dev_err_probe when getting clock fails clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRST clk: renesas: rcar-gen3: Switch to new SD clock handling mmc: renesas_sdhi: Flag non-standard SDnH handling for V3M clk: renesas: r8a779a0: Add SDnH clock to V3U clk: renesas: rcar-gen3: Add SDnH clock clk: renesas: rcar-gen3: Add dummy SDnH clock scsi: ufs: Fix double space in SCSI_UFS_HWMON description scsi: ufs: Wrap Universal Flash Storage drivers in SCSI_UFSHCD scsi: pm80xx: Add pm80xx_mpi_build_cmd() tracepoint scsi: pm80xx: Add tracepoints scsi: pm80xx: Use bitmap_zalloc() for tags bitmap allocation scsi: pm80xx: Update WARN_ON check in pm8001_mpi_build_cmd() scsi: pm80xx: Do not check the address-of value for NULL scsi: pm80xx: Apply byte mask for phy ID in mpi_phy_start_resp() scsi: core: Use eh_timeout for START STOP UNIT scsi: core: Remove Scsi_Host.shost_dev_attr_groups scsi: core: Simplify control flow in scmd_eh_abort_handler() Documentation: coresight: Fix documentation issue of: property: fw_devlink: Fixup behaviour when 'node_not_dev' is set ASoC: codecs: MBHC: Remove useless condition check ASoC: SOF: mediatek: Add DSP system PM callback for mt8195 ASoC: SOF: mediatek: Add mt8195 dsp clock support ASoC: SOF: mediatek: Add dai driver dsp ops callback for mt8195 ASoC: SOF: Add mt8195 device descriptor ASoC: SOF: mediatek: Add fw loader and mt8195 dsp ops to load firmware ASoC: SOF: topology: Add support for Mediatek AFE DAI ASoC: SOF: tokens: add token for Mediatek AFE ASoC: SOF: mediatek: Add mt8195 hardware support firmware: cs_dsp: Allow creation of event controls firmware: cs_dsp: Add offset to cs_dsp read/write firmware: cs_dsp: Clarify some kernel doc comments firmware: cs_dsp: Perform NULL check in cs_dsp_coeff_write/read_ctrl firmware: cs_dsp: Add support for rev 2 coefficient files firmware: cs_dsp: Print messages from bin files firmware: cs_dsp: Add pre_run callback firmware: cs_dsp: Add version checks on coefficient loading firmware: cs_dsp: Add lockdep asserts to interface functions ASoC: wm_adsp: Remove the wmfw_add_ctl helper function RDMA/hns: Validate the pkey index RDMA/ocrdma: Use helper function to set GUIDs iio: light: ltr501: Added ltr303 driver support iio: adc: rzg2l_adc: Remove unnecessary print function dev_err() iio: mpl3115: Use scan_type.shift and realbit in mpl3115_read_raw iio: xilinx-xadc-core: Use local variable in xadc_read_raw iio: ti-ads1015: Remove shift variable ads1015_read_raw iio: mag3110: Use scan_type when processing raw data iio: ti-adc12138: Use scan_type when processing raw data iio: ad7266: Use scan_type when processing raw data iio: stk8ba50: Use scan_type when processing raw data iio: stk8312: Use scan_type when processing raw data iio: sca3000: Use scan_type when processing raw data iio: mma7455: Use scan_type when processing raw data iio: kxcjk-1013: Use scan_type when processing raw data iio: bma220: Use scan_type when processing raw data iio: at91-sama5d2: Use dev_to_iio_dev() in sysfs callbacks iio: at91-sama5d2: Fix incorrect cast to platform_device iio: mma8452: Use correct type for return variable in IRQ handler iio: lmp91000: Remove no-op trigger ops iio: gp2ap020a00f: Remove no-op trigger ops iio: atlas-sensor: Remove no-op trigger ops iio: as3935: Remove no-op trigger ops iio: afe4404: Remove no-op trigger ops iio: afe4403: Remove no-op trigger ops iio: ad_sigma_delta: Remove no-op trigger ops iio: sysfs-trigger: Remove no-op trigger ops iio: interrupt-trigger: Remove no-op trigger ops iio: Mark iio_device_type as const iio/scmi: Add reading "raw" attribute. iio: core: Introduce IIO_VAL_INT_64. iio: adc: ina2xx: Avoid double reference counting from get_task_struct/put_task_struct() iio: adc: ina2xx: Make use of the helper macro kthread_run() iio: ms5611: Simplify IO callback parameters iio: imx7d_adc: Don't pass IIO device to imx7d_adc_{enable,disable}() iio: st-sensors: Use dev_to_iio_dev() in sysfs callbacks iio: adc: stm32-adc: Fix of_node_put() issue in stm32-adc iio: xilinx-xadc: Make IRQ optional iio: accel: mma7660: Warn about failure to put device in stand-by in .remove() iio: adc: lpc18xx_adc: Reorder clk_get_rate() function call ASoC: SOF: amd: Add support for SOF firmware authentication ASoC: SOF: amd: Add trace logger support ASoC: SOF: topology: Add support for AMD ACP DAIs ASoC: amd: acp-config: Remove legacy acpi based machine struct ASoC: SOF: amd: Add Renoir PCI driver interface ASoC: SOF: amd: Add machine driver dsp ops for Renoir platform ASoC: amd: Add module to determine ACP configuration ASoC: SOF: amd: Add PCM stream callback for Renoir dai's ASoC: SOF: amd: Add dai driver dsp ops callback for Renoir ASoC: SOF: amd: Add IPC support for ACP IP block ASoC: SOF: amd: Add fw loader and renoir dsp ops to load firmware ASoC: SOF: amd: Add helper callbacks for ACP's DMA configuration ASoC: SOF: amd: Add Renoir ACP HW support firmware: xilinx: export the feature check of zynqmp firmware firmware: xilinx: add macros of node ids for error event firmware: xilinx: add register notifier in zynqmp firmware nitro_enclaves: Add KUnit tests for contiguous physical memory regions merging nitro_enclaves: Add KUnit tests setup for the misc device functionality nitro_enclaves: Sanity check physical memory regions during merging nitro_enclaves: Merge contiguous physical memory regions nitro_enclaves: Remove redundant 'flush_workqueue()' calls perf: Drop guest callback (un)register stubs KVM: arm64: Drop perf.c and fold its tiny bits of code into arm.c KVM: arm64: Hide kvm_arm_pmu_available behind CONFIG_HW_PERF_EVENTS=y KVM: arm64: Convert to the generic perf callbacks KVM: x86: Move Intel Processor Trace interrupt handler to vmx.c KVM: Move x86's perf guest info callbacks to generic KVM KVM: x86: More precisely identify NMI from guest when handling PMI KVM: x86: Drop current_vcpu for kvm_running_vcpu + kvm_arch_vcpu variable perf/core: Use static_call to optimize perf_guest_info_callbacks perf: Force architectures to opt-in to guest callbacks perf: Add wrappers for invoking guest callbacks perf/core: Rework guest callbacks to prepare for static_call support perf: Drop dead and useless guest "support" from arm, csky, nds32 and riscv perf: Stop pretending that perf can handle multiple guest callbacks KVM: x86: Register Processor Trace interrupt hook iff PT enabled in guest KVM: x86: Register perf callbacks after calling vendor's hardware_setup() perf: Protect perf_guest_cbs with RCU ALSA: hda: Do disconnect jacks at codec unbind ASoC: stm32: sai: increase channels_max limit ASoC: SOF: debug: Add support for IPC message injection ASoC: SOF: intel: Use the generic helper to get the reply ASoC: SOF: imx: Use the generic helper to get the reply ASoC: SOF: utils: Add generic function to get the reply for a tx message ASoC: cs42l42: Remove redundant pll_divout member ASoC: cs42l42: Simplify reporting of jack unplug ASoC: cs42l42: Remove redundant writes to RS_PLUG/RS_UNPLUG masks ASoC: cs42l42: Remove redundant writes to DETECT_MODE RDMA/bnxt_re: Scan the whole bitmap when checking if "disabling RCFW with pending cmd-bit" RDMA/bnxt_re: Remove unneeded variable RDMA/irdma: Use helper function to set GUIDs coresight: Use devm_bitmap_zalloc when applicable clocksource/drivers/exynos_mct: Refactor resources allocation ASoC: SOF: i.MX: simplify Kconfig ASoC: qcom: sdm845: only setup slim ports once ALSA: memalloc: Unify x86 SG-buffer handling (take#3) ALSA: hda: Fix potential deadlock at codec unbinding ALSA: hda: Add missing rwsem around snd_ctl_remove() calls ALSA: PCM: Add missing rwsem around snd_ctl_remove() calls ALSA: jack: Add missing rwsem around snd_ctl_remove() calls ALSA: usb-audio: Fix dB level of Bose Revolve+ SoundLink ALSA: usb-audio: Add minimal-mute notion in dB mapping table ALSA: usb-audio: Use int for dB map values ASoC: wm8903: Convert txt bindings to yaml ASoC: codecs: MBHC: Add support for special headset ASoC: SOF: core: Unregister machine driver before IPC and debugfs ASoC: adau1701: Replace legacy gpio interface for gpiod firmware: cs_dsp: tidy includes in cs_dsp.c and cs_dsp.h ASoC: cs42l42: Add control for audio slow-start switch ASoC: Intel: add sof-nau8825 machine driver ASoC: codecs: Axe some dead code in 'wcd_mbhc_adc_hs_rem_irq()' ASoC: cs35l41: DSP Support ASoC: dt-bindings: cs42l42: Convert binding to yaml cxl/pmem: Fix module reload vs workqueue state ACPI: NUMA: Add a node and memblk for each CFMWS not in SRAT cxl/test: Mock acpi_table_parse_cedt() cxl/acpi: Convert CFMWS parsing to ACPI sub-table helpers ACPI: Add a context argument for table parsing handlers ACPI: Teach ACPI table parsing about the CEDT header format ACPI: Keep sub-table parsing infrastructure available for modules tools/testing/cxl: add mock output for the GET_HEALTH_INFO command cxl/memdev: Remove unused cxlmd field cxl/core: Convert to EXPORT_SYMBOL_NS_GPL cxl/memdev: Change cxl_mem to a more descriptive name cxl/mbox: Remove bad comment cxl/pmem: Fix reference counting for delayed work dt-bindings: vendor-prefixes: add T-Head Semiconductor dt-bindings: leds: Add bindings for MT6360 LED ASoC: intel: sof_sdw: add link adr order check ASoC: intel: sof_sdw: remove get_next_be_id ASoC: intel: sof_sdw: remove sof_sdw_mic_codec_mockup_init ASoC: intel: sof_sdw: remove SOF_RT715_DAI_ID_FIX quirk ASoC: intel: sof_sdw: move DMIC link id overwrite to create_sdw_dailink ASoC: intel: sof_sdw: Use a fixed DAI link id for AMP ASoC: intel: sof_sdw: rename be_index/link_id to link_index ASoC: Intel: sof_sdw: add SKU for Dell Latitude 9520 ASoC: Intel: sof_sdw: fix jack detection on HP Spectre x360 convertible ASoC: intel: sof_sdw: return the original error number ASoC: SOF: trace: send DMA_TRACE_FREE IPC during release ASoC: SOF: IPC: update ipc_log_header() ASoC: SOF: IPC: Add new IPC command to free trace DMA ASoC: codecs: tfa989x: Add support for tfa9897 optional rcv-gpios ASoC: dt-bindings: nxp, tfa989x: Add rcv-gpios property for tfa9897 clk: renesas: r9a07g044: Add OSTM clock and reset entries clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros clk: renesas: r9a07g044: Add WDT clock and reset entries clk: renesas: r9a07g044: Add clock and reset entry for SCI1 ALSA: hda: intel: More comprehensive PM runtime setup for controller driver clk: renesas: rzg2l: Add missing kerneldoc for resets gnss: drop stray semicolons dt-bindings: timer: remove rockchip,rk3066-timer compatible string from rockchip,rk-timer.yaml dt-bindings: timer: cadence_ttc: Add power-domains Bug: 120440972 Bug: 181024194 Bug: 204425264 Bug: 210713925 Bug: 211066171 Bug: 215310351 Bug: 216016261 Bug: 216312411 Bug: 216462633 Bug: 217583980 Bug: 218319878 Bug: 218328931 Bug: 218541542 Change-Id: I77163fd899b3fcebfadaff47691237f3fd7cabc0 Signed-off-by: Blagovest Kolenichev <quic_c_bkolen@quicinc.com>
2026-07-30 11:11:26 +02:00 · 2022-02-11 16:26:23 -08:00 · 2022-02-11 16:26:23 -08:00 · 174eff53b1
commit 174eff53b1
parent e98653b1be 8bbe6f703a
2592 changed files with 96576 additions and 53985 deletions
--- a/.clang-format
+++ b/.clang-format
@ -216,7 +216,6 @@ ForEachMacros:
  - 'for_each_migratetype_order'
  - 'for_each_msi_entry'
  - 'for_each_msi_entry_safe'
-  - 'for_each_msi_vector'
  - 'for_each_net'
  - 'for_each_net_continue_reverse'
  - 'for_each_netdev'
--- a/BUILD.bazel
+++ b/BUILD.bazel
@ -17,6 +17,6 @@ package(
    ],
 )

-load("//build/kleaf:common_kernels.bzl", "define_common_kernels")
+load("//build/kernel/kleaf:common_kernels.bzl", "define_common_kernels")

 define_common_kernels()
--- a/Documentation/ABI/obsolete/sysfs-class-dax
+++ b/Documentation/ABI/obsolete/sysfs-class-dax
@ -1,22 +0,0 @@
-What:           /sys/class/dax/
-Date:           May, 2016
-KernelVersion:  v4.7
-Contact:        nvdimm@lists.linux.dev
-Description:	Device DAX is the device-centric analogue of Filesystem
-		DAX (CONFIG_FS_DAX).  It allows memory ranges to be
-		allocated and mapped without need of an intervening file
-		system.  Device DAX is strict, precise and predictable.
-		Specifically this interface:
-
-		1. Guarantees fault granularity with respect to a given
-		   page size (pte, pmd, or pud) set at configuration time.
-
-		2. Enforces deterministic behavior by being strict about
-		   what fault scenarios are supported.
-
-		The /sys/class/dax/ interface enumerates all the
-		device-dax instances in the system. The ABI is
-		deprecated and will be removed after 2020. It is
-		replaced with the DAX bus interface /sys/bus/dax/ where
-		device-dax instances can be found under
-		/sys/bus/dax/devices/
--- a/Documentation/ABI/testing/debugfs-driver-habanalabs
+++ b/Documentation/ABI/testing/debugfs-driver-habanalabs
@ -21,11 +21,11 @@ Description:    Allow the root user to disable/enable in runtime the clock
                a different engine to disable/enable its clock gating feature.
                The bitmask is composed of 20 bits:

-		=======   ============
+                =======   ============
                0  -  7   DMA channels
                8  - 11   MME engines
                12 - 19   TPC engines
-		=======   ============
+                =======   ============

                The bit's location of a specific engine can be determined
                using (1 << GAUDI_ENGINE_ID_*). GAUDI_ENGINE_ID_* values
@ -155,6 +155,13 @@ Description:    Triggers an I2C transaction that is generated by the device's
                CPU. Writing to this file generates a write transaction while
                reading from the file generates a read transaction

+What:           /sys/kernel/debug/habanalabs/hl<n>/i2c_len
+Date:           Dec 2021
+KernelVersion:  5.17
+Contact:        obitton@habana.ai
+Description:    Sets I2C length in bytes for I2C transaction that is generated by
+                the device's CPU
+
 What:           /sys/kernel/debug/habanalabs/hl<n>/i2c_reg
 Date:           Jan 2019
 KernelVersion:  5.1
@ -226,12 +233,6 @@ Description:    Gets the state dump occurring on a CS timeout or failure.
                Writing an integer X discards X state dumps, so that the
                next read would return X+1-st newest state dump.

-What:           /sys/kernel/debug/habanalabs/hl<n>/timeout_locked
-Date:           Sep 2021
-KernelVersion:  5.16
-Contact:        obitton@habana.ai
-Description:    Sets the command submission timeout value in seconds.
-
 What:           /sys/kernel/debug/habanalabs/hl<n>/stop_on_err
 Date:           Mar 2020
 KernelVersion:  5.6
@ -239,6 +240,12 @@ Contact:        ogabbay@kernel.org
 Description:    Sets the stop-on_error option for the device engines. Value of
                "0" is for disable, otherwise enable.

+What:           /sys/kernel/debug/habanalabs/hl<n>/timeout_locked
+Date:           Sep 2021
+KernelVersion:  5.16
+Contact:        obitton@habana.ai
+Description:    Sets the command submission timeout value in seconds.
+
 What:           /sys/kernel/debug/habanalabs/hl<n>/userptr
 Date:           Jan 2019
 KernelVersion:  5.1
--- a/Documentation/ABI/testing/sysfs-bus-iio-filter-admv8818
+++ b/Documentation/ABI/testing/sysfs-bus-iio-filter-admv8818
@ -0,0 +1,16 @@
+What:		/sys/bus/iio/devices/iio:deviceX/filter_mode_available
+KernelVersion:
+Contact:	linux-iio@vger.kernel.org
+Description:
+		Reading this returns the valid values that can be written to the
+		on_altvoltage0_mode attribute:
+
+		- auto -> Adjust bandpass filter to track changes in input clock rate.
+		- manual -> disable/unregister the clock rate notifier / input clock tracking.
+
+What:		/sys/bus/iio/devices/iio:deviceX/filter_mode
+KernelVersion:
+Contact:	linux-iio@vger.kernel.org
+Description:
+		This attribute configures the filter mode.
+		Reading returns the actual mode.
--- a/Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1013
+++ b/Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1013
@ -0,0 +1,38 @@
+What:		/sys/bus/iio/devices/iio:deviceX/in_altvoltage0-1_i_calibphase
+KernelVersion:
+Contact:	linux-iio@vger.kernel.org
+Description:
+		Read/write unscaled value for the Local Oscillatior path quadrature I phase shift.
+
+What:		/sys/bus/iio/devices/iio:deviceX/in_altvoltage0-1_q_calibphase
+KernelVersion:
+Contact:	linux-iio@vger.kernel.org
+Description:
+		Read/write unscaled value for the Local Oscillatior path quadrature Q phase shift.
+
+What:		/sys/bus/iio/devices/iio:deviceX/in_altvoltage0_i_calibbias
+KernelVersion:
+Contact:	linux-iio@vger.kernel.org
+Description:
+		Read/write value for the Local Oscillatior Feedthrough Offset Calibration I Positive
+		side.
+
+What:		/sys/bus/iio/devices/iio:deviceX/in_altvoltage0_q_calibbias
+KernelVersion:
+Contact:	linux-iio@vger.kernel.org
+Description:
+		Read/write value for the Local Oscillatior Feedthrough Offset Calibration Q Positive side.
+
+What:		/sys/bus/iio/devices/iio:deviceX/in_altvoltage1_i_calibbias
+KernelVersion:
+Contact:	linux-iio@vger.kernel.org
+Description:
+		Read/write raw value for the Local Oscillatior Feedthrough Offset Calibration I Negative
+		side.
+
+What:		/sys/bus/iio/devices/iio:deviceX/in_altvoltage1_q_calibbias
+KernelVersion:
+Contact:	linux-iio@vger.kernel.org
+Description:
+		Read/write raw value for the Local Oscillatior Feedthrough Offset Calibration Q Negative
+		side.
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@ -612,8 +612,8 @@
 	clocksource.max_cswd_read_retries= [KNL]
 			Number of clocksource_watchdog() retries due to
 			external delays before the clock will be marked
-			unstable.  Defaults to three retries, that is,
-			four attempts to read the clock under test.
+			unstable.  Defaults to two retries, that is,
+			three attempts to read the clock under test.

 	clocksource.verify_n_cpus= [KNL]
 			Limit the number of CPUs checked for clocksources
@ -3397,7 +3397,7 @@
 			Disable SMAP (Supervisor Mode Access Prevention)
 			even if it is supported by processor.

-	nosmep		[X86,PPC]
+	nosmep		[X86,PPC64s]
 			Disable SMEP (Supervisor Mode Execution Prevention)
 			even if it is supported by processor.

@ -4170,6 +4170,14 @@
 			Override pmtimer IOPort with a hex value.
 			e.g. pmtmr=0x508

+	pmu_override=	[PPC] Override the PMU.
+			This option takes over the PMU facility, so it is no
+			longer usable by perf. Setting this option starts the
+			PMU counters by setting MMCR0 to 0 (the FC bit is
+			cleared). If a number is given, then MMCR1 is set to
+			that number, otherwise (e.g., 'pmu_override=on'), MMCR1
+			remains 0.
+
 	pm_debug_messages	[SUSPEND,KNL]
 			Enable suspend/resume debug messages during boot up.

@ -6498,6 +6506,12 @@
 				  controller on both pseries and powernv
 				  platforms. Only useful on POWER9 and above.

+	xive.store-eoi=off	[PPC]
+			By default on POWER10 and above, the kernel will use
+			stores for EOI handling when the XIVE interrupt mode
+			is active. This option allows the XIVE driver to use
+			loads instead, as on POWER9.
+
 	xhci-hcd.quirks		[USB,KNL]
 			A hex value specifying bitmask with supplemental xhci
 			host controller quirks. Meaning of each bit can be
--- a/Documentation/devicetree/bindings/Makefile
+++ b/Documentation/devicetree/bindings/Makefile
@ -65,7 +65,9 @@ DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd)))
 override DTC_FLAGS := \
 	-Wno-avoid_unnecessary_addr_size \
 	-Wno-graph_child_address \
-	-Wno-interrupt_provider
+	-Wno-interrupt_provider \
+	-Wno-unique_unit_address \
+	-Wunique_unit_address_if_enabled

 # Disable undocumented compatible checks until warning free
 override DT_CHECKER_FLAGS ?=
--- a/Documentation/devicetree/bindings/arm/arm,cci-400.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,cci-400.yaml
@ -166,16 +166,6 @@ examples:
              };
          };

-          dma0: dma@3000000 {
-              /* compatible = "arm,pl330", "arm,primecell"; */
-              cci-control-port = <&cci_control0>;
-              reg = <0x0 0x3000000 0x0 0x1000>;
-              interrupts = <10>;
-              #dma-cells = <1>;
-              #dma-channels = <8>;
-              #dma-requests = <32>;
-          };
-
          cci@2c090000 {
              compatible = "arm,cci-400";
              #address-cells = <1>;
--- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
+++ b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
@ -1,27 +0,0 @@
-* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
-
-ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
-with a shared L3 memory system, control logic and external interfaces to
-form a multicore cluster. The PMU enables to gather various statistics on
-the operations of the DSU. The PMU provides independent 32bit counters that
-can count any of the supported events, along with a 64bit cycle counter.
-The PMU is accessed via CPU system registers and has no MMIO component.
-
-** DSU PMU required properties:
-
- compatible	: should be one of :
-
-		"arm,dsu-pmu"
-
- interrupts	: Exactly 1 SPI must be listed.
-
- cpus		: List of phandles for the CPUs connected to this DSU instance.
-
-
-** Example:
-
-dsu-pmu-0 {
-	compatible = "arm,dsu-pmu";
-	interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
-	cpus = <&cpu_0>, <&cpu_1>;
-};
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@ -137,6 +137,9 @@ properties:
      - arm,cortex-a75
      - arm,cortex-a76
      - arm,cortex-a77
+      - arm,cortex-a78
+      - arm,cortex-a510
+      - arm,cortex-a710
      - arm,cortex-m0
      - arm,cortex-m0+
      - arm,cortex-m1
@ -145,8 +148,12 @@ properties:
      - arm,cortex-r4
      - arm,cortex-r5
      - arm,cortex-r7
+      - arm,cortex-x1
+      - arm,cortex-x2
      - arm,neoverse-e1
      - arm,neoverse-n1
+      - arm,neoverse-n2
+      - arm,neoverse-v1
      - brcm,brahma-b15
      - brcm,brahma-b53
      - brcm,vulcan
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@ -14,6 +14,7 @@ Required Properties:
 	- "mediatek,mt7622-apmixedsys"
 	- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
 	- "mediatek,mt7629-apmixedsys"
+	- "mediatek,mt7986-apmixedsys"
 	- "mediatek,mt8135-apmixedsys"
 	- "mediatek,mt8167-apmixedsys", "syscon"
 	- "mediatek,mt8173-apmixedsys"
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
@ -10,6 +10,7 @@ Required Properties:
 	- "mediatek,mt7622-ethsys", "syscon"
 	- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
 	- "mediatek,mt7629-ethsys", "syscon"
+	- "mediatek,mt7986-ethsys", "syscon"
 - #clock-cells: Must be 1
 - #reset-cells: Must be 1

--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
@ -15,6 +15,7 @@ Required Properties:
 	- "mediatek,mt7622-infracfg", "syscon"
 	- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
 	- "mediatek,mt7629-infracfg", "syscon"
+	- "mediatek,mt7986-infracfg", "syscon"
 	- "mediatek,mt8135-infracfg", "syscon"
 	- "mediatek,mt8167-infracfg", "syscon"
 	- "mediatek,mt8173-infracfg", "syscon"
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
@ -8,6 +8,8 @@ Required Properties:
 - compatible: Should be:
 	- "mediatek,mt7622-sgmiisys", "syscon"
 	- "mediatek,mt7629-sgmiisys", "syscon"
+	- "mediatek,mt7986-sgmiisys_0", "syscon"
+	- "mediatek,mt7986-sgmiisys_1", "syscon"
 - #clock-cells: Must be 1

 The SGMIISYS controller uses the common clk binding from
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
@ -14,6 +14,7 @@ Required Properties:
 	- "mediatek,mt7622-topckgen"
 	- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
 	- "mediatek,mt7629-topckgen"
+	- "mediatek,mt7986-topckgen", "syscon"
 	- "mediatek,mt8135-topckgen"
 	- "mediatek,mt8167-topckgen", "syscon"
 	- "mediatek,mt8173-topckgen"
--- a/Documentation/devicetree/bindings/arm/pmu.yaml
+++ b/Documentation/devicetree/bindings/arm/pmu.yaml
@ -44,10 +44,18 @@ properties:
          - arm,cortex-a76-pmu
          - arm,cortex-a77-pmu
          - arm,cortex-a78-pmu
+          - arm,cortex-a510-pmu
+          - arm,cortex-a710-pmu
+          - arm,cortex-x1-pmu
+          - arm,cortex-x2-pmu
          - arm,neoverse-e1-pmu
          - arm,neoverse-n1-pmu
+          - arm,neoverse-n2-pmu
+          - arm,neoverse-v1-pmu
          - brcm,vulcan-pmu
          - cavium,thunder-pmu
+          - nvidia,denver-pmu
+          - nvidia,carmel-pmu
          - qcom,krait-pmu
          - qcom,scorpion-pmu
          - qcom,scorpion-mp-pmu
--- a/Documentation/devicetree/bindings/arm/ux500.yaml
+++ b/Documentation/devicetree/bindings/arm/ux500.yaml
@ -20,6 +20,11 @@ properties:
          - const: st-ericsson,mop500
          - const: st-ericsson,u8500

+      - description: ST-Ericsson HREF520
+        items:
+          - const: st-ericsson,href520
+          - const: st-ericsson,u8500
+
      - description: ST-Ericsson HREF (v60+)
        items:
          - const: st-ericsson,hrefv60+
@ -30,9 +35,34 @@ properties:
          - const: calaosystems,snowball-a9500
          - const: st-ericsson,u9500

+      - description: Samsung Galaxy Ace 2 (GT-I8160)
+        items:
+          - const: samsung,codina
+          - const: st-ericsson,u8500
+
+      - description: Samsung Galaxy Beam (GT-I8530)
+        items:
+          - const: samsung,gavini
+          - const: st-ericsson,u8500
+
      - description: Samsung Galaxy S III mini (GT-I8190)
        items:
          - const: samsung,golden
          - const: st-ericsson,u8500

+      - description: Samsung Galaxy S Advance (GT-I9070)
+        items:
+          - const: samsung,janice
+          - const: st-ericsson,u8500
+
+      - description: Samsung Galaxy Amp (SGH-I407)
+        items:
+          - const: samsung,kyle
+          - const: st-ericsson,u8500
+
+      - description: Samsung Galaxy XCover 2 (GT-S7710)
+        items:
+          - const: samsung,skomer
+          - const: st-ericsson,u8500
+
 additionalProperties: true
--- a/Documentation/devicetree/bindings/arm/xen.txt
+++ b/Documentation/devicetree/bindings/arm/xen.txt
@ -7,15 +7,17 @@ the following properties:
 	compatible = "xen,xen-<version>", "xen,xen";
  where <version> is the version of the Xen ABI of the platform.

- reg: specifies the base physical address and size of a region in
-  memory where the grant table should be mapped to, using an
-  HYPERVISOR_memory_op hypercall. The memory region is large enough to map
-  the whole grant table (it is larger or equal to gnttab_max_grant_frames()).
-  This property is unnecessary when booting Dom0 using ACPI.
+- reg: specifies the base physical address and size of the regions in memory
+  where the special resources should be mapped to, using an HYPERVISOR_memory_op
+  hypercall.
+  Region 0 is reserved for mapping grant table, it must be always present.
+  The memory region is large enough to map the whole grant table (it is larger
+  or equal to gnttab_max_grant_frames()).
+  Regions 1...N are extended regions (unused address space) for mapping foreign
+  GFNs and grants, they might be absent if there is nothing to expose.

 - interrupts: the interrupt used by Xen to inject event notifications.
  A GIC node is also required.
-  This property is unnecessary when booting Dom0 using ACPI.

 To support UEFI on Xen ARM virtual platforms, Xen populates the FDT "uefi" node
 under /hypervisor with following parameters:
--- a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
+++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
@ -1,45 +0,0 @@
-* Broadcom SATA3 AHCI Controller
-
-SATA nodes are defined to describe on-chip Serial ATA controllers.
-Each SATA controller should have its own node.
-
-Required properties:
- compatible         : should be one or more of
-			"brcm,bcm7216-ahci"
-			"brcm,bcm7425-ahci"
-			"brcm,bcm7445-ahci"
-			"brcm,bcm-nsp-ahci"
-			"brcm,sata3-ahci"
-			"brcm,bcm63138-ahci"
- reg                : register mappings for AHCI and SATA_TOP_CTRL
- reg-names          : "ahci" and "top-ctrl"
- interrupts         : interrupt mapping for SATA IRQ
-
-Optional properties:
-
- reset: for "brcm,bcm7216-ahci" must be a valid reset phandle
-  pointing to the RESCAL reset controller provider node.
- reset-names: for "brcm,bcm7216-ahci", must be "rescal".
-
-Also see ahci-platform.txt.
-
-Example:
-
-	sata@f045a000 {
-		compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
-		reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>;
-		reg-names = "ahci", "top-ctrl";
-		interrupts = <0 30 0>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		sata0: sata-port@0 {
-			reg = <0>;
-			phys = <&sata_phy 0>;
-		};
-
-		sata1: sata-port@1 {
-			reg = <1>;
-			phys = <&sata_phy 1>;
-		};
-	};
--- a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml
+++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml
@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom SATA3 AHCI Controller
+
+description:
+  SATA nodes are defined to describe on-chip Serial ATA controllers.
+  Each SATA controller should have its own node.
+
+maintainers:
+  - Florian Fainelli <f.fainelli@gmail.com>
+
+allOf:
+  - $ref: sata-common.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - brcm,bcm7216-ahci
+              - brcm,bcm7445-ahci
+              - brcm,bcm7425-ahci
+              - brcm,bcm63138-ahci
+          - const: brcm,sata3-ahci
+      - items:
+          - const: brcm,bcm-nsp-ahci
+
+  reg:
+    minItems: 2
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: ahci
+      - const: top-ctrl
+
+  interrupts:
+    maxItems: 1
+
+  dma-coherent: true
+
+if:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - brcm,bcm7216-ahci
+          - brcm,bcm63138-ahci
+then:
+  properties:
+    resets:
+      maxItems: 1
+    reset-names:
+      enum:
+        - rescal
+        - ahci
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - "#address-cells"
+  - "#size-cells"
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    sata@f045a000 {
+        compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
+        reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>;
+        reg-names = "ahci", "top-ctrl";
+        interrupts = <0 30 0>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        sata0: sata-port@0 {
+            reg = <0>;
+            phys = <&sata_phy 0>;
+        };
+
+        sata1: sata-port@1 {
+            reg = <1>;
+            phys = <&sata_phy 1>;
+        };
+    };
--- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
+++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
@ -1,34 +0,0 @@
-Broadcom GISB bus Arbiter controller
-
-Required properties:
-
- compatible:
-    "brcm,bcm7278-gisb-arb" for V7 28nm chips
-    "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips
-    "brcm,bcm7435-gisb-arb" for newer 40nm chips
-    "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
-    "brcm,bcm7038-gisb-arb" for 130nm chips
- reg: specifies the base physical address and size of the registers
- interrupts: specifies the two interrupts (timeout and TEA) to be used from
-  the parent interrupt controller. A third optional interrupt may be specified
-  for breakpoints.
-
-Optional properties:
-
- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB
-  masters are valid at the system level
- brcm,gisb-arb-master-names: string list of the litteral name of the GISB
-  masters. Should match the number of bits set in brcm,gisb-master-mask and
-  the order in which they appear
-
-Example:
-
-gisb-arb@f0400000 {
-	compatible = "brcm,gisb-arb";
-	reg = <0xf0400000 0x800>;
-	interrupts = <0>, <2>;
-	interrupt-parent = <&sun_l2_intc>;
-
-	brcm,gisb-arb-master-mask = <0x7>;
-	brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
-};
--- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml
+++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml
@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom GISB bus Arbiter controller
+
+maintainers:
+  - Florian Fainelli <f.fainelli@gmail.com>
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - brcm,bcm7445-gisb-arb  # for other 28nm chips
+          - const: brcm,gisb-arb
+      - items:
+          - enum:
+              - brcm,bcm7278-gisb-arb  # for V7 28nm chips
+              - brcm,bcm7435-gisb-arb  # for newer 40nm chips
+              - brcm,bcm7400-gisb-arb  # for older 40nm chips and all 65nm chips
+              - brcm,bcm7038-gisb-arb  # for 130nm chips
+              - brcm,gisb-arb          # fallback compatible
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    minItems: 2
+    items:
+      - description: timeout interrupt line
+      - description: target abort interrupt line
+      - description: breakpoint interrupt line
+
+  brcm,gisb-arb-master-mask:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: >
+      32-bits wide bitmask used to specify which GISB masters are valid at the
+      system level
+
+  brcm,gisb-arb-master-names:
+    $ref: /schemas/types.yaml#/definitions/string-array
+    description: >
+      String list of the litteral name of the GISB masters. Should match the
+      number of bits set in brcm,gisb-master-mask and the order in which they
+      appear from MSB to LSB.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    gisb-arb@f0400000 {
+      compatible = "brcm,gisb-arb";
+      reg = <0xf0400000 0x800>;
+      interrupts = <0>, <2>;
+      interrupt-parent = <&sun_l2_intc>;
+      brcm,gisb-arb-master-mask = <0x7>;
+      brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
+    };
--- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
+++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
@ -34,6 +34,8 @@ properties:
      - allwinner,sun8i-v3-ccu
      - allwinner,sun8i-v3s-ccu
      - allwinner,sun9i-a80-ccu
+      - allwinner,sun20i-d1-ccu
+      - allwinner,sun20i-d1-r-ccu
      - allwinner,sun50i-a64-ccu
      - allwinner,sun50i-a64-r-ccu
      - allwinner,sun50i-a100-ccu
@ -79,6 +81,7 @@ if:
      enum:
        - allwinner,sun8i-a83t-r-ccu
        - allwinner,sun8i-h3-r-ccu
+        - allwinner,sun20i-d1-r-ccu
        - allwinner,sun50i-a64-r-ccu
        - allwinner,sun50i-a100-r-ccu
        - allwinner,sun50i-h6-r-ccu
@ -99,6 +102,7 @@ else:
    properties:
      compatible:
        enum:
+          - allwinner,sun20i-d1-ccu
          - allwinner,sun50i-a100-ccu
          - allwinner,sun50i-h6-ccu
          - allwinner,sun50i-h616-ccu
--- a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
@ -1,190 +0,0 @@
-* Samsung Exynos5260 Clock Controller
-
-Exynos5260 has 13 clock controllers which are instantiated
-independently from the device-tree. These clock controllers
-generate and supply clocks to various hardware blocks within
-the SoC.
-
-Each clock is assigned an identifier and client nodes can use
-this identifier to specify the clock which they consume. All
-available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos5260-clk.h header and can be used in
-device tree sources.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It
-is expected that they are defined using standard clock bindings
-with following clock-output-names:
-
- - "fin_pll" - PLL input clock from XXTI
- - "xrtcxti" - input clock from XRTCXTI
- - "ioclk_pcm_extclk" - pcm external operation clock
- - "ioclk_spdif_extclk" - spdif external operation clock
- - "ioclk_i2s_cdclk" - i2s0 codec clock
-
-Phy clocks:
-
-There are several clocks which are generated by specific PHYs.
-These clocks are fed into the clock controller and then routed to
-the hardware blocks. These clocks are defined as fixed clocks in the
-driver with following names:
-
- - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
- - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
- - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
- - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
- - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
- - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
- - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
- - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
- - "phyclk_dptx_phy_clk_div2"
- - "phyclk_mipi_dphy_4l_m_rxclkesc0"
- - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
- - "phyclk_usbhost20_phy_freeclk"
- - "phyclk_usbhost20_phy_clk48mohci"
- - "phyclk_usbdrd30_udrd30_pipe_pclk"
- - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
-
-Required Properties for Clock Controller:
-
- - compatible: should be one of the following.
-	1) "samsung,exynos5260-clock-top"
-	2) "samsung,exynos5260-clock-peri"
-	3) "samsung,exynos5260-clock-egl"
-	4) "samsung,exynos5260-clock-kfc"
-	5) "samsung,exynos5260-clock-g2d"
-	6) "samsung,exynos5260-clock-mif"
-	7) "samsung,exynos5260-clock-mfc"
-	8) "samsung,exynos5260-clock-g3d"
-	9) "samsung,exynos5260-clock-fsys"
-	10) "samsung,exynos5260-clock-aud"
-	11) "samsung,exynos5260-clock-isp"
-	12) "samsung,exynos5260-clock-gscl"
-	13) "samsung,exynos5260-clock-disp"
-
- - reg: physical base address of the controller and the length of
-	memory mapped region.
-
- - #clock-cells: should be 1.
-
- - clocks: list of clock identifiers which are fed as the input to
-	the given clock controller. Please refer the next section to find
-	the input clocks for a given controller.
-
- - clock-names: list of names of clocks which are fed as the input
-	to the given clock controller.
-
-Input clocks for top clock controller:
-	- fin_pll
-	- dout_mem_pll
-	- dout_bus_pll
-	- dout_media_pll
-
-Input clocks for peri clock controller:
-	- fin_pll
-	- ioclk_pcm_extclk
-	- ioclk_i2s_cdclk
-	- ioclk_spdif_extclk
-	- phyclk_hdmi_phy_ref_cko
-	- dout_aclk_peri_66
-	- dout_sclk_peri_uart0
-	- dout_sclk_peri_uart1
-	- dout_sclk_peri_uart2
-	- dout_sclk_peri_spi0_b
-	- dout_sclk_peri_spi1_b
-	- dout_sclk_peri_spi2_b
-	- dout_aclk_peri_aud
-	- dout_sclk_peri_spi0_b
-
-Input clocks for egl clock controller:
-	- fin_pll
-	- dout_bus_pll
-
-Input clocks for kfc clock controller:
-	- fin_pll
-	- dout_media_pll
-
-Input clocks for g2d clock controller:
-	- fin_pll
-	- dout_aclk_g2d_333
-
-Input clocks for mif clock controller:
-	- fin_pll
-
-Input clocks for mfc clock controller:
-	- fin_pll
-	- dout_aclk_mfc_333
-
-Input clocks for g3d clock controller:
-	- fin_pll
-
-Input clocks for fsys clock controller:
-	- fin_pll
-	- phyclk_usbhost20_phy_phyclock
-	- phyclk_usbhost20_phy_freeclk
-	- phyclk_usbhost20_phy_clk48mohci
-	- phyclk_usbdrd30_udrd30_pipe_pclk
-	- phyclk_usbdrd30_udrd30_phyclock
-	- dout_aclk_fsys_200
-
-Input clocks for aud clock controller:
-	- fin_pll
-	- fout_aud_pll
-	- ioclk_i2s_cdclk
-	- ioclk_pcm_extclk
-
-Input clocks for isp clock controller:
-	- fin_pll
-	- dout_aclk_isp1_266
-	- dout_aclk_isp1_400
-	- mout_aclk_isp1_266
-
-Input clocks for gscl clock controller:
-	- fin_pll
-	- dout_aclk_gscl_400
-	- dout_aclk_gscl_333
-
-Input clocks for disp clock controller:
-	- fin_pll
-	- phyclk_dptx_phy_ch3_txd_clk
-	- phyclk_dptx_phy_ch2_txd_clk
-	- phyclk_dptx_phy_ch1_txd_clk
-	- phyclk_dptx_phy_ch0_txd_clk
-	- phyclk_hdmi_phy_tmds_clko
-	- phyclk_hdmi_phy_ref_clko
-	- phyclk_hdmi_phy_pixel_clko
-	- phyclk_hdmi_link_o_tmds_clkhi
-	- phyclk_mipi_dphy_4l_m_txbyte_clkhs
-	- phyclk_dptx_phy_o_ref_clk_24m
-	- phyclk_dptx_phy_clk_div2
-	- phyclk_mipi_dphy_4l_m_rxclkesc0
-	- phyclk_hdmi_phy_ref_cko
-	- ioclk_spdif_extclk
-	- dout_aclk_peri_aud
-	- dout_aclk_disp_222
-	- dout_sclk_disp_pixel
-	- dout_aclk_disp_333
-
-Example 1: An example of a clock controller node is listed below.
-
-	clock_mfc: clock-controller@11090000 {
-		compatible = "samsung,exynos5260-clock-mfc";
-		clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>;
-		clock-names = "fin_pll", "dout_aclk_mfc_333";
-		reg = <0x11090000 0x10000>;
-		#clock-cells = <1>;
-	};
-
-Example 2: UART controller node that consumes the clock generated by the
-		peri clock controller. Refer to the standard clock bindings for
-		information about 'clocks' and 'clock-names' property.
-
-	serial@12c00000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x12C00000 0x100>;
-		interrupts = <0 146 0>;
-		clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
-		clock-names = "uart", "clk_uart_baud0";
-	};
-
--- a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@ -1,50 +0,0 @@
-* Samsung Exynos5410 Clock Controller
-
-The Exynos5410 clock controller generates and supplies clock to various
-controllers within the Exynos5410 SoC.
-
-Required Properties:
-
- compatible: should be "samsung,exynos5410-clock"
-
- reg: physical base address of the controller and length of memory mapped
-  region.
-
- #clock-cells: should be 1.
-
- clocks: should contain an entry specifying the root clock from external
-  oscillator supplied through XXTI or XusbXTI pin.  This clock should be
-  defined using standard clock bindings with "fin_pll" clock-output-name.
-  That clock is being passed internally to the 9 PLLs.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos5410.h header and can be used in device
-tree sources.
-
-Example 1: An example of a clock controller node is listed below.
-
-	fin_pll: xxti {
-		compatible = "fixed-clock";
-		clock-frequency = <24000000>;
-		clock-output-names = "fin_pll";
-		#clock-cells = <0>;
-	};
-
-	clock: clock-controller@10010000 {
-		compatible = "samsung,exynos5410-clock";
-		reg = <0x10010000 0x30000>;
-		#clock-cells = <1>;
-		clocks = <&fin_pll>;
-	};
-
-Example 2: UART controller node that consumes the clock generated by the clock
-	   controller. Refer to the standard clock bindings for information
-	   about 'clocks' and 'clock-names' property.
-
-	serial@12c20000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x12C00000 0x100>;
-		interrupts = <0 51 0>;
-		clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
-		clock-names = "uart", "clk_uart_baud0";
-	};
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@ -1,507 +0,0 @@
-* Samsung Exynos5433 CMU (Clock Management Units)
-
-The Exynos5433 clock controller generates and supplies clock to various
-controllers within the Exynos5433 SoC.
-
-Required Properties:
-
- compatible: should be one of the following.
-  - "samsung,exynos5433-cmu-top"   - clock controller compatible for CMU_TOP
-    which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
-    domains and bus clocks.
-  - "samsung,exynos5433-cmu-cpif"  - clock controller compatible for CMU_CPIF
-    which generates clocks for LLI (Low Latency Interface) IP.
-  - "samsung,exynos5433-cmu-mif"   - clock controller compatible for CMU_MIF
-    which generates clocks for DRAM Memory Controller domain.
-  - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
-    which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
-  - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
-    which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
-  - "samsung,exynos5433-cmu-fsys"  - clock controller compatible for CMU_FSYS
-    which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
-  - "samsung,exynos5433-cmu-g2d"   - clock controller compatible for CMU_G2D
-    which generates clocks for G2D/MDMA IPs.
-  - "samsung,exynos5433-cmu-disp"  - clock controller compatible for CMU_DISP
-    which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
-  - "samsung,exynos5433-cmu-aud"   - clock controller compatible for CMU_AUD
-    which generates clocks for Cortex-A5/BUS/AUDIO clocks.
-  - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
-    and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
-    which generates global data buses clock and global peripheral buses clock.
-  - "samsung,exynos5433-cmu-g3d"  - clock controller compatible for CMU_G3D
-    which generates clocks for 3D Graphics Engine IP.
-  - "samsung,exynos5433-cmu-gscl"  - clock controller compatible for CMU_GSCL
-    which generates clocks for GSCALER IPs.
-  - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
-    which generates clocks for Cortex-A53 Quad-core processor.
-  - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
-    which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
-    L2 cache controller.
-  - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
-    which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
-  - "samsung,exynos5433-cmu-mfc"  - clock controller compatible for CMU_MFC
-    which generates clocks for MFC(Multi-Format Codec) IP.
-  - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
-    which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
-  - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
-    which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
-  - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
-    which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
-    IPs.
-  - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
-    which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
-  - "samsung,exynos5433-cmu-imem"   - clock controller compatible for CMU_IMEM
-    which generates clocks for SSS (Security SubSystem) and SlimSSS IPs.
-
- reg: physical base address of the controller and length of memory mapped
-  region.
-
- #clock-cells: should be 1.
-
- clocks: list of the clock controller input clock identifiers,
-	from common clock bindings. Please refer the next section
-	to find the input clocks for a given controller.
-
- clock-names: list of the clock controller input clock names,
-	as described in clock-bindings.txt.
-
-	Input clocks for top clock controller:
-		- oscclk
-		- sclk_mphy_pll
-		- sclk_mfc_pll
-		- sclk_bus_pll
-
-	Input clocks for cpif clock controller:
-		- oscclk
-
-	Input clocks for mif clock controller:
-		- oscclk
-		- sclk_mphy_pll
-
-	Input clocks for fsys clock controller:
-		- oscclk
-		- sclk_ufs_mphy
-		- aclk_fsys_200
-		- sclk_pcie_100_fsys
-		- sclk_ufsunipro_fsys
-		- sclk_mmc2_fsys
-		- sclk_mmc1_fsys
-		- sclk_mmc0_fsys
-		- sclk_usbhost30_fsys
-		- sclk_usbdrd30_fsys
-
-	Input clocks for g2d clock controller:
-		- oscclk
-		- aclk_g2d_266
-		- aclk_g2d_400
-
-	Input clocks for disp clock controller:
-		- oscclk
-		- sclk_dsim1_disp
-		- sclk_dsim0_disp
-		- sclk_dsd_disp
-		- sclk_decon_tv_eclk_disp
-		- sclk_decon_vclk_disp
-		- sclk_decon_eclk_disp
-		- sclk_decon_tv_vclk_disp
-		- aclk_disp_333
-
-	Input clocks for audio clock controller:
-		- oscclk
-		- fout_aud_pll
-
-	Input clocks for bus0 clock controller:
-		- aclk_bus0_400
-
-	Input clocks for bus1 clock controller:
-		- aclk_bus1_400
-
-	Input clocks for bus2 clock controller:
-		- oscclk
-		- aclk_bus2_400
-
-	Input clocks for g3d clock controller:
-		- oscclk
-		- aclk_g3d_400
-
-	Input clocks for gscl clock controller:
-		- oscclk
-		- aclk_gscl_111
-		- aclk_gscl_333
-
-	Input clocks for apollo clock controller:
-		- oscclk
-		- sclk_bus_pll_apollo
-
-	Input clocks for atlas clock controller:
-		- oscclk
-		- sclk_bus_pll_atlas
-
-	Input clocks for mscl clock controller:
-		- oscclk
-		- sclk_jpeg_mscl
-		- aclk_mscl_400
-
-	Input clocks for mfc clock controller:
-		- oscclk
-		- aclk_mfc_400
-
-	Input clocks for hevc clock controller:
-		- oscclk
-		- aclk_hevc_400
-
-	Input clocks for isp clock controller:
-		- oscclk
-		- aclk_isp_dis_400
-		- aclk_isp_400
-
-	Input clocks for cam0 clock controller:
-		- oscclk
-		- aclk_cam0_333
-		- aclk_cam0_400
-		- aclk_cam0_552
-
-	Input clocks for cam1 clock controller:
-		- oscclk
-		- sclk_isp_uart_cam1
-		- sclk_isp_spi1_cam1
-		- sclk_isp_spi0_cam1
-		- aclk_cam1_333
-		- aclk_cam1_400
-		- aclk_cam1_552
-
-	Input clocks for imem clock controller:
-		- oscclk
-		- aclk_imem_sssx_266
-		- aclk_imem_266
-		- aclk_imem_200
-
-Optional properties:
-  - power-domains: a phandle to respective power domain node as described by
-	generic PM domain bindings (see power/power_domain.txt for more
-	information).
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos5433.h header and can be used in device
-tree sources.
-
-Example 1: Examples of 'oscclk' source clock node are listed below.
-
-	xxti: xxti {
-		compatible = "fixed-clock";
-		clock-output-names = "oscclk";
-		#clock-cells = <0>;
-	};
-
-Example 2: Examples of clock controller nodes are listed below.
-
-	cmu_top: clock-controller@10030000 {
-		compatible = "samsung,exynos5433-cmu-top";
-		reg = <0x10030000 0x0c04>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk",
-			"sclk_mphy_pll",
-			"sclk_mfc_pll",
-			"sclk_bus_pll";
-		clocks = <&xxti>,
-		       <&cmu_cpif CLK_SCLK_MPHY_PLL>,
-		       <&cmu_mif CLK_SCLK_MFC_PLL>,
-		       <&cmu_mif CLK_SCLK_BUS_PLL>;
-	};
-
-	cmu_cpif: clock-controller@10fc0000 {
-		compatible = "samsung,exynos5433-cmu-cpif";
-		reg = <0x10fc0000 0x0c04>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk";
-		clocks = <&xxti>;
-	};
-
-	cmu_mif: clock-controller@105b0000 {
-		compatible = "samsung,exynos5433-cmu-mif";
-		reg = <0x105b0000 0x100c>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk",
-			"sclk_mphy_pll";
-		clocks = <&xxti>,
-		       <&cmu_cpif CLK_SCLK_MPHY_PLL>;
-	};
-
-	cmu_peric: clock-controller@14c80000 {
-		compatible = "samsung,exynos5433-cmu-peric";
-		reg = <0x14c80000 0x0b08>;
-		#clock-cells = <1>;
-	};
-
-	cmu_peris: clock-controller@10040000 {
-		compatible = "samsung,exynos5433-cmu-peris";
-		reg = <0x10040000 0x0b20>;
-		#clock-cells = <1>;
-	};
-
-	cmu_fsys: clock-controller@156e0000 {
-		compatible = "samsung,exynos5433-cmu-fsys";
-		reg = <0x156e0000 0x0b04>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk",
-			"sclk_ufs_mphy",
-			"aclk_fsys_200",
-			"sclk_pcie_100_fsys",
-			"sclk_ufsunipro_fsys",
-			"sclk_mmc2_fsys",
-			"sclk_mmc1_fsys",
-			"sclk_mmc0_fsys",
-			"sclk_usbhost30_fsys",
-			"sclk_usbdrd30_fsys";
-		clocks = <&xxti>,
-		       <&cmu_cpif CLK_SCLK_UFS_MPHY>,
-		       <&cmu_top CLK_ACLK_FSYS_200>,
-		       <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
-		       <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
-		       <&cmu_top CLK_SCLK_MMC2_FSYS>,
-		       <&cmu_top CLK_SCLK_MMC1_FSYS>,
-		       <&cmu_top CLK_SCLK_MMC0_FSYS>,
-		       <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
-		       <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
-	};
-
-	cmu_g2d: clock-controller@12460000 {
-		compatible = "samsung,exynos5433-cmu-g2d";
-		reg = <0x12460000 0x0b08>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk",
-			"aclk_g2d_266",
-			"aclk_g2d_400";
-		clocks = <&xxti>,
-		       <&cmu_top CLK_ACLK_G2D_266>,
-		       <&cmu_top CLK_ACLK_G2D_400>;
-		power-domains = <&pd_g2d>;
-	};
-
-	cmu_disp: clock-controller@13b90000 {
-		compatible = "samsung,exynos5433-cmu-disp";
-		reg = <0x13b90000 0x0c04>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk",
-			"sclk_dsim1_disp",
-			"sclk_dsim0_disp",
-			"sclk_dsd_disp",
-			"sclk_decon_tv_eclk_disp",
-			"sclk_decon_vclk_disp",
-			"sclk_decon_eclk_disp",
-			"sclk_decon_tv_vclk_disp",
-			"aclk_disp_333";
-		clocks = <&xxti>,
-		       <&cmu_mif CLK_SCLK_DSIM1_DISP>,
-		       <&cmu_mif CLK_SCLK_DSIM0_DISP>,
-		       <&cmu_mif CLK_SCLK_DSD_DISP>,
-		       <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
-		       <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
-		       <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
-		       <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
-		       <&cmu_mif CLK_ACLK_DISP_333>;
-		power-domains = <&pd_disp>;
-	};
-
-	cmu_aud: clock-controller@114c0000 {
-		compatible = "samsung,exynos5433-cmu-aud";
-		reg = <0x114c0000 0x0b04>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk", "fout_aud_pll";
-		clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
-		power-domains = <&pd_aud>;
-	};
-
-	cmu_bus0: clock-controller@13600000 {
-		compatible = "samsung,exynos5433-cmu-bus0";
-		reg = <0x13600000 0x0b04>;
-		#clock-cells = <1>;
-
-		clock-names = "aclk_bus0_400";
-		clocks = <&cmu_top CLK_ACLK_BUS0_400>;
-	};
-
-	cmu_bus1: clock-controller@14800000 {
-		compatible = "samsung,exynos5433-cmu-bus1";
-		reg = <0x14800000 0x0b04>;
-		#clock-cells = <1>;
-
-		clock-names = "aclk_bus1_400";
-		clocks = <&cmu_top CLK_ACLK_BUS1_400>;
-	};
-
-	cmu_bus2: clock-controller@13400000 {
-		compatible = "samsung,exynos5433-cmu-bus2";
-		reg = <0x13400000 0x0b04>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk", "aclk_bus2_400";
-		clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
-	};
-
-	cmu_g3d: clock-controller@14aa0000 {
-		compatible = "samsung,exynos5433-cmu-g3d";
-		reg = <0x14aa0000 0x1000>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk", "aclk_g3d_400";
-		clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
-		power-domains = <&pd_g3d>;
-	};
-
-	cmu_gscl: clock-controller@13cf0000 {
-		compatible = "samsung,exynos5433-cmu-gscl";
-		reg = <0x13cf0000 0x0b10>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk",
-			"aclk_gscl_111",
-			"aclk_gscl_333";
-		clocks = <&xxti>,
-			<&cmu_top CLK_ACLK_GSCL_111>,
-			<&cmu_top CLK_ACLK_GSCL_333>;
-		power-domains = <&pd_gscl>;
-	};
-
-	cmu_apollo: clock-controller@11900000 {
-		compatible = "samsung,exynos5433-cmu-apollo";
-		reg = <0x11900000 0x1088>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk", "sclk_bus_pll_apollo";
-		clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
-	};
-
-	cmu_atlas: clock-controller@11800000 {
-		compatible = "samsung,exynos5433-cmu-atlas";
-		reg = <0x11800000 0x1088>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk", "sclk_bus_pll_atlas";
-		clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
-	};
-
-	cmu_mscl: clock-controller@105d0000 {
-		compatible = "samsung,exynos5433-cmu-mscl";
-		reg = <0x105d0000 0x0b10>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk",
-			"sclk_jpeg_mscl",
-			"aclk_mscl_400";
-		clocks = <&xxti>,
-		       <&cmu_top CLK_SCLK_JPEG_MSCL>,
-		       <&cmu_top CLK_ACLK_MSCL_400>;
-		power-domains = <&pd_mscl>;
-	};
-
-	cmu_mfc: clock-controller@15280000 {
-		compatible = "samsung,exynos5433-cmu-mfc";
-		reg = <0x15280000 0x0b08>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk", "aclk_mfc_400";
-		clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
-		power-domains = <&pd_mfc>;
-	};
-
-	cmu_hevc: clock-controller@14f80000 {
-		compatible = "samsung,exynos5433-cmu-hevc";
-		reg = <0x14f80000 0x0b08>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk", "aclk_hevc_400";
-		clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
-		power-domains = <&pd_hevc>;
-	};
-
-	cmu_isp: clock-controller@146d0000 {
-		compatible = "samsung,exynos5433-cmu-isp";
-		reg = <0x146d0000 0x0b0c>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk",
-			"aclk_isp_dis_400",
-			"aclk_isp_400";
-		clocks = <&xxti>,
-		       <&cmu_top CLK_ACLK_ISP_DIS_400>,
-		       <&cmu_top CLK_ACLK_ISP_400>;
-		power-domains = <&pd_isp>;
-	};
-
-	cmu_cam0: clock-controller@120d0000 {
-		compatible = "samsung,exynos5433-cmu-cam0";
-		reg = <0x120d0000 0x0b0c>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk",
-			"aclk_cam0_333",
-			"aclk_cam0_400",
-			"aclk_cam0_552";
-		clocks = <&xxti>,
-		       <&cmu_top CLK_ACLK_CAM0_333>,
-		       <&cmu_top CLK_ACLK_CAM0_400>,
-		       <&cmu_top CLK_ACLK_CAM0_552>;
-		power-domains = <&pd_cam0>;
-	};
-
-	cmu_cam1: clock-controller@145d0000 {
-		compatible = "samsung,exynos5433-cmu-cam1";
-		reg = <0x145d0000 0x0b08>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk",
-			"sclk_isp_uart_cam1",
-			"sclk_isp_spi1_cam1",
-			"sclk_isp_spi0_cam1",
-			"aclk_cam1_333",
-			"aclk_cam1_400",
-			"aclk_cam1_552";
-		clocks = <&xxti>,
-		       <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
-		       <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
-		       <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
-		       <&cmu_top CLK_ACLK_CAM1_333>,
-		       <&cmu_top CLK_ACLK_CAM1_400>,
-		       <&cmu_top CLK_ACLK_CAM1_552>;
-		power-domains = <&pd_cam1>;
-	};
-
-	cmu_imem: clock-controller@11060000 {
-		compatible = "samsung,exynos5433-cmu-imem";
-		reg = <0x11060000 0x1000>;
-		#clock-cells = <1>;
-
-		clock-names = "oscclk",
-			"aclk_imem_sssx_266",
-			"aclk_imem_266",
-			"aclk_imem_200";
-		clocks = <&xxti>,
-			<&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
-			<&cmu_top CLK_DIV_ACLK_IMEM_266>,
-			<&cmu_top CLK_DIV_ACLK_IMEM_200>;
-	};
-
-Example 3: UART controller node that consumes the clock generated by the clock
-	   controller.
-
-	serial_0: serial@14c10000 {
-		compatible = "samsung,exynos5433-uart";
-		reg = <0x14C10000 0x100>;
-		interrupts = <0 421 0>;
-		clocks = <&cmu_peric CLK_PCLK_UART0>,
-			 <&cmu_peric CLK_SCLK_UART0>;
-		clock-names = "uart", "clk_uart_baud0";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart0_bus>;
-	};
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@ -1,108 +0,0 @@
-* Samsung Exynos7 Clock Controller
-
-Exynos7 clock controller has various blocks which are instantiated
-independently from the device-tree. These clock controllers
-generate and supply clocks to various hardware blocks within
-the SoC.
-
-Each clock is assigned an identifier and client nodes can use
-this identifier to specify the clock which they consume. All
-available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos7-clk.h header and can be used in
-device tree sources.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It
-is expected that they are defined using standard clock bindings
-with following clock-output-names:
-
- - "fin_pll" - PLL input clock from XXTI
-
-Required Properties for Clock Controller:
-
- - compatible: clock controllers will use one of the following
-	compatible strings to indicate the clock controller
-	functionality.
-
-	- "samsung,exynos7-clock-topc"
-	- "samsung,exynos7-clock-top0"
-	- "samsung,exynos7-clock-top1"
-	- "samsung,exynos7-clock-ccore"
-	- "samsung,exynos7-clock-peric0"
-	- "samsung,exynos7-clock-peric1"
-	- "samsung,exynos7-clock-peris"
-	- "samsung,exynos7-clock-fsys0"
-	- "samsung,exynos7-clock-fsys1"
-	- "samsung,exynos7-clock-mscl"
-	- "samsung,exynos7-clock-aud"
-
- - reg: physical base address of the controller and the length of
-	memory mapped region.
-
- - #clock-cells: should be 1.
-
- - clocks: list of clock identifiers which are fed as the input to
-	the given clock controller. Please refer the next section to
-	find the input clocks for a given controller.
-
- clock-names: list of names of clocks which are fed as the input
-	to the given clock controller.
-
-Input clocks for top0 clock controller:
-	- fin_pll
-	- dout_sclk_bus0_pll
-	- dout_sclk_bus1_pll
-	- dout_sclk_cc_pll
-	- dout_sclk_mfc_pll
-	- dout_sclk_aud_pll
-
-Input clocks for top1 clock controller:
-	- fin_pll
-	- dout_sclk_bus0_pll
-	- dout_sclk_bus1_pll
-	- dout_sclk_cc_pll
-	- dout_sclk_mfc_pll
-
-Input clocks for ccore clock controller:
-	- fin_pll
-	- dout_aclk_ccore_133
-
-Input clocks for peric0 clock controller:
-	- fin_pll
-	- dout_aclk_peric0_66
-	- sclk_uart0
-
-Input clocks for peric1 clock controller:
-	- fin_pll
-	- dout_aclk_peric1_66
-	- sclk_uart1
-	- sclk_uart2
-	- sclk_uart3
-	- sclk_spi0
-	- sclk_spi1
-	- sclk_spi2
-	- sclk_spi3
-	- sclk_spi4
-	- sclk_i2s1
-	- sclk_pcm1
-	- sclk_spdif
-
-Input clocks for peris clock controller:
-	- fin_pll
-	- dout_aclk_peris_66
-
-Input clocks for fsys0 clock controller:
-	- fin_pll
-	- dout_aclk_fsys0_200
-	- dout_sclk_mmc2
-
-Input clocks for fsys1 clock controller:
-	- fin_pll
-	- dout_aclk_fsys1_200
-	- dout_sclk_mmc0
-	- dout_sclk_mmc1
-
-Input clocks for aud clock controller:
-	- fin_pll
-	- fout_aud_pll
--- a/Documentation/devicetree/bindings/clock/imx5-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.yaml
@ -55,11 +55,4 @@ examples:
                     <0 72 IRQ_TYPE_LEVEL_HIGH>;
        #clock-cells = <1>;
    };
-
-    can@53fc8000 {
-        compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
-        reg = <0x53fc8000 0x4000>;
-        interrupts = <82>;
-        clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
-        clock-names = "ipg", "per";
-    };
+...
--- a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
+++ b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip LAN966X Generic Clock Controller
+
+maintainers:
+  - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
+
+description: |
+  The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
+  ddr_clk and sys_clk. This clock controller generates and supplies
+  clock to various peripherals within the SoC.
+
+properties:
+  compatible:
+    const: microchip,lan966x-gck
+
+  reg:
+    minItems: 1
+    items:
+      - description: Generic clock registers
+      - description: Optional gate clock registers
+
+  clocks:
+    items:
+      - description: CPU clock source
+      - description: DDR clock source
+      - description: System clock source
+
+  clock-names:
+    items:
+      - const: cpu
+      - const: ddr
+      - const: sys
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clks: clock-controller@e00c00a8 {
+        compatible = "microchip,lan966x-gck";
+        #clock-cells = <1>;
+        clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
+        clock-names = "cpu", "ddr", "sys";
+        reg = <0xe00c00a8 0x38>;
+    };
+...
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for MSM8976
+
+maintainers:
+  - Stephen Boyd <sboyd@kernel.org>
+  - Taniya Das <tdas@codeaurora.org>
+
+description: |
+  Qualcomm global clock control module which supports the clocks, resets and
+  power domains on MSM8976.
+
+  See also:
+  - dt-bindings/clock/qcom,gcc-msm8976.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,gcc-msm8976
+      - qcom,gcc-msm8976-v1.1
+
+  clocks:
+    items:
+      - description: XO source
+      - description: Always-on XO source
+      - description: Pixel clock from DSI PHY0
+      - description: Byte clock from DSI PHY0
+      - description: Pixel clock from DSI PHY1
+      - description: Byte clock from DSI PHY1
+
+  clock-names:
+    items:
+      - const: xo
+      - const: xo_a
+      - const: dsi0pll
+      - const: dsi0pllbyte
+      - const: dsi1pll
+      - const: dsi1pllbyte
+
+  vdd_gfx-supply:
+    description:
+      Phandle to voltage regulator providing power to the GX domain.
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - vdd_gfx-supply
+  - '#clock-cells'
+  - '#reset-cells'
+  - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@1800000 {
+      compatible = "qcom,gcc-msm8976";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+      reg = <0x1800000 0x80000>;
+
+      clocks = <&xo_board>,
+               <&xo_board>,
+               <&dsi0_phy 1>,
+               <&dsi0_phy 0>,
+               <&dsi1_phy 1>,
+               <&dsi1_phy 0>;
+
+      clock-names = "xo",
+                    "xo_a",
+                    "dsi0pll",
+                    "dsi0pllbyte",
+                    "dsi1pll",
+                    "dsi1pllbyte";
+
+      vdd_gfx-supply = <&pm8004_s5>;
+    };
+...
--- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
@ -22,10 +22,12 @@ properties:
      - qcom,sc8180x-rpmh-clk
      - qcom,sdm845-rpmh-clk
      - qcom,sdx55-rpmh-clk
+      - qcom,sdx65-rpmh-clk
      - qcom,sm6350-rpmh-clk
      - qcom,sm8150-rpmh-clk
      - qcom,sm8250-rpmh-clk
      - qcom,sm8350-rpmh-clk
+      - qcom,sm8450-rpmh-clk

  clocks:
    maxItems: 1
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
@ -48,6 +48,7 @@ properties:
      - renesas,r8a77990-cpg-mssr # R-Car E3
      - renesas,r8a77995-cpg-mssr # R-Car D3
      - renesas,r8a779a0-cpg-mssr # R-Car V3U
+      - renesas,r8a779f0-cpg-mssr # R-Car S4-8

  reg:
    maxItems: 1
--- a/Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml
@ -0,0 +1,382 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos5260 SoC clock controller
+
+maintainers:
+  - Chanwoo Choi <cw00.choi@samsung.com>
+  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+  - Sylwester Nawrocki <s.nawrocki@samsung.com>
+  - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+  Expected external clocks, defined in DTS as fixed-rate clocks with a matching
+  name::
+    - "fin_pll" - PLL input clock from XXTI
+    - "xrtcxti" - input clock from XRTCXTI
+    - "ioclk_pcm_extclk" - pcm external operation clock
+    - "ioclk_spdif_extclk" - spdif external operation clock
+    - "ioclk_i2s_cdclk" - i2s0 codec clock
+
+  Phy clocks::
+  There are several clocks which are generated by specific PHYs.  These clocks
+  are fed into the clock controller and then routed to the hardware blocks.
+  These clocks are defined as fixed clocks in the driver with following names::
+    - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
+    - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
+    - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
+    - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
+    - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
+    - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
+    - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
+    - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
+    - "phyclk_dptx_phy_clk_div2"
+    - "phyclk_mipi_dphy_4l_m_rxclkesc0"
+    - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
+    - "phyclk_usbhost20_phy_freeclk"
+    - "phyclk_usbhost20_phy_clk48mohci"
+    - "phyclk_usbdrd30_udrd30_pipe_pclk"
+    - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
+
+  All available clocks are defined as preprocessor macros in
+  include/dt-bindings/clock/exynos5260-clk.h header.
+
+properties:
+  compatible:
+    enum:
+      - samsung,exynos5260-clock-top
+      - samsung,exynos5260-clock-peri
+      - samsung,exynos5260-clock-egl
+      - samsung,exynos5260-clock-kfc
+      - samsung,exynos5260-clock-g2d
+      - samsung,exynos5260-clock-mif
+      - samsung,exynos5260-clock-mfc
+      - samsung,exynos5260-clock-g3d
+      - samsung,exynos5260-clock-fsys
+      - samsung,exynos5260-clock-aud
+      - samsung,exynos5260-clock-isp
+      - samsung,exynos5260-clock-gscl
+      - samsung,exynos5260-clock-disp
+
+  clocks:
+    minItems: 1
+    maxItems: 19
+
+  clock-names:
+    minItems: 1
+    maxItems: 19
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - "#clock-cells"
+  - reg
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5260-clock-top
+    then:
+      properties:
+        clocks:
+          minItems: 4
+          maxItems: 4
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_mem_pll
+            - const: dout_bus_pll
+            - const: dout_media_pll
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5260-clock-peri
+    then:
+      properties:
+        clocks:
+          minItems: 13
+          maxItems: 13
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: ioclk_pcm_extclk
+            - const: ioclk_i2s_cdclk
+            - const: ioclk_spdif_extclk
+            - const: phyclk_hdmi_phy_ref_cko
+            - const: dout_aclk_peri_66
+            - const: dout_sclk_peri_uart0
+            - const: dout_sclk_peri_uart1
+            - const: dout_sclk_peri_uart2
+            - const: dout_sclk_peri_spi0_b
+            - const: dout_sclk_peri_spi1_b
+            - const: dout_sclk_peri_spi2_b
+            - const: dout_aclk_peri_aud
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5260-clock-egl
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_bus_pll
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5260-clock-kfc
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_media_pll
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5260-clock-g2d
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_aclk_g2d_333
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5260-clock-mif
+    then:
+      properties:
+        clocks:
+          minItems: 1
+          maxItems: 1
+        clock-names:
+          items:
+            - const: fin_pll
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5260-clock-mfc
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_aclk_mfc_333
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5260-clock-g3d
+    then:
+      properties:
+        clocks:
+          minItems: 1
+          maxItems: 1
+        clock-names:
+          items:
+            - const: fin_pll
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5260-clock-fsys
+    then:
+      properties:
+        clocks:
+          minItems: 7
+          maxItems: 7
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: phyclk_usbhost20_phy_phyclock
+            - const: phyclk_usbhost20_phy_freeclk
+            - const: phyclk_usbhost20_phy_clk48mohci
+            - const: phyclk_usbdrd30_udrd30_pipe_pclk
+            - const: phyclk_usbdrd30_udrd30_phyclock
+            - const: dout_aclk_fsys_200
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5260-clock-aud
+    then:
+      properties:
+        clocks:
+          minItems: 4
+          maxItems: 4
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: fout_aud_pll
+            - const: ioclk_i2s_cdclk
+            - const: ioclk_pcm_extclk
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5260-clock-isp
+    then:
+      properties:
+        clocks:
+          minItems: 4
+          maxItems: 4
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_aclk_isp1_266
+            - const: dout_aclk_isp1_400
+            - const: mout_aclk_isp1_266
+
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5260-clock-gscl
+    then:
+      properties:
+        clocks:
+          minItems: 3
+          maxItems: 3
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_aclk_gscl_400
+            - const: dout_aclk_gscl_333
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5260-clock-disp
+    then:
+      properties:
+        clocks:
+          minItems: 19
+          maxItems: 19
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: phyclk_dptx_phy_ch3_txd_clk
+            - const: phyclk_dptx_phy_ch2_txd_clk
+            - const: phyclk_dptx_phy_ch1_txd_clk
+            - const: phyclk_dptx_phy_ch0_txd_clk
+            - const: phyclk_hdmi_phy_tmds_clko
+            - const: phyclk_hdmi_phy_ref_clko
+            - const: phyclk_hdmi_phy_pixel_clko
+            - const: phyclk_hdmi_link_o_tmds_clkhi
+            - const: phyclk_mipi_dphy_4l_m_txbyte_clkhs
+            - const: phyclk_dptx_phy_o_ref_clk_24m
+            - const: phyclk_dptx_phy_clk_div2
+            - const: phyclk_mipi_dphy_4l_m_rxclkesc0
+            - const: phyclk_hdmi_phy_ref_cko
+            - const: ioclk_spdif_extclk
+            - const: dout_aclk_peri_aud
+            - const: dout_aclk_disp_222
+            - const: dout_sclk_disp_pixel
+            - const: dout_aclk_disp_333
+      required:
+        - clock-names
+        - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/exynos5260-clk.h>
+
+    fin_pll: clock {
+        compatible = "fixed-clock";
+        clock-output-names = "fin_pll";
+        #clock-cells = <0>;
+        clock-frequency = <24000000>;
+    };
+
+    clock-controller@10010000 {
+        compatible = "samsung,exynos5260-clock-top";
+        reg = <0x10010000 0x10000>;
+        #clock-cells = <1>;
+        clocks = <&fin_pll>,
+                 <&clock_mif MIF_DOUT_MEM_PLL>,
+                 <&clock_mif MIF_DOUT_BUS_PLL>,
+                 <&clock_mif MIF_DOUT_MEDIA_PLL>;
+        clock-names = "fin_pll",
+                      "dout_mem_pll",
+                      "dout_bus_pll",
+                      "dout_media_pll";
+    };
--- a/Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml
@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos5410 SoC clock controller
+
+maintainers:
+  - Chanwoo Choi <cw00.choi@samsung.com>
+  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+  - Sylwester Nawrocki <s.nawrocki@samsung.com>
+  - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+  Expected external clocks, defined in DTS as fixed-rate clocks with a matching
+  name::
+    - "fin_pll" - PLL input clock from XXTI
+
+  All available clocks are defined as preprocessor macros in
+  include/dt-bindings/clock/exynos5410.h header.
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - samsung,exynos5410-clock
+
+  clocks:
+    description:
+      Should contain an entry specifying the root clock from external
+      oscillator supplied through XXTI or XusbXTI pin.  This clock should be
+      defined using standard clock bindings with "fin_pll" clock-output-name.
+      That clock is being passed internally to the 9 PLLs.
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - "#clock-cells"
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/exynos5410.h>
+
+    fin_pll: osc-clock {
+        compatible = "fixed-clock";
+        clock-frequency = <24000000>;
+        clock-output-names = "fin_pll";
+        #clock-cells = <0>;
+    };
+
+    clock-controller@10010000 {
+        compatible = "samsung,exynos5410-clock";
+        reg = <0x10010000 0x30000>;
+        #clock-cells = <1>;
+        clocks = <&fin_pll>;
+    };
--- a/Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml
@ -0,0 +1,524 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos5433 SoC clock controller
+
+maintainers:
+  - Chanwoo Choi <cw00.choi@samsung.com>
+  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+  - Sylwester Nawrocki <s.nawrocki@samsung.com>
+  - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+  Expected external clocks, defined in DTS as fixed-rate clocks with a matching
+  name::
+    - "oscclk" - PLL input clock from XXTI
+
+  All available clocks are defined as preprocessor macros in
+  include/dt-bindings/clock/exynos5433.h header.
+
+properties:
+  compatible:
+    enum:
+        # CMU_TOP which generates clocks for
+        # IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS domains and bus
+        # clocks
+      - samsung,exynos5433-cmu-top
+        # CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP
+      - samsung,exynos5433-cmu-cpif
+        # CMU_MIF which generates clocks for DRAM Memory Controller domain
+      - samsung,exynos5433-cmu-mif
+        # CMU_PERIC which generates clocks for
+        # UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs
+      - samsung,exynos5433-cmu-peric
+        # CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs
+      - samsung,exynos5433-cmu-peris
+        # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
+      - samsung,exynos5433-cmu-fsys
+      - samsung,exynos5433-cmu-g2d
+        # CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs
+      - samsung,exynos5433-cmu-disp
+      - samsung,exynos5433-cmu-aud
+      - samsung,exynos5433-cmu-bus0
+      - samsung,exynos5433-cmu-bus1
+      - samsung,exynos5433-cmu-bus2
+      - samsung,exynos5433-cmu-g3d
+      - samsung,exynos5433-cmu-gscl
+      - samsung,exynos5433-cmu-apollo
+        # CMU_ATLAS which generates clocks for Cortex-A57 Quad-core processor,
+        # CoreSight and  L2 cache controller
+      - samsung,exynos5433-cmu-atlas
+        # CMU_MSCL which generates clocks for M2M (Memory to Memory) scaler and
+        # JPEG IPs
+      - samsung,exynos5433-cmu-mscl
+      - samsung,exynos5433-cmu-mfc
+      - samsung,exynos5433-cmu-hevc
+        # CMU_ISP which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs
+      - samsung,exynos5433-cmu-isp
+        # CMU_CAM0 which generates clocks for
+        # MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs
+      - samsung,exynos5433-cmu-cam0
+        # CMU_CAM1 which generates clocks for
+        # Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs
+      - samsung,exynos5433-cmu-cam1
+        # CMU_IMEM which generates clocks for SSS (Security SubSystem) and
+        # SlimSSS IPs
+      - samsung,exynos5433-cmu-imem
+
+  clocks:
+    minItems: 1
+    maxItems: 10
+
+  clock-names:
+    minItems: 1
+    maxItems: 10
+
+  "#clock-cells":
+    const: 1
+
+  power-domains:
+    maxItems: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - "#clock-cells"
+  - reg
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-top
+    then:
+      properties:
+        clocks:
+          minItems: 4
+          maxItems: 4
+        clock-names:
+          items:
+            - const: oscclk
+            - const: sclk_mphy_pll
+            - const: sclk_mfc_pll
+            - const: sclk_bus_pll
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-cpif
+    then:
+      properties:
+        clocks:
+          minItems: 1
+          maxItems: 1
+        clock-names:
+          items:
+            - const: oscclk
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-mif
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: oscclk
+            - const: sclk_mphy_pll
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-fsys
+    then:
+      properties:
+        clocks:
+          minItems: 10
+          maxItems: 10
+        clock-names:
+          items:
+            - const: oscclk
+            - const: sclk_ufs_mphy
+            - const: aclk_fsys_200
+            - const: sclk_pcie_100_fsys
+            - const: sclk_ufsunipro_fsys
+            - const: sclk_mmc2_fsys
+            - const: sclk_mmc1_fsys
+            - const: sclk_mmc0_fsys
+            - const: sclk_usbhost30_fsys
+            - const: sclk_usbdrd30_fsys
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-g2d
+    then:
+      properties:
+        clocks:
+          minItems: 3
+          maxItems: 3
+        clock-names:
+          items:
+            - const: oscclk
+            - const: aclk_g2d_266
+            - const: aclk_g2d_400
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-disp
+    then:
+      properties:
+        clocks:
+          minItems: 9
+          maxItems: 9
+        clock-names:
+          items:
+            - const: oscclk
+            - const: sclk_dsim1_disp
+            - const: sclk_dsim0_disp
+            - const: sclk_dsd_disp
+            - const: sclk_decon_tv_eclk_disp
+            - const: sclk_decon_vclk_disp
+            - const: sclk_decon_eclk_disp
+            - const: sclk_decon_tv_vclk_disp
+            - const: aclk_disp_333
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-aud
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: oscclk
+            - const: fout_aud_pll
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-bus0
+    then:
+      properties:
+        clocks:
+          minItems: 1
+          maxItems: 1
+        clock-names:
+          items:
+            - const: aclk_bus0_400
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-bus1
+    then:
+      properties:
+        clocks:
+          minItems: 1
+          maxItems: 1
+        clock-names:
+          items:
+            - const: aclk_bus1_400
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-bus2
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: oscclk
+            - const: aclk_bus2_400
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-g3d
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: oscclk
+            - const: aclk_g3d_400
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-gscl
+    then:
+      properties:
+        clocks:
+          minItems: 3
+          maxItems: 3
+        clock-names:
+          items:
+            - const: oscclk
+            - const: aclk_gscl_111
+            - const: aclk_gscl_333
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-apollo
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: oscclk
+            - const: sclk_bus_pll_apollo
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-atlas
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: oscclk
+            - const: sclk_bus_pll_atlas
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-mscl
+    then:
+      properties:
+        clocks:
+          minItems: 3
+          maxItems: 3
+        clock-names:
+          items:
+            - const: oscclk
+            - const: sclk_jpeg_mscl
+            - const: aclk_mscl_400
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-mfc
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: oscclk
+            - const: aclk_mfc_400
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-hevc
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: oscclk
+            - const: aclk_hevc_400
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-isp
+    then:
+      properties:
+        clocks:
+          minItems: 3
+          maxItems: 3
+        clock-names:
+          items:
+            - const: oscclk
+            - const: aclk_isp_dis_400
+            - const: aclk_isp_400
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-cam0
+    then:
+      properties:
+        clocks:
+          minItems: 4
+          maxItems: 4
+        clock-names:
+          items:
+            - const: oscclk
+            - const: aclk_cam0_333
+            - const: aclk_cam0_400
+            - const: aclk_cam0_552
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-cam1
+    then:
+      properties:
+        clocks:
+          minItems: 7
+          maxItems: 7
+        clock-names:
+          items:
+            - const: oscclk
+            - const: sclk_isp_uart_cam1
+            - const: sclk_isp_spi1_cam1
+            - const: sclk_isp_spi0_cam1
+            - const: aclk_cam1_333
+            - const: aclk_cam1_400
+            - const: aclk_cam1_552
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos5433-cmu-imem
+    then:
+      properties:
+        clocks:
+          minItems: 4
+          maxItems: 4
+        clock-names:
+          items:
+            - const: oscclk
+            - const: aclk_imem_sssx_266
+            - const: aclk_imem_266
+            - const: aclk_imem_200
+      required:
+        - clock-names
+        - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/exynos5433.h>
+    xxti: clock {
+        compatible = "fixed-clock";
+        clock-output-names = "oscclk";
+        #clock-cells = <0>;
+        clock-frequency = <24000000>;
+    };
+
+    clock-controller@10030000 {
+        compatible = "samsung,exynos5433-cmu-top";
+        reg = <0x10030000 0x1000>;
+        #clock-cells = <1>;
+
+        clock-names = "oscclk",
+                      "sclk_mphy_pll",
+                      "sclk_mfc_pll",
+                      "sclk_bus_pll";
+        clocks = <&xxti>,
+                 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
+                 <&cmu_mif CLK_SCLK_MFC_PLL>,
+                 <&cmu_mif CLK_SCLK_BUS_PLL>;
+    };
--- a/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
@ -0,0 +1,272 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos7 SoC clock controller
+
+maintainers:
+  - Chanwoo Choi <cw00.choi@samsung.com>
+  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+  - Sylwester Nawrocki <s.nawrocki@samsung.com>
+  - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+  Expected external clocks, defined in DTS as fixed-rate clocks with a matching
+  name::
+    - "fin_pll" - PLL input clock from XXTI
+
+  All available clocks are defined as preprocessor macros in
+  include/dt-bindings/clock/exynos7-clk.h header.
+
+properties:
+  compatible:
+    enum:
+      - samsung,exynos7-clock-topc
+      - samsung,exynos7-clock-top0
+      - samsung,exynos7-clock-top1
+      - samsung,exynos7-clock-ccore
+      - samsung,exynos7-clock-peric0
+      - samsung,exynos7-clock-peric1
+      - samsung,exynos7-clock-peris
+      - samsung,exynos7-clock-fsys0
+      - samsung,exynos7-clock-fsys1
+      - samsung,exynos7-clock-mscl
+      - samsung,exynos7-clock-aud
+
+  clocks:
+    minItems: 1
+    maxItems: 13
+
+  clock-names:
+    minItems: 1
+    maxItems: 13
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - "#clock-cells"
+  - reg
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7-clock-top0
+    then:
+      properties:
+        clocks:
+          minItems: 6
+          maxItems: 6
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_sclk_bus0_pll
+            - const: dout_sclk_bus1_pll
+            - const: dout_sclk_cc_pll
+            - const: dout_sclk_mfc_pll
+            - const: dout_sclk_aud_pll
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7-clock-top1
+    then:
+      properties:
+        clocks:
+          minItems: 5
+          maxItems: 5
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_sclk_bus0_pll
+            - const: dout_sclk_bus1_pll
+            - const: dout_sclk_cc_pll
+            - const: dout_sclk_mfc_pll
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7-clock-ccore
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_aclk_ccore_133
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7-clock-peric0
+    then:
+      properties:
+        clocks:
+          minItems: 3
+          maxItems: 3
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_aclk_peric0_66
+            - const: sclk_uart0
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7-clock-peric1
+    then:
+      properties:
+        clocks:
+          minItems: 13
+          maxItems: 13
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_aclk_peric1_66
+            - const: sclk_uart1
+            - const: sclk_uart2
+            - const: sclk_uart3
+            - const: sclk_spi0
+            - const: sclk_spi1
+            - const: sclk_spi2
+            - const: sclk_spi3
+            - const: sclk_spi4
+            - const: sclk_i2s1
+            - const: sclk_pcm1
+            - const: sclk_spdif
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7-clock-peris
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_aclk_peris_66
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7-clock-fsys0
+    then:
+      properties:
+        clocks:
+          minItems: 3
+          maxItems: 3
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_aclk_fsys0_200
+            - const: dout_sclk_mmc2
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7-clock-fsys1
+    then:
+      properties:
+        clocks:
+          minItems: 7
+          maxItems: 7
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_aclk_fsys1_200
+            - const: dout_sclk_mmc0
+            - const: dout_sclk_mmc1
+            - const: dout_sclk_ufsunipro20
+            - const: dout_sclk_phy_fsys1
+            - const: dout_sclk_phy_fsys1_26m
+      required:
+        - clock-names
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7-clock-aud
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: fout_aud_pll
+      required:
+        - clock-names
+        - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/exynos7-clk.h>
+
+    fin_pll: clock {
+        compatible = "fixed-clock";
+        clock-output-names = "fin_pll";
+        #clock-cells = <0>;
+        clock-frequency = <24000000>;
+    };
+
+    clock-controller@105e0000 {
+        compatible = "samsung,exynos7-clock-top1";
+        reg = <0x105e0000 0xb000>;
+        #clock-cells = <1>;
+        clocks = <&fin_pll>,
+                 <&clock_topc DOUT_SCLK_BUS0_PLL>,
+                 <&clock_topc DOUT_SCLK_BUS1_PLL>,
+                 <&clock_topc DOUT_SCLK_CC_PLL>,
+                 <&clock_topc DOUT_SCLK_MFC_PLL>;
+        clock-names = "fin_pll",
+                      "dout_sclk_bus0_pll",
+                      "dout_sclk_bus1_pll",
+                      "dout_sclk_cc_pll",
+                      "dout_sclk_mfc_pll";
+    };
--- a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
@ -0,0 +1,166 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos7885 SoC clock controller
+
+maintainers:
+  - Dávid Virág <virag.david003@gmail.com>
+  - Chanwoo Choi <cw00.choi@samsung.com>
+  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+  - Sylwester Nawrocki <s.nawrocki@samsung.com>
+  - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+  Exynos7885 clock controller is comprised of several CMU units, generating
+  clocks for different domains. Those CMU units are modeled as separate device
+  tree nodes, and might depend on each other. The root clock in that root tree
+  is an external clock: OSCCLK (26 MHz). This external clock must be defined
+  as a fixed-rate clock in dts.
+
+  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
+  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
+
+  Each clock is assigned an identifier and client nodes can use this identifier
+  to specify the clock which they consume. All clocks available for usage
+  in clock consumer nodes are defined as preprocessor macros in
+  'dt-bindings/clock/exynos7885.h' header.
+
+properties:
+  compatible:
+    enum:
+      - samsung,exynos7885-cmu-top
+      - samsung,exynos7885-cmu-core
+      - samsung,exynos7885-cmu-peri
+
+  clocks:
+    minItems: 1
+    maxItems: 10
+
+  clock-names:
+    minItems: 1
+    maxItems: 10
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7885-cmu-top
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+
+        clock-names:
+          items:
+            - const: oscclk
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7885-cmu-core
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_CORE bus clock (from CMU_TOP)
+            - description: CCI clock (from CMU_TOP)
+            - description: G3D clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_core_bus
+            - const: dout_core_cci
+            - const: dout_core_g3d
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7885-cmu-peri
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_PERI bus clock (from CMU_TOP)
+            - description: SPI0 clock (from CMU_TOP)
+            - description: SPI1 clock (from CMU_TOP)
+            - description: UART0 clock (from CMU_TOP)
+            - description: UART1 clock (from CMU_TOP)
+            - description: UART2 clock (from CMU_TOP)
+            - description: USI0 clock (from CMU_TOP)
+            - description: USI1 clock (from CMU_TOP)
+            - description: USI2 clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_peri_bus
+            - const: dout_peri_spi0
+            - const: dout_peri_spi1
+            - const: dout_peri_uart0
+            - const: dout_peri_uart1
+            - const: dout_peri_uart2
+            - const: dout_peri_usi0
+            - const: dout_peri_usi1
+            - const: dout_peri_usi2
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clocks
+  - clock-names
+  - reg
+
+additionalProperties: false
+
+examples:
+  # Clock controller node for CMU_PERI
+  - |
+    #include <dt-bindings/clock/exynos7885.h>
+
+    cmu_peri: clock-controller@10010000 {
+        compatible = "samsung,exynos7885-cmu-peri";
+        reg = <0x10010000 0x8000>;
+        #clock-cells = <1>;
+
+        clocks = <&oscclk>,
+                 <&cmu_top CLK_DOUT_PERI_BUS>,
+                 <&cmu_top CLK_DOUT_PERI_SPI0>,
+                 <&cmu_top CLK_DOUT_PERI_SPI1>,
+                 <&cmu_top CLK_DOUT_PERI_UART0>,
+                 <&cmu_top CLK_DOUT_PERI_UART1>,
+                 <&cmu_top CLK_DOUT_PERI_UART2>,
+                 <&cmu_top CLK_DOUT_PERI_USI0>,
+                 <&cmu_top CLK_DOUT_PERI_USI1>,
+                 <&cmu_top CLK_DOUT_PERI_USI2>;
+        clock-names = "oscclk",
+                      "dout_peri_bus",
+                      "dout_peri_spi0",
+                      "dout_peri_spi1",
+                      "dout_peri_uart0",
+                      "dout_peri_uart1",
+                      "dout_peri_uart2",
+                      "dout_peri_usi0",
+                      "dout_peri_usi1",
+                      "dout_peri_usi2";
+    };
+
+...
--- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
@ -32,6 +32,8 @@ properties:
  compatible:
    enum:
      - samsung,exynos850-cmu-top
+      - samsung,exynos850-cmu-apm
+      - samsung,exynos850-cmu-cmgp
      - samsung,exynos850-cmu-core
      - samsung,exynos850-cmu-dpu
      - samsung,exynos850-cmu-hsi
@ -68,6 +70,42 @@ allOf:
          items:
            - const: oscclk

+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos850-cmu-apm
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_APM bus clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_clkcmu_apm_bus
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos850-cmu-cmgp
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_CMGP bus clock (from CMU_APM)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: gout_clkcmu_cmgp_bus
+
  - if:
      properties:
        compatible:
--- a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
+++ b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
@ -1,77 +0,0 @@
-* Samsung S5P6442/S5PC110/S5PV210 Clock Controller
-
-Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
-controller, which generates and supplies clock to various controllers
-within the SoC.
-
-Required Properties:
-
- compatible: should be one of following:
-	- "samsung,s5pv210-clock" : for clock controller of Samsung
-	  S5PC110/S5PV210 SoCs,
-	- "samsung,s5p6442-clock" : for clock controller of Samsung
-	  S5P6442 SoC.
-
- reg: physical base address of the controller and length of memory mapped
-  region.
-
- #clock-cells: should be 1.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xxti": external crystal oscillator connected to XXTI and XXTO pins of
-the SoC,
- - "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO
-pins of the SoC,
-
-A subset of above clocks available on given board shall be specified in
-board device tree, including the system base clock, as selected by XOM[0]
-pin of the SoC. Refer to generic fixed rate clock bindings
-documentation[1] for more information how to specify these clocks.
-
-[1] Documentation/devicetree/bindings/clock/fixed-clock.yaml
-
-Example: Clock controller node:
-
-	clock: clock-controller@7e00f000 {
-		compatible = "samsung,s5pv210-clock";
-		reg = <0x7e00f000 0x1000>;
-		#clock-cells = <1>;
-	};
-
-Example: Required external clocks:
-
-	xxti: clock-xxti {
-		compatible = "fixed-clock";
-		clock-output-names = "xxti";
-		clock-frequency = <24000000>;
-		#clock-cells = <0>;
-	};
-
-	xusbxti: clock-xusbxti {
-		compatible = "fixed-clock";
-		clock-output-names = "xusbxti";
-		clock-frequency = <24000000>;
-		#clock-cells = <0>;
-	};
-
-Example: UART controller node that consumes the clock generated by the clock
-  controller (refer to the standard clock bindings for information about
-  "clocks" and "clock-names" properties):
-
-	uart0: serial@e2900000 {
-		compatible = "samsung,s5pv210-uart";
-		reg = <0xe2900000 0x400>;
-		interrupt-parent = <&vic1>;
-		interrupts = <10>;
-		clock-names = "uart", "clk_uart_baud0",
-				"clk_uart_baud1";
-		clocks = <&clocks UART0>, <&clocks UART0>,
-				<&clocks SCLK_UART0>;
-	};
--- a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml
@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller
+
+maintainers:
+  - Chanwoo Choi <cw00.choi@samsung.com>
+  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+  - Sylwester Nawrocki <s.nawrocki@samsung.com>
+  - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+  Expected external clocks, defined in DTS as fixed-rate clocks with a matching
+  name::
+    - "xxti" - external crystal oscillator connected to XXTI and XXTO pins of
+      the SoC,
+    - "xusbxti" - external crystal oscillator connected to XUSBXTI and XUSBXTO
+      pins of the SoC,
+
+  All available clocks are defined as preprocessor macros in
+  include/dt-bindings/clock/s5pv210.h header.
+
+properties:
+  compatible:
+    enum:
+      - samsung,s5pv210-clock
+      - samsung,s5p6442-clock
+
+  clocks:
+    items:
+      - description: xxti clock
+      - description: xusbxti clock
+
+  clock-names:
+    items:
+      - const: xxti
+      - const: xusbxti
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - "#clock-cells"
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/s5pv210.h>
+
+    xxti: clock-0 {
+        compatible = "fixed-clock";
+        clock-frequency = <0>;
+        clock-output-names = "xxti";
+        #clock-cells = <0>;
+    };
+
+    xusbxti: clock-1 {
+        compatible = "fixed-clock";
+        clock-frequency = <0>;
+        clock-output-names = "xusbxti";
+        #clock-cells = <0>;
+    };
+
+    clock-controller@e0100000 {
+        compatible = "samsung,s5pv210-clock";
+        reg = <0xe0100000 0x10000>;
+        clock-names = "xxti", "xusbxti";
+        clocks = <&xxti>, <&xusbxti>;
+        #clock-cells = <1>;
+    };
--- a/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml
+++ b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml
@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pipllct.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Toshiba Visconti5 TMPV770X PLL Controller Device Tree Bindings
+
+maintainers:
+  - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
+
+description:
+  Toshia Visconti5 PLL controller which supports the PLLs on TMPV770X.
+
+properties:
+  compatible:
+    const: toshiba,tmpv7708-pipllct
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  clocks:
+    description: External reference clock (OSC2)
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    osc2_clk: osc2-clk {
+      compatible = "fixed-clock";
+      clock-frequency = <20000000>;
+      #clock-cells = <0>;
+    };
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        pipllct: clock-controller@24220000 {
+            compatible = "toshiba,tmpv7708-pipllct";
+            reg = <0 0x24220000 0 0x820>;
+            #clock-cells = <1>;
+            clocks = <&osc2_clk>;
+        };
+    };
+...
--- a/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml
+++ b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml
@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pismu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Toshiba Visconti5 TMPV770x SMU controller Device Tree Bindings
+
+maintainers:
+  - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
+
+description:
+  Toshia Visconti5 SMU (System Management Unit) which supports the clock
+  and resets on TMPV770x.
+
+properties:
+  compatible:
+    items:
+      - const: toshiba,tmpv7708-pismu
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        pismu: syscon@24200000 {
+            compatible = "toshiba,tmpv7708-pismu", "syscon";
+            reg = <0 0x24200000 0 0x2140>;
+            #clock-cells = <1>;
+            #reset-cells = <1>;
+        };
+    };
+...
--- a/Documentation/devicetree/bindings/crypto/qcom,prng.txt
+++ b/Documentation/devicetree/bindings/crypto/qcom,prng.txt
@ -1,19 +0,0 @@
-Qualcomm MSM pseudo random number generator.
-
-Required properties:
-
- compatible  : should be "qcom,prng" for 8916 etc
-              : should be "qcom,prng-ee" for 8996 and later using EE
-		(Execution Environment) slice of prng
- reg         : specifies base physical address and size of the registers map
- clocks      : phandle to clock-controller plus clock-specifier pair
- clock-names : "core" clocks all registers, FIFO and circuits in PRNG IP block
-
-Example:
-
-	rng@f9bff000 {
-		compatible = "qcom,prng";
-		reg = <0xf9bff000 0x200>;
-		clocks = <&clock GCC_PRNG_AHB_CLK>;
-		clock-names = "core";
-	};
--- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/qcom,prng.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Pseudo Random Number Generator
+
+maintainers:
+  - Vinod Koul <vkoul@kernel.org>
+
+properties:
+  compatible:
+    enum:
+      - qcom,prng  # 8916 etc.
+      - qcom,prng-ee  # 8996 and later using EE
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: core
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    rng@f9bff000 {
+        compatible = "qcom,prng";
+        reg = <0xf9bff000 0x200>;
+        clocks = <&clk 125>;
+        clock-names = "core";
+    };
--- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
@ -31,13 +31,11 @@ properties:
  clocks:
    items:
      - description: Display AHB clock from gcc
-      - description: Display AXI clock
      - description: Display core clock

  clock-names:
    items:
      - const: iface
-      - const: bus
      - const: core

  interrupts:
@ -160,9 +158,8 @@ examples:
          power-domains = <&dispcc MDSS_GDSC>;

          clocks = <&gcc GCC_DISP_AHB_CLK>,
-                   <&gcc GCC_DISP_AXI_CLK>,
                   <&dispcc DISP_CC_MDSS_MDP_CLK>;
-          clock-names = "iface", "bus", "core";
+          clock-names = "iface", "core";

          interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
          interrupt-controller;
--- a/Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.yaml
+++ b/Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.yaml
@ -35,6 +35,8 @@ properties:
      phandle of the gpio for power ic line
      Power IC supply enable, High active

+  port: true
+
 required:
  - compatible
  - reg
--- a/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml
+++ b/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml
@ -34,7 +34,7 @@ properties:
    description: phandle of gpio for reset line - This should be 8mA, gpio
      can be configured using mux, pinctrl, pinctrl-names (active high)

-  vddio-supply:
+  vddi0-supply:
    description: phandle of the regulator that provides the supply voltage
      Power IC supply

@ -75,8 +75,6 @@ examples:

            reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;

-            #address-cells = <1>;
-            #size-cells = <0>;
            port {
                tianma_nt36672a_in_0: endpoint {
                    remote-endpoint = <&dsi0_out>;
--- a/Documentation/devicetree/bindings/display/simple-framebuffer.yaml
+++ b/Documentation/devicetree/bindings/display/simple-framebuffer.yaml
@ -83,13 +83,25 @@ properties:
  format:
    description: >
      Format of the framebuffer:
+        * `a1r5g5b5` - 16-bit pixels, d[15]=a, d[14:10]=r, d[9:5]=g, d[4:0]=b
+        * `a2r10g10b10` - 32-bit pixels, d[31:30]=a, d[29:20]=r, d[19:10]=g, d[9:0]=b
        * `a8b8g8r8` - 32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r
+        * `a8r8g8b8` - 32-bit pixels, d[31:24]=a, d[23:16]=r, d[15:8]=g, d[7:0]=b
        * `r5g6b5` - 16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b
+        * `r5g5b5a1` - 16-bit pixels, d[15:11]=r, d[10:6]=g, d[5:1]=b d[1:0]=a
+        * `r8g8b8` - 24-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b
+        * `x1r5g5b5` - 16-bit pixels, d[14:10]=r, d[9:5]=g, d[4:0]=b
        * `x2r10g10b10` - 32-bit pixels, d[29:20]=r, d[19:10]=g, d[9:0]=b
        * `x8r8g8b8` - 32-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b
    enum:
+      - a1r5g5b5
+      - a2r10g10b10
      - a8b8g8r8
+      - a8r8g8b8
      - r5g6b5
+      - r5g5b5a1
+      - r8g8b8
+      - x1r5g5b5
      - x2r10g10b10
      - x8r8g8b8

--- a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml
+++ b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml
@ -110,7 +110,7 @@ examples:
              };
        };

-        panel-dsi@0 {
+        panel@0 {
              compatible = "orisetech,otm8009a";
              reg = <0>;
              reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
@ -125,4 +125,3 @@ examples:
    };

 ...
-
--- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
+++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
@ -50,7 +50,7 @@ examples:
    dma@3000000 {
      compatible = "sifive,fu540-c000-pdma";
      reg = <0x3000000 0x8000>;
-      interrupts = <23 24 25 26 27 28 29 30>;
+      interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
      #dma-cells = <1>;
    };

--- a/Documentation/devicetree/bindings/eeprom/at24.yaml
+++ b/Documentation/devicetree/bindings/eeprom/at24.yaml
@ -86,6 +86,10 @@ properties:
                  pattern: c1024$
              - items:
                  pattern: cs1024$
+              - items:
+                  pattern: c1025$
+              - items:
+                  pattern: cs1025$
              - items:
                  pattern: c2048$
              - items:
@ -95,17 +99,20 @@ properties:
      # These are special cases that don't conform to the above pattern.
      # Each requires a standard at24 model as fallback.
      - items:
-          - const: nxp,se97b
+          - enum:
+              - rohm,br24g01
+              - rohm,br24t01
+          - const: atmel,24c01
+      - items:
+          - enum:
+              - nxp,se97b
+              - renesas,r1ex24002
          - const: atmel,24c02
      - items:
-          - const: onnn,cat24c04
+          - enum:
+              - onnn,cat24c04
+              - onnn,cat24c05
          - const: atmel,24c04
-      - items:
-          - const: onnn,cat24c05
-          - const: atmel,24c04
-      - items:
-          - const: renesas,r1ex24002
-          - const: atmel,24c02
      - items:
          - const: renesas,r1ex24016
          - const: atmel,24c16
@ -115,12 +122,6 @@ properties:
      - items:
          - const: renesas,r1ex24128
          - const: atmel,24c128
-      - items:
-          - const: rohm,br24g01
-          - const: atmel,24c01
-      - items:
-          - const: rohm,br24t01
-          - const: atmel,24c01

  label:
    description: Descriptive name of the EEPROM.
--- a/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
@ -1,83 +0,0 @@
-Broadcom STB "UPG GIO" GPIO controller
-
-The controller's registers are organized as sets of eight 32-bit
-registers with each set controlling a bank of up to 32 pins.  A single
-interrupt is shared for all of the banks handled by the controller.
-
-Required properties:
-
- compatible:
-    Must be "brcm,brcmstb-gpio"
-
- reg:
-    Define the base and range of the I/O address space containing
-    the brcmstb GPIO controller registers
-
- #gpio-cells:
-    Should be <2>.  The first cell is the pin number (within the controller's
-    pin space), and the second is used for the following:
-    bit[0]: polarity (0 for active-high, 1 for active-low)
-
- gpio-controller:
-    Specifies that the node is a GPIO controller.
-
- brcm,gpio-bank-widths:
-    Number of GPIO lines for each bank.  Number of elements must
-    correspond to number of banks suggested by the 'reg' property.
-
-Optional properties:
-
- interrupts:
-    The interrupt shared by all GPIO lines for this controller.
-
- interrupts-extended:
-    Alternate form of specifying interrupts and parents that allows for
-    multiple parents.  This takes precedence over 'interrupts' and
-    'interrupt-parent'.  Wakeup-capable GPIO controllers often route their
-    wakeup interrupt lines through a different interrupt controller than the
-    primary interrupt line, making this property necessary.
-
- #interrupt-cells:
-    Should be <2>.  The first cell is the GPIO number, the second should specify
-    flags.  The following subset of flags is supported:
-    - bits[3:0] trigger type and level flags
-        1 = low-to-high edge triggered
-        2 = high-to-low edge triggered
-        4 = active high level-sensitive
-        8 = active low level-sensitive
-      Valid combinations are 1, 2, 3, 4, 8.
-    See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-
- interrupt-controller:
-    Marks the device node as an interrupt controller
-
- wakeup-source:
-    GPIOs for this controller can be used as a wakeup source
-
-Example:
-	upg_gio: gpio@f040a700 {
-		#gpio-cells = <2>;
-		#interrupt-cells = <2>;
-		compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
-		gpio-controller;
-		interrupt-controller;
-		reg = <0xf040a700 0x80>;
-		interrupt-parent = <&irq0_intc>;
-		interrupts = <0x6>;
-		brcm,gpio-bank-widths = <32 32 32 24>;
-	};
-
-	upg_gio_aon: gpio@f04172c0 {
-		#gpio-cells = <2>;
-		#interrupt-cells = <2>;
-		compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
-		gpio-controller;
-		interrupt-controller;
-		reg = <0xf04172c0 0x40>;
-		interrupt-parent = <&irq0_aon_intc>;
-		interrupts = <0x6>;
-		interrupts-extended = <&irq0_aon_intc 0x6>,
-			<&aon_pm_l2_intc 0x5>;
-		wakeup-source;
-		brcm,gpio-bank-widths = <18 4>;
-	};
--- a/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom STB "UPG GIO" GPIO controller
+
+description: >
+  The controller's registers are organized as sets of eight 32-bit
+  registers with each set controlling a bank of up to 32 pins.  A single
+  interrupt is shared for all of the banks handled by the controller.
+
+maintainers:
+  - Doug Berger <opendmb@gmail.com>
+  - Florian Fainelli <f.fainelli@gmail.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - brcm,bcm7445-gpio
+      - const: brcm,brcmstb-gpio
+
+  reg:
+    maxItems: 1
+    description: >
+      Define the base and range of the I/O address space containing
+      the brcmstb GPIO controller registers
+
+  "#gpio-cells":
+    const: 2
+    description: >
+      The first cell is the pin number (within the controller's
+      pin space), and the second is used for the following:
+      bit[0]: polarity (0 for active-high, 1 for active-low)
+
+  gpio-controller: true
+
+  brcm,gpio-bank-widths:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: >
+      Number of GPIO lines for each bank.  Number of elements must
+      correspond to number of banks suggested by the 'reg' property.
+
+  interrupts:
+    maxItems: 1
+    description: >
+      The interrupt shared by all GPIO lines for this controller.
+
+  "#interrupt-cells":
+    const: 2
+    description: |
+      The first cell is the GPIO number, the second should specify
+      flags.  The following subset of flags is supported:
+      - bits[3:0] trigger type and level flags
+        1 = low-to-high edge triggered
+        2 = high-to-low edge triggered
+        4 = active high level-sensitive
+        8 = active low level-sensitive
+      Valid combinations are 1, 2, 3, 4, 8.
+
+  interrupt-controller: true
+
+  wakeup-source:
+    type: boolean
+    description: >
+      GPIOs for this controller can be used as a wakeup source
+
+required:
+  - compatible
+  - reg
+  - gpio-controller
+  - "#gpio-cells"
+  - "brcm,gpio-bank-widths"
+
+additionalProperties: false
+
+examples:
+  - |
+    upg_gio: gpio@f040a700 {
+        #gpio-cells = <2>;
+        #interrupt-cells = <2>;
+        compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
+        gpio-controller;
+        interrupt-controller;
+        reg = <0xf040a700 0x80>;
+        interrupt-parent = <&irq0_intc>;
+        interrupts = <0x6>;
+        brcm,gpio-bank-widths = <32 32 32 24>;
+    };
+
+    upg_gio_aon: gpio@f04172c0 {
+        #gpio-cells = <2>;
+        #interrupt-cells = <2>;
+        compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
+        gpio-controller;
+        interrupt-controller;
+        reg = <0xf04172c0 0x40>;
+        interrupt-parent = <&irq0_aon_intc>;
+        interrupts = <0x6>;
+        wakeup-source;
+        brcm,gpio-bank-widths = <18 4>;
+    };
--- a/Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml
+++ b/Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml
@ -43,7 +43,6 @@ required:
  - gpio-controller
  - interrupt-controller
  - "#interrupt-cells"
-  - interrupt-parent

 additionalProperties: false

--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
@ -19,6 +19,7 @@ properties:
          - amlogic,meson-g12a-mali
          - mediatek,mt8183-mali
          - realtek,rtd1619-mali
+          - renesas,r9a07g044-mali
          - rockchip,px30-mali
          - rockchip,rk3568-mali
      - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
@ -27,19 +28,26 @@ properties:
    maxItems: 1

  interrupts:
+    minItems: 3
    items:
      - description: Job interrupt
      - description: MMU interrupt
      - description: GPU interrupt
+      - description: Event interrupt

  interrupt-names:
+    minItems: 3
    items:
      - const: job
      - const: mmu
      - const: gpu
+      - const: event

  clocks:
-    maxItems: 1
+    minItems: 1
+    maxItems: 3
+
+  clock-names: true

  mali-supply: true

@ -52,7 +60,10 @@ properties:
    maxItems: 3

  resets:
-    maxItems: 2
+    minItems: 1
+    maxItems: 3
+
+  reset-names: true

  "#cooling-cells":
    const: 2
@ -94,6 +105,36 @@ allOf:
    then:
      required:
        - resets
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a07g044-mali
+    then:
+      properties:
+        interrupts:
+          minItems: 4
+        interrupt-names:
+          minItems: 4
+        clocks:
+          minItems: 3
+        clock-names:
+          items:
+            - const: gpu
+            - const: bus
+            - const: bus_ace
+        resets:
+          minItems: 3
+        reset-names:
+          items:
+            - const: rst
+            - const: axi_rst
+            - const: ace_rst
+      required:
+        - clock-names
+        - power-domains
+        - resets
+        - reset-names
  - if:
      properties:
        compatible:
--- a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
@ -63,7 +63,6 @@ examples:
    i2c0: i2c-bus@40 {
      #address-cells = <1>;
      #size-cells = <0>;
-      #interrupt-cells = <1>;
      compatible = "aspeed,ast2500-i2c-bus";
      reg = <0x40 0x40>;
      clocks = <&syscon ASPEED_CLK_APB>;
--- a/Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.txt
@ -1,22 +0,0 @@
-Broadcom BCM2835 I2C controller
-
-Required properties:
- compatible : Should be one of:
-	"brcm,bcm2711-i2c"
-	"brcm,bcm2835-i2c"
- reg: Should contain register location and length.
- interrupts: Should contain interrupt.
- clocks : The clock feeding the I2C controller.
-
-Recommended properties:
- clock-frequency : desired I2C bus clock frequency in Hz.
-
-Example:
-
-i2c@7e205000 {
-	compatible = "brcm,bcm2835-i2c";
-	reg = <0x7e205000 0x1000>;
-	interrupts = <2 21>;
-	clocks = <&clk_i2c>;
-	clock-frequency = <100000>;
-};
--- a/Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.yaml
@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/brcm,bcm2835-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM2835 I2C controller
+
+maintainers:
+  - Stephen Warren <swarren@wwwdotorg.org>
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - brcm,bcm2835-i2c
+      - items:
+          - const: brcm,bcm2711-i2c
+          - const: brcm,bcm2835-i2c
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clock-names:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-frequency: true
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    i2c@7e205000 {
+        compatible = "brcm,bcm2835-i2c";
+        reg = <0x7e205000 0x1000>;
+        interrupts = <2 21>;
+        clocks = <&clk_i2c>;
+        clock-frequency = <100000>;
+    };
--- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
@ -1,53 +0,0 @@
-* Samsung's High Speed I2C controller
-
-The Samsung's High Speed I2C controller is used to interface with I2C devices
-at various speeds ranging from 100khz to 3.4Mhz.
-
-Required properties:
-  - compatible: value should be.
-	-> "samsung,exynos5-hsi2c", (DEPRECATED)
-				for i2c compatible with HSI2C available
-				on Exynos5250 and Exynos5420 SoCs.
-	-> "samsung,exynos5250-hsi2c", for i2c compatible with HSI2C available
-				on Exynos5250 and Exynos5420 SoCs.
-	-> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available
-				on Exynos5260 SoCs.
-	-> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available
-				on Exynos7 SoCs.
-
-  - reg: physical base address of the controller and length of memory mapped
-    region.
-  - interrupts: interrupt number to the cpu.
-  - #address-cells: always 1 (for i2c addresses)
-  - #size-cells: always 0
-
-  - Pinctrl:
-    - pinctrl-0: Pin control group to be used for this controller.
-    - pinctrl-names: Should contain only one value - "default".
-
-Optional properties:
-  - clock-frequency: Desired operating frequency in Hz of the bus.
-    -> If not specified, the bus operates in fast-speed mode at
-       at 100khz.
-    -> If specified, the bus operates in high-speed mode only if the
-       clock-frequency is >= 1Mhz.
-
-Example:
-
-hsi2c@12ca0000 {
-	compatible = "samsung,exynos5250-hsi2c";
-	reg = <0x12ca0000 0x100>;
-	interrupts = <56>;
-	clock-frequency = <100000>;
-
-	pinctrl-0 = <&i2c4_bus>;
-	pinctrl-names = "default";
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	s2mps11_pmic@66 {
-		compatible = "samsung,s2mps11-pmic";
-		reg = <0x66>;
-	};
-};
--- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml
@ -0,0 +1,133 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-exynos5.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung's High Speed I2C controller
+
+maintainers:
+  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+description: |
+  The Samsung's High Speed I2C controller is used to interface with I2C devices
+  at various speeds ranging from 100kHz to 3.4MHz.
+
+  In case the HSI2C controller is encapsulated within USI block (it's the case
+  e.g. for Exynos850 and Exynos Auto V9 SoCs), it might be also necessary to
+  define USI node in device tree file, choosing "i2c" configuration. Please see
+  Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml for details.
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - samsung,exynos5250-hsi2c    # Exynos5250 and Exynos5420
+          - samsung,exynos5260-hsi2c    # Exynos5260
+          - samsung,exynos7-hsi2c       # Exynos7
+          - samsung,exynosautov9-hsi2c  # ExynosAutoV9 and Exynos850
+      - const: samsung,exynos5-hsi2c    # Exynos5250 and Exynos5420
+        deprecated: true
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clock-frequency:
+    default: 100000
+    description:
+      Desired operating frequency in Hz of the bus.
+
+      If not specified, the bus operates in fast-speed mode at 100kHz.
+
+      If specified, the bus operates in high-speed mode only if the
+      clock-frequency is >= 1MHz.
+
+  clocks:
+    minItems: 1
+    items:
+      - description: I2C operating clock
+      - description: Bus clock (APB)
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: hsi2c
+      - const: hsi2c_pclk
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - samsung,exynosautov9-hsi2c
+
+    then:
+      properties:
+        clocks:
+          minItems: 2
+
+        clock-names:
+          minItems: 2
+
+      required:
+        - clock-names
+
+    else:
+      properties:
+        clocks:
+          maxItems: 1
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/exynos5420.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    hsi2c_8: i2c@12e00000 {
+        compatible = "samsung,exynos5250-hsi2c";
+        reg = <0x12e00000 0x1000>;
+        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        clock-frequency = <100000>;
+        clocks = <&clock CLK_USI4>;
+        clock-names = "hsi2c";
+
+        pmic@66 {
+            /* compatible = "samsung,s2mps11-pmic"; */
+            reg = <0x66>;
+        };
+    };
+
+  - |
+    #include <dt-bindings/clock/exynos850.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    hsi2c_2: i2c@138c0000 {
+        compatible = "samsung,exynosautov9-hsi2c";
+        reg = <0x138c0000 0xc0>;
+        interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>,
+                 <&cmu_peri CLK_GOUT_HSI2C2_PCLK>;
+        clock-names = "hsi2c", "hsi2c_pclk";
+
+        pmic@66 {
+            /* compatible = "samsung,s2mps11-pmic"; */
+            reg = <0x66>;
+        };
+    };
--- a/Documentation/devicetree/bindings/i2c/i2c-gate.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-gate.yaml
@ -31,7 +31,7 @@ examples:
        #address-cells = <1>;
        #size-cells = <0>;
        ak8975@c {
-            compatible = "ak,ak8975";
+            compatible = "asahi-kasei,ak8975";
            reg = <0x0c>;
        };
    };
--- a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
@ -20,7 +20,9 @@ properties:
      - items:
          - enum:
              - fsl,imx8qxp-lpi2c
+              - fsl,imx8dxl-lpi2c
              - fsl,imx8qm-lpi2c
+              - fsl,imx8ulp-lpi2c
          - const: fsl,imx7ulp-lpi2c

  reg:
--- a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt
@ -1,80 +0,0 @@
-GPIO-based I2C Bus Mux
-
-This binding describes an I2C bus multiplexer that uses GPIOs to
-route the I2C signals.
-
-                                  +-----+  +-----+
-                                  | dev |  | dev |
-    +------------+                +-----+  +-----+
-    | SoC        |                   |        |
-    |            |          /--------+--------+
-    |   +------+ |  +------+    child bus A, on GPIO value set to 0
-    |   | I2C  |-|--| Mux  |
-    |   +------+ |  +--+---+    child bus B, on GPIO value set to 1
-    |            |     |    \----------+--------+--------+
-    |   +------+ |     |               |        |        |
-    |   | GPIO |-|-----+            +-----+  +-----+  +-----+
-    |   +------+ |                  | dev |  | dev |  | dev |
-    +------------+                  +-----+  +-----+  +-----+
-
-Required properties:
- compatible: i2c-mux-gpio
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
-  port is connected to.
- mux-gpios: list of gpios used to control the muxer
-* Standard I2C mux properties. See i2c-mux.yaml in this directory.
-* I2C child bus nodes. See i2c-mux.yaml in this directory.
-
-Optional properties:
- idle-state: value to set the muxer to when idle. When no value is
-  given, it defaults to the last value used.
-
-For each i2c child node, an I2C child bus will be created. They will
-be numbered based on their order in the device tree.
-
-Whenever an access is made to a device on a child bus, the value set
-in the relevant node's reg property will be output using the list of
-GPIOs, the first in the list holding the least-significant value.
-
-If an idle state is defined, using the idle-state (optional) property,
-whenever an access is not being made to a device on a child bus, the
-GPIOs will be set according to the idle value.
-
-If an idle state is not defined, the most recently used value will be
-left programmed into hardware whenever no access is being made to a
-device on a child bus.
-
-Example:
-	i2cmux {
-		compatible = "i2c-mux-gpio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		mux-gpios = <&gpio1 22 0 &gpio1 23 0>;
-		i2c-parent = <&i2c1>;
-
-		i2c@1 {
-			reg = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			ssd1307: oled@3c {
-				compatible = "solomon,ssd1307fb-i2c";
-				reg = <0x3c>;
-				pwms = <&pwm 4 3000>;
-				reset-gpios = <&gpio2 7 1>;
-			};
-		};
-
-		i2c@3 {
-			reg = <3>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			pca9555: pca9555@20 {
-				compatible = "nxp,pca9555";
-				gpio-controller;
-				#gpio-cells = <2>;
-				reg = <0x20>;
-			};
-		};
-	};
--- a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.yaml
@ -0,0 +1,104 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-mux-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GPIO-based I2C Bus Mux
+
+maintainers:
+  - Wolfram Sang <wsa@kernel.org>
+
+description: |
+  This binding describes an I2C bus multiplexer that uses GPIOs to route the I2C signals.
+
+                                  +-----+  +-----+
+                                  | dev |  | dev |
+    +------------+                +-----+  +-----+
+    | SoC        |                   |        |
+    |            |          /--------+--------+
+    |   +------+ |  +------+    child bus A, on GPIO value set to 0
+    |   | I2C  |-|--| Mux  |
+    |   +------+ |  +--+---+    child bus B, on GPIO value set to 1
+    |            |     |    \----------+--------+--------+
+    |   +------+ |     |               |        |        |
+    |   | GPIO |-|-----+            +-----+  +-----+  +-----+
+    |   +------+ |                  | dev |  | dev |  | dev |
+    +------------+                  +-----+  +-----+  +-----+
+
+  For each I2C child node, an I2C child bus will be created. They will be numbered based on their
+  order in the device tree.
+
+  Whenever an access is made to a device on a child bus, the value set in the relevant node's reg
+  property will be output using the list of GPIOs, the first in the list holding the least-
+  significant value.
+
+  If an idle state is defined, using the idle-state (optional) property, whenever an access is not
+  being made to a device on a child bus, the GPIOs will be set according to the idle value.
+
+  If an idle state is not defined, the most recently used value will be left programmed into
+  hardware whenever no access is being made to a device on a child bus.
+
+properties:
+  compatible:
+    const: i2c-mux-gpio
+
+  i2c-parent:
+    description: phandle of the I2C bus that this multiplexer's master-side port is connected to
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  mux-gpios:
+    description: list of GPIOs used to control the muxer
+    minItems: 1
+    maxItems: 4  # Should be enough
+
+  idle-state:
+    description: Value to set the muxer to when idle. When no value is given, it defaults to the
+      last value used.
+    $ref: "/schemas/types.yaml#/definitions/uint32"
+
+allOf:
+  - $ref: i2c-mux.yaml
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - i2c-parent
+  - mux-gpios
+
+examples:
+  - |
+    i2cmux {
+      compatible = "i2c-mux-gpio";
+      #address-cells = <1>;
+      #size-cells = <0>;
+      mux-gpios = <&gpio1 22 0>, <&gpio1 23 0>;
+      i2c-parent = <&i2c1>;
+
+      i2c@1 {
+        reg = <1>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        ssd1307: oled@3c {
+          compatible = "solomon,ssd1307fb-i2c";
+          reg = <0x3c>;
+          pwms = <&pwm 4 3000>;
+          reset-gpios = <&gpio2 7 1>;
+        };
+      };
+
+      i2c@3 {
+        reg = <3>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        pca9555: pca9555@20 {
+          compatible = "nxp,pca9555";
+          gpio-controller;
+          #gpio-cells = <2>;
+          reg = <0x20>;
+        };
+      };
+    };
--- a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt
@ -1,93 +0,0 @@
-Pinctrl-based I2C Bus Mux
-
-This binding describes an I2C bus multiplexer that uses pin multiplexing to
-route the I2C signals, and represents the pin multiplexing configuration
-using the pinctrl device tree bindings.
-
-                                 +-----+  +-----+
-                                 | dev |  | dev |
-    +------------------------+   +-----+  +-----+
-    | SoC                    |      |        |
-    |                   /----|------+--------+
-    |   +---+   +------+     | child bus A, on first set of pins
-    |   |I2C|---|Pinmux|     |
-    |   +---+   +------+     | child bus B, on second set of pins
-    |                   \----|------+--------+--------+
-    |                        |      |        |        |
-    +------------------------+  +-----+  +-----+  +-----+
-                                | dev |  | dev |  | dev |
-                                +-----+  +-----+  +-----+
-
-Required properties:
- compatible: i2c-mux-pinctrl
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
-  port is connected to.
-
-Also required are:
-
-* Standard pinctrl properties that specify the pin mux state for each child
-  bus. See ../pinctrl/pinctrl-bindings.txt.
-
-* Standard I2C mux properties. See i2c-mux.yaml in this directory.
-
-* I2C child bus nodes. See i2c-mux.yaml in this directory.
-
-For each named state defined in the pinctrl-names property, an I2C child bus
-will be created. I2C child bus numbers are assigned based on the index into
-the pinctrl-names property.
-
-The only exception is that no bus will be created for a state named "idle". If
-such a state is defined, it must be the last entry in pinctrl-names. For
-example:
-
-	pinctrl-names = "ddc", "pta", "idle"  ->  ddc = bus 0, pta = bus 1
-	pinctrl-names = "ddc", "idle", "pta"  ->  Invalid ("idle" not last)
-	pinctrl-names = "idle", "ddc", "pta"  ->  Invalid ("idle" not last)
-
-Whenever an access is made to a device on a child bus, the relevant pinctrl
-state will be programmed into hardware.
-
-If an idle state is defined, whenever an access is not being made to a device
-on a child bus, the idle pinctrl state will be programmed into hardware.
-
-If an idle state is not defined, the most recently used pinctrl state will be
-left programmed into hardware whenever no access is being made of a device on
-a child bus.
-
-Example:
-
-	i2cmux {
-		compatible = "i2c-mux-pinctrl";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		i2c-parent = <&i2c1>;
-
-		pinctrl-names = "ddc", "pta", "idle";
-		pinctrl-0 = <&state_i2cmux_ddc>;
-		pinctrl-1 = <&state_i2cmux_pta>;
-		pinctrl-2 = <&state_i2cmux_idle>;
-
-		i2c@0 {
-			reg = <0>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			eeprom {
-				compatible = "eeprom";
-				reg = <0x50>;
-			};
-		};
-
-		i2c@1 {
-			reg = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			eeprom {
-				compatible = "eeprom";
-				reg = <0x50>;
-			};
-		};
-	};
-
--- a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.yaml
@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-mux-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Pinctrl-based I2C Bus Mux
+
+maintainers:
+  - Wolfram Sang <wsa@kernel.org>
+
+description: |
+  This binding describes an I2C bus multiplexer that uses pin multiplexing to route the I2C
+  signals, and represents the pin multiplexing configuration using the pinctrl device tree
+  bindings.
+
+                                 +-----+  +-----+
+                                 | dev |  | dev |
+    +------------------------+   +-----+  +-----+
+    | SoC                    |      |        |
+    |                   /----|------+--------+
+    |   +---+   +------+     | child bus A, on first set of pins
+    |   |I2C|---|Pinmux|     |
+    |   +---+   +------+     | child bus B, on second set of pins
+    |                   \----|------+--------+--------+
+    |                        |      |        |        |
+    +------------------------+  +-----+  +-----+  +-----+
+                                | dev |  | dev |  | dev |
+                                +-----+  +-----+  +-----+
+
+  For each named state defined in the pinctrl-names property, an I2C child bus will be created.
+  I2C child bus numbers are assigned based on the index into the pinctrl-names property.
+
+  The only exception is that no bus will be created for a state named "idle". If such a state is
+  defined, it must be the last entry in pinctrl-names. For example:
+
+    pinctrl-names = "ddc", "pta", "idle"  ->  ddc = bus 0, pta = bus 1
+    pinctrl-names = "ddc", "idle", "pta"  ->  Invalid ("idle" not last)
+    pinctrl-names = "idle", "ddc", "pta"  ->  Invalid ("idle" not last)
+
+  Whenever an access is made to a device on a child bus, the relevant pinctrl state will be
+  programmed into hardware.
+
+  If an idle state is defined, whenever an access is not being made to a device on a child bus,
+  the idle pinctrl state will be programmed into hardware.
+
+  If an idle state is not defined, the most recently used pinctrl state will be left programmed
+  into hardware whenever no access is being made of a device on a child bus.
+
+properties:
+  compatible:
+    const: i2c-mux-pinctrl
+
+  i2c-parent:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: The phandle of the I2C bus that this multiplexer's master-side port is connected
+      to.
+
+allOf:
+  - $ref: i2c-mux.yaml
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - i2c-parent
+
+examples:
+  - |
+    i2cmux {
+      compatible = "i2c-mux-pinctrl";
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      i2c-parent = <&i2c1>;
+
+      pinctrl-names = "ddc", "pta", "idle";
+      pinctrl-0 = <&state_i2cmux_ddc>;
+      pinctrl-1 = <&state_i2cmux_pta>;
+      pinctrl-2 = <&state_i2cmux_idle>;
+
+      i2c@0 {
+        reg = <0>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        eeprom@50 {
+          compatible = "atmel,24c02";
+          reg = <0x50>;
+        };
+      };
+
+      i2c@1 {
+        reg = <1>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        eeprom@50 {
+          compatible = "atmel,24c02";
+          reg = <0x50>;
+        };
+      };
+    };
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
@ -1,42 +0,0 @@
-NVIDIA Tegra186 BPMP I2C controller
-
-In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
-devices, such as the I2C controller for the power management I2C bus. Software
-running on other CPUs must perform IPC to the BPMP in order to execute
-transactions on that I2C bus. This binding describes an I2C bus that is
-accessed in such a fashion.
-
-The BPMP I2C node must be located directly inside the main BPMP node. See
-../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
-
-This node represents an I2C controller. See ../i2c/i2c.txt for details of the
-core I2C binding.
-
-Required properties:
- compatible:
-    Array of strings.
-    One of:
-    - "nvidia,tegra186-bpmp-i2c".
- #address-cells: Address cells for I2C device address.
-    Single-cell integer.
-    Must be <1>.
- #size-cells:
-    Single-cell integer.
-    Must be <0>.
- nvidia,bpmp-bus-id:
-    Single-cell integer.
-    Indicates the I2C bus number this DT node represent, as defined by the
-    BPMP firmware.
-
-Example:
-
-bpmp {
-	...
-
-	i2c {
-		compatible = "nvidia,tegra186-bpmp-i2c";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		nvidia,bpmp-bus-id = <5>;
-	};
-};
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra186 (and later) BPMP I2C controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+  In Tegra186 and later, the BPMP (Boot and Power Management Processor)
+  owns certain HW devices, such as the I2C controller for the power
+  management I2C bus. Software running on other CPUs must perform IPC to
+  the BPMP in order to execute transactions on that I2C bus. This
+  binding describes an I2C bus that is accessed in such a fashion.
+
+  The BPMP I2C node must be located directly inside the main BPMP node.
+  See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
+  binding.
+
+  This node represents an I2C controller. See ../i2c/i2c.txt for details
+  of the core I2C binding.
+
+properties:
+  compatible:
+    const: nvidia,tegra186-bpmp-i2c
+
+  nvidia,bpmp-bus-id:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Indicates the I2C bus number this DT node represents,
+      as defined by the BPMP firmware.
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - "#address-cells"
+  - "#size-cells"
+  - nvidia,bpmp-bus-id
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
@ -1,87 +0,0 @@
-NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver.
-
-Required properties:
- compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
-  "nvidia,tegra20-i2c".  For Tegra30, must be "nvidia,tegra30-i2c".
-  For Tegra114, must be "nvidia,tegra114-i2c".  Otherwise, must be
-  "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
-  tegra124, tegra132, or tegra210.
-  Details of compatible are as follows:
-  nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
-	controller. This only support master mode of I2C communication. Register
-	interface/offset and interrupts handling are different than generic I2C
-	controller. Driver of DVC I2C controller is only compatible with
-	"nvidia,tegra20-i2c-dvc".
-  nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
-	master and slave mode of I2C communication. The i2c-tegra driver only
-	support master mode of I2C communication. Driver of I2C controller is
-	only compatible with "nvidia,tegra20-i2c".
-  nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
-	very much similar to Tegra20 I2C controller with additional feature:
-	Continue Transfer Support. This feature helps to implement M_NO_START
-	as per I2C core API transfer flags. Driver of I2C controller is
-	compatible with "nvidia,tegra30-i2c" to enable the continue transfer
-	support. This is also compatible with "nvidia,tegra20-i2c" without
-	continue transfer support.
-  nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is
-	very much similar to Tegra30 I2C controller with some hardware
-	modification:
-	 - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and
-	   fast-clk. Tegra114 has only one clock source called as div-clk and
-	   hence clock mechanism is changed in I2C controller.
-	 - Tegra30/Tegra20 I2C controller has enabled per packet transfer by
-	   default and there is no way to disable it. Tegra114 has this
-	   interrupt disable by default and SW need to enable explicitly.
-	Due to above changes, Tegra114 I2C driver makes incompatible with
-	previous hardware driver. Hence, tegra114 I2C controller is compatible
-	with "nvidia,tegra114-i2c".
-  nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is on host1x bus
-	and is part of VE power domain and typically used for camera use-cases.
-	This VI I2C controller is mostly compatible with the programming model
-	of the regular I2C controllers with a few exceptions. The I2C registers
-	start at an offset of 0xc00 (instead of 0), registers are 16 bytes
-	apart (rather than 4) and the controller does not support slave mode.
- reg: Should contain I2C controller registers physical address and length.
- interrupts: Should contain I2C controller interrupts.
- address-cells: Address cells for I2C device address.
- size-cells: Size of the I2C device address.
- clocks: Must contain an entry for each entry in clock-names.
-  See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
-  Tegra20/Tegra30:
-  - div-clk
-  - fast-clk
-  Tegra114:
-  - div-clk
-  Tegra210:
-  - div-clk
-  - slow (only for nvidia,tegra210-i2c-vi compatible node)
- resets: Must contain an entry for each entry in reset-names.
-  See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
-  - i2c
- power-domains: Only for nvidia,tegra210-i2c-vi compatible node and must
-  include venc powergate node as vi i2c is part of VE power domain.
-  tegra210-i2c-vi:
-  - pd_venc
- dmas: Must contain an entry for each entry in clock-names.
-  See ../dma/dma.txt for details.
- dma-names: Must include the following entries:
-  - rx
-  - tx
-
-Example:
-
-	i2c@7000c000 {
-		compatible = "nvidia,tegra20-i2c";
-		reg = <0x7000c000 0x100>;
-		interrupts = <0 38 0x04>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car 12>, <&tegra_car 124>;
-		clock-names = "div-clk", "fast-clk";
-		resets = <&tegra_car 12>;
-		reset-names = "i2c";
-		dmas = <&apbdma 16>, <&apbdma 16>;
-		dma-names = "rx", "tx";
-	};
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
@ -0,0 +1,192 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+title: NVIDIA Tegra I2C controller driver
+
+properties:
+  compatible:
+    oneOf:
+      - description: Tegra20 has 4 generic I2C controller. This can support
+          master and slave mode of I2C communication. The i2c-tegra driver
+          only support master mode of I2C communication. Driver of I2C
+          controller is only compatible with "nvidia,tegra20-i2c".
+        const: nvidia,tegra20-i2c
+      - description: Tegra20 has specific I2C controller called as DVC I2C
+          controller. This only support master mode of I2C communication.
+          Register interface/offset and interrupts handling are different than
+          generic I2C controller. Driver of DVC I2C controller is only
+          compatible with "nvidia,tegra20-i2c-dvc".
+        const: nvidia,tegra20-i2c-dvc
+      - description: |
+          Tegra30 has 5 generic I2C controller. This controller is very much
+          similar to Tegra20 I2C controller with additional feature: Continue
+          Transfer Support. This feature helps to implement M_NO_START as per
+          I2C core API transfer flags. Driver of I2C controller is compatible
+          with "nvidia,tegra30-i2c" to enable the continue transfer support.
+          This is also compatible with "nvidia,tegra20-i2c" without continue
+          transfer support.
+        items:
+          - const: nvidia,tegra30-i2c
+          - const: nvidia,tegra20-i2c
+      - description: |
+          Tegra114 has 5 generic I2C controllers. This controller is very much
+          similar to Tegra30 I2C controller with some hardware modification:
+            - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk
+              and fast-clk. Tegra114 has only one clock source called as
+              div-clk and hence clock mechanism is changed in I2C controller.
+            - Tegra30/Tegra20 I2C controller has enabled per packet transfer
+              by default and there is no way to disable it. Tegra114 has this
+              interrupt disable by default and SW need to enable explicitly.
+          Due to above changes, Tegra114 I2C driver makes incompatible with
+          previous hardware driver. Hence, Tegra114 I2C controller is
+          compatible with "nvidia,tegra114-i2c".
+        const: nvidia,tegra114-i2c
+      - description: |
+          Tegra124 has 6 generic I2C controllers. These controllers are very
+          similar to those found on Tegra114 but also contain several hardware
+          improvements and new registers.
+        const: nvidia,tegra124-i2c
+      - description: |
+          Tegra210 has 6 generic I2C controllers. These controllers are very
+          similar to those found on Tegra124.
+        items:
+          - const: nvidia,tegra210-i2c
+          - const: nvidia,tegra124-i2c
+      - description: |
+          Tegra210 has one I2C controller that is on host1x bus and is part of
+          the VE power domain and typically used for camera use-cases. This VI
+          I2C controller is mostly compatible with the programming model of
+          the regular I2C controllers with a few exceptions. The I2C registers
+          start at an offset of 0xc00 (instead of 0), registers are 16 bytes
+          apart (rather than 4) and the controller does not support slave
+          mode.
+        const: nvidia,tegra210-i2c-vi
+      - description: |
+          Tegra186 has 9 generic I2C controllers, two of which are in the AON
+          (always-on) partition of the SoC. All of these controllers are very
+          similar to those found on Tegra210.
+        const: nvidia,tegra186-i2c
+      - description: |
+          Tegra194 has 8 generic I2C controllers, two of which are in the AON
+          (always-on) partition of the SoC. All of these controllers are very
+          similar to those found on Tegra186. However, these controllers have
+          support for 64 KiB transactions whereas earlier chips supported no
+          more than 4 KiB per transactions.
+        const: nvidia,tegra194-i2c
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 0
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    maxItems: 2
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: i2c
+
+  dmas:
+    items:
+      - description: DMA channel for the reception FIFO
+      - description: DMA channel for the transmission FIFO
+
+  dma-names:
+    items:
+      - const: rx
+      - const: tx
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra20-i2c
+              - nvidia,tegra30-i2c
+    then:
+      properties:
+        clock-names:
+          items:
+            - const: div-clk
+            - const: fast-clk
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra114-i2c
+    then:
+      properties:
+        clock-names:
+          items:
+            - const: div-clk
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra210-i2c
+    then:
+      properties:
+        clock-names:
+          items:
+            - const: div-clk
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra210-i2c-vi
+    then:
+      properties:
+        clock-names:
+          items:
+            - const: div-clk
+            - const: slow
+        power-domains:
+          items:
+            - description: phandle to the VENC power domain
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    i2c@7000c000 {
+        compatible = "nvidia,tegra20-i2c";
+        reg = <0x7000c000 0x100>;
+        interrupts = <0 38 0x04>;
+        clocks = <&tegra_car 12>, <&tegra_car 124>;
+        clock-names = "div-clk", "fast-clk";
+        resets = <&tegra_car 12>;
+        reset-names = "i2c";
+        dmas = <&apbdma 16>, <&apbdma 16>;
+        dma-names = "rx", "tx";
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+    };
--- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
@ -112,6 +112,9 @@ examples:
          clocks = <&rcc 0 149>;
      };

+  - |
+    #include <dt-bindings/mfd/stm32f7-rcc.h>
+    #include <dt-bindings/clock/stm32fx-clock.h>
    //Example 2 (with st,stm32f7-i2c compatible)
      i2c@40005800 {
          compatible = "st,stm32f7-i2c";
@ -124,6 +127,9 @@ examples:
          clocks = <&rcc 1 CLK_I2C1>;
      };

+  - |
+    #include <dt-bindings/mfd/stm32f7-rcc.h>
+    #include <dt-bindings/clock/stm32fx-clock.h>
    //Example 3 (with st,stm32mp15-i2c compatible on stm32mp)
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
--- a/Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: ADC found on Freescale vf610 and similar SoCs

 maintainers:
-  - Fugang Duan <fugang.duan@nxp.com>
+  - Haibo Chen <haibo.chen@nxp.com>

 description:
  ADCs found on vf610/i.MX6slx and upward SoCs from Freescale.
--- a/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml
@ -27,6 +27,7 @@ description: |
   8 | batt_v
   9 | batt_chrg_i
  10 | batt_dischrg_i
+  11 | ts_v

  AXP22x
  ------
@ -34,6 +35,7 @@ description: |
   1 | batt_v
   2 | batt_chrg_i
   3 | batt_dischrg_i
+   4 | ts_v

  AXP813
  ------
@ -42,6 +44,7 @@ description: |
   2 | batt_v
   3 | batt_chrg_i
   4 | batt_dischrg_i
+   5 | ts_v


 properties:
--- a/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml
@ -0,0 +1,227 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/xlnx,zynqmp-ams.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq Ultrascale AMS controller
+
+maintainers:
+  - Anand Ashok Dumbre <anand.ashok.dumbre@xilinx.com>
+
+description: |
+  The AMS (Analog Monitoring System) includes an ADC as well as on-chip sensors
+  that can be used to sample external voltages and monitor on-die operating
+  conditions, such as temperature and supply voltage levels.
+  The AMS has two SYSMON blocks which are PL (Programmable Logic) SYSMON and
+  PS (Processing System) SYSMON.
+  All designs should have AMS registers, but PS and PL are optional. The
+  AMS controller can work with only PS, only PL and both PS and PL
+  configurations. Please specify registers according to your design. Devicetree
+  should always have AMS module property. Providing PS & PL module is optional.
+
+  AMS Channel Details
+  ```````````````````
+  Sysmon Block  |Channel|                       Details                                 |Measurement
+                |Number |                                                               |Type
+  ---------------------------------------------------------------------------------------------------------
+  AMS CTRL      |0      |System PLLs voltage measurement, VCC_PSPLL.                    |Voltage
+                |1      |Battery voltage measurement, VCC_PSBATT.                       |Voltage
+                |2      |PL Internal voltage measurement, VCCINT.                       |Voltage
+                |3      |Block RAM voltage measurement, VCCBRAM.                        |Voltage
+                |4      |PL Aux voltage measurement, VCCAUX.                            |Voltage
+                |5      |Voltage measurement for six DDR I/O PLLs, VCC_PSDDR_PLL.       |Voltage
+                |6      |VCC_PSINTFP_DDR voltage measurement.                           |Voltage
+  ---------------------------------------------------------------------------------------------------------
+  PS Sysmon     |7      |LPD temperature measurement.                                   |Temperature
+                |8      |FPD temperature measurement (REMOTE).                          |Temperature
+                |9      |VCC PS LPD voltage measurement (supply1).                      |Voltage
+                |10     |VCC PS FPD voltage measurement (supply2).                      |Voltage
+                |11     |PS Aux voltage reference (supply3).                            |Voltage
+                |12     |DDR I/O VCC voltage measurement.                               |Voltage
+                |13     |PS IO Bank 503 voltage measurement (supply5).                  |Voltage
+                |14     |PS IO Bank 500 voltage measurement (supply6).                  |Voltage
+                |15     |VCCO_PSIO1 voltage measurement.                                |Voltage
+                |16     |VCCO_PSIO2 voltage measurement.                                |Voltage
+                |17     |VCC_PS_GTR voltage measurement (VPS_MGTRAVCC).                 |Voltage
+                |18     |VTT_PS_GTR voltage measurement (VPS_MGTRAVTT).                 |Voltage
+                |19     |VCC_PSADC voltage measurement.                                 |Voltage
+  ---------------------------------------------------------------------------------------------------------
+  PL Sysmon     |20     |PL temperature measurement.                                    |Temperature
+                |21     |PL Internal voltage measurement, VCCINT.                       |Voltage
+                |22     |PL Auxiliary voltage measurement, VCCAUX.                      |Voltage
+                |23     |ADC Reference P+ voltage measurement.                          |Voltage
+                |24     |ADC Reference N- voltage measurement.                          |Voltage
+                |25     |PL Block RAM voltage measurement, VCCBRAM.                     |Voltage
+                |26     |LPD Internal voltage measurement, VCC_PSINTLP (supply4).       |Voltage
+                |27     |FPD Internal voltage measurement, VCC_PSINTFP (supply5).       |Voltage
+                |28     |PS Auxiliary voltage measurement (supply6).                    |Voltage
+                |29     |PL VCCADC voltage measurement (vccams).                        |Voltage
+                |30     |Differential analog input signal voltage measurment.           |Voltage
+                |31     |VUser0 voltage measurement (supply7).                          |Voltage
+                |32     |VUser1 voltage measurement (supply8).                          |Voltage
+                |33     |VUser2 voltage measurement (supply9).                          |Voltage
+                |34     |VUser3 voltage measurement (supply10).                         |Voltage
+                |35     |Auxiliary ch 0 voltage measurement (VAux0).                    |Voltage
+                |36     |Auxiliary ch 1 voltage measurement (VAux1).                    |Voltage
+                |37     |Auxiliary ch 2 voltage measurement (VAux2).                    |Voltage
+                |38     |Auxiliary ch 3 voltage measurement (VAux3).                    |Voltage
+                |39     |Auxiliary ch 4 voltage measurement (VAux4).                    |Voltage
+                |40     |Auxiliary ch 5 voltage measurement (VAux5).                    |Voltage
+                |41     |Auxiliary ch 6 voltage measurement (VAux6).                    |Voltage
+                |42     |Auxiliary ch 7 voltage measurement (VAux7).                    |Voltage
+                |43     |Auxiliary ch 8 voltage measurement (VAux8).                    |Voltage
+                |44     |Auxiliary ch 9 voltage measurement (VAux9).                    |Voltage
+                |45     |Auxiliary ch 10 voltage measurement (VAux10).                  |Voltage
+                |46     |Auxiliary ch 11 voltage measurement (VAux11).                  |Voltage
+                |47     |Auxiliary ch 12 voltage measurement (VAux12).                  |Voltage
+                |48     |Auxiliary ch 13 voltage measurement (VAux13).                  |Voltage
+                |49     |Auxiliary ch 14 voltage measurement (VAux14).                  |Voltage
+                |50     |Auxiliary ch 15 voltage measurement (VAux15).                  |Voltage
+  --------------------------------------------------------------------------------------------------------
+
+properties:
+  compatible:
+    enum:
+      - xlnx,zynqmp-ams
+
+  interrupts:
+    maxItems: 1
+
+  reg:
+    description: AMS Controller register space
+    maxItems: 1
+
+  ranges:
+    description:
+      Maps the child address space for PS and/or PL.
+    maxItems: 1
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 1
+
+  '#io-channel-cells':
+    const: 1
+
+  ams-ps@0:
+    type: object
+    description: |
+      PS (Processing System) SYSMON is memory mapped to PS. This block has
+      built-in alarm generation logic that is used to interrupt the processor
+      based on condition set.
+
+    properties:
+      compatible:
+        enum:
+          - xlnx,zynqmp-ams-ps
+
+      reg:
+        description: Register Space for PS-SYSMON
+        maxItems: 1
+
+    required:
+      - compatible
+      - reg
+
+    additionalProperties: false
+
+  ams-pl@400:
+    type: object
+    description:
+      PL-SYSMON is capable of monitoring off chip voltage and temperature.
+      PL-SYSMON block has DRP, JTAG and I2C interface to enable monitoring
+      from external master. Out of this interface currently only DRP is
+      supported. This block has alarm generation logic that is used to
+      interrupt the processor based on condition set.
+
+    properties:
+      compatible:
+        items:
+          - enum:
+              - xlnx,zynqmp-ams-pl
+
+      reg:
+        description: Register Space for PL-SYSMON.
+        maxItems: 1
+
+      '#address-cells':
+        const: 1
+
+      '#size-cells':
+        const: 0
+
+    patternProperties:
+      "^channel@([2-4][0-9]|50)$":
+        type: object
+        description:
+          Describes the external channels connected.
+
+        properties:
+          reg:
+            description:
+              Pair of pins the channel is connected to. This value is
+              same as Channel Number for a particular channel.
+            minimum: 20
+            maximum: 50
+
+          xlnx,bipolar:
+            $ref: /schemas/types.yaml#/definitions/flag
+            type: boolean
+            description:
+              If the set channel is used in bipolar mode.
+
+        required:
+          - reg
+
+        additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        xilinx_ams: ams@ffa50000 {
+            compatible = "xlnx,zynqmp-ams";
+            interrupt-parent = <&gic>;
+            interrupts = <0 56 4>;
+            reg = <0x0 0xffa50000 0x0 0x800>;
+            #address-cells = <1>;
+            #size-cells = <1>;
+            #io-channel-cells = <1>;
+            ranges = <0 0 0xffa50800 0x800>;
+
+            ams_ps: ams-ps@0 {
+                compatible = "xlnx,zynqmp-ams-ps";
+                reg = <0 0x400>;
+            };
+
+            ams_pl: ams-pl@400 {
+                compatible = "xlnx,zynqmp-ams-pl";
+                reg = <0x400 0x400>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                channel@30 {
+                    reg = <30>;
+                    xlnx,bipolar;
+                };
+                channel@31 {
+                    reg = <31>;
+                };
+                channel@38 {
+                    reg = <38>;
+                    xlnx,bipolar;
+                };
+            };
+        };
+    };
--- a/Documentation/devicetree/bindings/iio/addac/adi,ad74413r.yaml
+++ b/Documentation/devicetree/bindings/iio/addac/adi,ad74413r.yaml
@ -0,0 +1,158 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/addac/adi,ad74413r.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD74412R/AD74413R device
+
+maintainers:
+  - Cosmin Tanislav <cosmin.tanislav@analog.com>
+
+description: |
+  The AD74412R and AD74413R are quad-channel software configurable input/output
+  solutions for building and process control applications. They contain
+  functionality for analog output, analog input, digital input, resistance
+  temperature detector, and thermocouple measurements integrated
+  into a single chip solution with an SPI interface.
+  The devices feature a 16-bit ADC and four configurable 13-bit DACs to provide
+  four configurable input/output channels and a suite of diagnostic functions.
+  The AD74413R differentiates itself from the AD74412R by being HART-compatible.
+    https://www.analog.com/en/products/ad74412r.html
+    https://www.analog.com/en/products/ad74413r.html
+
+properties:
+  compatible:
+    enum:
+      - adi,ad74412r
+      - adi,ad74413r
+
+  reg:
+    maxItems: 1
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 0
+
+  spi-max-frequency:
+    maximum: 1000000
+
+  spi-cpol: true
+
+  interrupts:
+    maxItems: 1
+
+  refin-supply: true
+
+  shunt-resistor-micro-ohms:
+    description:
+      Shunt (sense) resistor value in micro-Ohms.
+    default: 100000000
+
+required:
+  - compatible
+  - reg
+  - spi-max-frequency
+  - spi-cpol
+  - refin-supply
+
+additionalProperties: false
+
+patternProperties:
+  "^channel@[0-3]$":
+    type: object
+    description: Represents the external channels which are connected to the device.
+
+    properties:
+      reg:
+        description: |
+          The channel number. It can have up to 4 channels numbered from 0 to 3.
+        minimum: 0
+        maximum: 3
+
+      adi,ch-func:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Channel function.
+          HART functions are not supported on AD74412R.
+          0 - CH_FUNC_HIGH_IMPEDANCE
+          1 - CH_FUNC_VOLTAGE_OUTPUT
+          2 - CH_FUNC_CURRENT_OUTPUT
+          3 - CH_FUNC_VOLTAGE_INPUT
+          4 - CH_FUNC_CURRENT_INPUT_EXT_POWER
+          5 - CH_FUNC_CURRENT_INPUT_LOOP_POWER
+          6 - CH_FUNC_RESISTANCE_INPUT
+          7 - CH_FUNC_DIGITAL_INPUT_LOGIC
+          8 - CH_FUNC_DIGITAL_INPUT_LOOP_POWER
+          9 - CH_FUNC_CURRENT_INPUT_EXT_POWER_HART
+          10 - CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART
+        minimum: 0
+        maximum: 10
+        default: 0
+
+      adi,gpo-comparator:
+        type: boolean
+        description: |
+          Whether to configure GPO as a comparator or not.
+          When not configured as a comparator, the GPO will be treated as an
+          output-only GPIO.
+
+    required:
+      - reg
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/iio/addac/adi,ad74413r.h>
+
+    spi {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      cs-gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+      status = "okay";
+
+      ad74413r@0 {
+        compatible = "adi,ad74413r";
+        reg = <0>;
+        spi-max-frequency = <1000000>;
+        spi-cpol;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        interrupt-parent = <&gpio>;
+        interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+
+        refin-supply = <&ad74413r_refin>;
+
+        channel@0 {
+          reg = <0>;
+
+          adi,ch-func = <CH_FUNC_VOLTAGE_OUTPUT>;
+        };
+
+        channel@1 {
+          reg = <1>;
+
+          adi,ch-func = <CH_FUNC_CURRENT_OUTPUT>;
+        };
+
+        channel@2 {
+          reg = <2>;
+
+          adi,ch-func = <CH_FUNC_DIGITAL_INPUT_LOGIC>;
+          adi,gpo-comparator;
+        };
+
+        channel@3 {
+          reg = <3>;
+
+          adi,ch-func = <CH_FUNC_CURRENT_INPUT_EXT_POWER>;
+        };
+      };
+    };
+...
--- a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
+++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
@ -0,0 +1,217 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2020 Analog Devices Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/adi,ad3552r.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD2552R DAC device driver
+
+maintainers:
+  - Mihail Chindris <mihail.chindris@analog.com>
+
+description: |
+  Bindings for the Analog Devices AD3552R DAC device and similar.
+  Datasheet can be found here:
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad3542r.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad3552r.pdf
+
+properties:
+  compatible:
+    enum:
+      - adi,ad3542r
+      - adi,ad3552r
+
+  reg:
+    maxItems: 1
+
+  spi-max-frequency:
+    maximum: 30000000
+
+  reset-gpios:
+    maxItems: 1
+
+  ldac-gpios:
+    description: |
+      LDAC pin to be used as a hardware trigger to update the DAC channels.
+    maxItems: 1
+
+  vref-supply:
+    description:
+      The regulator to use as an external reference. If it does not exists the
+      internal reference will be used. External reference must be 2.5V
+
+  adi,vref-out-en:
+    description: Vref I/O driven by internal vref to 2.5V. If not set, Vref pin
+      will be floating.
+    type: boolean
+
+  adi,sdo-drive-strength:
+    description: |
+      Configure SDIO0 and SDIO1 strength levels:
+        - 0: low SDO drive strength.
+        - 1: medium low SDO drive strength.
+        - 2: medium high SDO drive strength.
+        - 3: high SDO drive strength
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2, 3]
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 0
+
+patternProperties:
+  "^channel@([0-1])$":
+    type: object
+    description: Configurations of the DAC Channels
+
+    additionalProperties: false
+
+    properties:
+      reg:
+        description: Channel number
+        enum: [0, 1]
+
+      adi,output-range-microvolt: true
+
+      custom-output-range-config:
+        type: object
+        description: Configuration of custom range when
+          adi,output-range-microvolt is not present.
+          The formulas for calculation the output voltages are
+            Vout_fs = 2.5 + [(GainN + Offset/1024) * 2.5 * Rfbx * 1.03]
+            Vout_zs = 2.5 - [(GainP + Offset/1024) * 2.5 * Rfbx * 1.03]
+
+        properties:
+          adi,gain-offset:
+            description: Gain offset used in the above formula
+            $ref: /schemas/types.yaml#/definitions/int32
+            maximum: 511
+            minimum: -511
+
+          adi,gain-scaling-p-inv-log2:
+            description: GainP = 1 / ( 2 ^ adi,gain-scaling-p-inv-log2)
+            $ref: /schemas/types.yaml#/definitions/uint32
+            enum: [0, 1, 2, 3]
+
+          adi,gain-scaling-n-inv-log2:
+            description: GainN = 1 / ( 2 ^ adi,gain-scaling-n-inv-log2)
+            $ref: /schemas/types.yaml#/definitions/uint32
+            enum: [0, 1, 2, 3]
+
+          adi,rfb-ohms:
+            description: Feedback Resistor
+
+        required:
+          - adi,gain-offset
+          - adi,gain-scaling-p-inv-log2
+          - adi,gain-scaling-n-inv-log2
+          - adi,rfb-ohms
+
+    required:
+      - reg
+
+    oneOf:
+      # If adi,output-range-microvolt is missing,
+      # custom-output-range-config must be used
+      - required:
+          - adi,output-range-microvolt
+
+      - required:
+          - custom-output-range-config
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: adi,ad3542r
+    then:
+      patternProperties:
+        "^channel@([0-1])$":
+          type: object
+          properties:
+            adi,output-range-microvolt:
+              description: |
+                Voltage output range of the channel as <minimum, maximum>
+                Required connections:
+                  Rfb1x for: 0 to 2.5 V; 0 to 3V; 0 to 5 V;
+                  Rfb2x for: 0 to 10 V; 2.5 to 7.5V; -5 to 5 V;
+              oneOf:
+                - items:
+                    - const: 0
+                    - enum: [2500000, 3000000, 5000000, 10000000]
+                - items:
+                    - const: -2500000
+                    - const: 7500000
+                - items:
+                    - const: -5000000
+                    - const: 5000000
+
+          required:
+            - adi,output-range-microvolt
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: adi,ad3552r
+    then:
+      patternProperties:
+        "^channel@([0-1])$":
+          type: object
+          properties:
+            adi,output-range-microvolt:
+              description: |
+                Voltage output range of the channel as <minimum, maximum>
+                Required connections:
+                  Rfb1x for: 0 to 2.5 V; 0 to 5 V;
+                  Rfb2x for: 0 to 10 V; -5 to 5 V;
+                  Rfb4x for: -10 to 10V
+              oneOf:
+                - items:
+                    - const: 0
+                    - enum: [2500000, 5000000, 10000000]
+                - items:
+                    - const: -5000000
+                    - const: 5000000
+                - items:
+                    - const: -10000000
+                    - const: 10000000
+
+required:
+  - compatible
+  - reg
+  - spi-max-frequency
+
+additionalProperties: false
+
+examples:
+  - |
+    spi {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      ad3552r@0 {
+              compatible = "adi,ad3552r";
+              reg = <0>;
+              spi-max-frequency = <20000000>;
+              #address-cells = <1>;
+              #size-cells = <0>;
+              channel@0 {
+                      reg = <0>;
+                      adi,output-range-microvolt = <0 10000000>;
+              };
+              channel@1 {
+                      reg = <1>;
+                      custom-output-range-config {
+                              adi,gain-offset = <5>;
+                              adi,gain-scaling-p-inv-log2 = <1>;
+                              adi,gain-scaling-n-inv-log2 = <2>;
+                              adi,rfb-ohms = <1>;
+                      };
+            };
+        };
+    };
+...
--- a/Documentation/devicetree/bindings/iio/dac/adi,ad5755.yaml
+++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5755.yaml
@ -125,7 +125,6 @@ oneOf:

 examples:
  - |
-    #include <dt-bindings/iio/adi,ad5592r.h>
    spi {
        #address-cells = <1>;
        #size-cells = <0>;
--- a/Documentation/devicetree/bindings/iio/dac/adi,ad7293.yaml
+++ b/Documentation/devicetree/bindings/iio/dac/adi,ad7293.yaml
@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/adi,ad7293.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AD7293 12-Bit Power Amplifier Current Controller with ADC,
+       DACs, Temperature and Current Sensors
+
+maintainers:
+  - Antoniu Miclaus <antoniu.miclaus@analog.com>
+
+description: |
+   Power Amplifier drain current controller containing functionality
+   for general-purpose monitoring and control of current, voltage,
+   and temperature, integrated into a single chip solution with an
+   SPI-compatible interface.
+
+   https://www.analog.com/en/products/ad7293.html
+
+properties:
+  compatible:
+    enum:
+      - adi,ad7293
+
+  avdd-supply: true
+
+  vdrive-supply: true
+
+  reset-gpios:
+    maxItems: 1
+
+  reg:
+    maxItems: 1
+
+  spi-max-frequency:
+    maximum: 1000000
+
+required:
+  - compatible
+  - reg
+  - avdd-supply
+  - vdrive-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    spi {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      ad7293@0 {
+        compatible = "adi,ad7293";
+        reg = <0>;
+        spi-max-frequency = <1000000>;
+        avdd-supply = <&avdd>;
+        vdrive-supply = <&vdrive>;
+        reset-gpios = <&gpio 10 0>;
+      };
+    };
+...
--- a/Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml
+++ b/Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml
@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/filter/adi,admv8818.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADMV8818 Digitally Tunable, High-Pass and Low-Pass Filter
+
+maintainers:
+  - Antoniu Miclaus <antoniu.miclaus@analog.com>
+
+description: |
+    Fully monolithic microwave integrated circuit (MMIC) that
+    features a digitally selectable frequency of operation.
+    The device features four independently controlled high-pass
+    filters (HPFs) and four independently controlled low-pass filters
+    (LPFs) that span the 2 GHz to 18 GHz frequency range.
+
+    https://www.analog.com/en/products/admv8818.html
+
+properties:
+  compatible:
+    enum:
+      - adi,admv8818
+
+  reg:
+    maxItems: 1
+
+  spi-max-frequency:
+    maximum: 10000000
+
+  clocks:
+    description:
+      Definition of the external clock.
+    minItems: 1
+
+  clock-names:
+    items:
+      - const: rf_in
+
+  clock-output-names:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 0
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    spi {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      admv8818@0 {
+        compatible = "adi,admv8818";
+        reg = <0>;
+        spi-max-frequency = <10000000>;
+        clocks = <&admv8818_rfin>;
+        clock-names = "rf_in";
+      };
+    };
+...
--- a/Documentation/devicetree/bindings/iio/frequency/adi,admv1013.yaml
+++ b/Documentation/devicetree/bindings/iio/frequency/adi,admv1013.yaml
@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/frequency/adi,admv1013.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADMV1013 Microwave Upconverter
+
+maintainers:
+  - Antoniu Miclaus <antoniu.miclaus@analog.com>
+
+description: |
+   Wideband, microwave upconverter optimized for point to point microwave
+   radio designs operating in the 24 GHz to 44 GHz frequency range.
+
+   https://www.analog.com/en/products/admv1013.html
+
+properties:
+  compatible:
+    enum:
+      - adi,admv1013
+
+  reg:
+    maxItems: 1
+
+  spi-max-frequency:
+    maximum: 1000000
+
+  clocks:
+    description:
+      Definition of the external clock.
+    minItems: 1
+
+  clock-names:
+    items:
+      - const: lo_in
+
+  vcm-supply:
+    description:
+      Analog voltage regulator.
+
+  adi,detector-enable:
+    description:
+      Enable the Envelope Detector available at output pins VENV_P and
+      VENV_N. Disable to reduce power consumption.
+    type: boolean
+
+  adi,input-mode:
+    description:
+      Select the input mode.
+      iq - in-phase quadrature (I/Q) input
+      if - complex intermediate frequency (IF) input
+    enum: [iq, if]
+
+  adi,quad-se-mode:
+    description:
+      Switch the LO path from differential to single-ended operation.
+      se-neg - Single-Ended Mode, Negative Side Disabled.
+      se-pos - Single-Ended Mode, Positive Side Disabled.
+      diff - Differential Mode.
+    enum: [se-neg, se-pos, diff]
+
+  '#clock-cells':
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - vcm-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    spi {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      admv1013@0{
+        compatible = "adi,admv1013";
+        reg = <0>;
+        spi-max-frequency = <1000000>;
+        clocks = <&admv1013_lo>;
+        clock-names = "lo_in";
+        vcm-supply = <&vcm>;
+        adi,quad-se-mode = "diff";
+        adi,detector-enable;
+      };
+    };
+...
--- a/Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.yaml
+++ b/Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.yaml
@ -61,7 +61,7 @@ examples:
                #size-cells = <0>;

                magnetometer@c {
-                    compatible = "ak,ak8975";
+                    compatible = "asahi-kasei,ak8975";
                    reg = <0x0c>;
                };
            };
--- a/Documentation/devicetree/bindings/iio/imu/invensense,mpu6050.yaml
+++ b/Documentation/devicetree/bindings/iio/imu/invensense,mpu6050.yaml
@ -95,7 +95,7 @@ examples:
                #address-cells = <1>;
                #size-cells = <0>;
                magnetometer@c {
-                    compatible = "ak,ak8975";
+                    compatible = "asahi-kasei,ak8975";
                    reg = <0x0c>;
                };
            };
--- a/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml
+++ b/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml
@ -61,6 +61,13 @@ properties:
    type: boolean
    description: enable/disable internal i2c controller pullup resistors.

+  st,disable-sensor-hub:
+    type: boolean
+    description:
+      Enable/disable internal i2c controller slave autoprobing at bootstrap.
+      Disable sensor-hub is useful if i2c controller clock/data lines are
+      connected through a pull-up with other chip lines (e.g. SDO/SA0).
+
  drive-open-drain:
    type: boolean
    description:
--- a/Documentation/devicetree/bindings/iio/light/liteon,ltr501.yaml
+++ b/Documentation/devicetree/bindings/iio/light/liteon,ltr501.yaml
@ -9,6 +9,9 @@ title: LiteON LTR501 I2C Proximity and Light sensor
 maintainers:
  - Nikita Travkin <nikita@trvn.ru>

+allOf:
+  - $ref: ../common.yaml#
+
 properties:
  compatible:
    enum:
@ -25,6 +28,8 @@ properties:
  interrupts:
    maxItems: 1

+  proximity-near-level: true
+
 additionalProperties: false

 required:
@ -42,6 +47,8 @@ examples:
        light-sensor@23 {
            compatible = "liteon,ltr559";
            reg = <0x23>;
+            proximity-near-level = <75>;
+
            vdd-supply = <&pm8916_l17>;
            vddio-supply = <&pm8916_l6>;

--- a/Documentation/devicetree/bindings/iio/magnetometer/yamaha,yas530.yaml
+++ b/Documentation/devicetree/bindings/iio/magnetometer/yamaha,yas530.yaml
@ -96,7 +96,7 @@ examples:
          vdd-supply = <&ldo1_reg>;
          iovdd-supply = <&ldo2_reg>;
          reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
-          interrupts = <&gpio6 13 IRQ_TYPE_EDGE_RISING>;
+          interrupts = <13 IRQ_TYPE_EDGE_RISING>;
        };
    };

--- a/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml
+++ b/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml
@ -448,17 +448,17 @@ examples:
                        reg = <20>;
                        adi,sensor-type = <9>; //custom thermocouple
                        adi,single-ended;
-                        adi,custom-thermocouple = /bits/ 64
-                                 <(-50220000) 0>,
-                                 <(-30200000) 99100000>,
-                                 <(-5300000) 135400000>,
-                                 <0 273150000>,
-                                 <40200000 361200000>,
-                                 <55300000 522100000>,
-                                 <88300000 720300000>,
-                                 <132200000 811200000>,
-                                 <188700000 922500000>,
-                                 <460400000 1000000000>; //10 pairs
+                        adi,custom-thermocouple =
+                                 /bits/ 64 <(-50220000) 0>,
+                                 /bits/ 64 <(-30200000) 99100000>,
+                                 /bits/ 64 <(-5300000) 135400000>,
+                                 /bits/ 64 <0 273150000>,
+                                 /bits/ 64 <40200000 361200000>,
+                                 /bits/ 64 <55300000 522100000>,
+                                 /bits/ 64 <88300000 720300000>,
+                                 /bits/ 64 <132200000 811200000>,
+                                 /bits/ 64 <188700000 922500000>,
+                                 /bits/ 64 <460400000 1000000000>; //10 pairs
               };

        };
--- a/Documentation/devicetree/bindings/input/pwm-vibrator.txt
+++ b/Documentation/devicetree/bindings/input/pwm-vibrator.txt
@ -1,66 +0,0 @@
-* PWM vibrator device tree bindings
-
-Registers a PWM device as vibrator. It is expected, that the vibrator's
-strength increases based on the duty cycle of the enable PWM channel
-(100% duty cycle meaning strongest vibration, 0% meaning no vibration).
-
-The binding supports an optional direction PWM channel, that can be
-driven at fixed duty cycle. If available this is can be used to increase
-the vibration effect of some devices.
-
-Required properties:
- compatible: should contain "pwm-vibrator"
- pwm-names: Should contain "enable" and optionally "direction"
- pwms: Should contain a PWM handle for each entry in pwm-names
-
-Optional properties:
- vcc-supply: Phandle for the regulator supplying power
- direction-duty-cycle-ns: Duty cycle of the direction PWM channel in
-                           nanoseconds, defaults to 50% of the channel's
-			   period.
-
-Example from Motorola Droid 4:
-
-&omap4_pmx_core {
-	vibrator_direction_pin: pinmux_vibrator_direction_pin {
-		pinctrl-single,pins = <
-		OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */
-		>;
-	};
-
-	vibrator_enable_pin: pinmux_vibrator_enable_pin {
-		pinctrl-single,pins = <
-		OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */
-		>;
-	};
-};
-
-/ {
-	pwm8: dmtimer-pwm {
-		pinctrl-names = "default";
-		pinctrl-0 = <&vibrator_direction_pin>;
-
-		compatible = "ti,omap-dmtimer-pwm";
-		#pwm-cells = <3>;
-		ti,timers = <&timer8>;
-		ti,clock-source = <0x01>;
-	};
-
-	pwm9: dmtimer-pwm {
-		pinctrl-names = "default";
-		pinctrl-0 = <&vibrator_enable_pin>;
-
-		compatible = "ti,omap-dmtimer-pwm";
-		#pwm-cells = <3>;
-		ti,timers = <&timer9>;
-		ti,clock-source = <0x01>;
-	};
-
-	vibrator {
-		compatible = "pwm-vibrator";
-		pwms = <&pwm9 0 1000000000 0>,
-                       <&pwm8 0 1000000000 0>;
-		pwm-names = "enable", "direction";
-		direction-duty-cycle-ns = <1000000000>;
-	};
-};
--- a/Documentation/devicetree/bindings/input/pwm-vibrator.yaml
+++ b/Documentation/devicetree/bindings/input/pwm-vibrator.yaml
@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/input/pwm-vibrator.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: PWM vibrator
+
+maintainers:
+  - Sebastian Reichel <sre@kernel.org>
+
+description: >
+  Registers a PWM device as vibrator. It is expected, that the vibrator's
+  strength increases based on the duty cycle of the enable PWM channel
+  (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
+
+  The binding supports an optional direction PWM channel, that can be
+  driven at fixed duty cycle. If available this is can be used to increase
+  the vibration effect of some devices.
+
+properties:
+  compatible:
+    const: pwm-vibrator
+
+  pwm-names:
+    items:
+      - const: enable
+      - const: direction
+    minItems: 1
+
+  pwms:
+    minItems: 1
+    maxItems: 2
+
+  vcc-supply: true
+
+  direction-duty-cycle-ns:
+    description: >
+      Duty cycle of the direction PWM channel in nanoseconds,
+      defaults to 50% of the channel's period.
+
+required:
+  - compatible
+  - pwm-names
+  - pwms
+
+additionalProperties: false
+
+examples:
+  - |
+    vibrator {
+        compatible = "pwm-vibrator";
+        pwms = <&pwm9 0 1000000000 0>,
+               <&pwm8 0 1000000000 0>;
+        pwm-names = "enable", "direction";
+        direction-duty-cycle-ns = <1000000000>;
+    };
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@ -18,6 +18,7 @@ properties:
  compatible:
    enum:
      - qcom,sc7180-osm-l3
+      - qcom,sc7280-epss-l3
      - qcom,sc8180x-osm-l3
      - qcom,sdm845-osm-l3
      - qcom,sm8150-osm-l3
--- a/Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml
@ -0,0 +1,137 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,qcm2290.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QCM2290 Network-On-Chip interconnect
+
+maintainers:
+  - Shawn Guo <shawn.guo@linaro.org>
+
+description: |
+  The Qualcomm QCM2290 interconnect providers support adjusting the
+  bandwidth requirements between the various NoC fabrics.
+
+properties:
+  reg:
+    maxItems: 1
+
+  compatible:
+    enum:
+      - qcom,qcm2290-bimc
+      - qcom,qcm2290-cnoc
+      - qcom,qcm2290-snoc
+
+  '#interconnect-cells':
+    const: 1
+
+  clock-names:
+    items:
+      - const: bus
+      - const: bus_a
+
+  clocks:
+    items:
+      - description: Bus Clock
+      - description: Bus A Clock
+
+# Child node's properties
+patternProperties:
+  '^interconnect-[a-z0-9]+$':
+    type: object
+    description:
+      The interconnect providers do not have a separate QoS register space,
+      but share parent's space.
+
+    properties:
+      compatible:
+        enum:
+          - qcom,qcm2290-qup-virt
+          - qcom,qcm2290-mmrt-virt
+          - qcom,qcm2290-mmnrt-virt
+
+      '#interconnect-cells':
+        const: 1
+
+      clock-names:
+        items:
+          - const: bus
+          - const: bus_a
+
+      clocks:
+        items:
+          - description: Bus Clock
+          - description: Bus A Clock
+
+    required:
+      - compatible
+      - '#interconnect-cells'
+      - clock-names
+      - clocks
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - '#interconnect-cells'
+  - clock-names
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmcc.h>
+
+    snoc: interconnect@1880000 {
+        compatible = "qcom,qcm2290-snoc";
+        reg = <0x01880000 0x60200>;
+        #interconnect-cells = <1>;
+        clock-names = "bus", "bus_a";
+        clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+                 <&rpmcc RPM_SMD_SNOC_A_CLK>;
+
+        qup_virt: interconnect-qup {
+            compatible = "qcom,qcm2290-qup-virt";
+            #interconnect-cells = <1>;
+            clock-names = "bus", "bus_a";
+            clocks = <&rpmcc RPM_SMD_QUP_CLK>,
+                     <&rpmcc RPM_SMD_QUP_A_CLK>;
+        };
+
+        mmnrt_virt: interconnect-mmnrt {
+            compatible = "qcom,qcm2290-mmnrt-virt";
+            #interconnect-cells = <1>;
+            clock-names = "bus", "bus_a";
+            clocks = <&rpmcc RPM_SMD_MMNRT_CLK>,
+                     <&rpmcc RPM_SMD_MMNRT_A_CLK>;
+        };
+
+        mmrt_virt: interconnect-mmrt {
+            compatible = "qcom,qcm2290-mmrt-virt";
+            #interconnect-cells = <1>;
+            clock-names = "bus", "bus_a";
+            clocks = <&rpmcc RPM_SMD_MMRT_CLK>,
+                     <&rpmcc RPM_SMD_MMRT_A_CLK>;
+        };
+    };
+
+    cnoc: interconnect@1900000 {
+        compatible = "qcom,qcm2290-cnoc";
+        reg = <0x01900000 0x8200>;
+        #interconnect-cells = <1>;
+        clock-names = "bus", "bus_a";
+        clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
+                 <&rpmcc RPM_SMD_CNOC_A_CLK>;
+    };
+
+    bimc: interconnect@4480000 {
+        compatible = "qcom,qcm2290-bimc";
+        reg = <0x04480000 0x80000>;
+        #interconnect-cells = <1>;
+        clock-names = "bus", "bus_a";
+        clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
+                 <&rpmcc RPM_SMD_BIMC_A_CLK>;
+    };
--- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
@ -27,22 +27,37 @@ properties:
      - qcom,msm8939-pcnoc
      - qcom,msm8939-snoc
      - qcom,msm8939-snoc-mm
+      - qcom,msm8996-a0noc
+      - qcom,msm8996-a1noc
+      - qcom,msm8996-a2noc
+      - qcom,msm8996-bimc
+      - qcom,msm8996-cnoc
+      - qcom,msm8996-mnoc
+      - qcom,msm8996-pnoc
+      - qcom,msm8996-snoc
      - qcom,qcs404-bimc
      - qcom,qcs404-pcnoc
      - qcom,qcs404-snoc
+      - qcom,sdm660-a2noc
+      - qcom,sdm660-bimc
+      - qcom,sdm660-cnoc
+      - qcom,sdm660-gnoc
+      - qcom,sdm660-mnoc
+      - qcom,sdm660-snoc

  '#interconnect-cells':
    const: 1

-  clock-names:
-    items:
-      - const: bus
-      - const: bus_a
-
  clocks:
-    items:
-      - description: Bus Clock
-      - description: Bus A Clock
+    minItems: 2
+    maxItems: 7
+
+  clock-names:
+    minItems: 2
+    maxItems: 7
+
+  power-domains:
+    maxItems: 1

 required:
  - compatible
@ -53,6 +68,120 @@ required:

 additionalProperties: false

+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,msm8916-bimc
+              - qcom,msm8916-pcnoc
+              - qcom,msm8916-snoc
+              - qcom,msm8939-bimc
+              - qcom,msm8939-pcnoc
+              - qcom,msm8939-snoc
+              - qcom,msm8939-snoc-mm
+              - qcom,msm8996-a1noc
+              - qcom,msm8996-a2noc
+              - qcom,msm8996-bimc
+              - qcom,msm8996-cnoc
+              - qcom,msm8996-pnoc
+              - qcom,msm8996-snoc
+              - qcom,qcs404-bimc
+              - qcom,qcs404-pcnoc
+              - qcom,qcs404-snoc
+              - qcom,sdm660-bimc
+              - qcom,sdm660-cnoc
+              - qcom,sdm660-gnoc
+              - qcom,sdm660-snoc
+
+      then:
+        properties:
+          clock-names:
+            items:
+              - const: bus
+              - const: bus_a
+
+          clocks:
+            items:
+              - description: Bus Clock
+              - description: Bus A Clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,msm8996-mnoc
+              - qcom,sdm660-mnoc
+
+    then:
+      properties:
+        clock-names:
+          items:
+            - const: bus
+            - const: bus_a
+            - const: iface
+
+        clocks:
+          items:
+            - description: Bus Clock.
+            - description: Bus A Clock.
+            - description: CPU-NoC High-performance Bus Clock.
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,msm8996-a0noc
+
+    then:
+      properties:
+        clock-names:
+          items:
+            - const: aggre0_snoc_axi
+            - const: aggre0_cnoc_ahb
+            - const: aggre0_noc_mpu_cfg
+
+        clocks:
+          items:
+            - description: Aggregate0 System NoC AXI Clock.
+            - description: Aggregate0 Config NoC AHB Clock.
+            - description: Aggregate0 NoC MPU Clock.
+
+      required:
+        - power-domains
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sdm660-a2noc
+
+    then:
+      properties:
+        clock-names:
+          items:
+            - const: bus
+            - const: bus_a
+            - const: ipa
+            - const: ufs_axi
+            - const: aggre2_ufs_axi
+            - const: aggre2_usb3_axi
+            - const: cfg_noc_usb2_axi
+
+        clocks:
+          items:
+            - description: Bus Clock.
+            - description: Bus A Clock.
+            - description: IPA Clock.
+            - description: UFS AXI Clock.
+            - description: Aggregate2 UFS AXI Clock.
+            - description: Aggregate2 USB3 AXI Clock.
+            - description: Config NoC USB2 AXI Clock.
+
 examples:
  - |
      #include <dt-bindings/clock/qcom,rpmcc.h>
--- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
@ -104,6 +104,17 @@ properties:
      - qcom,sm8350-mmss-noc
      - qcom,sm8350-compute-noc
      - qcom,sm8350-system-noc
+      - qcom,sm8450-aggre1-noc
+      - qcom,sm8450-aggre2-noc
+      - qcom,sm8450-clk-virt
+      - qcom,sm8450-config-noc
+      - qcom,sm8450-gem-noc
+      - qcom,sm8450-lpass-ag-noc
+      - qcom,sm8450-mc-virt
+      - qcom,sm8450-mmss-noc
+      - qcom,sm8450-nsp-noc
+      - qcom,sm8450-pcie-anoc
+      - qcom,sm8450-system-noc

  '#interconnect-cells':
    enum: [ 1, 2 ]
--- a/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml
@ -1,185 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
---
-$id: http://devicetree.org/schemas/interconnect/qcom,sdm660.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm SDM660 Network-On-Chip interconnect
-
-maintainers:
-  - AngeloGioacchino Del Regno <kholk11@gmail.com>
-
-description: |
-  The Qualcomm SDM660 interconnect providers support adjusting the
-  bandwidth requirements between the various NoC fabrics.
-
-properties:
-  reg:
-    maxItems: 1
-
-  compatible:
-    enum:
-      - qcom,sdm660-a2noc
-      - qcom,sdm660-bimc
-      - qcom,sdm660-cnoc
-      - qcom,sdm660-gnoc
-      - qcom,sdm660-mnoc
-      - qcom,sdm660-snoc
-
-  '#interconnect-cells':
-    const: 1
-
-  clocks:
-    minItems: 1
-    maxItems: 7
-
-  clock-names:
-    minItems: 1
-    maxItems: 7
-
-required:
-  - compatible
-  - reg
-  - '#interconnect-cells'
-  - clock-names
-  - clocks
-
-additionalProperties: false
-
-allOf:
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - qcom,sdm660-mnoc
-    then:
-      properties:
-        clocks:
-          items:
-            - description: Bus Clock.
-            - description: Bus A Clock.
-            - description: CPU-NoC High-performance Bus Clock.
-        clock-names:
-          items:
-            - const: bus
-            - const: bus_a
-            - const: iface
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - qcom,sdm660-a2noc
-    then:
-      properties:
-        clocks:
-          items:
-            - description: Bus Clock.
-            - description: Bus A Clock.
-            - description: IPA Clock.
-            - description: UFS AXI Clock.
-            - description: Aggregate2 UFS AXI Clock.
-            - description: Aggregate2 USB3 AXI Clock.
-            - description: Config NoC USB2 AXI Clock.
-        clock-names:
-          items:
-            - const: bus
-            - const: bus_a
-            - const: ipa
-            - const: ufs_axi
-            - const: aggre2_ufs_axi
-            - const: aggre2_usb3_axi
-            - const: cfg_noc_usb2_axi
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - qcom,sdm660-bimc
-              - qcom,sdm660-cnoc
-              - qcom,sdm660-gnoc
-              - qcom,sdm660-snoc
-    then:
-      properties:
-        clocks:
-          items:
-            - description: Bus Clock.
-            - description: Bus A Clock.
-        clock-names:
-          items:
-            - const: bus
-            - const: bus_a
-
-examples:
-  - |
-      #include <dt-bindings/clock/qcom,rpmcc.h>
-      #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
-      #include <dt-bindings/clock/qcom,gcc-sdm660.h>
-
-      bimc: interconnect@1008000 {
-              compatible = "qcom,sdm660-bimc";
-              reg = <0x01008000 0x78000>;
-              #interconnect-cells = <1>;
-              clock-names = "bus", "bus_a";
-              clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
-                       <&rpmcc RPM_SMD_BIMC_A_CLK>;
-      };
-
-      cnoc: interconnect@1500000 {
-              compatible = "qcom,sdm660-cnoc";
-              reg = <0x01500000 0x10000>;
-              #interconnect-cells = <1>;
-              clock-names = "bus", "bus_a";
-              clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
-                       <&rpmcc RPM_SMD_CNOC_A_CLK>;
-      };
-
-      snoc: interconnect@1626000 {
-              compatible = "qcom,sdm660-snoc";
-              reg = <0x01626000 0x7090>;
-              #interconnect-cells = <1>;
-              clock-names = "bus", "bus_a";
-              clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
-                       <&rpmcc RPM_SMD_SNOC_A_CLK>;
-      };
-
-      a2noc: interconnect@1704000 {
-              compatible = "qcom,sdm660-a2noc";
-              reg = <0x01704000 0xc100>;
-              #interconnect-cells = <1>;
-              clock-names = "bus",
-                            "bus_a",
-                            "ipa",
-                            "ufs_axi",
-                            "aggre2_ufs_axi",
-                            "aggre2_usb3_axi",
-                            "cfg_noc_usb2_axi";
-              clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
-                       <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
-                       <&rpmcc RPM_SMD_IPA_CLK>,
-                       <&gcc GCC_UFS_AXI_CLK>,
-                       <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
-                       <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
-                       <&gcc GCC_CFG_NOC_USB2_AXI_CLK>;
-      };
-
-      mnoc: interconnect@1745000 {
-              compatible = "qcom,sdm660-mnoc";
-              reg = <0x01745000 0xa010>;
-              #interconnect-cells = <1>;
-              clock-names = "bus", "bus_a", "iface";
-              clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
-                       <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
-                       <&mmcc AHB_CLK_SRC>;
-      };
-
-      gnoc: interconnect@17900000 {
-              compatible = "qcom,sdm660-gnoc";
-              reg = <0x17900000 0xe000>;
-              #interconnect-cells = <1>;
-              clock-names = "bus", "bus_a";
-              clocks = <&xo_board>, <&xo_board>;
-      };
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
@ -239,6 +239,7 @@ examples:
      };
    };

+  - |
    interrupt-controller@2c010000 {
      compatible = "arm,gic-v3";
      #interrupt-cells = <4>;
@ -254,7 +255,7 @@ examples:
            <0x2c040000 0x2000>,  // GICC
            <0x2c060000 0x2000>,  // GICH
            <0x2c080000 0x2000>;  // GICV
-      interrupts = <1 9 4>;
+      interrupts = <1 9 4 0>;

      msi-controller@2c200000 {
        compatible = "arm,gic-v3-its";
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
@ -1,39 +0,0 @@
-Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
-
-This interrupt controller shows up in various forms on many BCM338x/BCM63xx
-chipsets.  It has the following properties:
-
- outputs a single interrupt signal to its interrupt controller parent
-
- contains one or more enable/status word pairs, which often appear at
-  different offsets in different blocks
-
- no atomic set/clear operations
-
-Required properties:
-
- compatible: should be "brcm,bcm3380-l2-intc"
- reg: specifies one or more enable/status pairs, in the following format:
-  <enable_reg 0x4 status_reg 0x4>...
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
-  source, should be 1.
- interrupts: specifies the interrupt line in the interrupt-parent controller
-  node, valid values depend on the type of parent interrupt controller
-
-Optional properties:
-
- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
-  wakeup source for system suspend/resume.
-
-Example:
-
-irq0_intc: interrupt-controller@10000020 {
-	compatible = "brcm,bcm3380-l2-intc";
-	reg = <0x10000024 0x4 0x1000002c 0x4>,
-	      <0x10000020 0x4 0x10000028 0x4>;
-	interrupt-controller;
-	#interrupt-cells = <1>;
-	interrupt-parent = <&cpu_intc>;
-	interrupts = <2>;
-};
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
@ -1,61 +0,0 @@
-Broadcom BCM7038-style Level 1 interrupt controller
-
-This block is a first level interrupt controller that is typically connected
-directly to one of the HW INT lines on each CPU.  Every BCM7xxx set-top chip
-since BCM7038 has contained this hardware.
-
-Key elements of the hardware design include:
-
- 64, 96, 128, or 160 incoming level IRQ lines
-
- Most onchip peripherals are wired directly to an L1 input
-
- A separate instance of the register set for each CPU, allowing individual
-  peripheral IRQs to be routed to any CPU
-
- Atomic mask/unmask operations
-
- No polarity/level/edge settings
-
- No FIFO or priority encoder logic; software is expected to read all
-  2-5 status words to determine which IRQs are pending
-
-Required properties:
-
- compatible: should be "brcm,bcm7038-l1-intc"
- reg: specifies the base physical address and size of the registers;
-  the number of supported IRQs is inferred from the size argument
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
-  source, should be 1.
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
-  node; valid values depend on the type of parent interrupt controller
-
-Optional properties:
-
- brcm,irq-can-wake: If present, this means the L1 controller can be used as a
-  wakeup source for system suspend/resume.
-
-Optional properties:
-
- brcm,int-fwd-mask: if present, a bit mask to indicate which interrupts
-  have already been configured by the firmware and should be left unmanaged.
-  This should have one 32-bit word per status/set/clear/mask group.
-
-If multiple reg ranges and interrupt-parent entries are present on an SMP
-system, the driver will allow IRQ SMP affinity to be set up through the
-/proc/irq/ interface.  In the simplest possible configuration, only one
-reg range and one interrupt-parent is needed.
-
-Example:
-
-periph_intc: periph_intc@1041a400 {
-        compatible = "brcm,bcm7038-l1-intc";
-        reg = <0x1041a400 0x30 0x1041a600 0x30>;
-
-        interrupt-controller;
-        #interrupt-cells = <1>;
-
-        interrupt-parent = <&cpu_intc>;
-        interrupts = <2>, <3>;
-};
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.yaml
@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM7038-style Level 1 interrupt controller
+
+description: >
+  This block is a first level interrupt controller that is typically connected
+  directly to one of the HW INT lines on each CPU.  Every BCM7xxx set-top chip
+  since BCM7038 has contained this hardware.
+
+  Key elements of the hardware design include:
+
+   - 64, 96, 128, or 160 incoming level IRQ lines
+
+   - Most onchip peripherals are wired directly to an L1 input
+
+   - A separate instance of the register set for each CPU, allowing individual
+     peripheral IRQs to be routed to any CPU
+
+   - Atomic mask/unmask operations
+
+   - No polarity/level/edge settings
+
+   - No FIFO or priority encoder logic; software is expected to read all
+     2-5 status words to determine which IRQs are pending
+
+   If multiple reg ranges and interrupt-parent entries are present on an SMP
+   system, the driver will allow IRQ SMP affinity to be set up through the
+   /proc/irq/ interface.  In the simplest possible configuration, only one
+   reg range and one interrupt-parent is needed.
+
+maintainers:
+  - Florian Fainelli <f.fainelli@gmail.com>
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+  compatible:
+    const: brcm,bcm7038-l1-intc
+
+  reg:
+    description: >
+      Specifies the base physical address and size of the registers
+      the number of supported IRQs is inferred from the size argument
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 1
+
+  interrupts:
+    description: >
+     Specifies the interrupt line(s) in the interrupt-parent controller node;
+     valid values depend on the type of parent interrupt controller
+
+  brcm,irq-can-wake:
+    type: boolean
+    description: >
+      If present, this means the L1 controller can be used as a
+      wakeup source for system suspend/resume.
+
+  brcm,int-fwd-mask:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description:
+      If present, a bit mask to indicate which interrupts have already been
+      configured by the firmware and should be left unmanaged. This should
+      have one 32-bit word per status/set/clear/mask group.
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+  - "#interrupt-cells"
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    periph_intc: interrupt-controller@1041a400 {
+      compatible = "brcm,bcm7038-l1-intc";
+      reg = <0x1041a400 0x30>, <0x1041a600 0x30>;
+      interrupt-controller;
+      #interrupt-cells = <1>;
+      interrupt-parent = <&cpu_intc>;
+      interrupts = <2>, <3>;
+    };
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
@ -1,88 +0,0 @@
-Broadcom BCM7120-style Level 2 interrupt controller
-
-This interrupt controller hardware is a second level interrupt controller that
-is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
-platforms. It can be found on BCM7xxx products starting with BCM7120.
-
-Such an interrupt controller has the following hardware design:
-
- outputs multiple interrupts signals towards its interrupt controller parent
-
- controls how some of the interrupts will be flowing, whether they will
-  directly output an interrupt signal towards the interrupt controller parent,
-  or if they will output an interrupt signal at this 2nd level interrupt
-  controller, in particular for UARTs
-
- has one 32-bit enable word and one 32-bit status word
-
- no atomic set/clear operations
-
- not all bits within the interrupt controller actually map to an interrupt
-
-The typical hardware layout for this controller is represented below:
-
-2nd level interrupt line		Outputs for the parent controller (e.g: ARM GIC)
-
-0 -----[ MUX ] ------------|==========> GIC interrupt 75
-          \-----------\
-                       |
-1 -----[ MUX ] --------)---|==========> GIC interrupt 76
-          \------------|
-                       |
-2 -----[ MUX ] --------)---|==========> GIC interrupt 77
-          \------------|
-                       |
-3 ---------------------|
-4 ---------------------|
-5 ---------------------|
-7 ---------------------|---|===========> GIC interrupt 66
-9 ---------------------|
-10 --------------------|
-11 --------------------/
-
-6 ------------------------\
-                           |===========> GIC interrupt 64
-8 ------------------------/
-
-12 ........................ X
-13 ........................ X 		(not connected)
-..
-31 ........................ X
-
-Required properties:
-
- compatible: should be "brcm,bcm7120-l2-intc"
- reg: specifies the base physical address and size of the registers
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
-  source, should be 1.
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
-  node, valid values depend on the type of parent interrupt controller
- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
-  are wired to this 2nd level interrupt controller, and how they match their
-  respective interrupt parents. Should match exactly the number of interrupts
-  specified in the 'interrupts' property.
-
-Optional properties:
-
- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
-  wakeup source for system suspend/resume.
-
- brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which
-  have a mux gate, typically UARTs. Setting these bits will make their
-  respective interrupt outputs bypass this 2nd level interrupt controller
-  completely; it is completely transparent for the interrupt controller
-  parent. This should have one 32-bit word per enable/status pair.
-
-Example:
-
-irq0_intc: interrupt-controller@f0406800 {
-	compatible = "brcm,bcm7120-l2-intc";
-	interrupt-parent = <&intc>;
-	#interrupt-cells = <1>;
-	reg = <0xf0406800 0x8>;
-	interrupt-controller;
-	interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
-	brcm,int-map-mask = <0xeb8>, <0x140>;
-	brcm,int-fwd-mask = <0x7>;
-};
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
@ -0,0 +1,151 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
+
+maintainers:
+  - Florian Fainelli <f.fainelli@gmail.com>
+
+description: >
+  This interrupt controller hardware is a second level interrupt controller that
+  is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
+  platforms. It can be found on BCM7xxx products starting with BCM7120.
+
+  Such an interrupt controller has the following hardware design:
+
+  - outputs multiple interrupts signals towards its interrupt controller parent
+
+  - controls how some of the interrupts will be flowing, whether they will
+    directly output an interrupt signal towards the interrupt controller parent,
+    or if they will output an interrupt signal at this 2nd level interrupt
+    controller, in particular for UARTs
+
+  - has one 32-bit enable word and one 32-bit status word
+
+  - no atomic set/clear operations
+
+  - not all bits within the interrupt controller actually map to an interrupt
+
+  The typical hardware layout for this controller is represented below:
+
+  2nd level interrupt line		Outputs for the parent controller (e.g: ARM GIC)
+
+  0 -----[ MUX ] ------------|==========> GIC interrupt 75
+            \-----------\
+                         |
+  1 -----[ MUX ] --------)---|==========> GIC interrupt 76
+            \------------|
+                         |
+  2 -----[ MUX ] --------)---|==========> GIC interrupt 77
+            \------------|
+                         |
+  3 ---------------------|
+  4 ---------------------|
+  5 ---------------------|
+  7 ---------------------|---|===========> GIC interrupt 66
+  9 ---------------------|
+  10 --------------------|
+  11 --------------------/
+
+  6 ------------------------\
+                            |===========> GIC interrupt 64
+  8 ------------------------/
+
+  12 ........................ X
+  13 ........................ X           (not connected)
+  ..
+  31 ........................ X
+
+  The BCM3380 Level 1 / Level 2 interrrupt controller shows up in various forms
+  on many BCM338x/BCM63xx chipsets. It has the following properties:
+
+  - outputs a single interrupt signal to its interrupt controller parent
+
+  - contains one or more enable/status word pairs, which often appear at
+    different offsets in different blocks
+
+  - no atomic set/clear operations
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - brcm,bcm7120-l2-intc
+          - brcm,bcm3380-l2-intc
+
+  reg:
+    minItems: 1
+    maxItems: 4
+    description: >
+      Specifies the base physical address and size of the registers
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 1
+
+  interrupts:
+    minItems: 1
+    maxItems: 32
+
+  brcm,int-map-mask:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: >
+      32-bits bit mask describing how many and which interrupts are wired to
+      this 2nd level interrupt controller, and how they match their respective
+      interrupt parents. Should match exactly the number of interrupts
+      specified in the 'interrupts' property.
+
+  brcm,irq-can-wake:
+    type: boolean
+    description: >
+      If present, this means the L2 controller can be used as a wakeup source
+      for system suspend/resume.
+
+  brcm,int-fwd-mask:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: >
+      if present, a bit mask to configure the interrupts which have a mux gate,
+      typically UARTs. Setting these bits will make their respective interrupt
+      outputs bypass this 2nd level interrupt controller completely; it is
+      completely transparent for the interrupt controller parent. This should
+      have one 32-bit word per enable/status pair.
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+  - "#interrupt-cells"
+  - interrupts
+
+examples:
+  - |
+    irq0_intc: interrupt-controller@f0406800 {
+      compatible = "brcm,bcm7120-l2-intc";
+      interrupt-parent = <&intc>;
+      #interrupt-cells = <1>;
+      reg = <0xf0406800 0x8>;
+      interrupt-controller;
+      interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
+      brcm,int-map-mask = <0xeb8>, <0x140>;
+      brcm,int-fwd-mask = <0x7>;
+    };
+
+  - |
+    irq1_intc: interrupt-controller@10000020 {
+       compatible = "brcm,bcm3380-l2-intc";
+       reg = <0x10000024 0x4>, <0x1000002c 0x4>,
+             <0x10000020 0x4>, <0x10000028 0x4>;
+       interrupt-controller;
+       #interrupt-cells = <1>;
+       interrupt-parent = <&cpu_intc>;
+       interrupts = <2>;
+    };
--- a/Show More
+++ b/Show More