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Renesas DTS updates for v7.2 (take two)

Browse Source 
- Add timer (MTU3) and xSPI FLASH support for the RZ/T2H and RZ/N2H
     SoCs and their EVK boards,
   - Add PCIe support for the RZ/V2N SoC and the RZ/V2N EVK board,
   - Add support for the R-Car M3Le SoC and the Geist development board,
   - Specify ethernet PHY reset timings on various R-Car boards,
   - Add (more) serial, I2C, DMA, and sound support for the RZ/G3L SoC,
   - Add PSCI, Multifunctional Interface (MFIS), and SCMI support for the
     R-Car X5H SoC and Ironhide development board,
   - Add serial DMA support for the RZ/G2L SoC,
   - Add keyboard, I2C, Versa clock, and audio support for the RZ/G3L
     SMARC SoM and EVK boards,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v7.2-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v7.2 (take two)

  - Add timer (MTU3) and xSPI FLASH support for the RZ/T2H and RZ/N2H
    SoCs and their EVK boards,
  - Add PCIe support for the RZ/V2N SoC and the RZ/V2N EVK board,
  - Add support for the R-Car M3Le SoC and the Geist development board,
  - Specify ethernet PHY reset timings on various R-Car boards,
  - Add (more) serial, I2C, DMA, and sound support for the RZ/G3L SoC,
  - Add PSCI, Multifunctional Interface (MFIS), and SCMI support for the
    R-Car X5H SoC and Ironhide development board,
  - Add serial DMA support for the RZ/G2L SoC,
  - Add keyboard, I2C, Versa clock, and audio support for the RZ/G3L
    SMARC SoM and EVK boards,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v7.2-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (56 commits)
  arm64: dts: renesas: r9a08g046l48-smarc: Enable audio
  arm64: dts: renesas: rzg3l-smarc-som: Enable Versa clock generator
  arm64: dts: renesas: r9a08g046l48-smarc: Enable I2C{2,3} devices
  arm64: dts: renesas: r9a08g046l48-smarc: Add gpio keys
  arm64: dts: renesas: rzt2h-n2h-evk: Enable xSPI nodes
  arm64: dts: renesas: r9a09g087: Add xSPI nodes
  arm64: dts: renesas: r9a09g077: Add xSPI nodes
  arm64: dts: renesas: rzg3e-smarc-som: Sort GMAC pinmux entries
  arm64: dts: renesas: r8a779md: Add support for R-Car M3Le R8A779MD Geist
  arm64: dts: renesas: r9a07g044: Add DMA properties to serial nodes
  arm64: dts: renesas: r9a07g054: Add max-frequency to SDHI nodes
  arm64: dts: renesas: r9a07g044: Add max-frequency to SDHI nodes
  arm64: dts: renesas: r9a07g043: Add max-frequency to SDHI nodes
  arm64: dts: renesas: r9a08g046: Add rsci{0..3} device nodes
  arm64: dts: renesas: ironhide: Enable to use SCMI
  arm64: dts: renesas: r8a78000: Add MFIS, MFIS-SCP, and transport nodes
  arm64: dts: renesas: ironhide: Describe all reserved memory
  arm64: dts: renesas: rzt2h-n2h-evk: Configure eMMC/SDHI pins
  arm64: dts: renesas: r8a78000: Fix GIC-720AE View 1 Redistributor description
  arm64: dts: renesas: r8a78000: Add PSCI node
  ...

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2026-06-09 12:55:38 +02:00
commit 91ee0f80cf
40 changed files with 2574 additions and 162 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml
View File

@ -11,14 +11,19 @@ maintainers:
description: |
The CS2000-CP is an extremely versatile system clocking device that
utilizes a programmable phase lock loop.
utilizes a programmable phase lock loop. CS2500 is a compatible
drop-in replacement for CS2000-CP.
Link: https://www.cirrus.com/products/cs2000/
Link: https://www.cirrus.com/products/cs2500/
properties:
compatible:
enum:
- cirrus,cs2000-cp
oneOf:
- items:
- const: cirrus,cs2500
- const: cirrus,cs2000-cp
- const: cirrus,cs2000-cp
clocks:
description:

187
Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml Normal file
View File

@ -0,0 +1,187 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/renesas/renesas,r8a78000-mfis.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas MFIS (Multifunctional Interface) controller
maintainers:
- Wolfram Sang <wsa+renesas@sang-engineering.com>
description:
The Renesas Multifunctional Interface (MFIS) provides various functionality
like mailboxes, hardware spinlocks, product identification, error injection,
error detection and such. Parts of it can be used for communication between
different CPU cores. Those cores can be in various domains like AP, RT, or
SCP. Often multiple domain-specific MFIS instances exist in one SoC.
properties:
compatible:
enum:
- renesas,r8a78000-mfis # R-Car X5H (AP<->AP, with PRR)
- renesas,r8a78000-mfis-scp # R-Car X5H (AP<->SCP, without PRR)
reg:
maxItems: 2
reg-names:
items:
- const: common
- const: mboxes
interrupts:
minItems: 32
maxItems: 128
description:
The interrupts raised by the remote doorbells.
interrupt-names:
minItems: 32
maxItems: 128
description:
An interrupt name is constructed with the prefix 'ch'. Then, the
channel number as specified in the documentation of the SoC. Finally,
the letter 'i' if the interrupt is raised by the IICR register. Or 'e'
if it is raised by the EICR register.
"#hwlock-cells":
const: 1
"#mbox-cells":
const: 2
description:
The first cell is the channel number as specified in the documentation
of the SoC. The second cell may specify flags as described in the file
<dt-bindings/soc/renesas,r8a78000-mfis.h>.
allOf:
- if:
properties:
compatible:
contains:
const: renesas,r8a78000-mfis
then:
properties:
interrupts:
minItems: 128
interrupt-names:
minItems: 128
items:
pattern: "^ch[0-9]+[ie]$"
- if:
properties:
compatible:
contains:
const: renesas,r8a78000-mfis-scp
then:
properties:
interrupts:
maxItems: 32
interrupt-names:
maxItems: 32
items:
pattern: "^ch[0-9]+i$"
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
- "#hwlock-cells"
- "#mbox-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
system-controller@189e0000 {
compatible = "renesas,r8a78000-mfis";
reg = <0x189e0000 0x1000>, <0x18800000 0x40000>;
reg-names = "common", "mboxes";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e", "ch3i", "ch3e",
"ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", "ch7i", "ch7e",
"ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e", "ch11i", "ch11e",
"ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch14e", "ch15i", "ch15e",
"ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch18e", "ch19i", "ch19e",
"ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch22e", "ch23i", "ch23e",
"ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch26e", "ch27i", "ch27e",
"ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch30e", "ch31i", "ch31e",
"ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch34e", "ch35i", "ch35e",
"ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch38e", "ch39i", "ch39e",
"ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch42e", "ch43i", "ch43e",
"ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch46e", "ch47i", "ch47e",
"ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch50e", "ch51i", "ch51e",
"ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch54e", "ch55i", "ch55e",
"ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch58e", "ch59i", "ch59e",
"ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch62e", "ch63i", "ch63e";
#hwlock-cells = <1>;
#mbox-cells = <2>;
};

6
Documentation/devicetree/bindings/soc/renesas/renesas.yaml
View File

@ -473,6 +473,12 @@ properties:
- const: renesas,r8a779mb
- const: renesas,r8a7795
- description: R-Car M3Le (R8A779MD)
items:
- const: renesas,geist # M3Le Geist (RTP8A779MDASKB0F10S)
- const: renesas,r8a779md
- const: renesas,r8a77965
- description: R-Car X5H (R8A78000)
items:
- enum:

1
arch/arm64/boot/dts/renesas/Makefile
View File

@ -60,6 +60,7 @@ r8a77965-salvator-xs-panel-aa104xd12-dtbs := r8a77965-salvator-xs.dtb salvator-p
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs-panel-aa104xd12.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a779md-geist.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle-function-expansion.dtbo

2
arch/arm64/boot/dts/renesas/condor-common.dtsi
View File

@ -168,6 +168,8 @@ phy0: ethernet-phy@0 {
reg = <0>;
interrupts-extended = <&gpio4 23 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};

33
arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso
View File

@ -6,36 +6,5 @@
* Copyright 2021 Ideas on Board Oy
*/
/dts-v1/;
/plugin/;
&{/} {
#define RENESAS_LVDS_OUTPUT lvds1
#include "panel-aa104xd12.dtsi"
};
&{/panel} {
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&lvds1_out>;
};
};
};
&lvds1 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
lvds1_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};

4
arch/arm64/boot/dts/renesas/draak.dtsi
View File

@ -249,6 +249,8 @@ phy0: ethernet-phy@0 {
reg = <0>;
interrupts-extended = <&gpio5 19 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
/*
* TX clock internal delay mode is required for reliable
* 1Gbps communication using the KSZ9031RNX phy present on
@ -435,7 +437,7 @@ adv7612_out: endpoint {
};
};
cs2000: clk-multiplier@4f {
cs2000: clock-controller@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;

4
arch/arm64/boot/dts/renesas/ebisu.dtsi
View File

@ -322,6 +322,8 @@ phy0: ethernet-phy@0 {
reg = <0>;
interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
/*
* TX clock internal delay mode is required for reliable
* 1Gbps communication using the KSZ9031RNX phy present on
@ -512,7 +514,7 @@ ak4613: codec@10 {
asahi-kasei,out6-single-end;
};
cs2000: clk-multiplier@4f {
cs2000: clock-controller@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;

2
arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi
View File

@ -213,6 +213,8 @@ avb0_phy: ethernet-phy@0 {
reg = <0>;
interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
};

2
arch/arm64/boot/dts/renesas/hihope-rev4.dtsi
View File

@ -50,7 +50,7 @@ &i2c2 {
pinctrl-names = "default";
status = "okay";
cs2000: clk-multiplier@4f {
cs2000: clock-controller@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;

62
arch/arm64/boot/dts/renesas/panel-aa104xd12.dtsi
View File

@ -5,26 +5,52 @@
* Copyright (C) 2014 Renesas Electronics Corp.
*/
panel {
compatible = "mitsubishi,aa104xd12", "panel-lvds";
/dts-v1/;
/plugin/;
width-mm = <210>;
height-mm = <158>;
data-mapping = "jeida-18";
&{/} {
panel {
compatible = "mitsubishi,aa104xd12", "panel-lvds";
backlight = <&backlight>;
panel-timing {
/* 1024x768 @65Hz */
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hsync-len = <136>;
hfront-porch = <20>;
hback-porch = <160>;
vfront-porch = <3>;
vback-porch = <29>;
vsync-len = <6>;
};
width-mm = <210>;
height-mm = <158>;
data-mapping = "jeida-18";
port {
panel-timing {
/* 1024x768 @65Hz */
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hsync-len = <136>;
hfront-porch = <20>;
hback-porch = <160>;
vfront-porch = <3>;
vback-porch = <29>;
vsync-len = <6>;
};
port {
lvds_panel_in: endpoint {
remote-endpoint = <&lvds_panel_out>;
};
};
};
};
&RENESAS_LVDS_OUTPUT {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
lvds_panel_out: endpoint {
remote-endpoint = <&lvds_panel_in>;
};
};
};
};

2
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
View File

@ -113,6 +113,8 @@ phy0: ethernet-phy@0 {
reg = <0>;
interrupts-extended = <&gpio1 17 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};

2
arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
View File

@ -119,6 +119,8 @@ phy0: ethernet-phy@0 {
reg = <0>;
interrupts-extended = <&gpio1 17 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};

2
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
View File

@ -126,6 +126,8 @@ phy0: ethernet-phy@0 {
reg = <0>;
interrupts-extended = <&gpio4 23 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};

2
arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
View File

@ -33,6 +33,8 @@ phy0: ethernet-phy@0 {
reg = <0>;
interrupts-extended = <&gpio4 16 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};

720
arch/arm64/boot/dts/renesas/r8a779md-geist.dts Normal file
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@ -0,0 +1,720 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the Geist board with R-Car M3Le
*
* Copyright (C) 2025-2026 Renesas Electronics Corp.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "r8a779md.dtsi"
/ {
model = "Renesas Geist board based on r8a779md";
compatible = "renesas,geist", "renesas,r8a779md", "renesas,r8a77965";
aliases {
serial0 = &scif2;
serial1 = &hscif1;
ethernet0 = &avb;
mmc0 = &sdhi2;
mmc1 = &sdhi0;
};
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2500/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 50000>;
brightness-levels = <256 128 64 16 8 4 0>;
default-brightness-level = <6>;
power-supply = <&reg_12v>;
enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
cvbs-in {
compatible = "composite-video-connector";
label = "CVBS IN";
port {
cvbs_con: endpoint {
remote-endpoint = <&adv7482_ain7>;
};
};
};
hdmi-in {
compatible = "hdmi-connector";
label = "HDMI IN";
type = "a";
port {
hdmi_in_con: endpoint {
remote-endpoint = <&adv7482_hdmi>;
};
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&keys_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "SW4-1";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "SW4-2";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW4-3";
wakeup-source;
debounce-interval = <20>;
};
key-4 {
gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
linux,code = <KEY_4>;
label = "SW4-4";
wakeup-source;
debounce-interval = <20>;
};
key-a {
gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_A>;
label = "TSW0";
wakeup-source;
debounce-interval = <20>;
};
key-b {
gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_B>;
label = "TSW1";
wakeup-source;
debounce-interval = <20>;
};
key-c {
gpios = <&gpio6 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_C>;
label = "TSW2";
wakeup-source;
debounce-interval = <20>;
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_12v: regulator-12v {
compatible = "regulator-fixed";
regulator-name = "fixed-12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
vbus0_usb2: regulator-vbus0-usb2 {
compatible = "regulator-fixed";
regulator-name = "USB20_VBUS0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
sound_card: sound {
compatible = "audio-graph-card";
label = "rcar-sound";
dais = <&rsnd_port0>; /* AK4619 Audio Codec */
};
x12_clk: x12-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
/* External DU dot clocks */
x21_clk: x21-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33000000>;
};
x22_clk: x22-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33000000>;
};
x23_clk: x23-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
x3013_clk: x3013-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
&audio_clk_a {
clock-frequency = <22579200>;
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622";
rxc-skew-ps = <1500>;
reg = <0>;
interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
&csi40 {
status = "okay";
ports {
port@0 {
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&adv7482_txa>;
};
};
};
};
&ehci0 {
dr_mode = "otg";
status = "okay";
};
&extalr_clk {
clock-frequency = <32768>;
};
&extal_clk {
clock-frequency = <16666666>;
};
&hscif1 {
pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
/* Please only enable hscif1 or scif1 */
status = "okay";
};
&hsusb {
dr_mode = "otg";
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
clock-frequency = <100000>;
status = "okay";
ak4619: codec@10 {
compatible = "asahi-kasei,ak4619";
reg = <0x10>;
clocks = <&rcar_sound 3>;
clock-names = "mclk";
#sound-dai-cells = <0>;
port {
ak4619_endpoint: endpoint {
remote-endpoint = <&rsnd_endpoint0>;
};
};
};
/* Pin-to-pin, register map, and control compatible with CS2000 and CS2200 */
cs2500: clock-controller@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2500", "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x12_clk>;
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2500>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
};
&i2c4 {
clock-frequency = <400000>;
status = "okay";
versaclock3: clock-controller@68 {
compatible = "renesas,5p35023";
reg = <0x68>;
#clock-cells = <1>;
clocks = <&x3013_clk>;
assigned-clocks = <&versaclock3 4>, <&versaclock3 5>;
assigned-clock-rates = <100000000>, <100000000>;
};
versaclock5: clock-controller@6a {
compatible = "idt,5p49v5923";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&x23_clk>;
clock-names = "xin";
};
video-receiver@70 {
compatible = "adi,adv7482";
reg = <0x70 0x71 0x72 0x73 0x74 0x75
0x60 0x61 0x62 0x63 0x64 0x65>;
reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
"infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
interrupts-extended = <&gpio6 30 IRQ_TYPE_LEVEL_LOW>,
<&gpio6 31 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "intrq1", "intrq2";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
adv7482_ain7: endpoint {
remote-endpoint = <&cvbs_con>;
};
};
port@8 {
reg = <8>;
adv7482_hdmi: endpoint {
remote-endpoint = <&hdmi_in_con>;
};
};
port@a {
reg = <10>;
adv7482_txa: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
};
csa_vdd: adc@7c {
compatible = "maxim,max9611";
reg = <0x7c>;
shunt-resistor-micro-ohms = <5000>;
};
csa_dvfs: adc@7f {
compatible = "maxim,max9611";
reg = <0x7f>;
shunt-resistor-micro-ohms = <5000>;
};
};
&i2c_dvfs {
status = "okay";
clock-frequency = <400000>;
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
};
};
&ohci0 {
dr_mode = "otg";
status = "okay";
};
&pcie_bus_clk {
status = "disabled";
};
&pciec0 {
clocks = <&cpg CPG_MOD 319>, <&versaclock3 4>;
status = "okay";
};
&pciec0_rp {
clocks = <&versaclock3 5>;
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb_pins: avb {
mux {
groups = "avb_link", "avb_mdio", "avb_mii";
function = "avb";
};
pins_mdio {
groups = "avb_mdio";
drive-strength = <24>;
};
pins_mii_tx {
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
drive-strength = <12>;
};
};
hscif1_pins: hscif1 {
groups = "hscif1_data_a", "hscif1_ctrl_a";
function = "hscif1";
};
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
irq0_pins: irq0 {
groups = "intc_ex_irq0";
function = "intc_ex";
};
keys_pins: keys {
pins = "GP_5_17", "GP_5_20", "GP_5_22";
bias-pull-up;
};
pwm1_pins: pwm1 {
groups = "pwm1_a";
function = "pwm1";
};
scif1_pins: scif1 {
groups = "scif1_data_a", "scif1_ctrl";
function = "scif1";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
function = "sdhi2";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
function = "ssi";
};
sound_clk_pins: sound_clk {
groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
"audio_clkout_a", "audio_clkout3_a";
function = "audio_clk";
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
};
&pwm1 {
pinctrl-0 = <&pwm1_pins>;
pinctrl-names = "default";
status = "okay";
};
&rcar_sound {
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
status = "okay";
/* update <audio_clk_b> to <cs2500> */
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2500>,
<&audio_clk_c>,
<&cpg CPG_MOD 922>;
ports {
#address-cells = <1>;
#size-cells = <0>;
rsnd_port0: port@0 {
reg = <0>;
rsnd_endpoint0: endpoint {
remote-endpoint = <&ak4619_endpoint>;
dai-format = "left_j";
bitclock-master = <&rsnd_endpoint0>;
frame-master = <&rsnd_endpoint0>;
playback = <&ssi0>, <&src0>, <&dvc0>;
capture = <&ssi1>, <&src1>, <&dvc1>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
/* Please only enable hscif1 or scif1 */
/* status = "okay"; */
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
no-sd;
no-sdio;
non-removable;
fixed-emmc-driver-type = <1>;
full-pwr-cycle-in-suspend;
status = "okay";
};
&ssi1 {
shared-pin;
};
&usb_extal_clk {
clock-frequency = <50000000>;
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
vbus-supply = <&vbus0_usb2>;
status = "okay";
};
&vin0 {
status = "okay";
};
&vin1 {
status = "okay";
};
&vin2 {
status = "okay";
};
&vin3 {
status = "okay";
};
&vin4 {
status = "okay";
};
&vin5 {
status = "okay";
};
&vin6 {
status = "okay";
};
&vin7 {
status = "okay";
};
&vspb {
status = "okay";
};
&vspi0 {
status = "okay";
};

59
arch/arm64/boot/dts/renesas/r8a779md.dtsi Normal file
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@ -0,0 +1,59 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car M3Le (R8A779MD) SoC
*
* Copyright (C) 2025-2026 Renesas Electronics Corp.
*/
#include "r8a77965.dtsi"
/ {
compatible = "renesas,r8a779md", "renesas,r8a77965";
};
/delete-node/ &csi20;
/delete-node/ &drif00;
/delete-node/ &drif01;
/delete-node/ &drif10;
/delete-node/ &drif11;
/delete-node/ &drif20;
/delete-node/ &drif21;
/delete-node/ &drif30;
/delete-node/ &drif31;
/delete-node/ &du;
/delete-node/ &ehci1;
/delete-node/ &hdmi0;
/delete-node/ &lvds0;
/delete-node/ &mlp;
/delete-node/ &ohci1;
/delete-node/ &pciec1;
/delete-node/ &sata;
/delete-node/ &usb2_phy1;
/delete-node/ &usb3_peri0;
/delete-node/ &usb3_phy0;
/delete-node/ &vin0csi20;
/delete-node/ &vin1csi20;
/delete-node/ &vin2csi20;
/delete-node/ &vin3csi20;
/delete-node/ &vin4csi20;
/delete-node/ &vin5csi20;
/delete-node/ &vin6csi20;
/delete-node/ &vin7csi20;
/delete-node/ &xhci0;
&sdhi0 {
compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi";
};
&sdhi1 {
compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi";
};
&sdhi2 {
compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi";
};
&sdhi3 {
compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi";
no-mmc;
};

65
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
View File

@ -6,6 +6,7 @@
*/
/dts-v1/;
#include <dt-bindings/soc/renesas,r8a78000-mfis.h>
#include "r8a78000.dtsi"
/ {
@ -20,10 +21,22 @@ chosen {
stdout-path = "serial0:1843200n8";
};
memory@60600000 {
firmware {
scmi: scmi {
compatible = "arm,scmi";
mboxes = <&mfis_scp 2 MFIS_CHANNEL_TX>,
<&mfis_scp 2 MFIS_CHANNEL_RX>;
mbox-names = "tx", "rx";
shmem = <&scmi_tx_shmem>, <&scmi_rx_shmem>;
arm,no-completion-irq;
#address-cells = <1>;
#size-cells = <0>;
};
};
memory@40000000 {
device_type = "memory";
/* first 518MiB is reserved for other purposes. */
reg = <0x0 0x60600000 0x0 0x5fa00000>;
reg = <0x0 0x40000000 0x0 0x80000000>;
};
memory@1080000000 {
@ -65,6 +78,36 @@ memory@1e00000000 {
device_type = "memory";
reg = <0x1e 0x00000000 0x1 0x00000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* First 518 MiB is reserved for other purposes. */
firmware@40000000 {
reg = <0x0 0x40000000 0x0 0x20600000>;
no-map;
};
/* Parameters set by IPL. */
parameters@8c100000 {
reg = <0x0 0x8c100000 0x0 0x00008000>;
no-map;
};
/* TFA BL31. */
tfa-bl31@8c200000 {
reg = <0x0 0x8c200000 0x0 0x00080000>;
no-map;
};
/* TEE TZ DRAM. */
tee@8c400000 {
reg = <0x0 0x8c400000 0x0 0x02000000>;
no-map;
};
};
};
&extal_clk {
@ -80,6 +123,22 @@ &hscif0 {
status = "okay";
};
&mfis_scp {
status = "okay";
};
&scif_clk {
clock-frequency = <26000000>;
};
&stcm_transport {
scmi_tx_shmem: sram@1200 {
compatible = "arm,scmi-shmem";
reg = <0x1200 0x0100>;
};
scmi_rx_shmem: sram@1300 {
compatible = "arm,scmi-shmem";
reg = <0x1300 0x100>;
};
};

170
arch/arm64/boot/dts/renesas/r8a78000.dtsi
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@ -665,6 +665,11 @@ extalr_clk: extalr-clk {
/* clock-frequency must be set on board */
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif-clk {
compatible = "fixed-clock";
@ -678,9 +683,123 @@ soc: soc {
#size-cells = <2>;
ranges;
prr: chipid@189e0044 {
compatible = "renesas,prr";
reg = <0 0x189e0044 0 4>;
mfis: system-controller@189e0000 {
compatible = "renesas,r8a78000-mfis";
reg = <0 0x189e0000 0 0x1000>, <0 0x18800000 0 0x40000>;
reg-names = "common", "mboxes";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e", "ch3i", "ch3e",
"ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", "ch7i", "ch7e",
"ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e", "ch11i", "ch11e",
"ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch14e", "ch15i", "ch15e",
"ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch18e", "ch19i", "ch19e",
"ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch22e", "ch23i", "ch23e",
"ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch26e", "ch27i", "ch27e",
"ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch30e", "ch31i", "ch31e",
"ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch34e", "ch35i", "ch35e",
"ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch38e", "ch39i", "ch39e",
"ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch42e", "ch43i", "ch43e",
"ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch46e", "ch47i", "ch47e",
"ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch50e", "ch51i", "ch51e",
"ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch54e", "ch55i", "ch55e",
"ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch58e", "ch59i", "ch59e",
"ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch62e", "ch63i", "ch63e";
#mbox-cells = <2>;
#hwlock-cells = <1>;
status = "disabled";
};
mfis_scp: system-controller@189e1000 {
compatible = "renesas,r8a78000-mfis-scp";
reg = <0 0x189e1000 0 0x1000>, <0 0x18840000 0 0x2c000>;
reg-names = "common", "mboxes";
interrupts = <GIC_ESPI 296 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 298 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 299 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 300 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 301 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 302 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 304 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 306 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 308 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 310 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 312 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 314 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 316 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 318 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 320 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 322 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 324 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 326 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 327 IRQ_TYPE_LEVEL_HIGH>;
/* SCP uses I side IRQ only */
interrupt-names = "ch0i", "ch1i", "ch2i", "ch3i", "ch4i", "ch5i", "ch6i", "ch7i",
"ch8i", "ch9i", "ch10i", "ch11i", "ch12i", "ch13i", "ch14i", "ch15i",
"ch16i", "ch17i", "ch18i", "ch19i", "ch20i", "ch21i", "ch22i", "ch23i",
"ch24i", "ch25i", "ch26i", "ch27i", "ch28i", "ch29i", "ch30i", "ch31i";
#mbox-cells = <2>;
#hwlock-cells = <1>;
status = "disabled";
};
/* Application Processors manage View-1 of a GIC-720AE */
@ -689,8 +808,40 @@ gic: interrupt-controller@39000000 {
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x39000000 0 0x10000>,
<0 0x39080000 0 0x800000>;
#redistributor-regions = <32>;
reg = <0x0 0x39000000 0x0 0x10000>,
<0x0 0x39080000 0x0 0x40000>,
<0x0 0x390c0000 0x0 0x40000>,
<0x0 0x39100000 0x0 0x40000>,
<0x0 0x39140000 0x0 0x40000>,
<0x0 0x39180000 0x0 0x40000>,
<0x0 0x391c0000 0x0 0x40000>,
<0x0 0x39200000 0x0 0x40000>,
<0x0 0x39240000 0x0 0x40000>,
<0x0 0x39280000 0x0 0x40000>,
<0x0 0x392c0000 0x0 0x40000>,
<0x0 0x39300000 0x0 0x40000>,
<0x0 0x39340000 0x0 0x40000>,
<0x0 0x39380000 0x0 0x40000>,
<0x0 0x393c0000 0x0 0x40000>,
<0x0 0x39400000 0x0 0x40000>,
<0x0 0x39440000 0x0 0x40000>,
<0x0 0x39480000 0x0 0x40000>,
<0x0 0x394c0000 0x0 0x40000>,
<0x0 0x39500000 0x0 0x40000>,
<0x0 0x39540000 0x0 0x40000>,
<0x0 0x39580000 0x0 0x40000>,
<0x0 0x395c0000 0x0 0x40000>,
<0x0 0x39600000 0x0 0x40000>,
<0x0 0x39640000 0x0 0x40000>,
<0x0 0x39680000 0x0 0x40000>,
<0x0 0x396c0000 0x0 0x40000>,
<0x0 0x39700000 0x0 0x40000>,
<0x0 0x39740000 0x0 0x40000>,
<0x0 0x39780000 0x0 0x40000>,
<0x0 0x397c0000 0x0 0x40000>,
<0x0 0x39800000 0x0 0x40000>,
<0x0 0x39840000 0x0 0x40000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
@ -773,6 +924,15 @@ hscif3: serial@c071c000 {
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
stcm_transport: sram@c1060000 {
compatible = "mmio-sram";
reg = <0x0 0xc1060000 0x0 0x1c00>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0xc1060000 0x1c00>;
/* actual transport nodes must be set per board file */
};
};
timer {

7
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
View File

@ -120,8 +120,7 @@ mtu3: timer@10001200 {
<SOC_PERIPHERAL_IRQ(209) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(210) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(211) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(212) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(213) IRQ_TYPE_EDGE_RISING>;
<SOC_PERIPHERAL_IRQ(212) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
"tciv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tciv1", "tciu1",
@ -136,7 +135,7 @@ mtu3: timer@10001200 {
"tgia7", "tgib7", "tgic7", "tgid7",
"tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
"tciv8", "tciu8";
"tciv8";
clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
@ -656,6 +655,7 @@ sdhi0: mmc@11c00000 {
<&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
<&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
max-frequency = <133333333>;
resets = <&cpg R9A07G043_SDHI0_IXRST>;
power-domains = <&cpg>;
status = "disabled";
@ -672,6 +672,7 @@ sdhi1: mmc@11c10000 {
<&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
<&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
max-frequency = <133333333>;
resets = <&cpg R9A07G043_SDHI1_IXRST>;
power-domains = <&cpg>;
status = "disabled";

17
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View File

@ -220,8 +220,7 @@ mtu3: timer@10001200 {
<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
<GIC_SPI 212 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
"tciv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tciv1", "tciu1",
@ -236,7 +235,7 @@ mtu3: timer@10001200 {
"tgia7", "tgib7", "tgic7", "tgid7",
"tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
"tciv8", "tciu8";
"tciv8";
clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
@ -505,6 +504,8 @@ scif0: serial@1004b800 {
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
clock-names = "fck";
dmas = <&dmac 0x4e79>, <&dmac 0x4e7a>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
status = "disabled";
@ -523,6 +524,8 @@ scif1: serial@1004bc00 {
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
clock-names = "fck";
dmas = <&dmac 0x4e7d>, <&dmac 0x4e7e>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
status = "disabled";
@ -541,6 +544,8 @@ scif2: serial@1004c000 {
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
clock-names = "fck";
dmas = <&dmac 0x4e81>, <&dmac 0x4e82>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
status = "disabled";
@ -559,6 +564,8 @@ scif3: serial@1004c400 {
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
clock-names = "fck";
dmas = <&dmac 0x4e85>, <&dmac 0x4e86>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
status = "disabled";
@ -577,6 +584,8 @@ scif4: serial@1004c800 {
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
clock-names = "fck";
dmas = <&dmac 0x4e89>, <&dmac 0x4e8a>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
status = "disabled";
@ -1175,6 +1184,7 @@ sdhi0: mmc@11c00000 {
<&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
<&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
max-frequency = <133333333>;
resets = <&cpg R9A07G044_SDHI0_IXRST>;
power-domains = <&cpg>;
status = "disabled";
@ -1191,6 +1201,7 @@ sdhi1: mmc@11c10000 {
<&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
<&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
max-frequency = <133333333>;
resets = <&cpg R9A07G044_SDHI1_IXRST>;
power-domains = <&cpg>;
status = "disabled";

7
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View File

@ -220,8 +220,7 @@ mtu3: timer@10001200 {
<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
<GIC_SPI 212 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
"tciv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tciv1", "tciu1",
@ -236,7 +235,7 @@ mtu3: timer@10001200 {
"tgia7", "tgib7", "tgic7", "tgid7",
"tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
"tciv8", "tciu8";
"tciv8";
clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
@ -1183,6 +1182,7 @@ sdhi0: mmc@11c00000 {
<&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
<&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
max-frequency = <133333333>;
resets = <&cpg R9A07G054_SDHI0_IXRST>;
power-domains = <&cpg>;
status = "disabled";
@ -1199,6 +1199,7 @@ sdhi1: mmc@11c10000 {
<&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
<&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
max-frequency = <133333333>;
resets = <&cpg R9A07G054_SDHI1_IXRST>;
power-domains = <&cpg>;
status = "disabled";

384
arch/arm64/boot/dts/renesas/r9a08g046.dtsi
View File

@ -14,6 +14,20 @@ / {
#size-cells = <2>;
interrupt-parent = <&gic>;
audio_clk1: audio1-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by boards that provide it. */
clock-frequency = <0>;
};
audio_clk2: audio2-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by boards that provide it. */
clock-frequency = <0>;
};
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
@ -166,11 +180,266 @@ scif0: serial@100ac000 {
status = "disabled";
};
scif1: serial@100ac400 {
compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
reg = <0 0x100ac400 0 0x400>;
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G046_SCIF1_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_SCIF1_RST_SYSTEM_N>;
status = "disabled";
};
scif2: serial@1004c000 {
compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
reg = <0 0x1004c000 0 0x400>;
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G046_SCIF2_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_SCIF2_RST_SYSTEM_N>;
status = "disabled";
};
scif3: serial@1004c400 {
compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
reg = <0 0x1004c400 0 0x400>;
interrupts = <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G046_SCIF3_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_SCIF3_RST_SYSTEM_N>;
status = "disabled";
};
scif4: serial@1004c800 {
compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
reg = <0 0x1004c800 0 0x400>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G046_SCIF4_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_SCIF4_RST_SYSTEM_N>;
status = "disabled";
};
scif5: serial@1004e000 {
compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
reg = <0 0x1004e000 0 0x400>;
interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G046_SCIF5_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_SCIF5_RST_SYSTEM_N>;
status = "disabled";
};
i2c0: i2c@100ae000 {
compatible = "renesas,riic-r9a08g046", "renesas,riic-r9a09g057";
reg = <0 0x100ae000 0 0x400>;
interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 329 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A08G046_I2C0_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A08G046_I2C0_MRST>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
/* placeholder */
status = "disabled";
};
i2c1: i2c@10090400 {
compatible = "renesas,riic-r9a08g046", "renesas,riic-r9a09g057";
reg = <0 0x10090400 0 0x400>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 337 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A08G046_I2C1_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A08G046_I2C1_MRST>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@10090800 {
compatible = "renesas,riic-r9a08g046", "renesas,riic-r9a09g057";
reg = <0 0x10090800 0 0x400>;
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 345 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A08G046_I2C2_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A08G046_I2C2_MRST>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@10090c00 {
compatible = "renesas,riic-r9a08g046", "renesas,riic-r9a09g057";
reg = <0 0x10090c00 0 0x400>;
interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 353 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A08G046_I2C3_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A08G046_I2C3_MRST>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rsci0: serial@100b8000 {
compatible = "renesas,r9a08g046-rsci";
reg = <0 0x100b8000 0 0x1000>;
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 417 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 418 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 420 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei",
"aed", "bfd";
clocks = <&cpg CPG_MOD R9A08G046_RSCI0_TCLK>,
<&cpg CPG_MOD R9A08G046_RSCI0_PCLK>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_RSCI0_PRESETN>,
<&cpg R9A08G046_RSCI0_TRESETN>;
reset-names = "presetn", "tresetn";
status = "disabled";
};
rsci1: serial@100f1000 {
compatible = "renesas,r9a08g046-rsci";
reg = <0 0x100f1000 0 0x1000>;
interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 424 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 426 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei",
"aed", "bfd";
clocks = <&cpg CPG_MOD R9A08G046_RSCI1_TCLK>,
<&cpg CPG_MOD R9A08G046_RSCI1_PCLK>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_RSCI1_PRESETN>,
<&cpg R9A08G046_RSCI1_TRESETN>;
reset-names = "presetn", "tresetn";
status = "disabled";
};
rsci2: serial@100f2000 {
compatible = "renesas,r9a08g046-rsci";
reg = <0 0x100f2000 0 0x1000>;
interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 429 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 430 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei",
"aed", "bfd";
clocks = <&cpg CPG_MOD R9A08G046_RSCI2_TCLK>,
<&cpg CPG_MOD R9A08G046_RSCI2_PCLK>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_RSCI2_PRESETN>,
<&cpg R9A08G046_RSCI2_TRESETN>;
reset-names = "presetn", "tresetn";
status = "disabled";
};
rsci3: serial@100f3000 {
compatible = "renesas,r9a08g046-rsci";
reg = <0 0x100f3000 0 0x1000>;
interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei",
"aed", "bfd";
clocks = <&cpg CPG_MOD R9A08G046_RSCI3_TCLK>,
<&cpg CPG_MOD R9A08G046_RSCI3_PCLK>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_RSCI3_PRESETN>,
<&cpg R9A08G046_RSCI3_TRESETN>;
reset-names = "presetn", "tresetn";
status = "disabled";
};
canfd: can@100c0000 {
@ -178,6 +447,82 @@ canfd: can@100c0000 {
/* placeholder */
};
ssi0: ssi@100e4000 {
compatible = "renesas,r9a08g046-ssi", "renesas,rz-ssi";
reg = <0 0x100e4000 0 0x400>;
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A08G046_SSI0_PCLK2>,
<&cpg CPG_MOD R9A08G046_SSI0_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A08G046_SSI0_RST_M2_REG>;
dmas = <&dmac 0x2665>, <&dmac 0x2666>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
};
ssi1: ssi@100e4400 {
compatible = "renesas,r9a08g046-ssi", "renesas,rz-ssi";
reg = <0 0x100e4400 0 0x400>;
interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 310 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A08G046_SSI1_PCLK2>,
<&cpg CPG_MOD R9A08G046_SSI1_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A08G046_SSI1_RST_M2_REG>;
dmas = <&dmac 0x2669>, <&dmac 0x266a>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
};
ssi2: ssi@100e4800 {
compatible = "renesas,r9a08g046-ssi", "renesas,rz-ssi";
reg = <0 0x100e4800 0 0x400>;
interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 313 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A08G046_SSI2_PCLK2>,
<&cpg CPG_MOD R9A08G046_SSI2_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A08G046_SSI2_RST_M2_REG>;
dmas = <&dmac 0x266d>, <&dmac 0x266e>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
};
ssi3: ssi@100e4c00 {
compatible = "renesas,r9a08g046-ssi", "renesas,rz-ssi";
reg = <0 0x100e4c00 0 0x400>;
interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 316 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A08G046_SSI3_PCLK2>,
<&cpg CPG_MOD R9A08G046_SSI3_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A08G046_SSI3_RST_M2_REG>;
dmas = <&dmac 0x2671>, <&dmac 0x2672>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
};
cpg: clock-controller@11010000 {
compatible = "renesas,r9a08g046-cpg";
reg = <0 0x11010000 0 0x10000>;
@ -311,6 +656,43 @@ icu: interrupt-controller@11050000 {
resets = <&cpg R9A08G046_IA55_RESETN>;
};
dmac: dma-controller@11820000 {
compatible = "renesas,r9a08g046-dmac", "renesas,rz-dmac";
reg = <0 0x11820000 0 0x10000>,
<0 0x11830000 0 0x10000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 154 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 155 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 156 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 161 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 164 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 165 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 168 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD R9A08G046_DMAC_ACLK>,
<&cpg CPG_MOD R9A08G046_DMAC_PCLK>;
clock-names = "main", "register";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_DMAC_ARESETN>,
<&cpg R9A08G046_DMAC_RST_ASYNC>;
reset-names = "arst", "rst_async";
#dma-cells = <1>;
dma-channels = <16>;
};
sdhi1: mmc@11c10000 {
reg = <0x0 0x11c10000 0 0x10000>;
/* placeholder */

127
arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
View File

@ -7,10 +7,20 @@
/dts-v1/;
/* Add place holder to avoid compilation error with renesas-smarc2.dtsi */
#define KEY_1_GPIO 1
#define KEY_2_GPIO 2
#define KEY_3_GPIO 3
/* Switch selection settings */
#define RZ_BOOT_MODE3 1
#define SW_SD2_EN 0
#define SW_DPI_EN 0
#define SW_GPIO4 1
#define SW_I3C_EN 0
#define PMOD_GPIO4 0
#define PMOD_GPIO6 0
#define PMOD_GPIO7 0
#define KEY_1_GPIO RZG3L_GPIO(J, 3)
#define KEY_2_GPIO RZG3L_GPIO(6, 4)
#define KEY_3_GPIO RZG3L_GPIO(6, 5)
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@ -25,26 +35,131 @@ / {
"renesas,r9a08g046l48", "renesas,r9a08g046";
aliases {
i2c2 = &i2c2;
i2c3 = &i2c3;
serial3 = &scif0;
};
#if !SW_SD2_EN && !SW_I3C_EN
snd_rzg3l: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "snd_rzg3l";
#address-cells = <1>;
#size-cells = <0>;
ssi_link_play: simple-audio-card,dai-link@0 {
reg = <0>;
format = "i2s";
bitclock-master = <&cpu_dai>;
frame-master = <&cpu_dai>;
mclk-fs = <256>;
cpu_dai: cpu {
sound-dai = <&ssi0>;
};
codec_dai: codec {
sound-dai = <&da7212>;
clocks = <&versa3 1>;
};
};
};
#endif
};
&keys {
status = "disabled";
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
};
#if !SW_I3C_EN
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
da7212: codec@1a {
compatible = "dlg,da7212";
reg = <0x1a>;
clocks = <&versa3 1>;
clock-names = "mclk";
#sound-dai-cells = <0>;
dlg,micbias1-lvl = <2500>;
dlg,micbias2-lvl = <2500>;
dlg,dmic-data-sel = "lrise_rfall";
dlg,dmic-samplephase = "between_clkedge";
dlg,dmic-clkrate = <3000000>;
VDDA-supply = <&reg_1p8v>;
VDDSP-supply = <&reg_3p3v>;
VDDMIC-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_1p8v>;
};
};
#endif
&keys {
#if !RZ_BOOT_MODE3 || !SW_GPIO4 || PMOD_GPIO4
/delete-node/ key-1;
#endif
#if SW_DPI_EN || PMOD_GPIO6
/delete-node/ key-2;
#endif
#if SW_DPI_EN || PMOD_GPIO7
/delete-node/ key-3;
#endif
};
&pinctrl {
audio_clk_pins: audio-clock {
pinmux = <RZG3L_PORT_PINMUX(H, 4, 6)>, /* AUDIO_CLK_B */
<RZG3L_PORT_PINMUX(H, 5, 6)>; /* AUDIO_CLK_C */
};
i2c2_pins: i2c2 {
pinmux = <RZG3L_PORT_PINMUX(A, 4, 4)>, /* RIIC2_SCL */
<RZG3L_PORT_PINMUX(A, 5, 4)>; /* RIIC2_SDA */
};
i2c3_pins: i2c3 {
pinmux = <RZG3L_PORT_PINMUX(2, 0, 4)>, /* RIIC3_SCL */
<RZG3L_PORT_PINMUX(2, 1, 4)>; /* RIIC3_SDA */
};
scif0_pins: scif0 {
pins = "SCIF0_TXD", "SCIF0_RXD";
power-source = <1800>;
};
ssi0_pins: ssi0 {
pinmux = <RZG3L_PORT_PINMUX(H, 0, 9)>, /* SSIF0_RXD */
<RZG3L_PORT_PINMUX(H, 1, 9)>, /* SSIF0_BCK */
<RZG3L_PORT_PINMUX(H, 2, 9)>, /* SSIF0_RCK */
<RZG3L_PORT_PINMUX(H, 3, 9)>; /* SSIF0_TXD */
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
};
#if !SW_SD2_EN
&ssi0 {
clocks = <&cpg CPG_MOD R9A08G046_SSI0_PCLK2>,
<&cpg CPG_MOD R9A08G046_SSI0_PCLK_SFR>,
<&versa3 2>, <&versa3 3>;
pinctrl-0 = <&audio_clk_pins>, <&ssi0_pins>;
pinctrl-names = "default";
status = "okay";
};
#endif

52
arch/arm64/boot/dts/renesas/r9a09g047.dtsi
View File

@ -1585,6 +1585,58 @@ csi2cru: endpoint@0 {
};
};
};
fcpvd0: fcp@16470000 {
compatible = "renesas,r9a09g047-fcpvd",
"renesas,fcpv";
reg = <0 0x16470000 0 0x10000>;
clocks = <&cpg CPG_MOD 0xed>,
<&cpg CPG_MOD 0xee>,
<&cpg CPG_MOD 0xef>;
clock-names = "aclk", "pclk", "vclk";
resets = <&cpg 0xdc>;
power-domains = <&cpg>;
};
fcpvd1: fcp@164a0000 {
compatible = "renesas,r9a09g047-fcpvd",
"renesas,fcpv";
reg = <0 0x164a0000 0 0x10000>;
clocks = <&cpg CPG_MOD 0x1a8>,
<&cpg CPG_MOD 0x1a9>,
<&cpg CPG_MOD 0x1aa>;
clock-names = "aclk", "pclk", "vclk";
resets = <&cpg 0x11e>;
power-domains = <&cpg>;
};
vspd0: vsp@16480000 {
compatible = "renesas,r9a09g047-vsp2",
"renesas,r9a07g044-vsp2";
reg = <0 0x16480000 0 0x10000>;
interrupts = <GIC_SPI 881 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xed>,
<&cpg CPG_MOD 0xee>,
<&cpg CPG_MOD 0xef>;
clock-names = "aclk", "pclk", "vclk";
resets = <&cpg 0xdc>;
power-domains = <&cpg>;
renesas,fcp = <&fcpvd0>;
};
vspd1: vsp@164b0000 {
compatible = "renesas,r9a09g047-vsp2",
"renesas,r9a07g044-vsp2";
reg = <0 0x164b0000 0 0x10000>;
interrupts = <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0x1a8>,
<&cpg CPG_MOD 0x1a9>,
<&cpg CPG_MOD 0x1aa>;
clock-names = "aclk", "pclk", "vclk";
resets = <&cpg 0x11e>;
power-domains = <&cpg>;
renesas,fcp = <&fcpvd1>;
};
};
stmmac_axi_setup: stmmac-axi-config {

69
arch/arm64/boot/dts/renesas/r9a09g056.dtsi
View File

@ -1044,6 +1044,75 @@ rsci9: serial@12803000 {
status = "disabled";
};
pcie: pcie@13400000 {
compatible = "renesas,r9a09g056-pcie", "renesas,r9a09g047-pcie";
reg = <0 0x13400000 0 0x10000>;
ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
<0x43000000 4 0x40000000 4 0x40000000 6 0x00000000>;
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 2 0x00000000>;
bus-range = <0x0 0xff>;
interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "serr", "serr_cor", "serr_nonfatal",
"serr_fatal", "axi_err", "inta",
"intb", "intc", "intd", "msi",
"link_bandwidth", "pm_pme", "dma",
"pcie_evt", "msg", "all",
"link_equalization_request",
"turn_off_event", "pmu_poweroff",
"d3_event_f0", "d3_event_f1",
"cfg_pmcsr_writeclear_f0",
"cfg_pmcsr_writeclear_f1";
#interrupt-cells = <1>;
interrupt-controller;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */
<0 0 0 2 &pcie 0 0 0 1>, /* INTB */
<0 0 0 3 &pcie 0 0 0 2>, /* INTC */
<0 0 0 4 &pcie 0 0 0 3>; /* INTD */
clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>;
clock-names = "aclk", "pmu";
resets = <&cpg 0xb2>;
reset-names = "aresetn";
power-domains = <&cpg>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
renesas,sysc = <&sys>;
status = "disabled";
pcie_port0: pcie@0,0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
ranges;
device_type = "pci";
vendor-id = <0x1912>;
device-id = <0x003b>;
#address-cells = <3>;
#size-cells = <2>;
};
};
i2c0: i2c@14400400 {
compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
reg = <0 0x14400400 0 0x400>;

24
arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
View File

@ -26,6 +26,7 @@ aliases {
i2c7 = &i2c7;
i2c8 = &i2c8;
mmc1 = &sdhi1;
rtc0 = &rtc;
serial0 = &scif;
};
@ -63,6 +64,12 @@ memory@48000000 {
reg = <0x0 0x48000000 0x1 0xf8000000>;
};
pcie_refclk: clock-pcie-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_0p8v: regulator-0p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-0.8V";
@ -333,6 +340,17 @@ &ostm7 {
status = "okay";
};
&pcie {
pinctrl-0 = <&pcie_pins>;
pinctrl-names = "default";
status = "okay";
};
&pcie_port0 {
clocks = <&pcie_refclk>;
clock-names = "ref";
};
&pinctrl {
eth0_pins: eth0 {
pins = "ET0_TXC_TXCLK";
@ -383,6 +401,12 @@ i2c8_pins: i2c8 {
<RZV2N_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
};
pcie_pins: pcie {
pins = "PCIE0_RSTOUTB";
slew-rate = <0>;
renesas,output-impedance = <2>;
};
scif_pins: scif {
pins = "SCIF_TXD", "SCIF_RXD";
renesas,output-impedance = <1>;

1
arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
View File

@ -27,6 +27,7 @@ aliases {
i2c7 = &i2c7;
i2c8 = &i2c8;
mmc1 = &sdhi1;
rtc0 = &rtc;
serial0 = &scif;
};

108
arch/arm64/boot/dts/renesas/r9a09g077.dtsi
View File

@ -1006,6 +1006,46 @@ mii_conv3: mii-conv@3 {
};
};
xspi0: spi@801c0000 {
compatible = "renesas,r9a09g077-xspi",
"renesas,r9a09g047-xspi";
reg = <0 0x801c0000 0 0x1000>,
<0 0x40000000 0 0x10000000>;
reg-names = "regs", "dirmap";
interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pulse", "err_pulse";
clocks = <&cpg CPG_MOD 4>,
<&cpg CPG_CORE R9A09G077_XSPI_CLK0>;
clock-names = "ahb", "spi";
resets = <&cpg 4>;
reset-names = "hresetn";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
xspi1: spi@801c1000 {
compatible = "renesas,r9a09g077-xspi",
"renesas,r9a09g047-xspi";
reg = <0 0x801c1000 0 0x1000>,
<0 0x50000000 0 0x10000000>;
reg-names = "regs", "dirmap";
interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pulse", "err_pulse";
clocks = <&cpg CPG_MOD 5>,
<&cpg CPG_CORE R9A09G077_XSPI_CLK1>;
clock-names = "ahb", "spi";
resets = <&cpg 5>;
reset-names = "hresetn";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
cpg: clock-controller@80280000 {
compatible = "renesas,r9a09g077-cpg-mssr";
reg = <0 0x80280000 0 0x10000>,
@ -1116,6 +1156,74 @@ gic: interrupt-controller@83000000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
mtu3: timer@90001200 {
compatible = "renesas,r9a09g077-mtu3",
"renesas,rz-mtu3";
reg = <0 0x90001200 0 0xb00>;
interrupts = <GIC_SPI 420 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 421 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 422 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 423 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 424 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 425 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 426 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 427 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 428 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 429 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 430 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 440 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 441 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 442 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 443 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 444 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 445 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 446 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 447 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 449 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 450 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 451 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 452 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 453 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 454 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 455 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 456 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 458 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 459 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 460 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 461 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
"tciv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tciv1", "tciu1",
"tgia2", "tgib2", "tciv2", "tciu2",
"tgia3", "tgib3", "tgic3", "tgid3",
"tciv3",
"tgia4", "tgib4", "tgic4", "tgid4",
"tciv4",
"tgiu5", "tgiv5", "tgiw5",
"tgia6", "tgib6", "tgic6", "tgid6",
"tciv6",
"tgia7", "tgib7", "tgic7", "tgid7",
"tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
"tciv8";
clocks = <&cpg CPG_MOD 200>;
power-domains = <&cpg>;
#pwm-cells = <3>;
status = "disabled";
};
adc0: adc@90014000 {
compatible = "renesas,r9a09g077-adc";
reg = <0 0x90014000 0 0x400>;

15
arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
View File

@ -345,3 +345,18 @@ usb_pins: usb-pins {
};
};
/*
* XSPI0 Pin Configuration:
* ------------------------
* Signal | Pin | SW5
* -----------|---------|---------------
* XSPI0_ECS | P07_5 | 5: OFF, 6: ON
*/
&xspi0_pins {
ecs-pins {
pinmux = <RZT2H_PORT_PINMUX(7, 5, 0x1c)>; /* XSPI0_ECS0 */
drive-strength-microamp = <2500>;
input-schmitt-disable;
slew-rate = <0>;
};
};

108
arch/arm64/boot/dts/renesas/r9a09g087.dtsi
View File

@ -1009,6 +1009,46 @@ mii_conv3: mii-conv@3 {
};
};
xspi0: spi@801c0000 {
compatible = "renesas,r9a09g087-xspi",
"renesas,r9a09g047-xspi";
reg = <0 0x801c0000 0 0x1000>,
<0 0x40000000 0 0x10000000>;
reg-names = "regs", "dirmap";
interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pulse", "err_pulse";
clocks = <&cpg CPG_MOD 4>,
<&cpg CPG_CORE R9A09G087_XSPI_CLK0>;
clock-names = "ahb", "spi";
resets = <&cpg 4>;
reset-names = "hresetn";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
xspi1: spi@801c1000 {
compatible = "renesas,r9a09g087-xspi",
"renesas,r9a09g047-xspi";
reg = <0 0x801c1000 0 0x1000>,
<0 0x50000000 0 0x10000000>;
reg-names = "regs", "dirmap";
interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pulse", "err_pulse";
clocks = <&cpg CPG_MOD 5>,
<&cpg CPG_CORE R9A09G087_XSPI_CLK1>;
clock-names = "ahb", "spi";
resets = <&cpg 5>;
reset-names = "hresetn";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
cpg: clock-controller@80280000 {
compatible = "renesas,r9a09g087-cpg-mssr";
reg = <0 0x80280000 0 0x10000>,
@ -1119,6 +1159,74 @@ gic: interrupt-controller@83000000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
mtu3: timer@90001200 {
compatible = "renesas,r9a09g087-mtu3",
"renesas,rz-mtu3";
reg = <0 0x90001200 0 0xb00>;
interrupts = <GIC_SPI 420 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 421 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 422 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 423 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 424 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 425 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 426 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 427 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 428 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 429 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 430 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 440 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 441 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 442 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 443 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 444 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 445 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 446 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 447 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 449 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 450 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 451 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 452 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 453 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 454 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 455 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 456 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 458 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 459 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 460 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 461 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
"tciv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tciv1", "tciu1",
"tgia2", "tgib2", "tciv2", "tciu2",
"tgia3", "tgib3", "tgic3", "tgid3",
"tciv3",
"tgia4", "tgib4", "tgic4", "tgid4",
"tciv4",
"tgiu5", "tgiv5", "tgiw5",
"tgia6", "tgib6", "tgic6", "tgid6",
"tciv6",
"tgia7", "tgib7", "tgic7", "tgid7",
"tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
"tciv8";
clocks = <&cpg CPG_MOD 200>;
power-domains = <&cpg>;
#pwm-cells = <3>;
status = "disabled";
};
adc0: adc@90014000 {
compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc";
reg = <0 0x90014000 0 0x400>;

15
arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi
View File

@ -24,19 +24,10 @@ &du {
pinctrl-names = "default";
status = "okay";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
du_out_rgb: endpoint {
remote-endpoint = <&adv7513_in>;
};
};
};
&du_out_rgb {
remote-endpoint = <&adv7513_in>;
};
&ADV7513_PARENT_I2C {

49
arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
View File

@ -193,20 +193,20 @@ clk {
};
ctrl {
pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
<RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
<RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
<RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
<RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
<RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
<RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
<RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
pinmux = <RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
<RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
<RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
<RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
<RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
<RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
<RZG3E_PORT_PINMUX(A, 3, 1)>, /* TX_CTL */
<RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
<RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
<RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
<RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
<RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
<RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
<RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
<RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
<RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
<RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
<RZG3E_PORT_PINMUX(C, 2, 15)>; /* PHY_INTR (IRQ2) */
};
};
@ -217,21 +217,20 @@ clk {
};
ctrl {
pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
<RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
<RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
<RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
<RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
<RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
<RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
<RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
pinmux = <RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
<RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
<RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
<RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
<RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
<RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
<RZG3E_PORT_PINMUX(D, 3, 1)>, /* TX_CTL */
<RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
<RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
<RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
<RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
<RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
<RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
<RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
<RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
<RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
<RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
<RZG3E_PORT_PINMUX(F, 2, 15)>; /* PHY_INTR (IRQ15) */
};
};

72
arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
View File

@ -5,12 +5,38 @@
* Copyright (C) 2026 Renesas Electronics Corp.
*/
/*
* Please set the below switch position on the SoM and the corresponding macro
* on the board DTS:
*
* Switch position SYS.2, Macro SW_I3C_EN:
* 0 - SMARC_I2C_GP is enabled
* 1 - I3C is enabled
*
* Switch position SYS.4, Macro SW_SD2_EN:
* 0 - Select I2S0
* 1 - Select SD2
*
* Switch position SYS.5, Macro SW_DPI_EN:
* 0 - Select multiple SMARC signals active
* 1 - Select LCD
*
* Switch position BOOT.1, Macro RZ_BOOT_MODE3:
* 0 - Select JTAG enabled
* 1 - Select SDIO {CD,IOVS,PWEN} and GPIO4 Active
*
* Switch position SW_GPIO4, Macro SW_GPIO4:
* 0 - Select RZ_VBAT_TAMPER (position 2-1)
* 1 - Select GPIO4 (position 2-3)
*/
/ {
compatible = "renesas,rzg3l-smarcm", "renesas,r9a08g046l48", "renesas,r9a08g046";
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
i2c0 = &i2c0;
};
memory@48000000 {
@ -18,6 +44,30 @@ memory@48000000 {
/* First 128MiB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
x2_clk: x2-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
&eth0 {
@ -50,6 +100,23 @@ &extal_clk {
clock-frequency = <24000000>;
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
versa3: clock-generator@68 {
compatible = "renesas,5p35023";
reg = <0x68>;
#clock-cells = <1>;
clocks = <&x2_clk>;
assigned-clocks = <&versa3 1>, <&versa3 2>,
<&versa3 3>, <&versa3 4>;
assigned-clock-rates = <12288000>, <11289600>,
<12288000>, <25000000>;
};
};
&mdio0 {
phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640";
@ -144,6 +211,11 @@ ctrl {
power-source = <1800>;
};
};
i2c0_pins: i2c0 {
pinmux = <RZG3L_PORT_PINMUX(L, 2, 4)>, /* RIIC0_SCL */
<RZG3L_PORT_PINMUX(L, 3, 4)>; /* RIIC0_SDA */
};
};
&wdt0 {

274
arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
View File

@ -5,6 +5,7 @@
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/mscc-phy-vsc8531.h>
@ -20,6 +21,8 @@ aliases {
mmc0 = &sdhi0;
mmc1 = &sdhi1;
serial0 = &sci0;
spi0 = &xspi0;
spi1 = &xspi1;
};
chosen {
@ -275,12 +278,63 @@ data-pins {
<RZT2H_PORT_PINMUX(12, 7, 0x29)>, /* SD0_DATA5 */
<RZT2H_PORT_PINMUX(13, 0, 0x29)>, /* SD0_DATA6 */
<RZT2H_PORT_PINMUX(13, 1, 0x29)>; /* SD0_DATA7 */
drive-strength-microamp = <5000>;
slew-rate = <1>;
input-schmitt-disable;
};
ctrl-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
<RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
<RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */
clk-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>; /* SD0_CLK */
drive-strength-microamp = <9000>;
slew-rate = <1>;
};
cmd-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
drive-strength-microamp = <5000>;
slew-rate = <1>;
input-schmitt-disable;
};
rst-pins {
pinmux = <RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */
drive-strength-microamp = <5000>;
slew-rate = <1>;
};
};
sdhi0_emmc_uhs_pins: sd0-emmc-uhs-group {
data-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 2, 0x29)>, /* SD0_DATA0 */
<RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */
<RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */
<RZT2H_PORT_PINMUX(12, 5, 0x29)>, /* SD0_DATA3 */
<RZT2H_PORT_PINMUX(12, 6, 0x29)>, /* SD0_DATA4 */
<RZT2H_PORT_PINMUX(12, 7, 0x29)>, /* SD0_DATA5 */
<RZT2H_PORT_PINMUX(13, 0, 0x29)>, /* SD0_DATA6 */
<RZT2H_PORT_PINMUX(13, 1, 0x29)>; /* SD0_DATA7 */
drive-strength-microamp = <9000>;
slew-rate = <1>;
input-schmitt-disable;
};
clk-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>; /* SD0_CLK */
drive-strength-microamp = <11800>;
slew-rate = <1>;
};
cmd-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
drive-strength-microamp = <9000>;
slew-rate = <1>;
input-schmitt-disable;
};
rst-pins {
pinmux = <RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */
drive-strength-microamp = <9000>;
slew-rate = <1>;
};
};
@ -299,12 +353,49 @@ data-pins {
<RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */
<RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */
<RZT2H_PORT_PINMUX(12, 5, 0x29)>; /* SD0_DATA3 */
drive-strength-microamp = <5000>;
slew-rate = <1>;
input-schmitt-disable;
};
clk-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>; /* SD0_CLK */
drive-strength-microamp = <9000>;
slew-rate = <1>;
};
ctrl-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
<RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
pinmux = <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
<RZT2H_PORT_PINMUX(22, 5, 0x29)>; /* SD0_CD */
drive-strength-microamp = <5000>;
slew-rate = <1>;
input-schmitt-disable;
};
};
sdhi0_sd_uhs_pins: sd0-sd-uhs-group {
data-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 2, 0x29)>, /* SD0_DATA0 */
<RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */
<RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */
<RZT2H_PORT_PINMUX(12, 5, 0x29)>; /* SD0_DATA3 */
drive-strength-microamp = <9000>;
slew-rate = <1>;
input-schmitt-disable;
};
clk-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>; /* SD0_CLK */
drive-strength-microamp = <11800>;
slew-rate = <1>;
};
ctrl-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
<RZT2H_PORT_PINMUX(22, 5, 0x29)>; /* SD0_CD */
drive-strength-microamp = <9000>;
slew-rate = <1>;
input-schmitt-disable;
};
};
@ -323,14 +414,90 @@ data-pins {
<RZT2H_PORT_PINMUX(17, 0, 0x29)>, /* SD1_DATA1 */
<RZT2H_PORT_PINMUX(17, 1, 0x29)>, /* SD1_DATA2 */
<RZT2H_PORT_PINMUX(17, 2, 0x29)>; /* SD1_DATA3 */
drive-strength-microamp = <5000>;
slew-rate = <1>;
input-schmitt-disable;
};
clk-pins {
pinmux = <RZT2H_PORT_PINMUX(16, 5, 0x29)>; /* SD1_CLK */
drive-strength-microamp = <9000>;
slew-rate = <1>;
};
ctrl-pins {
pinmux = <RZT2H_PORT_PINMUX(16, 5, 0x29)>, /* SD1_CLK */
<RZT2H_PORT_PINMUX(16, 6, 0x29)>, /* SD1_CMD */
pinmux = <RZT2H_PORT_PINMUX(16, 6, 0x29)>, /* SD1_CMD */
<RZT2H_PORT_PINMUX(17, 4, 0x29)>; /* SD1_CD */
drive-strength-microamp = <5000>;
slew-rate = <1>;
input-schmitt-disable;
};
};
sdhi1_uhs_pins: sd1-uhs-group {
data-pins {
pinmux = <RZT2H_PORT_PINMUX(16, 7, 0x29)>, /* SD1_DATA0 */
<RZT2H_PORT_PINMUX(17, 0, 0x29)>, /* SD1_DATA1 */
<RZT2H_PORT_PINMUX(17, 1, 0x29)>, /* SD1_DATA2 */
<RZT2H_PORT_PINMUX(17, 2, 0x29)>; /* SD1_DATA3 */
drive-strength-microamp = <9000>;
slew-rate = <1>;
input-schmitt-disable;
};
clk-pins {
pinmux = <RZT2H_PORT_PINMUX(16, 5, 0x29)>; /* SD1_CLK */
drive-strength-microamp = <11800>;
slew-rate = <1>;
};
ctrl-pins {
pinmux = <RZT2H_PORT_PINMUX(16, 6, 0x29)>, /* SD1_CMD */
<RZT2H_PORT_PINMUX(17, 4, 0x29)>; /* SD1_CD */
drive-strength-microamp = <9000>;
slew-rate = <1>;
input-schmitt-disable;
};
};
xspi0_pins: xspi0-group {
ctrl-data-pins {
pinmux = <RZT2H_PORT_PINMUX(5, 1, 0x1c)>, /* XSPI0_CKP */
<RZT2H_PORT_PINMUX(5, 3, 0x1c)>, /* XSPI0_CS0 */
<RZT2H_PORT_PINMUX(5, 5, 0x1c)>, /* XSPI0_DS */
<RZT2H_PORT_PINMUX(5, 6, 0x1c)>, /* XSPI0_IO0 */
<RZT2H_PORT_PINMUX(5, 7, 0x1c)>, /* XSPI0_IO1 */
<RZT2H_PORT_PINMUX(6, 0, 0x1c)>, /* XSPI0_IO2 */
<RZT2H_PORT_PINMUX(6, 1, 0x1c)>, /* XSPI0_IO3 */
<RZT2H_PORT_PINMUX(6, 2, 0x1c)>, /* XSPI0_IO4 */
<RZT2H_PORT_PINMUX(6, 3, 0x1c)>, /* XSPI0_IO5 */
<RZT2H_PORT_PINMUX(6, 4, 0x1c)>, /* XSPI0_IO6 */
<RZT2H_PORT_PINMUX(6, 5, 0x1c)>, /* XSPI0_IO7 */
<RZT2H_PORT_PINMUX(6, 6, 0x1c)>; /* XSPI0_RESET0 */
drive-strength-microamp = <9000>;
input-schmitt-disable;
slew-rate = <1>;
};
};
/*
* XSPI1 Pin Configuration:
* ------------------------
* Signal | Pin | RZ/T2H (SW1) | RZ/N2H (DSW2)
* -----------|----------|---------------|---------------
* ALL | Multiple | 6: ON | 6: ON
*/
xspi1_pins: xspi1-pins {
pinmux = <RZT2H_PORT_PINMUX(1, 0, 0x1c)>, /* XSPI1_CKP */
<RZT2H_PORT_PINMUX(1, 1, 0x1c)>, /* XSPI1_CS0 */
<RZT2H_PORT_PINMUX(1, 4, 0x1c)>, /* XSPI1_IO0 */
<RZT2H_PORT_PINMUX(1, 5, 0x1c)>, /* XSPI1_IO1 */
<RZT2H_PORT_PINMUX(1, 6, 0x1c)>, /* XSPI1_IO2 */
<RZT2H_PORT_PINMUX(1, 7, 0x1c)>; /* XSPI1_IO3 */
drive-strength-microamp = <9000>;
input-schmitt-enable;
slew-rate = <1>;
};
};
&sci0 {
@ -342,7 +509,7 @@ &sci0 {
#if SD0_EMMC
&sdhi0 {
pinctrl-0 = <&sdhi0_emmc_pins>;
pinctrl-1 = <&sdhi0_emmc_pins>;
pinctrl-1 = <&sdhi0_emmc_uhs_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
@ -357,7 +524,7 @@ &sdhi0 {
#if SD0_SD
&sdhi0 {
pinctrl-0 = <&sdhi0_sd_pins>;
pinctrl-1 = <&sdhi0_sd_pins>;
pinctrl-1 = <&sdhi0_sd_uhs_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vqmmc_sdhi0>;
@ -372,7 +539,7 @@ &sdhi0 {
#if SD1_MICRO_SD
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_uhs_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vccq_sdhi1>;
@ -395,3 +562,88 @@ &wdt2 {
timeout-sec = <60>;
};
&xspi0 {
pinctrl-0 = <&xspi0_pins>;
pinctrl-names = "default";
status = "okay";
assigned-clocks = <&cpg CPG_CORE R9A09G077_XSPI_CLK0>;
assigned-clock-rates = <50000000>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
vcc-supply = <&reg_3p3v>;
m25p,fast-read;
/*
* Configure for 1-bit mode to prevent the BootROM from failing
* to load the first-stage bootloader following a watchdog reset.
*/
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bl2-0";
reg = <0x00000000 0x00060000>;
read-only;
};
partition@60000 {
label = "fip-0";
reg = <0x00060000 0x007a0000>;
read-only;
};
partition@800000 {
label = "user-0";
reg = <0x800000 0x003800000>;
};
};
};
};
&xspi1 {
pinctrl-0 = <&xspi1_pins>;
pinctrl-names = "default";
status = "okay";
assigned-clocks = <&cpg CPG_CORE R9A09G077_XSPI_CLK1>;
assigned-clock-rates = <50000000>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
vcc-supply = <&reg_3p3v>;
m25p,fast-read;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bl2-1";
reg = <0x00000000 0x00060000>;
};
partition@60000 {
label = "fip-1";
reg = <0x00060000 0x007a0000>;
};
partition@800000 {
label = "user-1";
reg = <0x800000 0x800000>;
};
};
};
};

4
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View File

@ -361,6 +361,8 @@ phy0: ethernet-phy@0 {
reg = <0>;
interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
@ -507,7 +509,7 @@ ak4613_endpoint: endpoint {
};
};
cs2000: clk-multiplier@4f {
cs2000: clock-controller@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;

33
arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso
View File

@ -6,36 +6,5 @@
* Copyright 2021 Ideas on Board Oy
*/
/dts-v1/;
/plugin/;
&{/} {
#define RENESAS_LVDS_OUTPUT lvds0
#include "panel-aa104xd12.dtsi"
};
&{/panel} {
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
&lvds0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};

4
arch/arm64/boot/dts/renesas/ulcb.dtsi
View File

@ -163,6 +163,8 @@ phy0: ethernet-phy@0 {
reg = <0>;
interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
@ -221,7 +223,7 @@ ak4613: codec@10 {
asahi-kasei,out6-single-end;
};
cs2000: clk-multiplier@4f {
cs2000: clock-controller@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;

2
arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi
View File

@ -169,6 +169,8 @@ avb0_phy: ethernet-phy@0 {
reg = <0>;
interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
};

28
include/dt-bindings/soc/renesas,r8a78000-mfis.h Normal file
View File

@ -0,0 +1,28 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
#ifndef _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H
#define _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H
/*
* Constants for the second mbox-cell of the Renesas MFIS IP core. To be treated
* as bit flags which can be ORed.
*/
/*
* MFIS HW design before r8a78001 requires a channel to be marked as either
* TX or RX.
*/
#define MFIS_CHANNEL_TX (0 << 0)
#define MFIS_CHANNEL_RX (1 << 0)
/*
* MFIS variants before r8a78001 work with pairs of IICR and EICR registers.
* Usually, it is specified in the datasheets which of the two a specific core
* should use. Then, it does not need extra description in DT. For plain MFIS
* of r8a78000, this is selectable, though. According to the system design and
* the firmware in use, these channels need to be marked. This is not needed
* with other versions of the MFIS, not even with MFIS-SCP of r8a78000.
*/
#define MFIS_CHANNEL_IICR (0 << 1)
#define MFIS_CHANNEL_EICR (1 << 1)
#endif /* _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H */