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arm64: dts: renesas: r9a08g046l48-smarc: Enable audio

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Enable audio on the RZ/G3L SMARC EVK by linking SSI0 with the DA7212
audio CODEC.  The SSI0 signals are multiplexed with SD2 and are selected
by switch SW_SD2_EN#.  Add regulator nodes regulator-{1p8v,3p3v} to the
SoM DTSI for reuse by eMMC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260528074615.91110-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2026-05-28 08:45:45 +01:00 committed by Geert Uytterhoeven
parent 80e32321c3
commit 0d4ed95406
2 changed files with 94 additions and 0 deletions
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72
arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
View File

@ -9,6 +9,7 @@
/* Switch selection settings */
#define RZ_BOOT_MODE3 1
#define SW_SD2_EN 0
#define SW_DPI_EN 0
#define SW_GPIO4 1
#define SW_I3C_EN 0
@ -38,6 +39,32 @@ aliases {
i2c3 = &i2c3;
serial3 = &scif0;
};
#if !SW_SD2_EN && !SW_I3C_EN
snd_rzg3l: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "snd_rzg3l";
#address-cells = <1>;
#size-cells = <0>;
ssi_link_play: simple-audio-card,dai-link@0 {
reg = <0>;
format = "i2s";
bitclock-master = <&cpu_dai>;
frame-master = <&cpu_dai>;
mclk-fs = <256>;
cpu_dai: cpu {
sound-dai = <&ssi0>;
};
codec_dai: codec {
sound-dai = <&da7212>;
clocks = <&versa3 1>;
};
};
};
#endif
};
&i2c2 {
@ -53,6 +80,27 @@ &i2c3 {
pinctrl-names = "default";
status = "okay";
da7212: codec@1a {
compatible = "dlg,da7212";
reg = <0x1a>;
clocks = <&versa3 1>;
clock-names = "mclk";
#sound-dai-cells = <0>;
dlg,micbias1-lvl = <2500>;
dlg,micbias2-lvl = <2500>;
dlg,dmic-data-sel = "lrise_rfall";
dlg,dmic-samplephase = "between_clkedge";
dlg,dmic-clkrate = <3000000>;
VDDA-supply = <&reg_1p8v>;
VDDSP-supply = <&reg_3p3v>;
VDDMIC-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_1p8v>;
};
};
#endif
@ -71,6 +119,11 @@ &keys {
};
&pinctrl {
audio_clk_pins: audio-clock {
pinmux = <RZG3L_PORT_PINMUX(H, 4, 6)>, /* AUDIO_CLK_B */
<RZG3L_PORT_PINMUX(H, 5, 6)>; /* AUDIO_CLK_C */
};
i2c2_pins: i2c2 {
pinmux = <RZG3L_PORT_PINMUX(A, 4, 4)>, /* RIIC2_SCL */
<RZG3L_PORT_PINMUX(A, 5, 4)>; /* RIIC2_SDA */
@ -85,9 +138,28 @@ scif0_pins: scif0 {
pins = "SCIF0_TXD", "SCIF0_RXD";
power-source = <1800>;
};
ssi0_pins: ssi0 {
pinmux = <RZG3L_PORT_PINMUX(H, 0, 9)>, /* SSIF0_RXD */
<RZG3L_PORT_PINMUX(H, 1, 9)>, /* SSIF0_BCK */
<RZG3L_PORT_PINMUX(H, 2, 9)>, /* SSIF0_RCK */
<RZG3L_PORT_PINMUX(H, 3, 9)>; /* SSIF0_TXD */
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
};
#if !SW_SD2_EN
&ssi0 {
clocks = <&cpg CPG_MOD R9A08G046_SSI0_PCLK2>,
<&cpg CPG_MOD R9A08G046_SSI0_PCLK_SFR>,
<&versa3 2>, <&versa3 3>;
pinctrl-0 = <&audio_clk_pins>, <&ssi0_pins>;
pinctrl-names = "default";
status = "okay";
};
#endif

22
arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
View File

@ -13,6 +13,10 @@
* 0 - SMARC_I2C_GP is enabled
* 1 - I3C is enabled
*
* Switch position SYS.4, Macro SW_SD2_EN:
* 0 - Select I2S0
* 1 - Select SD2
*
* Switch position SYS.5, Macro SW_DPI_EN:
* 0 - Select multiple SMARC signals active
* 1 - Select LCD
@ -41,6 +45,24 @@ memory@48000000 {
reg = <0x0 0x48000000 0x0 0x78000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
x2_clk: x2-clock {
compatible = "fixed-clock";
#clock-cells = <0>;