github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-07-28 01:55:51 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

arm64: dts: renesas: rzg3l-smarc-som: Enable Versa clock generator

Browse Source 
The RZ/G3L SMARC SoM has a Versa 5P35023B clock generator to generate
the following clocks:
  - ref: Not connected,
  - se1: AUDIO_MCK (11.2896 or 12.2880 MHz),
  - se2: RZ_AUDIO_CLK_B (11.2896 MHz),
  - se3: RZ_AUDIO_CLK_C (12.2880 MHz),
  - diff{1,1B}: ET{0,1}_PHY_CLK (25 MHz),
  - diff2{2,2B}: Not connected.

Enable the Vversa 5P35023B clock generator on the RZ/G3L SoM DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260528074615.91110-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2026-05-28 08:45:44 +01:00 committed by Geert Uytterhoeven
parent 3f9c7afdfa
commit 80e32321c3
1 changed files with 18 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
View File

@ -40,6 +40,12 @@ memory@48000000 {
/* First 128MiB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
x2_clk: x2-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
&eth0 {
@ -75,6 +81,18 @@ &extal_clk {
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
versa3: clock-generator@68 {
compatible = "renesas,5p35023";
reg = <0x68>;
#clock-cells = <1>;
clocks = <&x2_clk>;
assigned-clocks = <&versa3 1>, <&versa3 2>,
<&versa3 3>, <&versa3 4>;
assigned-clock-rates = <12288000>, <11289600>,
<12288000>, <25000000>;
};
};
&mdio0 {