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gpio: mpc8xxx: use new generic GPIO chip API
Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20250825-gpio-mmio-gpio-conv-v1-13-356b4b1d5110@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
This commit is contained in:
Bartosz Golaszewski
parent
67e4be48f4
commit
90ab705035
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@ -9,6 +9,7 @@
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#include <linux/acpi.h>
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#include <linux/bitops.h>
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#include <linux/gpio/driver.h>
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#include <linux/gpio/generic.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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@ -34,7 +35,7 @@
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#define GPIO_IBE 0x18
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struct mpc8xxx_gpio_chip {
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struct gpio_chip gc;
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struct gpio_generic_chip chip;
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void __iomem *regs;
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raw_spinlock_t lock;
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@ -66,8 +67,10 @@ static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
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u32 out_mask, out_shadow;
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out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
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val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
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out_mask = gpio_generic_read_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_DIR);
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val = gpio_generic_read_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
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out_shadow = gc->bgpio_data & out_mask;
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return !!((val | out_shadow) & mpc_pin2mask(gpio));
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@ -108,12 +111,13 @@ static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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unsigned long mask;
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int i;
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mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
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& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
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mask = gpio_generic_read_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_IER) &
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gpio_generic_read_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_IMR);
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for_each_set_bit(i, &mask, 32)
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generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
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@ -124,15 +128,17 @@ static void mpc8xxx_irq_unmask(struct irq_data *d)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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struct gpio_chip *gc = &mpc8xxx_gc->chip.gc;
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unsigned long flags;
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gpiochip_enable_irq(gc, hwirq);
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
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gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
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gpio_generic_write_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_IMR,
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gpio_generic_read_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_IMR)
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| mpc_pin2mask(irqd_to_hwirq(d)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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@ -142,13 +148,14 @@ static void mpc8xxx_irq_mask(struct irq_data *d)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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struct gpio_chip *gc = &mpc8xxx_gc->chip.gc;
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unsigned long flags;
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
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gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
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gpio_generic_write_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_IMR,
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gpio_generic_read_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_IMR)
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& ~mpc_pin2mask(irqd_to_hwirq(d)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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@ -159,32 +166,34 @@ static void mpc8xxx_irq_mask(struct irq_data *d)
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static void mpc8xxx_irq_ack(struct irq_data *d)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
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gpio_generic_write_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_IER,
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mpc_pin2mask(irqd_to_hwirq(d)));
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}
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static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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unsigned long flags;
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switch (flow_type) {
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_LEVEL_LOW:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
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gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
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gpio_generic_write_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_ICR,
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gpio_generic_read_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_ICR)
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| mpc_pin2mask(irqd_to_hwirq(d)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
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gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
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gpio_generic_write_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_ICR,
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gpio_generic_read_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_ICR)
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& ~mpc_pin2mask(irqd_to_hwirq(d)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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@ -199,7 +208,6 @@ static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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unsigned long gpio = irqd_to_hwirq(d);
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void __iomem *reg;
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unsigned int shift;
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@ -217,7 +225,9 @@ static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_LEVEL_LOW:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
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gpio_generic_write_reg(&mpc8xxx_gc->chip, reg,
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(gpio_generic_read_reg(&mpc8xxx_gc->chip,
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reg) & ~(3 << shift))
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| (2 << shift));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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@ -225,14 +235,18 @@ static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
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gpio_generic_write_reg(&mpc8xxx_gc->chip, reg,
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(gpio_generic_read_reg(&mpc8xxx_gc->chip,
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reg) & ~(3 << shift))
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| (1 << shift));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
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gpio_generic_write_reg(&mpc8xxx_gc->chip, reg,
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(gpio_generic_read_reg(&mpc8xxx_gc->chip,
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reg) & ~(3 << shift)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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@ -309,6 +323,7 @@ static const struct of_device_id mpc8xxx_gpio_ids[] = {
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static int mpc8xxx_probe(struct platform_device *pdev)
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{
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const struct mpc8xxx_gpio_devtype *devtype = NULL;
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struct gpio_generic_chip_config config;
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struct mpc8xxx_gpio_chip *mpc8xxx_gc;
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struct device *dev = &pdev->dev;
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struct fwnode_handle *fwnode;
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@ -327,26 +342,28 @@ static int mpc8xxx_probe(struct platform_device *pdev)
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if (IS_ERR(mpc8xxx_gc->regs))
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return PTR_ERR(mpc8xxx_gc->regs);
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gc = &mpc8xxx_gc->gc;
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gc = &mpc8xxx_gc->chip.gc;
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gc->parent = dev;
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config = (typeof(config)){
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.dev = dev,
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.sz = 4,
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.dat = mpc8xxx_gc->regs + GPIO_DAT,
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.dirout = mpc8xxx_gc->regs + GPIO_DIR,
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.flags = BGPIOF_BIG_ENDIAN
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};
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if (device_property_read_bool(dev, "little-endian")) {
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ret = bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT,
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NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR,
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NULL, BGPIOF_BIG_ENDIAN);
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if (ret)
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return ret;
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dev_dbg(dev, "GPIO registers are LITTLE endian\n");
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} else {
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ret = bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT,
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NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR,
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NULL, BGPIOF_BIG_ENDIAN
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| BGPIOF_BIG_ENDIAN_BYTE_ORDER);
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if (ret)
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return ret;
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config.flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
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dev_dbg(dev, "GPIO registers are BIG endian\n");
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}
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ret = gpio_generic_chip_init(&mpc8xxx_gc->chip, &config);
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if (ret)
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return ret;
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mpc8xxx_gc->direction_output = gc->direction_output;
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devtype = device_get_match_data(dev);
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@ -379,10 +396,13 @@ static int mpc8xxx_probe(struct platform_device *pdev)
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device_is_compatible(dev, "fsl,ls1028a-gpio") ||
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device_is_compatible(dev, "fsl,ls1088a-gpio") ||
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is_acpi_node(fwnode)) {
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
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gpio_generic_write_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
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/* Also, latch state of GPIOs configured as output by bootloader. */
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gc->bgpio_data = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) &
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gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
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gc->bgpio_data = gpio_generic_read_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_DAT) &
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gpio_generic_read_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_DIR);
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}
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ret = devm_gpiochip_add_data(dev, gc, mpc8xxx_gc);
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@ -405,8 +425,10 @@ static int mpc8xxx_probe(struct platform_device *pdev)
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return 0;
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/* ack and mask all irqs */
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
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gpio_generic_write_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
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gpio_generic_write_reg(&mpc8xxx_gc->chip,
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mpc8xxx_gc->regs + GPIO_IMR, 0);
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ret = devm_request_irq(dev, mpc8xxx_gc->irqn,
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mpc8xxx_gpio_irq_cascade,
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