mirror of
https://github.com/torvalds/linux.git
synced 2026-06-01 02:53:36 +02:00
gpio: grgpio: use new generic GPIO chip API
Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20250825-gpio-mmio-gpio-conv-v1-12-356b4b1d5110@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
This commit is contained in:
Bartosz Golaszewski
parent
ebd63ab0f2
commit
67e4be48f4
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/bitops.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/gpio/generic.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
|
|
@ -59,7 +60,7 @@ struct grgpio_lirq {
|
|||
};
|
||||
|
||||
struct grgpio_priv {
|
||||
struct gpio_chip gc;
|
||||
struct gpio_generic_chip chip;
|
||||
void __iomem *regs;
|
||||
struct device *dev;
|
||||
|
||||
|
|
@ -91,13 +92,12 @@ struct grgpio_priv {
|
|||
static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
|
||||
int val)
|
||||
{
|
||||
struct gpio_chip *gc = &priv->gc;
|
||||
|
||||
if (val)
|
||||
priv->imask |= BIT(offset);
|
||||
else
|
||||
priv->imask &= ~BIT(offset);
|
||||
gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
|
||||
|
||||
gpio_generic_write_reg(&priv->chip, priv->regs + GRGPIO_IMASK, priv->imask);
|
||||
}
|
||||
|
||||
static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
|
||||
|
|
@ -118,7 +118,6 @@ static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
|
|||
static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
|
||||
unsigned long flags;
|
||||
u32 mask = BIT(d->hwirq);
|
||||
u32 ipol;
|
||||
u32 iedge;
|
||||
|
|
@ -146,15 +145,13 @@ static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
|
||||
guard(gpio_generic_lock_irqsave)(&priv->chip);
|
||||
|
||||
ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
|
||||
iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
|
||||
ipol = gpio_generic_read_reg(&priv->chip, priv->regs + GRGPIO_IPOL) & ~mask;
|
||||
iedge = gpio_generic_read_reg(&priv->chip, priv->regs + GRGPIO_IEDGE) & ~mask;
|
||||
|
||||
priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
|
||||
priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
|
||||
|
||||
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
gpio_generic_write_reg(&priv->chip, priv->regs + GRGPIO_IPOL, ipol | pol);
|
||||
gpio_generic_write_reg(&priv->chip, priv->regs + GRGPIO_IEDGE, iedge | edge);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -163,29 +160,23 @@ static void grgpio_irq_mask(struct irq_data *d)
|
|||
{
|
||||
struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
|
||||
int offset = d->hwirq;
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
|
||||
scoped_guard(gpio_generic_lock_irqsave, &priv->chip)
|
||||
grgpio_set_imask(priv, offset, 0);
|
||||
|
||||
grgpio_set_imask(priv, offset, 0);
|
||||
|
||||
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
|
||||
gpiochip_disable_irq(&priv->gc, d->hwirq);
|
||||
gpiochip_disable_irq(&priv->chip.gc, d->hwirq);
|
||||
}
|
||||
|
||||
static void grgpio_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
|
||||
int offset = d->hwirq;
|
||||
unsigned long flags;
|
||||
|
||||
gpiochip_enable_irq(&priv->gc, d->hwirq);
|
||||
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
|
||||
gpiochip_enable_irq(&priv->chip.gc, d->hwirq);
|
||||
|
||||
guard(gpio_generic_lock_irqsave)(&priv->chip);
|
||||
|
||||
grgpio_set_imask(priv, offset, 1);
|
||||
|
||||
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static const struct irq_chip grgpio_irq_chip = {
|
||||
|
|
@ -200,12 +191,11 @@ static const struct irq_chip grgpio_irq_chip = {
|
|||
static irqreturn_t grgpio_irq_handler(int irq, void *dev)
|
||||
{
|
||||
struct grgpio_priv *priv = dev;
|
||||
int ngpio = priv->gc.ngpio;
|
||||
unsigned long flags;
|
||||
int ngpio = priv->chip.gc.ngpio;
|
||||
int i;
|
||||
int match = 0;
|
||||
|
||||
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
|
||||
guard(gpio_generic_lock_irqsave)(&priv->chip);
|
||||
|
||||
/*
|
||||
* For each gpio line, call its interrupt handler if it its underlying
|
||||
|
|
@ -221,8 +211,6 @@ static irqreturn_t grgpio_irq_handler(int irq, void *dev)
|
|||
}
|
||||
}
|
||||
|
||||
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
|
||||
if (!match)
|
||||
dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
|
||||
|
||||
|
|
@ -253,13 +241,18 @@ static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
|
|||
dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
|
||||
irq, offset);
|
||||
|
||||
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
|
||||
gpio_generic_chip_lock_irqsave(&priv->chip, flags);
|
||||
|
||||
/* Request underlying irq if not already requested */
|
||||
lirq->irq = irq;
|
||||
uirq = &priv->uirqs[lirq->index];
|
||||
if (uirq->refcnt == 0) {
|
||||
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
/*
|
||||
* FIXME: This is not how locking works at all, you can't just
|
||||
* release the lock for a moment to do something that can't
|
||||
* sleep...
|
||||
*/
|
||||
gpio_generic_chip_unlock_irqrestore(&priv->chip, flags);
|
||||
ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
|
||||
dev_name(priv->dev), priv);
|
||||
if (ret) {
|
||||
|
|
@ -268,11 +261,11 @@ static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
|
|||
uirq->uirq);
|
||||
return ret;
|
||||
}
|
||||
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
|
||||
gpio_generic_chip_lock_irqsave(&priv->chip, flags);
|
||||
}
|
||||
uirq->refcnt++;
|
||||
|
||||
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
gpio_generic_chip_unlock_irqrestore(&priv->chip, flags);
|
||||
|
||||
/* Setup irq */
|
||||
irq_set_chip_data(irq, priv);
|
||||
|
|
@ -290,13 +283,13 @@ static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
|
|||
struct grgpio_lirq *lirq;
|
||||
struct grgpio_uirq *uirq;
|
||||
unsigned long flags;
|
||||
int ngpio = priv->gc.ngpio;
|
||||
int ngpio = priv->chip.gc.ngpio;
|
||||
int i;
|
||||
|
||||
irq_set_chip_and_handler(irq, NULL, NULL);
|
||||
irq_set_chip_data(irq, NULL);
|
||||
|
||||
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
|
||||
gpio_generic_chip_lock_irqsave(&priv->chip, flags);
|
||||
|
||||
/* Free underlying irq if last user unmapped */
|
||||
index = -1;
|
||||
|
|
@ -315,13 +308,13 @@ static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
|
|||
uirq = &priv->uirqs[lirq->index];
|
||||
uirq->refcnt--;
|
||||
if (uirq->refcnt == 0) {
|
||||
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
gpio_generic_chip_unlock_irqrestore(&priv->chip, flags);
|
||||
free_irq(uirq->uirq, priv);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
gpio_generic_chip_unlock_irqrestore(&priv->chip, flags);
|
||||
}
|
||||
|
||||
static void grgpio_irq_domain_remove(void *data)
|
||||
|
|
@ -341,6 +334,7 @@ static const struct irq_domain_ops grgpio_irq_domain_ops = {
|
|||
static int grgpio_probe(struct platform_device *ofdev)
|
||||
{
|
||||
struct device_node *np = ofdev->dev.of_node;
|
||||
struct gpio_generic_chip_config config;
|
||||
struct device *dev = &ofdev->dev;
|
||||
void __iomem *regs;
|
||||
struct gpio_chip *gc;
|
||||
|
|
@ -359,17 +353,24 @@ static int grgpio_probe(struct platform_device *ofdev)
|
|||
if (IS_ERR(regs))
|
||||
return PTR_ERR(regs);
|
||||
|
||||
gc = &priv->gc;
|
||||
err = bgpio_init(gc, dev, 4, regs + GRGPIO_DATA,
|
||||
regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
|
||||
BGPIOF_BIG_ENDIAN_BYTE_ORDER);
|
||||
config = (typeof(config)){
|
||||
.dev = dev,
|
||||
.sz = 4,
|
||||
.dat = regs + GRGPIO_DATA,
|
||||
.set = regs + GRGPIO_OUTPUT,
|
||||
.dirout = regs + GRGPIO_DIR,
|
||||
.flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER,
|
||||
};
|
||||
|
||||
gc = &priv->chip.gc;
|
||||
err = gpio_generic_chip_init(&priv->chip, &config);
|
||||
if (err) {
|
||||
dev_err(dev, "bgpio_init() failed\n");
|
||||
dev_err(dev, "failed to initialize the generic GPIO chip\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
priv->regs = regs;
|
||||
priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
|
||||
priv->imask = gpio_generic_read_reg(&priv->chip, regs + GRGPIO_IMASK);
|
||||
priv->dev = dev;
|
||||
|
||||
gc->owner = THIS_MODULE;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user