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arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node

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The non-mmio pinctrl node is not supposed to be inside the soc simple-bus
as dtc points out:

../arch/arm64/boot/dts/rockchip/rk3576.dtsi:2351.20-2417.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property

Move the pinctrl node outside and adapt the indentation.

Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250518220449.2722673-3-heiko@sntech.de
This commit is contained in:
Heiko Stuebner 2025-05-19 00:04:44 +02:00
parent 4d2587e0e1
commit 8ff721f602
1 changed files with 68 additions and 68 deletions
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136
arch/arm64/boot/dts/rockchip/rk3576.dtsi
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@ -429,6 +429,74 @@ simple-audio-card,cpu {
};
};
pinctrl: pinctrl {
compatible = "rockchip,rk3576-pinctrl";
rockchip,grf = <&ioc_grf>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio0: gpio@27320000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0x27320000 0x0 0x200>;
clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gpio1: gpio@2ae10000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0x2ae10000 0x0 0x200>;
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
gpio-controller;
gpio-ranges = <&pinctrl 0 32 32>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gpio2: gpio@2ae20000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0x2ae20000 0x0 0x200>;
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
gpio-controller;
gpio-ranges = <&pinctrl 0 64 32>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gpio3: gpio@2ae30000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0x2ae30000 0x0 0x200>;
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
gpio-controller;
gpio-ranges = <&pinctrl 0 96 32>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gpio4: gpio@2ae40000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0x2ae40000 0x0 0x200>;
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
gpio-controller;
gpio-ranges = <&pinctrl 0 128 32>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
};
pmu_a53: pmu-a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
@ -2349,74 +2417,6 @@ scmi_shmem: scmi-shmem@4010f000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x4010f000 0x0 0x100>;
};
pinctrl: pinctrl {
compatible = "rockchip,rk3576-pinctrl";
rockchip,grf = <&ioc_grf>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio0: gpio@27320000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0x27320000 0x0 0x200>;
clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gpio1: gpio@2ae10000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0x2ae10000 0x0 0x200>;
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
gpio-controller;
gpio-ranges = <&pinctrl 0 32 32>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gpio2: gpio@2ae20000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0x2ae20000 0x0 0x200>;
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
gpio-controller;
gpio-ranges = <&pinctrl 0 64 32>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gpio3: gpio@2ae30000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0x2ae30000 0x0 0x200>;
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
gpio-controller;
gpio-ranges = <&pinctrl 0 96 32>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gpio4: gpio@2ae40000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0x2ae40000 0x0 0x200>;
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
gpio-controller;
gpio-ranges = <&pinctrl 0 128 32>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
};
};
};