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tools/power/x86/intel-speed-select: Increase wait time after SST PP level switch

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After an Intel Speed Select Performance Profile (SST PP) level switch, hardware
takes time to update the HWP CAPABILITIES register. The current 2 ms wait time
is insufficient on some platforms, leading to stale capability readings.

Increase the wait time to 10 ms. Because level switching is an infrequent operation
done only during configuration and not in a fast path, the slight delay has
negligible impact.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
This commit is contained in:
Srinivas Pandruvada 2026-09-10 16:12:20 -07:00 committed by Ilpo Järvinen
parent 346629565a
commit 8f91d453a5
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1 changed files with 1 additions and 1 deletions
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tools/power/x86/intel-speed-select/isst-config.c
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@ -1545,7 +1545,7 @@ static void set_tdp_level_for_cpu(struct isst_id *id, void *arg1, void *arg2, vo
struct isst_pkg_ctdp_level_info ctdp_level;
/* Wait for updated base frequencies */
usleep(2000);
usleep(10000);
/* Adjusting uncore freq */
if (!is_dmr_plus_platform())