From 8f91d453a541026ff7d00d9daa634228c8a2bf45 Mon Sep 17 00:00:00 2001 From: Srinivas Pandruvada Date: Thu, 10 Sep 2026 16:12:20 -0700 Subject: [PATCH] tools/power/x86/intel-speed-select: Increase wait time after SST PP level switch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After an Intel Speed Select Performance Profile (SST PP) level switch, hardware takes time to update the HWP CAPABILITIES register. The current 2 ms wait time is insufficient on some platforms, leading to stale capability readings. Increase the wait time to 10 ms. Because level switching is an infrequent operation done only during configuration and not in a fast path, the slight delay has negligible impact. Signed-off-by: Srinivas Pandruvada Signed-off-by: Ilpo Järvinen --- tools/power/x86/intel-speed-select/isst-config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/power/x86/intel-speed-select/isst-config.c b/tools/power/x86/intel-speed-select/isst-config.c index 2faff1aead52..e1aa4c2853b3 100644 --- a/tools/power/x86/intel-speed-select/isst-config.c +++ b/tools/power/x86/intel-speed-select/isst-config.c @@ -1545,7 +1545,7 @@ static void set_tdp_level_for_cpu(struct isst_id *id, void *arg1, void *arg2, vo struct isst_pkg_ctdp_level_info ctdp_level; /* Wait for updated base frequencies */ - usleep(2000); + usleep(10000); /* Adjusting uncore freq */ if (!is_dmr_plus_platform())