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wifi: ath12k: Move rxdma ring config functions to wifi7 directory
Move architecture specific RxDMA functions to wifi7 directory. The moved APIs will be a part of dp_rx.c file inside wifi7 directory. wifi7/dp_rx.c file will continue to be part of ath12k.ko temporarily until the corresponding infra for movement to ath12k_wifi7.ko arrives in upcoming patches. Architecture specific APIs: ath12k_dp_rxdma_ring_sel_config_qcn9274 ath12k_dp_rxdma_ring_sel_config_wcn7850 Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.4.1-00199-QCAHKSWPL_SILICONZ-1 Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3 Signed-off-by: Pavankumar Nandeshwar <quic_pnandesh@quicinc.com> Signed-off-by: Ripan Deuri <quic_rdeuri@quicinc.com> Reviewed-by: Vasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com> Reviewed-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com> Link: https://patch.msgid.link/20250828173553.3341351-9-quic_rdeuri@quicinc.com Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
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@ -3765,91 +3765,6 @@ void ath12k_dp_rx_pdev_free(struct ath12k_base *ab, int mac_id)
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ath12k_dp_rx_pdev_srng_free(ar);
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}
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int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab)
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{
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struct ath12k_dp *dp = &ab->dp;
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struct htt_rx_ring_tlv_filter tlv_filter = {};
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u32 ring_id;
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int ret;
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u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
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ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
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tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING;
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tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR;
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tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST |
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HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST |
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HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA;
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tlv_filter.offset_valid = true;
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tlv_filter.rx_packet_offset = hal_rx_desc_sz;
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tlv_filter.rx_mpdu_start_offset =
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ab->hal_rx_ops->rx_desc_get_mpdu_start_offset();
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tlv_filter.rx_msdu_end_offset =
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ab->hal_rx_ops->rx_desc_get_msdu_end_offset();
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if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) {
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tlv_filter.rx_mpdu_start_wmask =
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ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start();
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tlv_filter.rx_msdu_end_wmask =
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ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end();
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ath12k_dbg(ab, ATH12K_DBG_DATA,
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"Configuring compact tlv masks rx_mpdu_start_wmask 0x%x rx_msdu_end_wmask 0x%x\n",
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tlv_filter.rx_mpdu_start_wmask, tlv_filter.rx_msdu_end_wmask);
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}
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ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 0,
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HAL_RXDMA_BUF,
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DP_RXDMA_REFILL_RING_SIZE,
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&tlv_filter);
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return ret;
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}
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EXPORT_SYMBOL(ath12k_dp_rxdma_ring_sel_config_qcn9274);
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int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab)
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{
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struct ath12k_dp *dp = &ab->dp;
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struct htt_rx_ring_tlv_filter tlv_filter = {};
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u32 ring_id;
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int ret = 0;
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u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
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int i;
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ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
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tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING;
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tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR;
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tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST |
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HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST |
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HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA;
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tlv_filter.offset_valid = true;
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tlv_filter.rx_packet_offset = hal_rx_desc_sz;
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tlv_filter.rx_header_offset = offsetof(struct hal_rx_desc_wcn7850, pkt_hdr_tlv);
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tlv_filter.rx_mpdu_start_offset =
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ab->hal_rx_ops->rx_desc_get_mpdu_start_offset();
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tlv_filter.rx_msdu_end_offset =
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ab->hal_rx_ops->rx_desc_get_msdu_end_offset();
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/* TODO: Selectively subscribe to required qwords within msdu_end
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* and mpdu_start and setup the mask in below msg
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* and modify the rx_desc struct
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*/
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for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
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ring_id = dp->rx_mac_buf_ring[i].ring_id;
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ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, i,
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HAL_RXDMA_BUF,
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DP_RXDMA_REFILL_RING_SIZE,
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&tlv_filter);
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}
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return ret;
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}
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EXPORT_SYMBOL(ath12k_dp_rxdma_ring_sel_config_wcn7850);
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int ath12k_dp_rx_htt_setup(struct ath12k_base *ab)
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{
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struct ath12k_dp *dp = &ab->dp;
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@ -402,9 +402,6 @@ u8 ath12k_dp_rx_h_decap_type(struct ath12k_base *ab,
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struct hal_rx_desc *desc);
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u32 ath12k_dp_rx_h_mpdu_err(struct ath12k_base *ab,
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struct hal_rx_desc *desc);
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int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab);
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int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab);
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int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len,
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int (*iter)(struct ath12k_base *ar, u16 tag, u16 len,
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const void *ptr, void *data),
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@ -348,3 +348,88 @@ int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab,
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done:
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return total_num_buffs_reaped;
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}
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int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab)
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{
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struct ath12k_dp *dp = &ab->dp;
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struct htt_rx_ring_tlv_filter tlv_filter = {};
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u32 ring_id;
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int ret;
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u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
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ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
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tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING;
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tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR;
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tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST |
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HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST |
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HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA;
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tlv_filter.offset_valid = true;
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tlv_filter.rx_packet_offset = hal_rx_desc_sz;
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tlv_filter.rx_mpdu_start_offset =
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ab->hal_rx_ops->rx_desc_get_mpdu_start_offset();
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tlv_filter.rx_msdu_end_offset =
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ab->hal_rx_ops->rx_desc_get_msdu_end_offset();
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if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) {
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tlv_filter.rx_mpdu_start_wmask =
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ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start();
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tlv_filter.rx_msdu_end_wmask =
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ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end();
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ath12k_dbg(ab, ATH12K_DBG_DATA,
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"Configuring compact tlv masks rx_mpdu_start_wmask 0x%x rx_msdu_end_wmask 0x%x\n",
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tlv_filter.rx_mpdu_start_wmask, tlv_filter.rx_msdu_end_wmask);
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}
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ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 0,
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HAL_RXDMA_BUF,
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DP_RXDMA_REFILL_RING_SIZE,
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&tlv_filter);
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return ret;
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}
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EXPORT_SYMBOL(ath12k_dp_rxdma_ring_sel_config_qcn9274);
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int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab)
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{
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struct ath12k_dp *dp = &ab->dp;
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struct htt_rx_ring_tlv_filter tlv_filter = {};
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u32 ring_id;
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int ret = 0;
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u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
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int i;
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ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
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tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING;
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tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR;
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tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST |
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HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST |
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HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA;
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tlv_filter.offset_valid = true;
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tlv_filter.rx_packet_offset = hal_rx_desc_sz;
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tlv_filter.rx_header_offset = offsetof(struct hal_rx_desc_wcn7850, pkt_hdr_tlv);
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tlv_filter.rx_mpdu_start_offset =
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ab->hal_rx_ops->rx_desc_get_mpdu_start_offset();
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tlv_filter.rx_msdu_end_offset =
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ab->hal_rx_ops->rx_desc_get_msdu_end_offset();
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/* TODO: Selectively subscribe to required qwords within msdu_end
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* and mpdu_start and setup the mask in below msg
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* and modify the rx_desc struct
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*/
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for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
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ring_id = dp->rx_mac_buf_ring[i].ring_id;
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ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, i,
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HAL_RXDMA_BUF,
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DP_RXDMA_REFILL_RING_SIZE,
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&tlv_filter);
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}
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return ret;
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}
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EXPORT_SYMBOL(ath12k_dp_rxdma_ring_sel_config_wcn7850);
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@ -11,4 +11,6 @@
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int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab,
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struct napi_struct *napi, int budget);
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int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab);
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int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab);
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#endif
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@ -1,7 +1,7 @@
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// SPDX-License-Identifier: BSD-3-Clause-Clear
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/*
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* Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <linux/types.h>
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@ -16,7 +16,7 @@
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#include "hw.h"
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#include "../mhi.h"
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#include "mhi.h"
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#include "../dp_rx.h"
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#include "dp_rx.h"
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#include "../peer.h"
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#include "wmi.h"
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