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wifi: ath12k: Move rx_desc.h file to wifi7 directory

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Move wifi7 architecture specific file rx_desc.h to wifi7 directory
and rename it to hal_rx_desc.h to match the naming convention used,
and move the common part from it to hal.h file which is in the
common directory.

Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.4.1-00199-QCAHKSWPL_SILICONZ-1
Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3

Signed-off-by: Pavankumar Nandeshwar <quic_pnandesh@quicinc.com>
Signed-off-by: Ripan Deuri <quic_rdeuri@quicinc.com>
Reviewed-by: Vasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com>
Reviewed-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com>
Link: https://patch.msgid.link/20250828173553.3341351-8-quic_rdeuri@quicinc.com
Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
This commit is contained in:
Pavankumar Nandeshwar 2025-08-28 23:05:40 +05:30 committed by Jeff Johnson
parent 87a230ec2b
commit 8658abc713
3 changed files with 49 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/wireless/ath/ath12k/dp_rx.h
View File

@ -7,7 +7,7 @@
#define ATH12K_DP_RX_H
#include "core.h"
#include "rx_desc.h"
#include "wifi7/hal_rx_desc.h"
#include "debug.h"
#define DP_MAX_NWIFI_HDR_LEN 30

48
drivers/net/wireless/ath/ath12k/hal.h
View File

@ -8,7 +8,7 @@
#define ATH12K_HAL_H
#include "wifi7/hal_desc.h"
#include "rx_desc.h"
#include "wifi7/hal_rx_desc.h"
struct ath12k_base;
@ -30,6 +30,11 @@ struct ath12k_base;
#define HAL_RX_MON_MAX_AGGR_SIZE 128
#define HAL_MAX_UL_MU_USERS 37
#define MAX_USER_POS 8
#define MAX_MU_GROUP_ID 64
#define MAX_MU_GROUP_SHOW 16
#define MAX_MU_GROUP_LENGTH (6 * MAX_MU_GROUP_SHOW)
#define HAL_CE_REMAP_REG_BASE (ab->ce_remap_base_addr)
#define HAL_LINK_DESC_SIZE (32 << 2)
@ -824,6 +829,47 @@ enum hal_srng_dir {
HAL_SRNG_DIR_DST
};
enum rx_msdu_start_pkt_type {
RX_MSDU_START_PKT_TYPE_11A,
RX_MSDU_START_PKT_TYPE_11B,
RX_MSDU_START_PKT_TYPE_11N,
RX_MSDU_START_PKT_TYPE_11AC,
RX_MSDU_START_PKT_TYPE_11AX,
RX_MSDU_START_PKT_TYPE_11BA,
RX_MSDU_START_PKT_TYPE_11BE,
};
enum rx_msdu_start_sgi {
RX_MSDU_START_SGI_0_8_US,
RX_MSDU_START_SGI_0_4_US,
RX_MSDU_START_SGI_1_6_US,
RX_MSDU_START_SGI_3_2_US,
};
enum rx_msdu_start_recv_bw {
RX_MSDU_START_RECV_BW_20MHZ,
RX_MSDU_START_RECV_BW_40MHZ,
RX_MSDU_START_RECV_BW_80MHZ,
RX_MSDU_START_RECV_BW_160MHZ,
};
enum rx_msdu_start_reception_type {
RX_MSDU_START_RECEPTION_TYPE_SU,
RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO,
RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA,
RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO,
RX_MSDU_START_RECEPTION_TYPE_UL_MU_MIMO,
RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA,
RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA_MIMO,
};
enum rx_desc_decap_type {
RX_DESC_DECAP_TYPE_RAW,
RX_DESC_DECAP_TYPE_NATIVE_WIFI,
RX_DESC_DECAP_TYPE_ETHERNET2_DIX,
RX_DESC_DECAP_TYPE_8023,
};
struct hal_rx_user_status {
u32 mcs:4,
nss:3,

48
drivers/net/wireless/ath/ath12k/rx_desc.h → drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h
View File

@ -1,18 +1,11 @@
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
* Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef ATH12K_RX_DESC_H
#define ATH12K_RX_DESC_H
enum rx_desc_decap_type {
RX_DESC_DECAP_TYPE_RAW,
RX_DESC_DECAP_TYPE_NATIVE_WIFI,
RX_DESC_DECAP_TYPE_ETHERNET2_DIX,
RX_DESC_DECAP_TYPE_8023,
};
enum rx_desc_decrypt_status_code {
RX_DESC_DECRYPT_STATUS_CODE_OK,
RX_DESC_DECRYPT_STATUS_CODE_UNPROTECTED_FRAME,
@ -631,40 +624,6 @@ struct rx_mpdu_start_qcn9274_compact {
*
*/
enum rx_msdu_start_pkt_type {
RX_MSDU_START_PKT_TYPE_11A,
RX_MSDU_START_PKT_TYPE_11B,
RX_MSDU_START_PKT_TYPE_11N,
RX_MSDU_START_PKT_TYPE_11AC,
RX_MSDU_START_PKT_TYPE_11AX,
RX_MSDU_START_PKT_TYPE_11BA,
RX_MSDU_START_PKT_TYPE_11BE,
};
enum rx_msdu_start_sgi {
RX_MSDU_START_SGI_0_8_US,
RX_MSDU_START_SGI_0_4_US,
RX_MSDU_START_SGI_1_6_US,
RX_MSDU_START_SGI_3_2_US,
};
enum rx_msdu_start_recv_bw {
RX_MSDU_START_RECV_BW_20MHZ,
RX_MSDU_START_RECV_BW_40MHZ,
RX_MSDU_START_RECV_BW_80MHZ,
RX_MSDU_START_RECV_BW_160MHZ,
};
enum rx_msdu_start_reception_type {
RX_MSDU_START_RECEPTION_TYPE_SU,
RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO,
RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA,
RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO,
RX_MSDU_START_RECEPTION_TYPE_UL_MU_MIMO,
RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA,
RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA_MIMO,
};
#define RX_MSDU_END_64_TLV_SRC_LINK_ID GENMASK(24, 22)
#define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0)
@ -1536,9 +1495,4 @@ struct hal_rx_desc {
} u;
} __packed;
#define MAX_USER_POS 8
#define MAX_MU_GROUP_ID 64
#define MAX_MU_GROUP_SHOW 16
#define MAX_MU_GROUP_LENGTH (6 * MAX_MU_GROUP_SHOW)
#endif /* ATH12K_RX_DESC_H */