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Fix check warnings all over the place.

Browse Source 
mt7986:
 - Add crypto, I2C and SPI nodes
 
 mt6795:
 - Add clock nodes
 - Add DMA support for UARTs
 - Add MMC nodes
 - Add basic support for Sonyx Xperia M5
 
 mt8195:
 - Add video enconder node
 - Add PCIe support
 - Fine tune capacity-dmips-mhz
 - Add support for internal and external display port
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Merge tag 'v6.1-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into soc/dt

Fix check warnings all over the place.

mt7986:
- Add crypto, I2C and SPI nodes

mt6795:
- Add clock nodes
- Add DMA support for UARTs
- Add MMC nodes
- Add basic support for Sonyx Xperia M5

mt8195:
- Add video enconder node
- Add PCIe support
- Fine tune capacity-dmips-mhz
- Add support for internal and external display port

* tag 'v6.1-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (35 commits)
  arm64: dts: mt7986: add spi related device nodes
  arm64: dts: mt7986: move wed_pcie node
  arm64: dts: mediatek: Add support for MT6795 Sony Xperia M5 smartphone
  dt-bindings: arm: mediatek: Add compatible for MT6795 Sony Xperia M5
  arm64: dts: mediatek: mt6795: Add support for eMMC/SD/SDIO controllers
  arm64: dts: mediatek: mt6795: Add support for APDMA and wire up UART DMAs
  arm64: dts: mediatek: mt6795: Replace UART dummy clocks with pericfg
  arm64: dts: mediatek: mt6795: Add topckgen, infra, peri clocks/resets
  arm64: dts: mediatek: cherry: Add edptx and dptx support
  arm64: dts: mediatek: cherry: Add dp-intf ports
  arm64: dts: mt8195: Add edptx and dptx nodes
  arm64: dts: mt8195: Add dp-intf nodes
  arm64: dts: mediatek: mt6797: Fix 26M oscillator unit name
  arm64: dts: mediatek: pumpkin-common: Fix devicetree warnings
  arm64: dts: mt2712-evb: Fix usb vbus regulators unit names
  arm64: dts: mt2712-evb: Fix vproc fixed regulators unit names
  arm64: dts: mt2712e: Fix unit address for pinctrl node
  arm64: dts: mt2712e: Fix unit_address_vs_reg warning for oscillators
  arm64: dts: mt6779: Fix devicetree build warnings
  arm64: dts: mt7896a: Fix unit_address_vs_reg warning for oscillator
  ...

Link: https://lore.kernel.org/r/8933d687-71f0-e9ad-a7c6-2e5a8993463d@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-11-22 23:10:15 +01:00
commit 8ccf49d7fb
20 changed files with 750 additions and 110 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/mediatek.yaml
View File

@ -58,6 +58,7 @@ properties:
- items:
- enum:
- mediatek,mt6795-evb
- sony,xperia-m5
- const: mediatek,mt6795
- items:
- enum:
@ -83,6 +84,7 @@ properties:
- const: mediatek,mt7629
- items:
- enum:
- bananapi,bpi-r3
- mediatek,mt7986a-rfb
- const: mediatek,mt7986a
- items:

1
arch/arm64/boot/dts/mediatek/Makefile
View File

@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-sony-xperia-m5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb

12
arch/arm64/boot/dts/mediatek/mt2712-evb.dts
View File

@ -26,14 +26,14 @@ chosen {
stdout-path = "serial0:921600n8";
};
cpus_fixed_vproc0: fixedregulator@0 {
cpus_fixed_vproc0: regulator-vproc-buck0 {
compatible = "regulator-fixed";
regulator-name = "vproc_buck0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
cpus_fixed_vproc1: fixedregulator@1 {
cpus_fixed_vproc1: regulator-vproc-buck1 {
compatible = "regulator-fixed";
regulator-name = "vproc_buck1";
regulator-min-microvolt = <1000000>;
@ -50,7 +50,7 @@ extcon_usb1: extcon_iddig1 {
id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>;
};
usb_p0_vbus: regulator@2 {
usb_p0_vbus: regulator-usb-p0-vbus {
compatible = "regulator-fixed";
regulator-name = "p0_vbus";
regulator-min-microvolt = <5000000>;
@ -59,7 +59,7 @@ usb_p0_vbus: regulator@2 {
enable-active-high;
};
usb_p1_vbus: regulator@3 {
usb_p1_vbus: regulator-usb-p1-vbus {
compatible = "regulator-fixed";
regulator-name = "p1_vbus";
regulator-min-microvolt = <5000000>;
@ -68,7 +68,7 @@ usb_p1_vbus: regulator@3 {
enable-active-high;
};
usb_p2_vbus: regulator@4 {
usb_p2_vbus: regulator-usb-p2-vbus {
compatible = "regulator-fixed";
regulator-name = "p2_vbus";
regulator-min-microvolt = <5000000>;
@ -77,7 +77,7 @@ usb_p2_vbus: regulator@4 {
enable-active-high;
};
usb_p3_vbus: regulator@5 {
usb_p3_vbus: regulator-usb-p3-vbus {
compatible = "regulator-fixed";
regulator-name = "p3_vbus";
regulator-min-microvolt = <5000000>;

28
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
View File

@ -160,70 +160,70 @@ sys_clk: dummyclk {
#clock-cells = <0>;
};
clk26m: oscillator@0 {
clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
clk32k: oscillator@1 {
clk32k: oscillator-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "clk32k";
};
clkfpc: oscillator@2 {
clkfpc: oscillator-50m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "clkfpc";
};
clkaud_ext_i_0: oscillator@3 {
clkaud_ext_i_0: oscillator-aud0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <6500000>;
clock-output-names = "clkaud_ext_i_0";
};
clkaud_ext_i_1: oscillator@4 {
clkaud_ext_i_1: oscillator-aud1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <196608000>;
clock-output-names = "clkaud_ext_i_1";
};
clkaud_ext_i_2: oscillator@5 {
clkaud_ext_i_2: oscillator-aud2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <180633600>;
clock-output-names = "clkaud_ext_i_2";
};
clki2si0_mck_i: oscillator@6 {
clki2si0_mck_i: oscillator-i2s0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <30000000>;
clock-output-names = "clki2si0_mck_i";
};
clki2si1_mck_i: oscillator@7 {
clki2si1_mck_i: oscillator-i2s1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <30000000>;
clock-output-names = "clki2si1_mck_i";
};
clki2si2_mck_i: oscillator@8 {
clki2si2_mck_i: oscillator-i2s2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <30000000>;
clock-output-names = "clki2si2_mck_i";
};
clktdmin_mclk_i: oscillator@9 {
clktdmin_mclk_i: oscillator-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <30000000>;
@ -266,7 +266,7 @@ syscfg_pctl_a: syscfg_pctl_a@10005000 {
reg = <0 0x10005000 0 0x1000>;
};
pio: pinctrl@10005000 {
pio: pinctrl@1000b000 {
compatible = "mediatek,mt2712-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>;
@ -766,9 +766,9 @@ mmc0: mmc@11230000 {
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_0>,
<&pericfg CLK_PERI_MSDC50_0_HCLK_EN>,
<&pericfg CLK_PERI_MSDC30_0_QTR_EN>,
<&pericfg CLK_PERI_MSDC50_0_EN>;
clock-names = "source", "hclk", "bus_clk", "source_cg";
<&pericfg CLK_PERI_MSDC50_0_EN>,
<&pericfg CLK_PERI_MSDC30_0_QTR_EN>;
clock-names = "source", "hclk", "source_cg", "bus_clk";
status = "disabled";
};

10
arch/arm64/boot/dts/mediatek/mt6779.dtsi
View File

@ -88,14 +88,14 @@ pmu {
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
};
clk26m: oscillator@0 {
clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
clk32k: oscillator@1 {
clk32k: oscillator-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@ -117,7 +117,7 @@ soc {
compatible = "simple-bus";
ranges;
gic: interrupt-controller@0c000000 {
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
interrupt-parent = <&gic>;
@ -138,7 +138,7 @@ ppi_cluster1: interrupt-partition-1 {
};
sysirq: intpol-controller@0c53a650 {
sysirq: intpol-controller@c53a650 {
compatible = "mediatek,mt6779-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
@ -160,7 +160,7 @@ infracfg_ao: clock-controller@10001000 {
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt6779-pinctrl", "syscon";
compatible = "mediatek,mt6779-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11c20000 0 0x1000>,
<0 0x11d10000 0 0x1000>,

88
arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts Normal file
View File

@ -0,0 +1,88 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022, Collabora Ltd
* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
/dts-v1/;
#include "mt6795.dtsi"
/ {
model = "Sony Xperia M5";
compatible = "sony,xperia-m5", "mediatek,mt6795";
chassis-type = "handset";
aliases {
mmc0 = &mmc0;
mmc1 = &mmc1;
serial0 = &uart0;
serial1 = &uart1;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x1e800000>;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 128 KiB reserved for ARM Trusted Firmware (BL31) */
bl31_secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>;
no-map;
};
/* preloader and bootloader regions cannot be touched */
preloader-region@44800000 {
reg = <0 0x44800000 0 0x100000>;
no-map;
};
bootloader-region@46000000 {
reg = <0 0x46000000 0 0x400000>;
no-map;
};
};
};
&pio {
uart0_pins: uart0-pins {
pins-rx {
pinmux = <PINMUX_GPIO113__FUNC_URXD0>;
bias-pull-up;
input-enable;
};
pins-tx {
pinmux = <PINMUX_GPIO114__FUNC_UTXD0>;
output-high;
};
};
uart2_pins: uart2-pins {
pins-rx {
pinmux = <PINMUX_GPIO31__FUNC_URXD2>;
bias-pull-up;
input-enable;
};
pins-tx {
pinmux = <PINMUX_GPIO32__FUNC_UTXD2>;
};
};
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};

109
arch/arm64/boot/dts/mediatek/mt6795.dtsi
View File

@ -6,7 +6,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
#include <dt-bindings/reset/mediatek,mt6795-resets.h>
/ {
compatible = "mediatek,mt6795";
@ -192,6 +194,26 @@ soc {
compatible = "simple-bus";
ranges;
topckgen: syscon@10000000 {
compatible = "mediatek,mt6795-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg: syscon@10001000 {
compatible = "mediatek,mt6795-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pericfg: syscon@10003000 {
compatible = "mediatek,mt6795-pericfg", "syscon";
reg = <0 0x10003000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt6795-pinctrl";
reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
@ -292,7 +314,10 @@ uart0: serial@11002000 {
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>;
clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
clock-names = "baud", "bus";
dmas = <&apdma 0>, <&apdma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -301,16 +326,48 @@ uart1: serial@11003000 {
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>;
clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
clock-names = "baud", "bus";
dmas = <&apdma 2>, <&apdma 3>;
dma-names = "tx", "rx";
status = "disabled";
};
apdma: dma-controller@11000380 {
compatible = "mediatek,mt6795-uart-dma",
"mediatek,mt6577-uart-dma";
reg = <0 0x11000380 0 0x60>,
<0 0x11000400 0 0x60>,
<0 0x11000480 0 0x60>,
<0 0x11000500 0 0x60>,
<0 0x11000580 0 0x60>,
<0 0x11000600 0 0x60>,
<0 0x11000680 0 0x60>,
<0 0x11000700 0 0x60>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
dma-requests = <8>;
clocks = <&pericfg CLK_PERI_AP_DMA>;
clock-names = "apdma";
mediatek,dma-33bits;
#dma-cells = <1>;
};
uart2: serial@11004000 {
compatible = "mediatek,mt6795-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>;
clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
clock-names = "baud", "bus";
dmas = <&apdma 4>, <&apdma 5>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -319,7 +376,51 @@ uart3: serial@11005000 {
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>;
clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
clock-names = "baud", "bus";
dmas = <&apdma 6>, <&apdma 7>;
dma-names = "tx", "rx";
status = "disabled";
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt6795-mmc";
reg = <0 0x11230000 0 0x1000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_0>,
<&topckgen CLK_TOP_MSDC50_0_H_SEL>,
<&topckgen CLK_TOP_MSDC50_0_SEL>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
mmc1: mmc@11240000 {
compatible = "mediatek,mt6795-mmc";
reg = <0 0x11240000 0 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_1>,
<&topckgen CLK_TOP_AXI_SEL>;
clock-names = "source", "hclk";
status = "disabled";
};
mmc2: mmc@11250000 {
compatible = "mediatek,mt6795-mmc";
reg = <0 0x11250000 0 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_2>,
<&topckgen CLK_TOP_AXI_SEL>;
clock-names = "source", "hclk";
status = "disabled";
};
mmc3: mmc@11260000 {
compatible = "mediatek,mt6795-mmc";
reg = <0 0x11260000 0 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_3>,
<&topckgen CLK_TOP_AXI_SEL>;
clock-names = "source", "hclk";
status = "disabled";
};
};

2
arch/arm64/boot/dts/mediatek/mt6797.dtsi
View File

@ -95,7 +95,7 @@ cpu9: cpu@201 {
};
};
clk26m: oscillator@0 {
clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;

1
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
View File

@ -235,7 +235,6 @@ &mmc1 {
bus-width = <4>;
max-frequency = <50000000>;
cap-sd-highspeed;
r_smpl = <1>;
cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;

1
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
View File

@ -208,7 +208,6 @@ &mmc1 {
bus-width = <4>;
max-frequency = <50000000>;
cap-sd-highspeed;
r_smpl = <1>;
cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;

135
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
View File

@ -9,7 +9,7 @@
/ {
model = "MediaTek MT7986a RFB";
compatible = "mediatek,mt7986a-rfb";
compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
aliases {
serial0 = &uart0;
@ -25,6 +25,10 @@ memory@40000000 {
};
};
&crypto {
status = "okay";
};
&eth {
status = "okay";
@ -54,6 +58,88 @@ switch: switch@0 {
};
};
&pio {
spi_flash_pins: spi-flash-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
spic_pins: spic-pins {
mux {
function = "spi";
groups = "spi1_2";
};
};
uart1_pins: uart1-pins {
mux {
function = "uart";
groups = "uart1";
};
};
uart2_pins: uart2-pins {
mux {
function = "uart";
groups = "uart2";
};
};
wf_2g_5g_pins: wf-2g-5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_dbdc_pins: wf-dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA";
drive-strength = <4>;
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
cs-gpios = <0>, <0>;
status = "okay";
spi_nand: spi_nand@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <10000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
};
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic_pins>;
cs-gpios = <0>, <0>;
status = "okay";
};
&switch {
ports {
#address-cells = <1>;
@ -121,50 +207,3 @@ &wifi {
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
};
&pio {
uart1_pins: uart1-pins {
mux {
function = "uart";
groups = "uart1";
};
};
uart2_pins: uart2-pins {
mux {
function = "uart";
groups = "uart2";
};
};
wf_2g_5g_pins: wf-2g-5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_dbdc_pins: wf-dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA";
drive-strength = <4>;
};
};
};

74
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
View File

@ -10,11 +10,12 @@
#include <dt-bindings/reset/mt7986-resets.h>
/ {
compatible = "mediatek,mt7986a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
clk40m: oscillator@0 {
clk40m: oscillator-40m {
compatible = "fixed-clock";
clock-frequency = <40000000>;
#clock-cells = <0>;
@ -112,6 +113,12 @@ infracfg: infracfg@10001000 {
#clock-cells = <1>;
};
wed_pcie: wed-pcie@10003000 {
compatible = "mediatek,mt7986-wed-pcie",
"syscon";
reg = <0 0x10003000 0 0x10>;
};
topckgen: topckgen@1001b000 {
compatible = "mediatek,mt7986-topckgen", "syscon";
reg = <0 0x1001B000 0 0x1000>;
@ -168,7 +175,7 @@ sgmiisys1: syscon@10070000 {
#clock-cells = <1>;
};
trng: trng@1020f000 {
trng: rng@1020f000 {
compatible = "mediatek,mt7986-rng",
"mediatek,mt7623-rng";
reg = <0 0x1020f000 0 0x100>;
@ -177,6 +184,21 @@ trng: trng@1020f000 {
status = "disabled";
};
crypto: crypto@10320000 {
compatible = "inside-secure,safexcel-eip97";
reg = <0 0x10320000 0 0x40000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ring0", "ring1", "ring2", "ring3";
clocks = <&infracfg CLK_INFRA_EIP97_CK>;
clock-names = "infra_eip97_ck";
assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
status = "disabled";
};
uart0: serial@11002000 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";
@ -218,6 +240,48 @@ uart2: serial@11004000 {
status = "disabled";
};
i2c0: i2c@11008000 {
compatible = "mediatek,mt7986-i2c";
reg = <0 0x11008000 0 0x90>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <5>;
clocks = <&infracfg CLK_INFRA_I2C0_CK>,
<&infracfg CLK_INFRA_AP_DMA_CK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@1100a000 {
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x1100a000 0 0x100>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_MPLL_D2>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI0_CK>,
<&infracfg CLK_INFRA_SPI0_HCK_CK>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
status = "disabled";
};
spi1: spi@1100b000 {
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x1100b000 0 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_MPLL_D2>,
<&topckgen CLK_TOP_SPIM_MST_SEL>,
<&infracfg CLK_INFRA_SPI1_CK>,
<&infracfg CLK_INFRA_SPI1_HCK_CK>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
status = "disabled";
};
ethsys: syscon@15000000 {
#address-cells = <1>;
#size-cells = <1>;
@ -228,12 +292,6 @@ ethsys: syscon@15000000 {
#reset-cells = <1>;
};
wed_pcie: wed-pcie@10003000 {
compatible = "mediatek,mt7986-wed-pcie",
"syscon";
reg = <0 0x10003000 0 0x10>;
};
wed0: wed@15010000 {
compatible = "mediatek,mt7986-wed",
"syscon";

57
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
View File

@ -9,7 +9,7 @@
/ {
model = "MediaTek MT7986b RFB";
compatible = "mediatek,mt7986b-rfb";
compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
aliases {
serial0 = &uart0;
@ -25,7 +25,7 @@ memory@40000000 {
};
};
&uart0 {
&crypto {
status = "okay";
};
@ -99,14 +99,21 @@ fixed-link {
};
};
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
};
&pio {
spi_flash_pins: spi-flash-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
spic_pins: spic-pins {
mux {
function = "spi";
groups = "spi1_2";
};
};
wf_2g_5g_pins: wf-2g-5g-pins {
mux {
function = "wifi";
@ -138,3 +145,35 @@ conf {
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
cs-gpios = <0>, <0>;
status = "okay";
spi_nand: spi_nand@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <10000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
};
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic_pins>;
cs-gpios = <0>, <0>;
status = "okay";
};
&uart0 {
status = "okay";
};
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
};

3
arch/arm64/boot/dts/mediatek/mt7986b.dtsi
View File

@ -5,6 +5,9 @@
*/
#include "mt7986a.dtsi"
/ {
compatible = "mediatek,mt7986b";
};
&pio {
compatible = "mediatek,mt7986b-pinctrl";

6
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View File

@ -221,11 +221,6 @@ tboard_thermistor2: thermal-sensor2 {
};
};
&afe {
i2s3-share = "I2S2";
i2s0-share = "I2S5";
};
&auxadc {
status = "okay";
};
@ -378,7 +373,6 @@ &mmc1 {
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
max-frequency = <200000000>;
drv-type = <2>;
cap-sd-highspeed;
sd-uhs-sdr50;
sd-uhs-sdr104;

3
arch/arm64/boot/dts/mediatek/mt8186.dtsi
View File

@ -198,16 +198,19 @@ cluster_off_b: cluster-off-b {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
};
};

3
arch/arm64/boot/dts/mediatek/mt8192.dtsi
View File

@ -169,16 +169,19 @@ core3 {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
};
idle-states {

86
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
View File

@ -120,6 +120,78 @@ scp_mem: memory@50000000 {
};
};
&dp_intf0 {
status = "okay";
port {
dp_intf0_out: endpoint {
remote-endpoint = <&edp_in>;
};
};
};
&dp_intf1 {
status = "okay";
port {
dp_intf1_out: endpoint {
remote-endpoint = <&dptx_in>;
};
};
};
&edp_tx {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&edptx_pins_default>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
edp_in: endpoint {
remote-endpoint = <&dp_intf0_out>;
};
};
port@1 {
reg = <1>;
edp_out: endpoint {
data-lanes = <0 1 2 3>;
};
};
};
};
&dp_tx {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dptx_pin>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dptx_in: endpoint {
remote-endpoint = <&dp_intf1_out>;
};
};
port@1 {
reg = <1>;
dptx_out: endpoint {
data-lanes = <0 1 2 3>;
};
};
};
};
&i2c0 {
status = "okay";
@ -479,6 +551,20 @@ pins-ec-ap-int-odl {
};
};
edptx_pins_default: edptx-default-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>;
bias-pull-up;
};
};
dptx_pin: dptx-default-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>;
bias-pull-up;
};
};
i2c0_pins: i2c0-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,

233
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@ -13,6 +13,7 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/power/mt8195-power.h>
#include <dt-bindings/reset/mt8195-resets.h>
/ {
compatible = "mediatek,mt8195";
@ -36,7 +37,7 @@ cpu0: cpu@0 {
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
@ -49,7 +50,7 @@ cpu1: cpu@100 {
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
@ -62,7 +63,7 @@ cpu2: cpu@200 {
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
@ -75,7 +76,7 @@ cpu3: cpu@300 {
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
@ -213,16 +214,19 @@ cluster_off_b: cluster-off-b {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
};
};
@ -1182,6 +1186,110 @@ xhci3: usb@112b0000 {
status = "disabled";
};
pcie0: pcie@112f0000 {
compatible = "mediatek,mt8195-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x112f0000 0 0x4000>;
reg-names = "pcie-mac";
interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x20000000
0x0 0x20000000 0 0x200000>,
<0x82000000 0 0x20200000
0x0 0x20200000 0 0x3e00000>;
iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
iommu-map-mask = <0x0>;
clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
<&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
<&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
clock-names = "pl_250m", "tl_26m", "tl_96m",
"tl_32k", "peri_26m", "peri_mem";
assigned-clocks = <&topckgen CLK_TOP_TL>;
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
phys = <&pciephy>;
phy-names = "pcie-phy";
power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
reset-names = "mac";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
status = "disabled";
pcie_intc0: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie1: pcie@112f8000 {
compatible = "mediatek,mt8195-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x112f8000 0 0x4000>;
reg-names = "pcie-mac";
interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x24000000
0x0 0x24000000 0 0x200000>,
<0x82000000 0 0x24200000
0x0 0x24200000 0 0x3e00000>;
iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
iommu-map-mask = <0x0>;
clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
<&clk26m>,
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
<&clk26m>,
<&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
/* Designer has connect pcie1 with peri_mem_p0 clock */
<&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
clock-names = "pl_250m", "tl_26m", "tl_96m",
"tl_32k", "peri_26m", "peri_mem";
assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
phys = <&u3port1 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
reset-names = "mac";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
status = "disabled";
pcie_intc1: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
nor_flash: spi@1132c000 {
compatible = "mediatek,mt8195-nor",
"mediatek,mt8173-nor";
@ -1241,6 +1349,37 @@ u2_intr_p3: usb2-intr-p3@189,2 {
reg = <0x189 0x2>;
bits = <7 5>;
};
pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
reg = <0x190 0x1>;
bits = <0 4>;
};
pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
reg = <0x190 0x1>;
bits = <4 4>;
};
pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
reg = <0x191 0x1>;
bits = <0 4>;
};
pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
reg = <0x191 0x1>;
bits = <4 4>;
};
pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
reg = <0x192 0x1>;
bits = <0 4>;
};
pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
reg = <0x192 0x1>;
bits = <4 4>;
};
pciephy_glb_intr: pciephy-glb-intr@193 {
reg = <0x193 0x1>;
bits = <0 4>;
};
dp_calibration: dp-data@1ac {
reg = <0x1ac 0x10>;
};
};
u3phy2: t-phy@11c40000 {
@ -1461,6 +1600,23 @@ u3port0: usb-phy@700 {
};
};
pciephy: phy@11e80000 {
compatible = "mediatek,mt8195-pcie-phy";
reg = <0 0x11e80000 0 0x10000>;
reg-names = "sif";
nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
<&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>,
<&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>,
<&pciephy_rx_ln1>;
nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
"tx_ln0_nmos", "rx_ln0",
"tx_ln1_pmos", "tx_ln1_nmos",
"rx_ln1";
power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
#phy-cells = <0>;
status = "disabled";
};
ufsphy: ufs-phy@11fa0000 {
compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
reg = <0 0x11fa0000 0 0xc000>;
@ -1959,6 +2115,30 @@ larb19: larb@1a010000 {
power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
};
venc: video-codec@1a020000 {
compatible = "mediatek,mt8195-vcodec-enc";
reg = <0 0x1a020000 0 0x10000>;
iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
<&iommu_vdo M4U_PORT_L19_VENC_REC>,
<&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
<&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
<&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
<&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
<&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
<&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
<&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,scp = <&scp>;
clocks = <&vencsys CLK_VENC_VENC>;
clock-names = "venc_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
};
vencsys_core1: clock-controller@1b000000 {
compatible = "mediatek,mt8195-vencsys_core1";
reg = <0 0x1b000000 0 0x1000>;
@ -2067,6 +2247,17 @@ merge0: merge@1c014000 {
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
};
dp_intf0: dp-intf@1c015000 {
compatible = "mediatek,mt8195-dp-intf";
reg = <0 0x1c015000 0 0x1000>;
interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
<&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
<&apmixedsys CLK_APMIXED_TVDPLL1>;
clock-names = "engine", "pixel", "pll";
status = "disabled";
};
mutex: mutex@1c016000 {
compatible = "mediatek,mt8195-disp-mutex";
reg = <0 0x1c016000 0 0x1000>;
@ -2155,5 +2346,39 @@ larb3: larb@1c103000 {
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
};
dp_intf1: dp-intf@1c113000 {
compatible = "mediatek,mt8195-dp-intf";
reg = <0 0x1c113000 0 0x1000>;
interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
<&vdosys1 CLK_VDO1_DPINTF>,
<&apmixedsys CLK_APMIXED_TVDPLL2>;
clock-names = "engine", "pixel", "pll";
status = "disabled";
};
edp_tx: edp-tx@1c500000 {
compatible = "mediatek,mt8195-edp-tx";
reg = <0 0x1c500000 0 0x8000>;
nvmem-cells = <&dp_calibration>;
nvmem-cell-names = "dp_calibration_data";
power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
max-linkrate-mhz = <8100>;
status = "disabled";
};
dp_tx: dp-tx@1c600000 {
compatible = "mediatek,mt8195-dp-tx";
reg = <0 0x1c600000 0 0x8000>;
nvmem-cells = <&dp_calibration>;
nvmem-cell-names = "dp_calibration_data";
power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
max-linkrate-mhz = <8100>;
status = "disabled";
};
};
};

6
arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
View File

@ -17,7 +17,7 @@ chosen {
};
firmware {
optee: optee@4fd00000 {
optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
};
@ -209,7 +209,7 @@ pins_cmd_dat {
};
};
i2c0_pins_a: i2c0@0 {
i2c0_pins_a: i2c0 {
pins1 {
pinmux = <MT8516_PIN_58_SDA0__FUNC_SDA0_0>,
<MT8516_PIN_59_SCL0__FUNC_SCL0_0>;
@ -217,7 +217,7 @@ pins1 {
};
};
i2c2_pins_a: i2c2@0 {
i2c2_pins_a: i2c2 {
pins1 {
pinmux = <MT8516_PIN_60_SDA2__FUNC_SDA2_0>,
<MT8516_PIN_61_SCL2__FUNC_SCL2_0>;