From ce459b1da752cf1dc0b81aba999a6542ab866993 Mon Sep 17 00:00:00 2001 From: Pierre Gondois Date: Mon, 7 Nov 2022 16:57:05 +0100 Subject: [PATCH 01/35] arm64: dts: Update cache properties for mediatek The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois Link: https://lore.kernel.org/r/20221107155825.1644604-13-pierre.gondois@arm.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 3 +++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +++ 3 files changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 64693c17af9e..c326aeb33a10 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -198,16 +198,19 @@ cluster_off_b: cluster-off-b { l2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 6b20376191a7..424fc89cc6f7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -169,16 +169,19 @@ core3 { l2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; idle-states { diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 905d1a90b406..cb74905cfbb8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -213,16 +213,19 @@ cluster_off_b: cluster-off-b { l2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; From 1d53a48eaa1ea2e1c013edfd62e0ffb5b171e97d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Thu, 8 Sep 2022 12:11:51 -0400 Subject: [PATCH 02/35] arm64: dts: mediatek: kukui: Remove i2s-share properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The i2sN-share properties were never documented in the dt-binding and thus shouldn't be used. Now that the ASoC machine drivers are setting the I2S clock sharing internally, these properties are no longer needed, so remove them. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220908161154.648557-8-nfraprado@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index b4b86bb1f1a7..42191b3025a9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -221,11 +221,6 @@ tboard_thermistor2: thermal-sensor2 { }; }; -&afe { - i2s3-share = "I2S2"; - i2s0-share = "I2S5"; -}; - &auxadc { status = "okay"; }; From db962d0d4593cf2aa36881786ac039f1ad3a5f3f Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Fri, 28 Oct 2022 18:34:53 +0300 Subject: [PATCH 03/35] arm64: dts: mediatek: mt6779: Remove syscon compatible from pin controller Remove syscon compatible string from pin controller to follow DT bindings and pass checks. Adding the syscon compatible to the DT bindings documentation instead causes a different check error due to the syscon document specifying a maximum of 1 item in the reg property, while this has 9. This pin controller has never been, and will never be, used as a syscon, hence it is safe to drop this compatible. Signed-off-by: Yassine Oudjana Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20221028153505.23741-2-y.oudjana@protonmail.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6779.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi index 9bdf5145966c..a6fa5212da4e 100644 --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -160,7 +160,7 @@ infracfg_ao: clock-controller@10001000 { }; pio: pinctrl@10005000 { - compatible = "mediatek,mt6779-pinctrl", "syscon"; + compatible = "mediatek,mt6779-pinctrl"; reg = <0 0x10005000 0 0x1000>, <0 0x11c20000 0 0x1000>, <0 0x11d10000 0 0x1000>, From b747fa226910179a1b78818f97358b788f5cb532 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 25 Oct 2022 15:29:50 +0200 Subject: [PATCH 04/35] arm64: dts: mediatek: mt2712e: swap last 2 clocks to match binding First 3 clocks for mt2712 need to be "source", "hclk", "source_cg" so swap last 2 of mmc0 to match the binding. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221025132953.81286-4-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index e6d7453e56e0..9dc0794fcd2e 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -766,9 +766,9 @@ mmc0: mmc@11230000 { interrupts = ; clocks = <&pericfg CLK_PERI_MSDC30_0>, <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>, - <&pericfg CLK_PERI_MSDC30_0_QTR_EN>, - <&pericfg CLK_PERI_MSDC50_0_EN>; - clock-names = "source", "hclk", "bus_clk", "source_cg"; + <&pericfg CLK_PERI_MSDC50_0_EN>, + <&pericfg CLK_PERI_MSDC30_0_QTR_EN>; + clock-names = "source", "hclk", "source_cg", "bus_clk"; status = "disabled"; }; From d76c99057815b07742448c1b4b6d7cfc833536a2 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 25 Oct 2022 15:29:51 +0200 Subject: [PATCH 05/35] arm64: dts: mt8183: drop drv-type from mmc-node This property is not defined in binding and driver. Fixes: cd894e274b74 ("arm64: dts: mt8183: Add krane-sku176 board") Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221025132953.81286-5-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 42191b3025a9..7fc4c592a908 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -373,7 +373,6 @@ &mmc1 { mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; max-frequency = <200000000>; - drv-type = <2>; cap-sd-highspeed; sd-uhs-sdr50; sd-uhs-sdr104; From c4f8593955cde03d48ed33face58c09d980a32e3 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 25 Oct 2022 15:29:52 +0200 Subject: [PATCH 06/35] arm64: dts: mt7622: drop r_smpl property from mmc node This property is not defined in binding and driver. Fixes: 2c002a3049f7 ("arm64: dts: mt7622: add mmc related device nodes") Fixes: 0b6286dd96c0 ("arm64: dts: mt7622: add bananapi BPI-R64 board") Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221025132953.81286-6-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 1 - arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index d3f9eab2b784..af3fe61e4093 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -235,7 +235,6 @@ &mmc1 { bus-width = <4>; max-frequency = <50000000>; cap-sd-highspeed; - r_smpl = <1>; cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; vmmc-supply = <®_3p3v>; vqmmc-supply = <®_3p3v>; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index 36722cabe626..b74e774c6eba 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -208,7 +208,6 @@ &mmc1 { bus-width = <4>; max-frequency = <50000000>; cap-sd-highspeed; - r_smpl = <1>; cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; vmmc-supply = <®_3p3v>; vqmmc-supply = <®_3p3v>; From ee3f54cf6ea8f7032946689de1cafc1c467f6d11 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Thu, 3 Nov 2022 10:56:56 +0800 Subject: [PATCH 07/35] arm64: dts: mt8195: Add venc node Add venc node for mt8195 SoC. Signed-off-by: Irui Wang Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221103025656.8714-4-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index cb74905cfbb8..2edfc21ece56 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1962,6 +1962,30 @@ larb19: larb@1a010000 { power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; }; + venc: video-codec@1a020000 { + compatible = "mediatek,mt8195-vcodec-enc"; + reg = <0 0x1a020000 0 0x10000>; + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, + <&iommu_vdo M4U_PORT_L19_VENC_REC>, + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; + interrupts = ; + mediatek,scp = <&scp>; + clocks = <&vencsys CLK_VENC_VENC>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + }; + vencsys_core1: clock-controller@1b000000 { compatible = "mediatek,mt8195-vencsys_core1"; reg = <0 0x1b000000 0 0x1000>; From 07ce611c705217507c2a036bba8695cbd82c9e36 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Thu, 27 Oct 2022 17:10:22 +0200 Subject: [PATCH 08/35] arm64: dts: mt7986: fix trng node name Binding requires node name to be rng not trng: trng@1020f000: $nodename:0: 'trng@1020f000' does not match '^rng@[0-9a-f]+$' Fixes: 50137c150f5f ("arm64: dts: mediatek: add basic mt7986 support") Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221027151022.5541-1-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 72e0d9722e07..226648f48df2 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -168,7 +168,7 @@ sgmiisys1: syscon@10070000 { #clock-cells = <1>; }; - trng: trng@1020f000 { + trng: rng@1020f000 { compatible = "mediatek,mt7986-rng", "mediatek,mt7623-rng"; reg = <0 0x1020f000 0 0x100>; From ecc0af6a3fe6ae47a341438f299b9439a6572def Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Thu, 3 Nov 2022 10:56:55 +0800 Subject: [PATCH 09/35] arm64: dts: mt8195: Add pcie and pcie phy nodes Add pcie and pcie phy nodes for mt8195. Signed-off-by: Jianjun Wang Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221103025656.8714-3-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 150 +++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 2edfc21ece56..6c90ff4b3746 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8195"; @@ -1185,6 +1186,110 @@ xhci3: usb@112b0000 { status = "disabled"; }; + pcie0: pcie@112f0000 { + compatible = "mediatek,mt8195-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x112f0000 0 0x4000>; + reg-names = "pcie-mac"; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x20000000 + 0x0 0x20000000 0 0x200000>, + <0x82000000 0 0x20200000 + 0x0 0x20200000 0 0x3e00000>; + + iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; + iommu-map-mask = <0x0>; + + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names = "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks = <&topckgen CLK_TOP_TL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys = <&pciephy>; + phy-names = "pcie-phy"; + + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; + + resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; + reset-names = "mac"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + status = "disabled"; + + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@112f8000 { + compatible = "mediatek,mt8195-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x112f8000 0 0x4000>; + reg-names = "pcie-mac"; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x24000000 + 0x0 0x24000000 0 0x200000>, + <0x82000000 0 0x24200000 + 0x0 0x24200000 0 0x3e00000>; + + iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; + iommu-map-mask = <0x0>; + + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + /* Designer has connect pcie1 with peri_mem_p0 clock */ + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names = "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks = <&topckgen CLK_TOP_TL_P1>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys = <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; + + resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; + reset-names = "mac"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + status = "disabled"; + + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + nor_flash: spi@1132c000 { compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor"; @@ -1244,6 +1349,34 @@ u2_intr_p3: usb2-intr-p3@189,2 { reg = <0x189 0x2>; bits = <7 5>; }; + pciephy_rx_ln1: pciephy-rx-ln1@190,1 { + reg = <0x190 0x1>; + bits = <0 4>; + }; + pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { + reg = <0x190 0x1>; + bits = <4 4>; + }; + pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { + reg = <0x191 0x1>; + bits = <0 4>; + }; + pciephy_rx_ln0: pciephy-rx-ln0@191,2 { + reg = <0x191 0x1>; + bits = <4 4>; + }; + pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { + reg = <0x192 0x1>; + bits = <0 4>; + }; + pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { + reg = <0x192 0x1>; + bits = <4 4>; + }; + pciephy_glb_intr: pciephy-glb-intr@193 { + reg = <0x193 0x1>; + bits = <0 4>; + }; }; u3phy2: t-phy@11c40000 { @@ -1464,6 +1597,23 @@ u3port0: usb-phy@700 { }; }; + pciephy: phy@11e80000 { + compatible = "mediatek,mt8195-pcie-phy"; + reg = <0 0x11e80000 0 0x10000>; + reg-names = "sif"; + nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, + <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, + <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, + <&pciephy_rx_ln1>; + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", + "tx_ln0_nmos", "rx_ln0", + "tx_ln1_pmos", "tx_ln1_nmos", + "rx_ln1"; + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + ufsphy: ufs-phy@11fa0000 { compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; reg = <0 0x11fa0000 0 0xc000>; From 965f2c0491ebbb6995233c0b167fb9e0cf0853da Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Sun, 6 Nov 2022 09:50:24 +0100 Subject: [PATCH 10/35] arm64: dts: mt7986: harmonize device node order This arrange device tree nodes in alphabetical order. Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221106085034.12582-2-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 94 ++++++++++---------- arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 22 ++--- 2 files changed, 58 insertions(+), 58 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index afe37b702eef..6189436fe31d 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -54,6 +54,53 @@ switch: switch@0 { }; }; +&pio { + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + &switch { ports { #address-cells = <1>; @@ -121,50 +168,3 @@ &wifi { pinctrl-0 = <&wf_2g_5g_pins>; pinctrl-1 = <&wf_dbdc_pins>; }; - -&pio { - uart1_pins: uart1-pins { - mux { - function = "uart"; - groups = "uart1"; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2"; - }; - }; - - wf_2g_5g_pins: wf-2g-5g-pins { - mux { - function = "wifi"; - groups = "wf_2g", "wf_5g"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; - - wf_dbdc_pins: wf-dbdc-pins { - mux { - function = "wifi"; - groups = "wf_dbdc"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA"; - drive-strength = <4>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index 3443013b5971..7459ddb6b6f0 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -25,10 +25,6 @@ memory@40000000 { }; }; -&uart0 { - status = "okay"; -}; - ð { status = "okay"; @@ -99,13 +95,6 @@ fixed-link { }; }; -&wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>; - pinctrl-1 = <&wf_dbdc_pins>; -}; - &pio { wf_2g_5g_pins: wf-2g-5g-pins { mux { @@ -138,3 +127,14 @@ conf { }; }; }; + +&uart0 { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; +}; From ecc5287cfe5359e454ca705ef02aae0c9756eaad Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Sun, 6 Nov 2022 09:50:27 +0100 Subject: [PATCH 11/35] arm64: dts: mt7986: add crypto related device nodes This patch adds crypto engine support for MT7986. Signed-off-by: Vic Wu Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20221106085034.12582-5-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 4 ++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 4 ++++ 3 files changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index 6189436fe31d..2f48cc3d3ddb 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -25,6 +25,10 @@ memory@40000000 { }; }; +&crypto { + status = "okay"; +}; + ð { status = "okay"; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 226648f48df2..aa57835dcbe9 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -177,6 +177,21 @@ trng: rng@1020f000 { status = "disabled"; }; + crypto: crypto@10320000 { + compatible = "inside-secure,safexcel-eip97"; + reg = <0 0x10320000 0 0x40000>; + interrupts = , + , + , + ; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + clocks = <&infracfg CLK_INFRA_EIP97_CK>; + clock-names = "infra_eip97_ck"; + assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; + status = "disabled"; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7986-uart", "mediatek,mt6577-uart"; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index 7459ddb6b6f0..79c5c78f7a14 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -25,6 +25,10 @@ memory@40000000 { }; }; +&crypto { + status = "okay"; +}; + ð { status = "okay"; From 640a298b34f28c29f839cb047e6fc00ab0451f8a Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Sun, 6 Nov 2022 09:50:29 +0100 Subject: [PATCH 12/35] arm64: dts: mt7986: add i2c node Add i2c Node to mt7986 devicetree. Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20221106085034.12582-7-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index aa57835dcbe9..a22e10e89ab9 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -233,6 +233,20 @@ uart2: serial@11004000 { status = "disabled"; }; + i2c0: i2c@11008000 { + compatible = "mediatek,mt7986-i2c"; + reg = <0 0x11008000 0 0x90>, + <0 0x10217080 0 0x80>; + interrupts = ; + clock-div = <5>; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + ethsys: syscon@15000000 { #address-cells = <1>; #size-cells = <1>; From 8c80453864efea0a0ed5ca2b399fd97f2f55a5ae Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Sun, 6 Nov 2022 09:50:31 +0100 Subject: [PATCH 13/35] dt-bindings: arm64: dts: mediatek: add compatible for bananapi r3 Add compatible for mt7986 based BananaPi R3 SBC. Signed-off-by: Frank Wunderlich Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221106085034.12582-9-linux@fw-web.de Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index d76ce4c3819d..7642f9350d2c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -83,6 +83,7 @@ properties: - const: mediatek,mt7629 - items: - enum: + - bananapi,bpi-r3 - mediatek,mt7986a-rfb - const: mediatek,mt7986a - items: From 2658963084567eb9505292470d40f7322006a69a Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Mon, 14 Nov 2022 13:16:53 +0100 Subject: [PATCH 14/35] arm64: dts: mediatek: mt7986: Add SoC compatible Missing SoC compatible in the board file causes dt bindings check. Signed-off-by: Matthias Brugger Link: https://lore.kernel.org/r/20221114121653.14739-1-matthias.bgg@kernel.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 2 +- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 1 + arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 2 +- arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 3 +++ 4 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index 2f48cc3d3ddb..1dd54e8a3a90 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -9,7 +9,7 @@ / { model = "MediaTek MT7986a RFB"; - compatible = "mediatek,mt7986a-rfb"; + compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; aliases { serial0 = &uart0; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index a22e10e89ab9..90dbb3c6d348 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -10,6 +10,7 @@ #include / { + compatible = "mediatek,mt7986a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index 79c5c78f7a14..7cfcbb95bc52 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -9,7 +9,7 @@ / { model = "MediaTek MT7986b RFB"; - compatible = "mediatek,mt7986b-rfb"; + compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b"; aliases { serial0 = &uart0; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi index 23923b9f8944..db5189664c29 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi @@ -5,6 +5,9 @@ */ #include "mt7986a.dtsi" +/ { + compatible = "mediatek,mt7986b"; +}; &pio { compatible = "mediatek,mt7986b-pinctrl"; From 513c43328b189874fdfee3ae99cac81e5502e7f7 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 5 Oct 2022 11:34:03 +0200 Subject: [PATCH 15/35] arm64: dts: mediatek: mt8195: Fix CPUs capacity-dmips-mhz The capacity-dmips-mhz parameter was miscalculated: this SoC runs the first (Cortex-A55) cluster at a maximum of 2000MHz and the second (Cortex-A78) cluster at a maximum of 3000MHz. In order to calculate the right capacity-dmips-mhz, the following test was performed: 1. CPUFREQ governor was set to 'performance' on both clusters 2. Ran dhrystone with 500000000 iterations for 10 times on each cluster 3. Calculate the mean result for each cluster 4. Calculate DMIPS/MHz: dmips_mhz = dmips_per_second / cpu_mhz 5. Scale results to 1024: result_c0 = (dmips_mhz_c0 - min_dmips_mhz(c0, c1)) / (max_dmips_mhz(c0, c1) - min_dmips_mhz(c0, c1)) * 1024 The mean results for this SoC are: Cluster 0 (LITTLE): 11990400 Dhry/s Cluster 1 (BIG): 59809036 Dhry/s The calculated scaled results are: Cluster 0: 307,934312801831 (rounded to 308) Cluster 1: 1024 Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board") Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221005093404.33102-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 6c90ff4b3746..e078703674ed 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -37,7 +37,7 @@ cpu0: cpu@0 { enable-method = "psci"; performance-domains = <&performance 0>; clock-frequency = <1701000000>; - capacity-dmips-mhz = <578>; + capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; next-level-cache = <&l2_0>; #cooling-cells = <2>; @@ -50,7 +50,7 @@ cpu1: cpu@100 { enable-method = "psci"; performance-domains = <&performance 0>; clock-frequency = <1701000000>; - capacity-dmips-mhz = <578>; + capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; next-level-cache = <&l2_0>; #cooling-cells = <2>; @@ -63,7 +63,7 @@ cpu2: cpu@200 { enable-method = "psci"; performance-domains = <&performance 0>; clock-frequency = <1701000000>; - capacity-dmips-mhz = <578>; + capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; next-level-cache = <&l2_0>; #cooling-cells = <2>; @@ -76,7 +76,7 @@ cpu3: cpu@300 { enable-method = "psci"; performance-domains = <&performance 0>; clock-frequency = <1701000000>; - capacity-dmips-mhz = <578>; + capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; next-level-cache = <&l2_0>; #cooling-cells = <2>; From 7898d047b1eb2bec2622668cd70181442a580c6d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 13 Oct 2022 17:22:05 +0200 Subject: [PATCH 16/35] arm64: dts: mt7896a: Fix unit_address_vs_reg warning for oscillator Rename the oscillator fixed-clock to oscillator-40m and remove the unit address to fix warnings. arch/arm64/boot/dts/mediatek/mt7986a.dtsi:17.23-22.4: Warning (unit_address_vs_reg): /oscillator@0: node has a unit name, but no reg or ranges property Fixes: 1f9986b258c2 ("arm64: dts: mediatek: add clock support for mt7986a") Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221013152212.416661-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 90dbb3c6d348..ebb5a6a672dd 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -15,7 +15,7 @@ / { #address-cells = <2>; #size-cells = <2>; - clk40m: oscillator@0 { + clk40m: oscillator-40m { compatible = "fixed-clock"; clock-frequency = <40000000>; #clock-cells = <0>; From 4d759c524c15dc4151e40b9e3f368147fda7b789 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 13 Oct 2022 17:22:06 +0200 Subject: [PATCH 17/35] arm64: dts: mt6779: Fix devicetree build warnings Rename fixed-clock oscillators to oscillator-26m and oscillator-32k and remove the unit address to fix the unit_address_vs_reg warning; fix the unit address for interrupt and intpol controllers by removing a leading zero in their unit address. This commit fixes the following warnings: (unit_address_vs_reg): /oscillator@0: node has a unit name, but no reg or ranges property (unit_address_vs_reg): /oscillator@1: node has a unit name, but no reg or ranges property (simple_bus_reg): /soc/interrupt-controller@0c000000: simple-bus unit address format error, expected "c000000" (simple_bus_reg): /soc/intpol-controller@0c53a650: simple-bus unit address format error, expected "c53a650" Fixes: 4c7a6260775d ("arm64: dts: add dts nodes for MT6779") Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221013152212.416661-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6779.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi index a6fa5212da4e..5c579e88e749 100644 --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -88,14 +88,14 @@ pmu { interrupts = ; }; - clk26m: oscillator@0 { + clk26m: oscillator-26m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; clock-output-names = "clk26m"; }; - clk32k: oscillator@1 { + clk32k: oscillator-32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -117,7 +117,7 @@ soc { compatible = "simple-bus"; ranges; - gic: interrupt-controller@0c000000 { + gic: interrupt-controller@c000000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; interrupt-parent = <&gic>; @@ -138,7 +138,7 @@ ppi_cluster1: interrupt-partition-1 { }; - sysirq: intpol-controller@0c53a650 { + sysirq: intpol-controller@c53a650 { compatible = "mediatek,mt6779-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; From e4495a0a8b3d84816c9a46edf3ce060bbf267475 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 13 Oct 2022 17:22:07 +0200 Subject: [PATCH 18/35] arm64: dts: mt2712e: Fix unit_address_vs_reg warning for oscillators Rename the fixed-clock oscillators to remove the unit address. This solves unit_address_vs_reg warnings. Fixes: 5d4839709c8e ("arm64: dts: mt2712: Add clock controller device nodes") Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221013152212.416661-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 9dc0794fcd2e..677584348d5c 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -160,70 +160,70 @@ sys_clk: dummyclk { #clock-cells = <0>; }; - clk26m: oscillator@0 { + clk26m: oscillator-26m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; clock-output-names = "clk26m"; }; - clk32k: oscillator@1 { + clk32k: oscillator-32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "clk32k"; }; - clkfpc: oscillator@2 { + clkfpc: oscillator-50m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; clock-output-names = "clkfpc"; }; - clkaud_ext_i_0: oscillator@3 { + clkaud_ext_i_0: oscillator-aud0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <6500000>; clock-output-names = "clkaud_ext_i_0"; }; - clkaud_ext_i_1: oscillator@4 { + clkaud_ext_i_1: oscillator-aud1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <196608000>; clock-output-names = "clkaud_ext_i_1"; }; - clkaud_ext_i_2: oscillator@5 { + clkaud_ext_i_2: oscillator-aud2 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <180633600>; clock-output-names = "clkaud_ext_i_2"; }; - clki2si0_mck_i: oscillator@6 { + clki2si0_mck_i: oscillator-i2s0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <30000000>; clock-output-names = "clki2si0_mck_i"; }; - clki2si1_mck_i: oscillator@7 { + clki2si1_mck_i: oscillator-i2s1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <30000000>; clock-output-names = "clki2si1_mck_i"; }; - clki2si2_mck_i: oscillator@8 { + clki2si2_mck_i: oscillator-i2s2 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <30000000>; clock-output-names = "clki2si2_mck_i"; }; - clktdmin_mclk_i: oscillator@9 { + clktdmin_mclk_i: oscillator-mclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <30000000>; From 1d4516f53a611b362db7ba7a8889923d469f57e1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 13 Oct 2022 17:22:08 +0200 Subject: [PATCH 19/35] arm64: dts: mt2712e: Fix unit address for pinctrl node The unit address for the pinctrl node is (0x)1000b000 and not (0x)10005000, which is the syscfg_pctl_a address instead. This fixes the following warning: arch/arm64/boot/dts/mediatek/mt2712e.dtsi:264.40-267.4: Warning (unique_unit_address): /syscfg_pctl_a@10005000: duplicate unit-address (also used in node /pinctrl@10005000) Fixes: f0c64340b748 ("arm64: dts: mt2712: add pintcrl device node.") Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221013152212.416661-5-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 677584348d5c..92212cddd37e 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -266,7 +266,7 @@ syscfg_pctl_a: syscfg_pctl_a@10005000 { reg = <0 0x10005000 0 0x1000>; }; - pio: pinctrl@10005000 { + pio: pinctrl@1000b000 { compatible = "mediatek,mt2712-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; From 377063156893bf6c088309ac799fe5c6dce2822d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 13 Oct 2022 17:22:09 +0200 Subject: [PATCH 20/35] arm64: dts: mt2712-evb: Fix vproc fixed regulators unit names Update the names to regulator-vproc-buck{0,1} to fix unit_addres_vs_reg warnings for those. Fixes: f75dd8bdd344 ("arm64: dts: mediatek: add mt2712 cpufreq related device nodes") Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221013152212.416661-6-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts index 9b1af9c80130..638908773706 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -26,14 +26,14 @@ chosen { stdout-path = "serial0:921600n8"; }; - cpus_fixed_vproc0: fixedregulator@0 { + cpus_fixed_vproc0: regulator-vproc-buck0 { compatible = "regulator-fixed"; regulator-name = "vproc_buck0"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; - cpus_fixed_vproc1: fixedregulator@1 { + cpus_fixed_vproc1: regulator-vproc-buck1 { compatible = "regulator-fixed"; regulator-name = "vproc_buck1"; regulator-min-microvolt = <1000000>; From ec1ae39a8d25cfb067b5459fac7c5b7b9bce6f6a Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 13 Oct 2022 17:22:10 +0200 Subject: [PATCH 21/35] arm64: dts: mt2712-evb: Fix usb vbus regulators unit names Update the names to regulator-usb-p{0-3}-vbus to fix unit_address_vs_reg warnings for those. Fixes: 1724f4cc5133 ("arm64: dts: Add USB3 related nodes for MT2712") Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221013152212.416661-7-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts index 638908773706..d31a194124c9 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -50,7 +50,7 @@ extcon_usb1: extcon_iddig1 { id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>; }; - usb_p0_vbus: regulator@2 { + usb_p0_vbus: regulator-usb-p0-vbus { compatible = "regulator-fixed"; regulator-name = "p0_vbus"; regulator-min-microvolt = <5000000>; @@ -59,7 +59,7 @@ usb_p0_vbus: regulator@2 { enable-active-high; }; - usb_p1_vbus: regulator@3 { + usb_p1_vbus: regulator-usb-p1-vbus { compatible = "regulator-fixed"; regulator-name = "p1_vbus"; regulator-min-microvolt = <5000000>; @@ -68,7 +68,7 @@ usb_p1_vbus: regulator@3 { enable-active-high; }; - usb_p2_vbus: regulator@4 { + usb_p2_vbus: regulator-usb-p2-vbus { compatible = "regulator-fixed"; regulator-name = "p2_vbus"; regulator-min-microvolt = <5000000>; @@ -77,7 +77,7 @@ usb_p2_vbus: regulator@4 { enable-active-high; }; - usb_p3_vbus: regulator@5 { + usb_p3_vbus: regulator-usb-p3-vbus { compatible = "regulator-fixed"; regulator-name = "p3_vbus"; regulator-min-microvolt = <5000000>; From 509438336ce75c8b4e6ce8e8d507dc77d0783bdd Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 13 Oct 2022 17:22:11 +0200 Subject: [PATCH 22/35] arm64: dts: mediatek: pumpkin-common: Fix devicetree warnings Fix the pinctrl submodes and optee node to remove unneeded unit address, fixing all unit_address_vs_reg warnings. Fixes: 9983822c8cf9 ("arm64: dts: mediatek: add pumpkin board dts") Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221013152212.416661-8-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index 8ee1529683a3..ec8dfb3d1c6d 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -17,7 +17,7 @@ chosen { }; firmware { - optee: optee@4fd00000 { + optee: optee { compatible = "linaro,optee-tz"; method = "smc"; }; @@ -209,7 +209,7 @@ pins_cmd_dat { }; }; - i2c0_pins_a: i2c0@0 { + i2c0_pins_a: i2c0 { pins1 { pinmux = , ; @@ -217,7 +217,7 @@ pins1 { }; }; - i2c2_pins_a: i2c2@0 { + i2c2_pins_a: i2c2 { pins1 { pinmux = , ; From 5f535cc583759c9c60d4cc9b8d221762e2d75387 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 13 Oct 2022 17:22:12 +0200 Subject: [PATCH 23/35] arm64: dts: mediatek: mt6797: Fix 26M oscillator unit name Update its unit name to oscillator-26m and remove the unneeded unit address to fix a unit_address_vs_reg warning. Fixes: 464c510f60c6 ("arm64: dts: mediatek: add mt6797 support") Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221013152212.416661-9-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6797.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index 15616231022a..c3677d77e0a4 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -95,7 +95,7 @@ cpu9: cpu@201 { }; }; - clk26m: oscillator@0 { + clk26m: oscillator-26m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; From 6c2503b5856aa5fbeb7f9147400dd7d6988b9373 Mon Sep 17 00:00:00 2001 From: Bo-Chen Chen Date: Thu, 10 Nov 2022 14:37:13 +0800 Subject: [PATCH 24/35] arm64: dts: mt8195: Add dp-intf nodes Dp-intfs provide the pixel data to edptx and dptx. To support edptx and dptx, we need to add dp-intf0 and dp-intf1 nodes. Dp-intf0 is for edptx and dp-intf1 is for dptx. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221110063716.25677-2-rex-bc.chen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index e078703674ed..62a1d06a7f2d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2244,6 +2244,17 @@ merge0: merge@1c014000 { mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; }; + dp_intf0: dp-intf@1c015000 { + compatible = "mediatek,mt8195-dp-intf"; + reg = <0 0x1c015000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, + <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + <&apmixedsys CLK_APMIXED_TVDPLL1>; + clock-names = "engine", "pixel", "pll"; + status = "disabled"; + }; + mutex: mutex@1c016000 { compatible = "mediatek,mt8195-disp-mutex"; reg = <0 0x1c016000 0 0x1000>; @@ -2332,5 +2343,17 @@ larb3: larb@1c103000 { clock-names = "apb", "smi", "gals"; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; }; + + dp_intf1: dp-intf@1c113000 { + compatible = "mediatek,mt8195-dp-intf"; + reg = <0 0x1c113000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, + <&vdosys1 CLK_VDO1_DPINTF>, + <&apmixedsys CLK_APMIXED_TVDPLL2>; + clock-names = "engine", "pixel", "pll"; + status = "disabled"; + }; }; }; From 64196979f91832b7b7bae1fb60f7998b7b88935f Mon Sep 17 00:00:00 2001 From: Bo-Chen Chen Date: Thu, 10 Nov 2022 14:37:14 +0800 Subject: [PATCH 25/35] arm64: dts: mt8195: Add edptx and dptx nodes In MT8195, we use edptx as the internal display interface and use dptx as the external display interface. Therefore, we need to add these nodes to support the internal display and the external display. - Add dp calibration data in the efuse node. - Add edptx and dptx nodes for MT8195. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221110063716.25677-3-rex-bc.chen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 62a1d06a7f2d..5d31536f4c48 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1377,6 +1377,9 @@ pciephy_glb_intr: pciephy-glb-intr@193 { reg = <0x193 0x1>; bits = <0 4>; }; + dp_calibration: dp-data@1ac { + reg = <0x1ac 0x10>; + }; }; u3phy2: t-phy@11c40000 { @@ -2355,5 +2358,27 @@ dp_intf1: dp-intf@1c113000 { clock-names = "engine", "pixel", "pll"; status = "disabled"; }; + + edp_tx: edp-tx@1c500000 { + compatible = "mediatek,mt8195-edp-tx"; + reg = <0 0x1c500000 0 0x8000>; + nvmem-cells = <&dp_calibration>; + nvmem-cell-names = "dp_calibration_data"; + power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; + interrupts = ; + max-linkrate-mhz = <8100>; + status = "disabled"; + }; + + dp_tx: dp-tx@1c600000 { + compatible = "mediatek,mt8195-dp-tx"; + reg = <0 0x1c600000 0 0x8000>; + nvmem-cells = <&dp_calibration>; + nvmem-cell-names = "dp_calibration_data"; + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; + interrupts = ; + max-linkrate-mhz = <8100>; + status = "disabled"; + }; }; }; From b1bf55700a247ac30f2afcfdbae9a6fb31342124 Mon Sep 17 00:00:00 2001 From: Bo-Chen Chen Date: Thu, 10 Nov 2022 14:37:15 +0800 Subject: [PATCH 26/35] arm64: dts: mediatek: cherry: Add dp-intf ports Dp-intfs provide the pixel data to edptx and dptx. To support edptx and dptx, we need to add dp-intf0 and dp-intf1 ports. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221110063716.25677-4-rex-bc.chen@mediatek.com Signed-off-by: Matthias Brugger --- .../arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 9b62e161db26..303dc32c64dc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -120,6 +120,24 @@ scp_mem: memory@50000000 { }; }; +&dp_intf0 { + status = "okay"; + + port { + dp_intf0_out: endpoint { + }; + }; +}; + +&dp_intf1 { + status = "okay"; + + port { + dp_intf1_out: endpoint { + }; + }; +}; + &i2c0 { status = "okay"; From 957d4ac7c51a5b142a223433f20b51c1a0afde81 Mon Sep 17 00:00:00 2001 From: Bo-Chen Chen Date: Thu, 10 Nov 2022 14:37:16 +0800 Subject: [PATCH 27/35] arm64: dts: mediatek: cherry: Add edptx and dptx support In cherry projects, we use edptx as the internal display interface and use dptx as the external display interface. To support this, we need to add more properties. - Add pinctrls for edptx and dptx. - Add ports for edptx and dptx. The port connections for the internal and external display: dp-intf0 -> edptx -> panel dp-intf1 -> dptx The edptx endpoint is kept empty for now, as the panel addition will come in a later commit. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221110063716.25677-5-rex-bc.chen@mediatek.com Signed-off-by: Matthias Brugger --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 303dc32c64dc..560103e29017 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -125,6 +125,7 @@ &dp_intf0 { port { dp_intf0_out: endpoint { + remote-endpoint = <&edp_in>; }; }; }; @@ -134,6 +135,59 @@ &dp_intf1 { port { dp_intf1_out: endpoint { + remote-endpoint = <&dptx_in>; + }; + }; +}; + +&edp_tx { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&edptx_pins_default>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + edp_in: endpoint { + remote-endpoint = <&dp_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + edp_out: endpoint { + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dp_tx { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dptx_pin>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dptx_in: endpoint { + remote-endpoint = <&dp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dptx_out: endpoint { + data-lanes = <0 1 2 3>; + }; }; }; }; @@ -497,6 +551,20 @@ pins-ec-ap-int-odl { }; }; + edptx_pins_default: edptx-default-pins { + pins-cmd-dat { + pinmux = ; + bias-pull-up; + }; + }; + + dptx_pin: dptx-default-pins { + pins-cmd-dat { + pinmux = ; + bias-pull-up; + }; + }; + i2c0_pins: i2c0-default-pins { pins-bus { pinmux = , From f89afcfc33b2e83970215a2dbaa30ad41e97b00c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 27 Oct 2022 11:54:59 +0200 Subject: [PATCH 28/35] arm64: dts: mediatek: mt6795: Add topckgen, infra, peri clocks/resets Add nodes for topckgen, infracfg and pericfg, providing various clocks and resets and needed to support basic IPs of this SoC. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221027095504.37432-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 46f0e54be766..aff9a5bf9fcf 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -6,7 +6,9 @@ #include #include +#include #include +#include / { compatible = "mediatek,mt6795"; @@ -192,6 +194,26 @@ soc { compatible = "simple-bus"; ranges; + topckgen: syscon@10000000 { + compatible = "mediatek,mt6795-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt6795-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt6795-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + pio: pinctrl@10005000 { compatible = "mediatek,mt6795-pinctrl"; reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; From 12a36f028af0188d19e449f964f9591c61f4eb0e Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 27 Oct 2022 11:55:00 +0200 Subject: [PATCH 29/35] arm64: dts: mediatek: mt6795: Replace UART dummy clocks with pericfg The UART nodes had a dummy clock for early bringup, as it is expected that these are left on by the bootloader: now that the pericfg clock controller is supported, we can replace them with the real clocks. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221027095504.37432-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index aff9a5bf9fcf..34e1f10f74fd 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -314,7 +314,8 @@ uart0: serial@11002000 { "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -323,7 +324,8 @@ uart1: serial@11003000 { "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = ; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -332,7 +334,8 @@ uart2: serial@11004000 { "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = ; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -341,7 +344,8 @@ uart3: serial@11005000 { "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = ; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; status = "disabled"; }; }; From 09608ccc8a8c92d0d7fabaf8c7699163fc0f16d9 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 27 Oct 2022 11:55:01 +0200 Subject: [PATCH 30/35] arm64: dts: mediatek: mt6795: Add support for APDMA and wire up UART DMAs This SoC has a DMA controller with tx/rx channels for all of the UART controller IPs: add the apdma node and wire up the DMAs on all controllers. When one of the UART controllers is used as a serial console, the DMA will be automatically ignored. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221027095504.37432-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 34e1f10f74fd..ae2eaad99cda 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -316,6 +316,8 @@ uart0: serial@11002000 { interrupts = ; clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -326,9 +328,37 @@ uart1: serial@11003000 { interrupts = ; clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; + apdma: dma-controller@11000380 { + compatible = "mediatek,mt6795-uart-dma", + "mediatek,mt6577-uart-dma"; + reg = <0 0x11000380 0 0x60>, + <0 0x11000400 0 0x60>, + <0 0x11000480 0 0x60>, + <0 0x11000500 0 0x60>, + <0 0x11000580 0 0x60>, + <0 0x11000600 0 0x60>, + <0 0x11000680 0 0x60>, + <0 0x11000700 0 0x60>; + interrupts = , + , + , + , + , + , + , + ; + dma-requests = <8>; + clocks = <&pericfg CLK_PERI_AP_DMA>; + clock-names = "apdma"; + mediatek,dma-33bits; + #dma-cells = <1>; + }; + uart2: serial@11004000 { compatible = "mediatek,mt6795-uart", "mediatek,mt6577-uart"; @@ -336,6 +366,8 @@ uart2: serial@11004000 { interrupts = ; clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -346,6 +378,8 @@ uart3: serial@11005000 { interrupts = ; clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; clock-names = "baud", "bus"; + dmas = <&apdma 6>, <&apdma 7>; + dma-names = "tx", "rx"; status = "disabled"; }; }; From d83f8a42e601b60e3133c6406ed4d16c67b316da Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 27 Oct 2022 11:55:02 +0200 Subject: [PATCH 31/35] arm64: dts: mediatek: mt6795: Add support for eMMC/SD/SDIO controllers Add the mmc nodes to support all of the four controllers, used for eMMC, SD/MicroSD and SDIO storage. All of these controller nodes are left disabled by default, as usage is board dependent. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221027095504.37432-5-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index ae2eaad99cda..bb575837e4ce 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -382,5 +382,46 @@ uart3: serial@11005000 { dma-names = "tx", "rx"; status = "disabled"; }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt6795-mmc"; + reg = <0 0x11230000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_0>, + <&topckgen CLK_TOP_MSDC50_0_H_SEL>, + <&topckgen CLK_TOP_MSDC50_0_SEL>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt6795-mmc"; + reg = <0 0x11240000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_1>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt6795-mmc"; + reg = <0 0x11250000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_2>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc3: mmc@11260000 { + compatible = "mediatek,mt6795-mmc"; + reg = <0 0x11260000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_3>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; }; }; From 434cdafabcbafdd2b6cc65c59ba7a6a7120d491e Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 27 Oct 2022 11:55:03 +0200 Subject: [PATCH 32/35] dt-bindings: arm: mediatek: Add compatible for MT6795 Sony Xperia M5 Add a compatible for the Sony Xperia M5 smartphone. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221027095504.37432-6-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 7642f9350d2c..2275e5d93721 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -58,6 +58,7 @@ properties: - items: - enum: - mediatek,mt6795-evb + - sony,xperia-m5 - const: mediatek,mt6795 - items: - enum: From c9e7d2166a71030bcad4d4814421202537b660c9 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 27 Oct 2022 11:55:04 +0200 Subject: [PATCH 33/35] arm64: dts: mediatek: Add support for MT6795 Sony Xperia M5 smartphone Add a basic support for the Sony Xperia M5 (codename "Holly") smartphone, powered by a MediaTek Helio X10 SoC. This achieves a console boot. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221027095504.37432-7-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt6795-sony-xperia-m5.dts | 88 +++++++++++++++++++ 2 files changed, 89 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 0ec90cb3ef28..813e735c5b96 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-sony-xperia-m5.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts new file mode 100644 index 000000000000..d3415527d389 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Collabora Ltd + * Author: AngeloGioacchino Del Regno + */ + +/dts-v1/; +#include "mt6795.dtsi" + +/ { + model = "Sony Xperia M5"; + compatible = "sony,xperia-m5", "mediatek,mt6795"; + chassis-type = "handset"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + serial0 = &uart0; + serial1 = &uart1; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1e800000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + + /* preloader and bootloader regions cannot be touched */ + preloader-region@44800000 { + reg = <0 0x44800000 0 0x100000>; + no-map; + }; + + bootloader-region@46000000 { + reg = <0 0x46000000 0 0x400000>; + no-map; + }; + }; +}; + +&pio { + uart0_pins: uart0-pins { + pins-rx { + pinmux = ; + bias-pull-up; + input-enable; + }; + pins-tx { + pinmux = ; + output-high; + }; + }; + + uart2_pins: uart2-pins { + pins-rx { + pinmux = ; + bias-pull-up; + input-enable; + }; + pins-tx { + pinmux = ; + }; + }; +}; + +&uart0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; From 99cce13b82a9366cfdd230ba6ddb48ba30d2741f Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 18 Nov 2022 20:01:16 +0100 Subject: [PATCH 34/35] arm64: dts: mt7986: move wed_pcie node Move the wed_pcie node to have node aligned by address. Fixes: 00b9903996b3 ("arm64: dts: mediatek: mt7986: add support for Wireless Ethernet Dispatch") Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221118190126.100895-2-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index ebb5a6a672dd..cf6c490e9033 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -113,6 +113,12 @@ infracfg: infracfg@10001000 { #clock-cells = <1>; }; + wed_pcie: wed-pcie@10003000 { + compatible = "mediatek,mt7986-wed-pcie", + "syscon"; + reg = <0 0x10003000 0 0x10>; + }; + topckgen: topckgen@1001b000 { compatible = "mediatek,mt7986-topckgen", "syscon"; reg = <0 0x1001B000 0 0x1000>; @@ -258,12 +264,6 @@ ethsys: syscon@15000000 { #reset-cells = <1>; }; - wed_pcie: wed-pcie@10003000 { - compatible = "mediatek,mt7986-wed-pcie", - "syscon"; - reg = <0 0x10003000 0 0x10>; - }; - wed0: wed@15010000 { compatible = "mediatek,mt7986-wed", "syscon"; From 885e153ed7c1b0ec8bc25651f0644b3cb65ecaf4 Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Fri, 18 Nov 2022 20:01:21 +0100 Subject: [PATCH 35/35] arm64: dts: mt7986: add spi related device nodes This patch adds spi support for MT7986. Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 ++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++ 3 files changed, 98 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index 1dd54e8a3a90..9b83925893b7 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -59,6 +59,20 @@ switch: switch@0 { }; &pio { + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spic-pins { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + uart1_pins: uart1-pins { mux { function = "uart"; @@ -105,6 +119,27 @@ conf { }; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + cs-gpios = <0>, <0>; + status = "okay"; + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins>; + cs-gpios = <0>, <0>; + status = "okay"; +}; + &switch { ports { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index cf6c490e9033..ed703025a7cc 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -254,6 +254,34 @@ i2c0: i2c@11008000 { status = "disabled"; }; + spi0: spi@1100a000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0_CK>, + <&infracfg CLK_INFRA_SPI0_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + status = "disabled"; + }; + + spi1: spi@1100b000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100b000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPIM_MST_SEL>, + <&infracfg CLK_INFRA_SPI1_CK>, + <&infracfg CLK_INFRA_SPI1_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + status = "disabled"; + }; + ethsys: syscon@15000000 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index 7cfcbb95bc52..243760cd3011 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -100,6 +100,20 @@ fixed-link { }; &pio { + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spic-pins { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + wf_2g_5g_pins: wf-2g-5g-pins { mux { function = "wifi"; @@ -132,6 +146,27 @@ conf { }; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + cs-gpios = <0>, <0>; + status = "okay"; + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins>; + cs-gpios = <0>, <0>; + status = "okay"; +}; + &uart0 { status = "okay"; };