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drm/i915/display: move GLK clock gating init to display

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Move the GLK-specific display clock gating programming into display
intel_display_clock_gating.c, to remove more dependencies from i915 to
display registers.

Now that all remaining Gen9-family callers moved into display, we can
move the shared Gen9 display clock gating helper into display and
remove the old local helper from intel_clock_gating.c.

Additionally, the SKL_DE_COMPRESSED_HASH_MODE programming was
protected by HAS_LLC(), but that's incidental, because in Gen9
platforms, only SKL and KBL, for which this workaround applies, have
LLC().  In order not to use HAS_LLC() in display code, we can simply
remove this check from the generic Gen9 function and move the
SKL_DE_COMPRESSED_HASH_MODE programming to the KBL and SKL specific
functions.  And, intentionally or not, CFL and CML were also using
this workaround, because they also have LLC, even though the comments
were only mentioning SKL and KBL.  In order not to change anything
functionally with this patch, the workaround was also added to
intel_display_cfl_init_clock_gating().

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260428095104.818360-6-luciano.coelho@intel.com
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
Luca Coelho 2026-04-28 12:48:23 +03:00
parent fa00ae490c
commit 8aa0771182
3 changed files with 74 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

72
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
View File

@ -6,11 +6,39 @@
#include <drm/intel/intel_gmd_misc_regs.h>
#include "intel_de.h"
#include "intel_display.h"
#include "intel_display_clock_gating.h"
#include "intel_display_core.h"
#include "intel_display_regs.h"
static void intel_display_gen9_init_clock_gating(struct intel_display *display)
{
/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
/*
* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
* Display WA #0859: skl,bxt,kbl,glk,cfl
*/
intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
}
void intel_display_skl_init_clock_gating(struct intel_display *display)
{
/*
* WaCompressedResourceDisplayNewHashMode:skl,kbl
* Display WA #0390: skl,kbl
*
* Must match Sampler, Pixel Back End, and Media. See
* WaCompressedResourceSamplerPbeMediaNewHashMode.
*/
intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
intel_display_gen9_init_clock_gating(display);
/*
* WaFbcTurnOffFbcWatermark:skl
* Display WA #0562: skl
@ -20,6 +48,17 @@ void intel_display_skl_init_clock_gating(struct intel_display *display)
void intel_display_kbl_init_clock_gating(struct intel_display *display)
{
/*
* WaCompressedResourceDisplayNewHashMode:skl,kbl
* Display WA #0390: skl,kbl
*
* Must match Sampler, Pixel Back End, and Media. See
* WaCompressedResourceSamplerPbeMediaNewHashMode.
*/
intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
intel_display_gen9_init_clock_gating(display);
/*
* WaFbcTurnOffFbcWatermark:kbl
* Display WA #0562: kbl
@ -29,6 +68,23 @@ void intel_display_kbl_init_clock_gating(struct intel_display *display)
void intel_display_cfl_init_clock_gating(struct intel_display *display)
{
/*
* WaCompressedResourceDisplayNewHashMode:skl,kbl (and cfl, cml)
* Display WA #0390: skl,kbl (and cfl, cml)
*
* Must match Sampler, Pixel Back End, and Media. See
* WaCompressedResourceSamplerPbeMediaNewHashMode.
*
* NOTE: this is the same workaround used for skl and kbl,
* because the original implementation was checking HAS_LLC(),
* which cfl/cml have, even though the comment for the
* workaround doesn't mention it.
*
*/
intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
intel_display_gen9_init_clock_gating(display);
/*
* WaFbcTurnOffFbcWatermark:cfl
* Display WA #0562: cfl
@ -38,6 +94,8 @@ void intel_display_cfl_init_clock_gating(struct intel_display *display)
void intel_display_bxt_init_clock_gating(struct intel_display *display)
{
intel_display_gen9_init_clock_gating(display);
/*
* Wa: Backlight PWM may stop in the asserted state, causing backlight
* to stay fully on.
@ -60,3 +118,17 @@ void intel_display_bxt_init_clock_gating(struct intel_display *display)
*/
intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
}
void intel_display_glk_init_clock_gating(struct intel_display *display)
{
intel_display_gen9_init_clock_gating(display);
/*
* WaDisablePWMClockGating:glk
* Backlight PWM may stop in the asserted state, causing backlight
* to stay fully on.
*/
intel_de_write(display, GEN9_CLKGATE_DIS_0,
intel_de_read(display, GEN9_CLKGATE_DIS_0) |
PWM1_GATING_DIS | PWM2_GATING_DIS);
}

1
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
View File

@ -12,5 +12,6 @@ void intel_display_skl_init_clock_gating(struct intel_display *display);
void intel_display_kbl_init_clock_gating(struct intel_display *display);
void intel_display_cfl_init_clock_gating(struct intel_display *display);
void intel_display_bxt_init_clock_gating(struct intel_display *display);
void intel_display_glk_init_clock_gating(struct intel_display *display);
#endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */

44
drivers/gpu/drm/i915/intel_clock_gating.c
View File

@ -49,36 +49,8 @@ struct drm_i915_clock_gating_funcs {
void (*init_clock_gating)(struct drm_i915_private *i915);
};
static void gen9_init_clock_gating(struct drm_i915_private *i915)
{
if (HAS_LLC(i915)) {
/*
* WaCompressedResourceDisplayNewHashMode:skl,kbl
* Display WA #0390: skl,kbl
*
* Must match Sampler, Pixel Back End, and Media. See
* WaCompressedResourceSamplerPbeMediaNewHashMode.
*/
intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
}
/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
/*
* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
* Display WA #0859: skl,bxt,kbl,glk,cfl
*/
intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
}
static void bxt_init_clock_gating(struct drm_i915_private *i915)
{
gen9_init_clock_gating(i915);
/* WaDisableSDEUnitClockGating:bxt */
intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
@ -93,16 +65,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *i915)
static void glk_init_clock_gating(struct drm_i915_private *i915)
{
gen9_init_clock_gating(i915);
/*
* WaDisablePWMClockGating:glk
* Backlight PWM may stop in the asserted state, causing backlight
* to stay fully on.
*/
intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
PWM1_GATING_DIS | PWM2_GATING_DIS);
intel_display_glk_init_clock_gating(i915->display);
}
static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
@ -282,7 +245,6 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915)
static void cfl_init_clock_gating(struct drm_i915_private *i915)
{
intel_pch_init_clock_gating(i915->display);
gen9_init_clock_gating(i915);
/* WAC6entrylatency:cfl */
intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
@ -292,8 +254,6 @@ static void cfl_init_clock_gating(struct drm_i915_private *i915)
static void kbl_init_clock_gating(struct drm_i915_private *i915)
{
gen9_init_clock_gating(i915);
/* WAC6entrylatency:kbl */
intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
@ -312,8 +272,6 @@ static void kbl_init_clock_gating(struct drm_i915_private *i915)
static void skl_init_clock_gating(struct drm_i915_private *i915)
{
gen9_init_clock_gating(i915);
/* WaDisableDopClockGating:skl */
intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,
GEN7_DOP_CLOCK_GATE_ENABLE, 0);