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drm/i915/display: move BXT clock gating init to display

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Move the BXT-specific display clock gating programming into display
intel_display_clock_gating.c, to remove more dependencies from i915.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260428095104.818360-5-luciano.coelho@intel.com
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
Luca Coelho 2026-04-28 12:48:22 +03:00
parent 1f842b5e70
commit fa00ae490c
3 changed files with 27 additions and 21 deletions
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25
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
View File

@ -35,3 +35,28 @@ void intel_display_cfl_init_clock_gating(struct intel_display *display)
*/
intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
}
void intel_display_bxt_init_clock_gating(struct intel_display *display)
{
/*
* Wa: Backlight PWM may stop in the asserted state, causing backlight
* to stay fully on.
*/
intel_de_write(display, GEN9_CLKGATE_DIS_0,
intel_de_read(display, GEN9_CLKGATE_DIS_0) |
PWM1_GATING_DIS | PWM2_GATING_DIS);
/*
* Lower the display internal timeout.
* This is needed to avoid any hard hangs when DSI port PLL
* is off and a MMIO access is attempted by any privilege
* application, using batch buffers or any other means.
*/
intel_de_write(display, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
/*
* WaFbcTurnOffFbcWatermark:bxt
* Display WA #0562: bxt
*/
intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
}

1
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
View File

@ -11,5 +11,6 @@ struct intel_display;
void intel_display_skl_init_clock_gating(struct intel_display *display);
void intel_display_kbl_init_clock_gating(struct intel_display *display);
void intel_display_cfl_init_clock_gating(struct intel_display *display);
void intel_display_bxt_init_clock_gating(struct intel_display *display);
#endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */

22
drivers/gpu/drm/i915/intel_clock_gating.c
View File

@ -88,27 +88,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *i915)
*/
intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
/*
* Wa: Backlight PWM may stop in the asserted state, causing backlight
* to stay fully on.
*/
intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
PWM1_GATING_DIS | PWM2_GATING_DIS);
/*
* Lower the display internal timeout.
* This is needed to avoid any hard hangs when DSI port PLL
* is off and a MMIO access is attempted by any privilege
* application, using batch buffers or any other means.
*/
intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
/*
* WaFbcTurnOffFbcWatermark:bxt
* Display WA #0562: bxt
*/
intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
intel_display_bxt_init_clock_gating(i915->display);
}
static void glk_init_clock_gating(struct drm_i915_private *i915)