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drm/i915/gmbus: s/gmbus_pins_skl/gmbus_pins_spt/
The GMBUS pin pair <-> GPIO mapping is purely a property of the PCH (on the platforms where GMBUS lives in the PCH). So rename gmbus_pins_skl[] to gmbus_pins_spt[] and apply it based on the presence of the correct PCH type. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260623125111.6632-5-ville.syrjala@linux.intel.com Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
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@ -98,7 +98,7 @@ static const struct gmbus_pin gmbus_pins_lpt_lp[] = {
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[GMBUS_PIN_DPB] = { "dpb", GPIO_4 },
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};
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static const struct gmbus_pin gmbus_pins_skl[] = {
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static const struct gmbus_pin gmbus_pins_spt[] = {
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[GMBUS_PIN_DPC] = { "dpc", GPIO_3 },
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[GMBUS_PIN_DPB] = { "dpb", GPIO_4 },
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[GMBUS_PIN_DPD] = { "dpd", GPIO_5 },
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@ -180,9 +180,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display,
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} else if (display->platform.geminilake || display->platform.broxton) {
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pins = gmbus_pins_bxt;
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size = ARRAY_SIZE(gmbus_pins_bxt);
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} else if (DISPLAY_VER(display) == 9) {
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pins = gmbus_pins_skl;
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size = ARRAY_SIZE(gmbus_pins_skl);
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} else if (HAS_PCH_SPT(display)) {
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pins = gmbus_pins_spt;
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size = ARRAY_SIZE(gmbus_pins_spt);
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} else if (HAS_PCH_LPT_LP(display)) {
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pins = gmbus_pins_lpt_lp;
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size = ARRAY_SIZE(gmbus_pins_lpt_lp);
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