From 85b4ba03d54933056451c9c873cbe16173aeba27 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 23 Jun 2026 15:51:09 +0300 Subject: [PATCH] drm/i915/gmbus: s/gmbus_pins_skl/gmbus_pins_spt/ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The GMBUS pin pair <-> GPIO mapping is purely a property of the PCH (on the platforms where GMBUS lives in the PCH). So rename gmbus_pins_skl[] to gmbus_pins_spt[] and apply it based on the presence of the correct PCH type. Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260623125111.6632-5-ville.syrjala@linux.intel.com Reviewed-by: Michał Grzelak --- drivers/gpu/drm/i915/display/intel_gmbus.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index f69b8841c5dd..dec0f66f756f 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -98,7 +98,7 @@ static const struct gmbus_pin gmbus_pins_lpt_lp[] = { [GMBUS_PIN_DPB] = { "dpb", GPIO_4 }, }; -static const struct gmbus_pin gmbus_pins_skl[] = { +static const struct gmbus_pin gmbus_pins_spt[] = { [GMBUS_PIN_DPC] = { "dpc", GPIO_3 }, [GMBUS_PIN_DPB] = { "dpb", GPIO_4 }, [GMBUS_PIN_DPD] = { "dpd", GPIO_5 }, @@ -180,9 +180,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display, } else if (display->platform.geminilake || display->platform.broxton) { pins = gmbus_pins_bxt; size = ARRAY_SIZE(gmbus_pins_bxt); - } else if (DISPLAY_VER(display) == 9) { - pins = gmbus_pins_skl; - size = ARRAY_SIZE(gmbus_pins_skl); + } else if (HAS_PCH_SPT(display)) { + pins = gmbus_pins_spt; + size = ARRAY_SIZE(gmbus_pins_spt); } else if (HAS_PCH_LPT_LP(display)) { pins = gmbus_pins_lpt_lp; size = ARRAY_SIZE(gmbus_pins_lpt_lp);