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arm64: dts: imx8-ss-audio: Fix LPCG clock indices for ASRC0

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The LPCG clock indices for ASRC0 and AUD_PLL_DIV0 are swapped. The ASRC0
LPCG provides only IMX_LPCG_CLK_4, so update the ASRC0 clock consumer to
use IMX_LPCG_CLK_4 instead of the non-existent IMX_LPCG_CLK_0.

Likewise, the AUD_PLL_DIV0 LPCG provides only IMX_LPCG_CLK_0, so update its
clock consumer to use IMX_LPCG_CLK_0 instead of the non-existent
IMX_LPCG_CLK_4.

Fixes: 5125617c7a ("arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif0 and sai[4,5]")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Frank Li 2026-07-09 16:29:46 -04:00
parent 617bcacbf0
commit 8563591f76
1 changed files with 4 additions and 4 deletions
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8
arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
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@ -124,10 +124,10 @@ asrc0: asrc@59000000 {
compatible = "fsl,imx8qm-asrc";
reg = <0x59000000 0x10000>;
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>,
<&asrc0_lpcg IMX_LPCG_CLK_0>,
<&aud_pll_div0_lpcg IMX_LPCG_CLK_4>,
<&aud_pll_div1_lpcg IMX_LPCG_CLK_4>,
clocks = <&asrc0_lpcg IMX_LPCG_CLK_4>,
<&asrc0_lpcg IMX_LPCG_CLK_4>,
<&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
<&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
<&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
<&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
<&clk_dummy>,