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arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif0 and sai[4,5]
Add asrc[0,1], esai0, spdif0, sai[4,5] and related lpcg node for imx8 audio subsystem. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Frank Li
Shawn Guo
parent
cb8d3006d5
commit
5125617c7a
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@ -6,6 +6,7 @@
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#include <dt-bindings/clock/imx8-clock.h>
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/dma/fsl-edma.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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audio_ipg_clk: clock-audio-ipg {
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@ -119,6 +120,89 @@ audio_subsys: bus@59000000 {
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#size-cells = <1>;
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ranges = <0x59000000 0x0 0x59000000 0x1000000>;
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asrc0: asrc@59000000 {
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compatible = "fsl,imx8qm-asrc";
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reg = <0x59000000 0x10000>;
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interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>,
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<&asrc0_lpcg IMX_LPCG_CLK_0>,
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<&aud_pll_div0_lpcg IMX_LPCG_CLK_4>,
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<&aud_pll_div1_lpcg IMX_LPCG_CLK_4>,
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<&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
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<&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>;
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clock-names = "mem", "ipg",
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"asrck_0", "asrck_1", "asrck_2", "asrck_3",
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"asrck_4", "asrck_5", "asrck_6", "asrck_7",
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"asrck_8", "asrck_9", "asrck_a", "asrck_b",
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"asrck_c", "asrck_d", "asrck_e", "asrck_f",
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"spba";
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dmas = <&edma0 0 0 0>,
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<&edma0 1 0 0>,
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<&edma0 2 0 0>,
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<&edma0 3 0 FSL_EDMA_RX>,
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<&edma0 4 0 FSL_EDMA_RX>,
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<&edma0 5 0 FSL_EDMA_RX>;
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/* tx* is output channel of asrc, it is rx channel for eDMA */
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dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
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fsl,asrc-rate = <8000>;
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fsl,asrc-width = <16>;
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fsl,asrc-clk-map = <0>;
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power-domains = <&pd IMX_SC_R_ASRC_0>;
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status = "disabled";
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};
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esai0: esai@59010000 {
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compatible = "fsl,imx8qm-esai";
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reg = <0x59010000 0x10000>;
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interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&esai0_lpcg IMX_LPCG_CLK_4>,
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<&esai0_lpcg IMX_LPCG_CLK_0>,
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<&esai0_lpcg IMX_LPCG_CLK_4>,
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<&clk_dummy>;
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clock-names = "core", "extal", "fsys", "spba";
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dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>;
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dma-names = "rx", "tx";
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power-domains = <&pd IMX_SC_R_ESAI_0>;
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status = "disabled";
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};
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spdif0: spdif@59020000 {
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compatible = "fsl,imx8qm-spdif";
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reg = <0x59020000 0x10000>;
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interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
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<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
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clocks = <&spdif0_lpcg IMX_LPCG_CLK_4>, /* core */
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<&clk_dummy>, /* rxtx0 */
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<&spdif0_lpcg IMX_LPCG_CLK_0>, /* rxtx1 */
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<&clk_dummy>, /* rxtx2 */
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<&clk_dummy>, /* rxtx3 */
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<&clk_dummy>, /* rxtx4 */
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<&audio_ipg_clk>, /* rxtx5 */
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<&clk_dummy>, /* rxtx6 */
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<&clk_dummy>, /* rxtx7 */
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<&clk_dummy>; /* spba */
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clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4",
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"rxtx5", "rxtx6", "rxtx7", "spba";
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dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>,
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<&edma0 9 0 FSL_EDMA_MULTI_FIFO>;
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dma-names = "rx", "tx";
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power-domains = <&pd IMX_SC_R_SPDIF_0>;
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status = "disabled";
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};
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sai0: sai@59040000 {
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compatible = "fsl,imx8qm-sai";
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reg = <0x59040000 0x10000>;
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@ -239,6 +323,40 @@ edma0: dma-controller@591f0000 {
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<&pd IMX_SC_R_DMA_0_CH23>;
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};
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asrc0_lpcg: clock-controller@59400000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x59400000 0x10000>;
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#clock-cells = <1>;
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clocks = <&audio_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "asrc0_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_ASRC_0>;
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};
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esai0_lpcg: clock-controller@59410000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x59410000 0x10000>;
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#clock-cells = <1>;
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clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
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<&audio_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "esai0_lpcg_extal_clk",
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"esai0_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_ESAI_0>;
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};
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spdif0_lpcg: clock-controller@59420000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x59420000 0x10000>;
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#clock-cells = <1>;
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clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>,
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<&audio_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "spdif0_lpcg_tx_clk",
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"spdif0_lpcg_gclkw";
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power-domains = <&pd IMX_SC_R_SPDIF_0>;
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};
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sai0_lpcg: clock-controller@59440000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x59440000 0x10000>;
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@ -333,6 +451,101 @@ dsp: dsp@596e8000 {
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status = "disabled";
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};
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asrc1: asrc@59800000 {
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compatible = "fsl,imx8qm-asrc";
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reg = <0x59800000 0x10000>;
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interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&asrc1_lpcg IMX_LPCG_CLK_4>,
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<&asrc1_lpcg IMX_LPCG_CLK_4>,
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<&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
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<&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
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<&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
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<&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>,
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<&clk_dummy>;
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clock-names = "mem", "ipg",
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"asrck_0", "asrck_1", "asrck_2", "asrck_3",
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"asrck_4", "asrck_5", "asrck_6", "asrck_7",
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"asrck_8", "asrck_9", "asrck_a", "asrck_b",
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"asrck_c", "asrck_d", "asrck_e", "asrck_f",
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"spba";
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dmas = <&edma1 0 0 0>,
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<&edma1 1 0 0>,
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<&edma1 2 0 0>,
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<&edma1 3 0 FSL_EDMA_RX>,
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<&edma1 4 0 FSL_EDMA_RX>,
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<&edma1 5 0 FSL_EDMA_RX>;
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/* tx* is output channel of asrc, it is rx channel for eDMA */
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dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
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fsl,asrc-rate = <8000>;
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fsl,asrc-width = <16>;
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fsl,asrc-clk-map = <1>;
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power-domains = <&pd IMX_SC_R_ASRC_1>;
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status = "disabled";
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};
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sai4: sai@59820000 {
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compatible = "fsl,imx8qm-sai";
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reg = <0x59820000 0x10000>;
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interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sai4_lpcg IMX_LPCG_CLK_4>,
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<&clk_dummy>,
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<&sai4_lpcg IMX_LPCG_CLK_0>,
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<&clk_dummy>,
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<&clk_dummy>;
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clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
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dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>;
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dma-names = "rx", "tx";
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power-domains = <&pd IMX_SC_R_SAI_4>;
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status = "disabled";
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};
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sai5: sai@59830000 {
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compatible = "fsl,imx8qm-sai";
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reg = <0x59830000 0x10000>;
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interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sai5_lpcg IMX_LPCG_CLK_4>,
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<&clk_dummy>,
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<&sai5_lpcg IMX_LPCG_CLK_0>,
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<&clk_dummy>,
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<&clk_dummy>;
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clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
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dmas = <&edma1 10 0 0>;
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dma-names = "tx";
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power-domains = <&pd IMX_SC_R_SAI_5>;
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status = "disabled";
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};
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amix: amix@59840000 {
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compatible = "fsl,imx8qm-audmix";
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reg = <0x59840000 0x10000>;
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clocks = <&amix_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg";
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power-domains = <&pd IMX_SC_R_AMIX>;
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dais = <&sai4>, <&sai5>;
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status = "disabled";
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};
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mqs: mqs@59850000 {
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compatible = "fsl,imx8qm-mqs";
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reg = <0x59850000 0x10000>;
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clocks = <&mqs0_lpcg IMX_LPCG_CLK_4>, <&mqs0_lpcg IMX_LPCG_CLK_0>;
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clock-names = "mclk", "core";
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power-domains = <&pd IMX_SC_R_MQS_0>;
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status = "disabled";
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};
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edma1: dma-controller@599f0000 {
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compatible = "fsl,imx8qm-edma";
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reg = <0x599f0000 0xc0000>;
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@ -481,4 +694,60 @@ acm: acm@59e00000 {
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"sai3_rx_bclk",
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"sai4_rx_bclk";
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};
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asrc1_lpcg: clock-controller@59c00000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x59c00000 0x10000>;
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#clock-cells = <1>;
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clocks = <&audio_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "asrc1_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_ASRC_1>;
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};
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sai4_lpcg: clock-controller@59c20000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x59c20000 0x10000>;
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#clock-cells = <1>;
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clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
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<&audio_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "sai4_lpcg_mclk",
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"sai4_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_SAI_4>;
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};
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sai5_lpcg: clock-controller@59c30000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x59c30000 0x10000>;
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#clock-cells = <1>;
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clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
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<&audio_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "sai5_lpcg_mclk",
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"sai5_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_SAI_5>;
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};
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amix_lpcg: clock-controller@59c40000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x59c40000 0x10000>;
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#clock-cells = <1>;
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clocks = <&audio_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "amix_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_AMIX>;
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};
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mqs0_lpcg: clock-controller@59c50000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x59c50000 0x10000>;
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#clock-cells = <1>;
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clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>,
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<&audio_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "mqs0_lpcg_mclk",
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"mqs0_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MQS_0>;
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};
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};
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