mirror of
https://github.com/torvalds/linux.git
synced 2026-09-24 06:24:02 +02:00
Merge branch 'k230-basic' into riscv-dt-for-next
Add basic support for the k230 SoC, which has been sitting in linux-next for a long time waiting for the clock driver to reach an acceptable state. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
commit
82ab962ef6
59
Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml
Normal file
59
Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/canaan,k230-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Canaan Kendryte K230 Clock
|
||||
|
||||
maintainers:
|
||||
- Xukai Wang <kingxukai@zohomail.com>
|
||||
|
||||
description:
|
||||
The Canaan K230 clock controller generates various clocks for SoC
|
||||
peripherals. See include/dt-bindings/clock/canaan,k230-clk.h for
|
||||
valid clock IDs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: canaan,k230-clk
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: PLL control registers
|
||||
- description: Sysclk control registers
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Main external reference clock
|
||||
- description:
|
||||
External clock which used as the pulse input
|
||||
for the timer to provide timing signals.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: osc24m
|
||||
- const: timer-pulse-in
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@91102000 {
|
||||
compatible = "canaan,k230-clk";
|
||||
reg = <0x91102000 0x40>,
|
||||
<0x91100000 0x108>;
|
||||
clocks = <&osc24m>, <&timerx_pulse_in>;
|
||||
clock-names = "osc24m", "timer-pulse-in";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -71,6 +71,7 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- allwinner,sun20i-d1-plic
|
||||
- canaan,k230-plic
|
||||
- sophgo,cv1800b-plic
|
||||
- sophgo,cv1812h-plic
|
||||
- sophgo,sg2002-plic
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ maintainers:
|
|||
- Damien Le Moal <dlemoal@kernel.org>
|
||||
|
||||
description:
|
||||
Canaan Kendryte K210 SoC-based boards
|
||||
Canaan Kendryte SoC-based boards
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
|
|
@ -42,6 +42,12 @@ properties:
|
|||
- items:
|
||||
- const: canaan,kendryte-k210
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- canaan,canmv-k230
|
||||
- canaan,k230-usip-lp3-evb
|
||||
- const: canaan,kendryte-k230
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- allwinner,sun20i-d1-clint
|
||||
- canaan,k230-clint
|
||||
- sophgo,cv1800b-clint
|
||||
- sophgo,cv1812h-clint
|
||||
- sophgo,sg2002-clint
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb
|
||||
dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb
|
||||
dtb-$(CONFIG_ARCH_CANAAN) += k230-canmv.dtb
|
||||
dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb
|
||||
dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb
|
||||
dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb
|
||||
|
|
|
|||
343
arch/riscv/boot/dts/canaan/k230-canmv.dts
Normal file
343
arch/riscv/boot/dts/canaan/k230-canmv.dts
Normal file
|
|
@ -0,0 +1,343 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
|
||||
*/
|
||||
|
||||
#include "k230.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Canaan CanMV-K230";
|
||||
compatible = "canaan,canmv-k230", "canaan,kendryte-k230";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
ddr: memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x20000000>;
|
||||
};
|
||||
|
||||
timerx_pulse_in: clock-50000000 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
jtag_pins: jtag-pins {
|
||||
jtag-tck-cfg {
|
||||
pinmux = <K230_PINMUX(2, 1)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <4>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
input-enable;
|
||||
bias-pull-down;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
jtag-tdi-cfg {
|
||||
pinmux = <K230_PINMUX(3, 1)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <4>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
input-enable;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
jtag-tdo-cfg {
|
||||
pinmux = <K230_PINMUX(4, 1)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <4>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
jtag-tms-cfg {
|
||||
pinmux = <K230_PINMUX(5, 1)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <4>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
uart2-pins-cfg {
|
||||
pinmux = <K230_PINMUX(5, 3)>, /* uart2 txd */
|
||||
<K230_PINMUX(6, 3)>; /* uart2 rxd */
|
||||
slew-rate = <0>;
|
||||
drive-strength = <4>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
input-enable;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pwm2_pins: pwm2-pins {
|
||||
pwm2-pin-cfg {
|
||||
pinmux = <K230_PINMUX(7, 1)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
input-enable;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3_pins: pwm3-pins {
|
||||
pwm3-pin-cfg {
|
||||
pinmux = <K230_PINMUX(8, 1)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
input-enable;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
pwm4_pins: pwm4-pins {
|
||||
pwm4-pin-cfg {
|
||||
pinmux = <K230_PINMUX(9, 1)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
input-enable;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
iis_pins: iis-pins {
|
||||
iis-clk-cfg {
|
||||
pinmux = <K230_PINMUX(32, 2)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <4>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
iis-ws-cfg {
|
||||
pinmux = <K230_PINMUX(33, 2)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <4>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
iis-din0-cfg {
|
||||
pinmux = <K230_PINMUX(34, 2)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <4>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
input-enable;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
iis-dout0-cfg {
|
||||
pinmux = <K230_PINMUX(35, 2)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <4>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_pins: uart4-pins {
|
||||
uart4-txd-cfg {
|
||||
pinmux = <K230_PINMUX(36, 4)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
uart4-rxd-cfg {
|
||||
pinmux = <K230_PINMUX(37, 4)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
input-enable;
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins: uart0-pins {
|
||||
uart0-txd-cfg {
|
||||
pinmux = <K230_PINMUX(38, 1)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
uart0-rxd-cfg {
|
||||
pinmux = <K230_PINMUX(39, 1)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
input-enable;
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
iic1_pins: iic1-pins {
|
||||
iic1-pins-cfg {
|
||||
pinmux = <K230_PINMUX(40, 2)>, /* iic1 scl */
|
||||
<K230_PINMUX(41, 2)>; /* iic1 sda */
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
input-enable;
|
||||
output-enable;
|
||||
bias-pull-up;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
iic3_pins: iic3-pins {
|
||||
iic3-pins-cfg {
|
||||
pinmux = <K230_PINMUX(44, 2)>, /* iic3 scl */
|
||||
<K230_PINMUX(45, 2)>; /* iic3 sda */
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
input-enable;
|
||||
output-enable;
|
||||
bias-pull-up;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
iic4_pins: iic4-pins {
|
||||
iic4-pins-cfg {
|
||||
pinmux = <K230_PINMUX(46, 3)>, /* iic4 scl */
|
||||
<K230_PINMUX(47, 3)>; /* iic4 sda */
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
input-enable;
|
||||
output-enable;
|
||||
bias-pull-up;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
iic0_pins: iic0-pins {
|
||||
iic0-pins-cfg {
|
||||
pinmux = <K230_PINMUX(48, 3)>, /* iic0 scl */
|
||||
<K230_PINMUX(49, 3)>; /* iic0 sda */
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_1V8>;
|
||||
input-enable;
|
||||
output-enable;
|
||||
bias-pull-up;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
uart3_pins: uart3-pins {
|
||||
uart3-txd-cfg {
|
||||
pinmux = <K230_PINMUX(50, 1)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_3V3>;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
uart3-rxd-cfg {
|
||||
pinmux = <K230_PINMUX(51, 1)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_3V3>;
|
||||
input-enable;
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
key_pins: key-pins {
|
||||
key-pins-cfg {
|
||||
pinmux = <K230_PINMUX(52, 0)>, /* key0 */
|
||||
<K230_PINMUX(53, 0)>; /* key1 */
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_3V3>;
|
||||
input-enable;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
mmc1_pins: mmc1-pins {
|
||||
mmc1-cmd-cfg {
|
||||
pinmux = <K230_PINMUX(54, 2)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_3V3>;
|
||||
input-enable;
|
||||
output-enable;
|
||||
bias-pull-up;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
mmc1-clk-cfg {
|
||||
pinmux = <K230_PINMUX(55, 2)>;
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_3V3>;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
mmc1-data-cfg {
|
||||
pinmux = <K230_PINMUX(56, 2)>, /* mmc1 data0 */
|
||||
<K230_PINMUX(57, 2)>, /* mmc1 data1 */
|
||||
<K230_PINMUX(58, 2)>, /* mmc1 data2 */
|
||||
<K230_PINMUX(59, 2)>; /* mmc1 data3 */
|
||||
slew-rate = <0>;
|
||||
drive-strength = <7>;
|
||||
power-source = <K230_MSC_3V3>;
|
||||
input-enable;
|
||||
output-enable;
|
||||
bias-pull-up;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sysclk {
|
||||
clocks = <&osc24m>, <&timerx_pulse_in>;
|
||||
clock-names = "osc24m", "timer-pulse-in";
|
||||
};
|
||||
39
arch/riscv/boot/dts/canaan/k230-evb.dts
Normal file
39
arch/riscv/boot/dts/canaan/k230-evb.dts
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
|
||||
*/
|
||||
|
||||
#include "k230.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Kendryte K230 EVB";
|
||||
compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-k230";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
ddr: memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x20000000>;
|
||||
};
|
||||
|
||||
timerx_pulse_in: clock-50000000 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sysclk {
|
||||
clocks = <&osc24m>, <&timerx_pulse_in>;
|
||||
clock-names = "osc24m", "timer-pulse-in";
|
||||
};
|
||||
18
arch/riscv/boot/dts/canaan/k230-pinctrl.h
Normal file
18
arch/riscv/boot/dts/canaan/k230-pinctrl.h
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
|
||||
/*
|
||||
* Copyright (C) 2024 Canaan Bright Sight Co. Ltd
|
||||
* Copyright (C) 2024 Ze Huang <18771902331@163.com>
|
||||
*/
|
||||
|
||||
#ifndef _K230_PINCTRL_H
|
||||
#define _K230_PINCTRL_H
|
||||
|
||||
#define K230_MSC_3V3 0
|
||||
#define K230_MSC_1V8 1
|
||||
|
||||
#define BANK_VOLTAGE_DEFAULT K230_MSC_1V8
|
||||
#define BANK_VOLTAGE_IO50_IO61 K230_MSC_3V3
|
||||
|
||||
#define K230_PINMUX(pin, mode) (((pin) << 8) | (mode))
|
||||
|
||||
#endif /* _K230_PINCTRL_H */
|
||||
167
arch/riscv/boot/dts/canaan/k230.dtsi
Normal file
167
arch/riscv/boot/dts/canaan/k230.dtsi
Normal file
|
|
@ -0,0 +1,167 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/canaan,k230-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/reset/canaan,k230-rst.h>
|
||||
#include "k230-pinctrl.h"
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "canaan,kendryte-k230";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
timebase-frequency = <27000000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "thead,c908", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_zihpm_zfh_zba_zbb_zbc_zbs_zvfh_svpbmt";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
|
||||
"zicbop", "zicboz", "zicntr", "zicsr", "zifencei",
|
||||
"zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zvfh",
|
||||
"svpbmt";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <128>;
|
||||
i-cache-size = <32768>;
|
||||
next-level-cache = <&l2_cache>;
|
||||
mmu-type = "riscv,sv39";
|
||||
|
||||
cpu0_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
l2_cache: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-block-size = <64>;
|
||||
cache-level = <2>;
|
||||
cache-size = <262144>;
|
||||
cache-sets = <256>;
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
|
||||
osc24m: clock-24000000 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "osc24m";
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&plic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
dma-noncoherent;
|
||||
ranges;
|
||||
|
||||
plic: interrupt-controller@f00000000 {
|
||||
compatible = "canaan,k230-plic", "thead,c900-plic";
|
||||
reg = <0xf 0x00000000 0x0 0x04000000>;
|
||||
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
riscv,ndev = <208>;
|
||||
};
|
||||
|
||||
clint: timer@f04000000 {
|
||||
compatible = "canaan,k230-clint", "thead,c900-clint";
|
||||
reg = <0xf 0x04000000 0x0 0x00010000>;
|
||||
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
|
||||
};
|
||||
|
||||
rst: reset-controller@91101000 {
|
||||
compatible = "canaan,k230-rst";
|
||||
reg = <0x0 0x91101000 0x0 0x1000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@91105000 {
|
||||
compatible = "canaan,k230-pinctrl";
|
||||
reg = <0x0 0x91105000 0x0 0x100>;
|
||||
};
|
||||
|
||||
sysclk: clock-controller@91102000 {
|
||||
compatible = "canaan,k230-clk";
|
||||
reg = <0x0 0x91102000 0x0 0x40>,
|
||||
<0x0 0x91100000 0x0 0x108>;
|
||||
clocks = <&osc24m>;
|
||||
clock-names = "osc24m";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: serial@91400000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x91400000 0x0 0x1000>;
|
||||
clocks = <&sysclk K230_LS_UART0_RATE>;
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
resets = <&rst RST_UART0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@91401000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x91401000 0x0 0x1000>;
|
||||
clocks = <&sysclk K230_LS_UART1_RATE>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
resets = <&rst RST_UART1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@91402000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x91402000 0x0 0x1000>;
|
||||
clocks = <&sysclk K230_LS_UART2_RATE>;
|
||||
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
resets = <&rst RST_UART2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@91403000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x91403000 0x0 0x1000>;
|
||||
clocks = <&sysclk K230_LS_UART3_RATE>;
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
resets = <&rst RST_UART3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@91404000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x91404000 0x0 0x1000>;
|
||||
clocks = <&sysclk K230_LS_UART4_RATE>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
resets = <&rst RST_UART4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
220
include/dt-bindings/clock/canaan,k230-clk.h
Normal file
220
include/dt-bindings/clock/canaan,k230-clk.h
Normal file
|
|
@ -0,0 +1,220 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Kendryte Canaan K230 Clock Drivers
|
||||
*
|
||||
* Author: Xukai Wang <kingxukai@zohomail.com>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CANAAN_K230_CLOCK_H__
|
||||
#define __DT_BINDINGS_CANAAN_K230_CLOCK_H__
|
||||
|
||||
#define K230_CPU0_SRC_GATE 0
|
||||
#define K230_CPU0_PLIC_GATE 1
|
||||
#define K230_CPU0_NOC_DDRCP4_GATE 2
|
||||
#define K230_CPU0_APB_GATE 3
|
||||
#define K230_CPU0_SRC_RATE 4
|
||||
#define K230_CPU0_AXI_RATE 5
|
||||
#define K230_CPU0_PLIC_RATE 6
|
||||
#define K230_CPU0_APB_RATE 7
|
||||
#define K230_HS_SSI0_MUX 8
|
||||
#define K230_HS_USB_REF_MUX 9
|
||||
#define K230_HS_HCLK_HIGH_GATE 10
|
||||
#define K230_HS_HCLK_GATE 11
|
||||
#define K230_HS_SD0_AHB_GATE 12
|
||||
#define K230_HS_SD1_AHB_GATE 13
|
||||
#define K230_HS_SSI1_AHB_GATE 14
|
||||
#define K230_HS_SSI2_AHB_GATE 15
|
||||
#define K230_HS_USB0_AHB_GATE 16
|
||||
#define K230_HS_USB1_AHB_GATE 17
|
||||
#define K230_HS_SSI0_AXI_GATE 18
|
||||
#define K230_HS_SSI1_GATE 19
|
||||
#define K230_HS_SSI2_GATE 20
|
||||
#define K230_HS_QSPI_AXI_SRC_GATE 21
|
||||
#define K230_HS_SSI1_AXI_GATE 22
|
||||
#define K230_HS_SSI2_AXI_GATE 23
|
||||
#define K230_HS_SD_CARD_SRC_GATE 24
|
||||
#define K230_HS_SD0_CARD_GATE 25
|
||||
#define K230_HS_SD1_CARD_GATE 26
|
||||
#define K230_HS_SD_AXI_SRC_GATE 27
|
||||
#define K230_HS_SD0_AXI_GATE 28
|
||||
#define K230_HS_SD1_AXI_GATE 29
|
||||
#define K230_HS_SD0_BASE_GATE 30
|
||||
#define K230_HS_SD1_BASE_GATE 31
|
||||
#define K230_HS_SSI0_GATE 32
|
||||
#define K230_HS_SD_TIMER_SRC_GATE 33
|
||||
#define K230_HS_SD0_TIMER_GATE 34
|
||||
#define K230_HS_SD1_TIMER_GATE 35
|
||||
#define K230_HS_USB0_REF_GATE 36
|
||||
#define K230_HS_USB1_REF_GATE 37
|
||||
#define K230_HS_HCLK_HIGH_RATE 38
|
||||
#define K230_HS_HCLK_RATE 39
|
||||
#define K230_HS_SSI0_AXI_RATE 40
|
||||
#define K230_HS_SSI1_RATE 41
|
||||
#define K230_HS_SSI2_RATE 42
|
||||
#define K230_HS_QSPI_AXI_SRC_RATE 43
|
||||
#define K230_HS_SD_CARD_SRC_RATE 44
|
||||
#define K230_HS_SD_AXI_SRC_RATE 45
|
||||
#define K230_HS_USB_REF_50M_RATE 46
|
||||
#define K230_HS_SD_TIMER_SRC_RATE 47
|
||||
#define K230_TIMER0_MUX 48
|
||||
#define K230_TIMER1_MUX 49
|
||||
#define K230_TIMER2_MUX 50
|
||||
#define K230_TIMER3_MUX 51
|
||||
#define K230_TIMER4_MUX 52
|
||||
#define K230_TIMER5_MUX 53
|
||||
#define K230_SHRM_SRAM_MUX 54
|
||||
#define K230_DDRC_SRC_MUX 55
|
||||
#define K230_AI_SRC_MUX 56
|
||||
#define K230_CAMERA0_MUX 57
|
||||
#define K230_CAMERA1_MUX 58
|
||||
#define K230_CAMERA2_MUX 59
|
||||
#define K230_CPU1_SRC_MUX 60
|
||||
#define K230_CPU1_SRC_GATE 61
|
||||
#define K230_CPU1_PLIC_GATE 62
|
||||
#define K230_CPU1_APB_GATE 63
|
||||
#define K230_CPU1_SRC_RATE 64
|
||||
#define K230_CPU1_AXI_RATE 65
|
||||
#define K230_CPU1_PLIC_RATE 66
|
||||
#define K230_PMU_APB_GATE 67
|
||||
#define K230_LS_APB_SRC_GATE 68
|
||||
#define K230_LS_UART0_APB_GATE 69
|
||||
#define K230_LS_UART1_APB_GATE 70
|
||||
#define K230_LS_UART2_APB_GATE 71
|
||||
#define K230_LS_UART3_APB_GATE 72
|
||||
#define K230_LS_UART4_APB_GATE 73
|
||||
#define K230_LS_I2C0_APB_GATE 74
|
||||
#define K230_LS_I2C1_APB_GATE 75
|
||||
#define K230_LS_I2C2_APB_GATE 76
|
||||
#define K230_LS_I2C3_APB_GATE 77
|
||||
#define K230_LS_I2C4_APB_GATE 78
|
||||
#define K230_LS_GPIO_APB_GATE 79
|
||||
#define K230_LS_PWM_APB_GATE 80
|
||||
#define K230_LS_JAMLINK0_APB_GATE 81
|
||||
#define K230_LS_JAMLINK1_APB_GATE 82
|
||||
#define K230_LS_JAMLINK2_APB_GATE 83
|
||||
#define K230_LS_JAMLINK3_APB_GATE 84
|
||||
#define K230_LS_AUDIO_APB_GATE 85
|
||||
#define K230_LS_ADC_APB_GATE 86
|
||||
#define K230_LS_CODEC_APB_GATE 87
|
||||
#define K230_LS_I2C0_GATE 88
|
||||
#define K230_LS_I2C1_GATE 89
|
||||
#define K230_LS_I2C2_GATE 90
|
||||
#define K230_LS_I2C3_GATE 91
|
||||
#define K230_LS_I2C4_GATE 92
|
||||
#define K230_LS_CODEC_ADC_GATE 93
|
||||
#define K230_LS_CODEC_DAC_GATE 94
|
||||
#define K230_LS_AUDIO_DEV_GATE 95
|
||||
#define K230_LS_PDM_GATE 96
|
||||
#define K230_LS_ADC_GATE 97
|
||||
#define K230_LS_UART0_GATE 98
|
||||
#define K230_LS_UART1_GATE 99
|
||||
#define K230_LS_UART2_GATE 100
|
||||
#define K230_LS_UART3_GATE 101
|
||||
#define K230_LS_UART4_GATE 102
|
||||
#define K230_LS_JAMLINK0CO_GATE 103
|
||||
#define K230_LS_JAMLINK1CO_GATE 104
|
||||
#define K230_LS_JAMLINK2CO_GATE 105
|
||||
#define K230_LS_JAMLINK3CO_GATE 106
|
||||
#define K230_LS_GPIO_DEBOUNCE_GATE 107
|
||||
#define K230_SYSCTL_WDT0_APB_GATE 108
|
||||
#define K230_SYSCTL_WDT1_APB_GATE 109
|
||||
#define K230_SYSCTL_TIMER_APB_GATE 110
|
||||
#define K230_SYSCTL_IOMUX_APB_GATE 111
|
||||
#define K230_SYSCTL_MAILBOX_APB_GATE 112
|
||||
#define K230_SYSCTL_HDI_GATE 113
|
||||
#define K230_SYSCTL_TIME_STAMP_GATE 114
|
||||
#define K230_SYSCTL_WDT0_GATE 115
|
||||
#define K230_SYSCTL_WDT1_GATE 116
|
||||
#define K230_TIMER0_GATE 117
|
||||
#define K230_TIMER1_GATE 118
|
||||
#define K230_TIMER2_GATE 119
|
||||
#define K230_TIMER3_GATE 120
|
||||
#define K230_TIMER4_GATE 121
|
||||
#define K230_TIMER5_GATE 122
|
||||
#define K230_SHRM_APB_GATE 123
|
||||
#define K230_SHRM_AXI_GATE 124
|
||||
#define K230_SHRM_AXI_SLAVE_GATE 125
|
||||
#define K230_SHRM_NONAI2D_AXI_GATE 126
|
||||
#define K230_SHRM_SRAM_GATE 127
|
||||
#define K230_SHRM_DECOMPRESS_AXI_GATE 128
|
||||
#define K230_SHRM_SDMA_AXI_GATE 129
|
||||
#define K230_SHRM_PDMA_AXI_GATE 130
|
||||
#define K230_DDRC_SRC_GATE 131
|
||||
#define K230_DDRC_BYPASS_GATE 132
|
||||
#define K230_DDRC_APB_GATE 133
|
||||
#define K230_DISPLAY_AHB_GATE 134
|
||||
#define K230_DISPLAY_AXI_GATE 135
|
||||
#define K230_DISPLAY_GPU_GATE 136
|
||||
#define K230_DISPLAY_DPIP_GATE 137
|
||||
#define K230_DISPLAY_CFG_GATE 138
|
||||
#define K230_DISPLAY_REF_GATE 139
|
||||
#define K230_USB_480M_GATE 140
|
||||
#define K230_USB_100M_GATE 141
|
||||
#define K230_DPHY_DFT_GATE 142
|
||||
#define K230_SPI2AXI_GATE 143
|
||||
#define K230_AI_SRC_GATE 144
|
||||
#define K230_AI_AXI_GATE 145
|
||||
#define K230_AI_SRC_RATE 146
|
||||
#define K230_CAMERA0_GATE 147
|
||||
#define K230_CAMERA1_GATE 148
|
||||
#define K230_CAMERA2_GATE 149
|
||||
#define K230_LS_APB_SRC_RATE 150
|
||||
#define K230_LS_I2C0_RATE 151
|
||||
#define K230_LS_I2C1_RATE 152
|
||||
#define K230_LS_I2C2_RATE 153
|
||||
#define K230_LS_I2C3_RATE 154
|
||||
#define K230_LS_I2C4_RATE 155
|
||||
#define K230_LS_CODEC_ADC_RATE 156
|
||||
#define K230_LS_CODEC_DAC_RATE 157
|
||||
#define K230_LS_AUDIO_DEV_RATE 158
|
||||
#define K230_LS_PDM_RATE 159
|
||||
#define K230_LS_ADC_RATE 160
|
||||
#define K230_LS_UART0_RATE 161
|
||||
#define K230_LS_UART1_RATE 162
|
||||
#define K230_LS_UART2_RATE 163
|
||||
#define K230_LS_UART3_RATE 164
|
||||
#define K230_LS_UART4_RATE 165
|
||||
#define K230_LS_JAMLINKCO_SRC_RATE 166
|
||||
#define K230_LS_GPIO_DEBOUNCE_RATE 167
|
||||
#define K230_SYSCTL_HDI_RATE 168
|
||||
#define K230_SYSCTL_TIME_STAMP_RATE 169
|
||||
#define K230_SYSCTL_TEMP_SENSOR_RATE 170
|
||||
#define K230_SYSCTL_WDT0_RATE 171
|
||||
#define K230_SYSCTL_WDT1_RATE 172
|
||||
#define K230_TIMER0_SRC_RATE 173
|
||||
#define K230_TIMER1_SRC_RATE 174
|
||||
#define K230_TIMER2_SRC_RATE 175
|
||||
#define K230_TIMER3_SRC_RATE 176
|
||||
#define K230_TIMER4_SRC_RATE 177
|
||||
#define K230_TIMER5_SRC_RATE 178
|
||||
#define K230_SHRM_APB_RATE 179
|
||||
#define K230_DDRC_SRC_RATE 180
|
||||
#define K230_DDRC_APB_RATE 181
|
||||
#define K230_DISPLAY_AHB_RATE 182
|
||||
#define K230_DISPLAY_CLKEXT_RATE 183
|
||||
#define K230_DISPLAY_GPU_RATE 184
|
||||
#define K230_DISPLAY_DPIP_RATE 185
|
||||
#define K230_DISPLAY_CFG_RATE 186
|
||||
#define K230_VPU_SRC_GATE 187
|
||||
#define K230_VPU_AXI_GATE 188
|
||||
#define K230_VPU_DDRCP2_GATE 189
|
||||
#define K230_VPU_CFG_GATE 190
|
||||
#define K230_VPU_SRC_RATE 191
|
||||
#define K230_VPU_AXI_SRC_RATE 192
|
||||
#define K230_VPU_CFG_RATE 193
|
||||
#define K230_SEC_APB_GATE 194
|
||||
#define K230_SEC_FIX_GATE 195
|
||||
#define K230_SEC_AXI_GATE 196
|
||||
#define K230_SEC_APB_RATE 197
|
||||
#define K230_SEC_FIX_RATE 198
|
||||
#define K230_SEC_AXI_RATE 199
|
||||
#define K230_USB_480M_RATE 200
|
||||
#define K230_USB_100M_RATE 201
|
||||
#define K230_DPHY_DFT_RATE 202
|
||||
#define K230_SPI2AXI_RATE 203
|
||||
#define K230_CAMERA0_RATE 204
|
||||
#define K230_CAMERA1_RATE 205
|
||||
#define K230_CAMERA2_RATE 206
|
||||
#define K230_SHRM_SRAM_DIV2 207
|
||||
|
||||
#endif /* __DT_BINDINGS_CANAAN_K230_CLOCK_H__ */
|
||||
Loading…
Reference in New Issue
Block a user