From 44730eac1778c72d3667ff5372f254056f542da8 Mon Sep 17 00:00:00 2001 From: Xukai Wang Date: Sat, 25 Apr 2026 17:29:31 +0800 Subject: [PATCH 01/10] dt-bindings: clock: Add Canaan K230 clock controller This patch adds the Device Tree binding for the clock controller on Canaan k230. The binding defines the clocks and the required properties to configure them correctly. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Xukai Wang Signed-off-by: Conor Dooley --- .../bindings/clock/canaan,k230-clk.yaml | 59 +++++ include/dt-bindings/clock/canaan,k230-clk.h | 220 ++++++++++++++++++ 2 files changed, 279 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml create mode 100644 include/dt-bindings/clock/canaan,k230-clk.h diff --git a/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml b/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml new file mode 100644 index 000000000000..34c93cb5db40 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/canaan,k230-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan Kendryte K230 Clock + +maintainers: + - Xukai Wang + +description: + The Canaan K230 clock controller generates various clocks for SoC + peripherals. See include/dt-bindings/clock/canaan,k230-clk.h for + valid clock IDs. + +properties: + compatible: + const: canaan,k230-clk + + reg: + items: + - description: PLL control registers + - description: Sysclk control registers + + clocks: + items: + - description: Main external reference clock + - description: + External clock which used as the pulse input + for the timer to provide timing signals. + + clock-names: + items: + - const: osc24m + - const: timer-pulse-in + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@91102000 { + compatible = "canaan,k230-clk"; + reg = <0x91102000 0x40>, + <0x91100000 0x108>; + clocks = <&osc24m>, <&timerx_pulse_in>; + clock-names = "osc24m", "timer-pulse-in"; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/canaan,k230-clk.h b/include/dt-bindings/clock/canaan,k230-clk.h new file mode 100644 index 000000000000..3b916678cc5b --- /dev/null +++ b/include/dt-bindings/clock/canaan,k230-clk.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Kendryte Canaan K230 Clock Drivers + * + * Author: Xukai Wang + */ + +#ifndef __DT_BINDINGS_CANAAN_K230_CLOCK_H__ +#define __DT_BINDINGS_CANAAN_K230_CLOCK_H__ + +#define K230_CPU0_SRC_GATE 0 +#define K230_CPU0_PLIC_GATE 1 +#define K230_CPU0_NOC_DDRCP4_GATE 2 +#define K230_CPU0_APB_GATE 3 +#define K230_CPU0_SRC_RATE 4 +#define K230_CPU0_AXI_RATE 5 +#define K230_CPU0_PLIC_RATE 6 +#define K230_CPU0_APB_RATE 7 +#define K230_HS_SSI0_MUX 8 +#define K230_HS_USB_REF_MUX 9 +#define K230_HS_HCLK_HIGH_GATE 10 +#define K230_HS_HCLK_GATE 11 +#define K230_HS_SD0_AHB_GATE 12 +#define K230_HS_SD1_AHB_GATE 13 +#define K230_HS_SSI1_AHB_GATE 14 +#define K230_HS_SSI2_AHB_GATE 15 +#define K230_HS_USB0_AHB_GATE 16 +#define K230_HS_USB1_AHB_GATE 17 +#define K230_HS_SSI0_AXI_GATE 18 +#define K230_HS_SSI1_GATE 19 +#define K230_HS_SSI2_GATE 20 +#define K230_HS_QSPI_AXI_SRC_GATE 21 +#define K230_HS_SSI1_AXI_GATE 22 +#define K230_HS_SSI2_AXI_GATE 23 +#define K230_HS_SD_CARD_SRC_GATE 24 +#define K230_HS_SD0_CARD_GATE 25 +#define K230_HS_SD1_CARD_GATE 26 +#define K230_HS_SD_AXI_SRC_GATE 27 +#define K230_HS_SD0_AXI_GATE 28 +#define K230_HS_SD1_AXI_GATE 29 +#define K230_HS_SD0_BASE_GATE 30 +#define K230_HS_SD1_BASE_GATE 31 +#define K230_HS_SSI0_GATE 32 +#define K230_HS_SD_TIMER_SRC_GATE 33 +#define K230_HS_SD0_TIMER_GATE 34 +#define K230_HS_SD1_TIMER_GATE 35 +#define K230_HS_USB0_REF_GATE 36 +#define K230_HS_USB1_REF_GATE 37 +#define K230_HS_HCLK_HIGH_RATE 38 +#define K230_HS_HCLK_RATE 39 +#define K230_HS_SSI0_AXI_RATE 40 +#define K230_HS_SSI1_RATE 41 +#define K230_HS_SSI2_RATE 42 +#define K230_HS_QSPI_AXI_SRC_RATE 43 +#define K230_HS_SD_CARD_SRC_RATE 44 +#define K230_HS_SD_AXI_SRC_RATE 45 +#define K230_HS_USB_REF_50M_RATE 46 +#define K230_HS_SD_TIMER_SRC_RATE 47 +#define K230_TIMER0_MUX 48 +#define K230_TIMER1_MUX 49 +#define K230_TIMER2_MUX 50 +#define K230_TIMER3_MUX 51 +#define K230_TIMER4_MUX 52 +#define K230_TIMER5_MUX 53 +#define K230_SHRM_SRAM_MUX 54 +#define K230_DDRC_SRC_MUX 55 +#define K230_AI_SRC_MUX 56 +#define K230_CAMERA0_MUX 57 +#define K230_CAMERA1_MUX 58 +#define K230_CAMERA2_MUX 59 +#define K230_CPU1_SRC_MUX 60 +#define K230_CPU1_SRC_GATE 61 +#define K230_CPU1_PLIC_GATE 62 +#define K230_CPU1_APB_GATE 63 +#define K230_CPU1_SRC_RATE 64 +#define K230_CPU1_AXI_RATE 65 +#define K230_CPU1_PLIC_RATE 66 +#define K230_PMU_APB_GATE 67 +#define K230_LS_APB_SRC_GATE 68 +#define K230_LS_UART0_APB_GATE 69 +#define K230_LS_UART1_APB_GATE 70 +#define K230_LS_UART2_APB_GATE 71 +#define K230_LS_UART3_APB_GATE 72 +#define K230_LS_UART4_APB_GATE 73 +#define K230_LS_I2C0_APB_GATE 74 +#define K230_LS_I2C1_APB_GATE 75 +#define K230_LS_I2C2_APB_GATE 76 +#define K230_LS_I2C3_APB_GATE 77 +#define K230_LS_I2C4_APB_GATE 78 +#define K230_LS_GPIO_APB_GATE 79 +#define K230_LS_PWM_APB_GATE 80 +#define K230_LS_JAMLINK0_APB_GATE 81 +#define K230_LS_JAMLINK1_APB_GATE 82 +#define K230_LS_JAMLINK2_APB_GATE 83 +#define K230_LS_JAMLINK3_APB_GATE 84 +#define K230_LS_AUDIO_APB_GATE 85 +#define K230_LS_ADC_APB_GATE 86 +#define K230_LS_CODEC_APB_GATE 87 +#define K230_LS_I2C0_GATE 88 +#define K230_LS_I2C1_GATE 89 +#define K230_LS_I2C2_GATE 90 +#define K230_LS_I2C3_GATE 91 +#define K230_LS_I2C4_GATE 92 +#define K230_LS_CODEC_ADC_GATE 93 +#define K230_LS_CODEC_DAC_GATE 94 +#define K230_LS_AUDIO_DEV_GATE 95 +#define K230_LS_PDM_GATE 96 +#define K230_LS_ADC_GATE 97 +#define K230_LS_UART0_GATE 98 +#define K230_LS_UART1_GATE 99 +#define K230_LS_UART2_GATE 100 +#define K230_LS_UART3_GATE 101 +#define K230_LS_UART4_GATE 102 +#define K230_LS_JAMLINK0CO_GATE 103 +#define K230_LS_JAMLINK1CO_GATE 104 +#define K230_LS_JAMLINK2CO_GATE 105 +#define K230_LS_JAMLINK3CO_GATE 106 +#define K230_LS_GPIO_DEBOUNCE_GATE 107 +#define K230_SYSCTL_WDT0_APB_GATE 108 +#define K230_SYSCTL_WDT1_APB_GATE 109 +#define K230_SYSCTL_TIMER_APB_GATE 110 +#define K230_SYSCTL_IOMUX_APB_GATE 111 +#define K230_SYSCTL_MAILBOX_APB_GATE 112 +#define K230_SYSCTL_HDI_GATE 113 +#define K230_SYSCTL_TIME_STAMP_GATE 114 +#define K230_SYSCTL_WDT0_GATE 115 +#define K230_SYSCTL_WDT1_GATE 116 +#define K230_TIMER0_GATE 117 +#define K230_TIMER1_GATE 118 +#define K230_TIMER2_GATE 119 +#define K230_TIMER3_GATE 120 +#define K230_TIMER4_GATE 121 +#define K230_TIMER5_GATE 122 +#define K230_SHRM_APB_GATE 123 +#define K230_SHRM_AXI_GATE 124 +#define K230_SHRM_AXI_SLAVE_GATE 125 +#define K230_SHRM_NONAI2D_AXI_GATE 126 +#define K230_SHRM_SRAM_GATE 127 +#define K230_SHRM_DECOMPRESS_AXI_GATE 128 +#define K230_SHRM_SDMA_AXI_GATE 129 +#define K230_SHRM_PDMA_AXI_GATE 130 +#define K230_DDRC_SRC_GATE 131 +#define K230_DDRC_BYPASS_GATE 132 +#define K230_DDRC_APB_GATE 133 +#define K230_DISPLAY_AHB_GATE 134 +#define K230_DISPLAY_AXI_GATE 135 +#define K230_DISPLAY_GPU_GATE 136 +#define K230_DISPLAY_DPIP_GATE 137 +#define K230_DISPLAY_CFG_GATE 138 +#define K230_DISPLAY_REF_GATE 139 +#define K230_USB_480M_GATE 140 +#define K230_USB_100M_GATE 141 +#define K230_DPHY_DFT_GATE 142 +#define K230_SPI2AXI_GATE 143 +#define K230_AI_SRC_GATE 144 +#define K230_AI_AXI_GATE 145 +#define K230_AI_SRC_RATE 146 +#define K230_CAMERA0_GATE 147 +#define K230_CAMERA1_GATE 148 +#define K230_CAMERA2_GATE 149 +#define K230_LS_APB_SRC_RATE 150 +#define K230_LS_I2C0_RATE 151 +#define K230_LS_I2C1_RATE 152 +#define K230_LS_I2C2_RATE 153 +#define K230_LS_I2C3_RATE 154 +#define K230_LS_I2C4_RATE 155 +#define K230_LS_CODEC_ADC_RATE 156 +#define K230_LS_CODEC_DAC_RATE 157 +#define K230_LS_AUDIO_DEV_RATE 158 +#define K230_LS_PDM_RATE 159 +#define K230_LS_ADC_RATE 160 +#define K230_LS_UART0_RATE 161 +#define K230_LS_UART1_RATE 162 +#define K230_LS_UART2_RATE 163 +#define K230_LS_UART3_RATE 164 +#define K230_LS_UART4_RATE 165 +#define K230_LS_JAMLINKCO_SRC_RATE 166 +#define K230_LS_GPIO_DEBOUNCE_RATE 167 +#define K230_SYSCTL_HDI_RATE 168 +#define K230_SYSCTL_TIME_STAMP_RATE 169 +#define K230_SYSCTL_TEMP_SENSOR_RATE 170 +#define K230_SYSCTL_WDT0_RATE 171 +#define K230_SYSCTL_WDT1_RATE 172 +#define K230_TIMER0_SRC_RATE 173 +#define K230_TIMER1_SRC_RATE 174 +#define K230_TIMER2_SRC_RATE 175 +#define K230_TIMER3_SRC_RATE 176 +#define K230_TIMER4_SRC_RATE 177 +#define K230_TIMER5_SRC_RATE 178 +#define K230_SHRM_APB_RATE 179 +#define K230_DDRC_SRC_RATE 180 +#define K230_DDRC_APB_RATE 181 +#define K230_DISPLAY_AHB_RATE 182 +#define K230_DISPLAY_CLKEXT_RATE 183 +#define K230_DISPLAY_GPU_RATE 184 +#define K230_DISPLAY_DPIP_RATE 185 +#define K230_DISPLAY_CFG_RATE 186 +#define K230_VPU_SRC_GATE 187 +#define K230_VPU_AXI_GATE 188 +#define K230_VPU_DDRCP2_GATE 189 +#define K230_VPU_CFG_GATE 190 +#define K230_VPU_SRC_RATE 191 +#define K230_VPU_AXI_SRC_RATE 192 +#define K230_VPU_CFG_RATE 193 +#define K230_SEC_APB_GATE 194 +#define K230_SEC_FIX_GATE 195 +#define K230_SEC_AXI_GATE 196 +#define K230_SEC_APB_RATE 197 +#define K230_SEC_FIX_RATE 198 +#define K230_SEC_AXI_RATE 199 +#define K230_USB_480M_RATE 200 +#define K230_USB_100M_RATE 201 +#define K230_DPHY_DFT_RATE 202 +#define K230_SPI2AXI_RATE 203 +#define K230_CAMERA0_RATE 204 +#define K230_CAMERA1_RATE 205 +#define K230_CAMERA2_RATE 206 +#define K230_SHRM_SRAM_DIV2 207 + +#endif /* __DT_BINDINGS_CANAAN_K230_CLOCK_H__ */ From 6e3e43605b0ddd813bcc27c809bd80d5fb37fbf3 Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Mon, 8 Apr 2024 00:28:31 +0800 Subject: [PATCH 02/10] dt-bindings: add Canaan K230 boards compatible strings Since K230 was released, K210 is no longer the only SoC in the Kendryte series, so remove the K210 string from the description. Also, add two boards based on k230 to compatible strings to allow them to be used in the dt. Signed-off-by: Yangyu Chen Acked-by: Krzysztof Kozlowski Reviewed-by: Damien Le Moal Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/canaan.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/canaan.yaml b/Documentation/devicetree/bindings/riscv/canaan.yaml index 41fd11f70a49..f9854ff43ac6 100644 --- a/Documentation/devicetree/bindings/riscv/canaan.yaml +++ b/Documentation/devicetree/bindings/riscv/canaan.yaml @@ -10,7 +10,7 @@ maintainers: - Damien Le Moal description: - Canaan Kendryte K210 SoC-based boards + Canaan Kendryte SoC-based boards properties: $nodename: @@ -42,6 +42,12 @@ properties: - items: - const: canaan,kendryte-k210 + - items: + - enum: + - canaan,canmv-k230 + - canaan,k230-usip-lp3-evb + - const: canaan,kendryte-k230 + additionalProperties: true ... From e43a725a4d58e8cfb9bdc28fef12e3809caceee8 Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Mon, 8 Apr 2024 00:28:32 +0800 Subject: [PATCH 03/10] dt-bindings: timer: Add Canaan K230 CLINT Add compatible string for Canaan K230 CLINT. Signed-off-by: Yangyu Chen Acked-by: Rob Herring Reviewed-by: Guo Ren Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 3c16b260db04..7936aebe1765 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -49,6 +49,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-clint + - canaan,k230-clint - sophgo,cv1800b-clint - sophgo,cv1812h-clint - sophgo,sg2002-clint From 85dca15595e58d06ac3e305b1464d2cc9520b184 Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Mon, 8 Apr 2024 00:28:33 +0800 Subject: [PATCH 04/10] dt-bindings: interrupt-controller: Add Canaan K230 PLIC Add compatible string for Canaan K230 PLIC. Signed-off-by: Yangyu Chen Acked-by: Rob Herring Reviewed-by: Guo Ren Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index e0267223887e..639bbeb1f6bd 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -71,6 +71,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-plic + - canaan,k230-plic - sophgo,cv1800b-plic - sophgo,cv1812h-plic - sophgo,sg2002-plic From 980512a5ca6f4ada16824a139b063c2c877cd319 Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Mon, 8 Apr 2024 00:28:34 +0800 Subject: [PATCH 05/10] riscv: dts: add initial canmv-k230 and k230-evb dts Add initial dts for CanMV-K230 and K230-EVB powered by Canaan Kendryte K230 SoC [1]. Some key consideration: - Only place BigCore which is 1.6GHz RV64GCBV The existence of cache coherence between the two cores remains unknown since they have dedicated L2 caches. And the factory SDK uses it for other OS by default. I don't know whether the two CPUs on K230 SoC can be used in one system. So only place BigCore here. Meanwhile, although docs from Canaan said 1.6GHz Core with Vector is CPU1, the CSR.MHARTID of this core is 0. - Support for "zba" "zbb" "zbc" "zbs" are tested by hand The user manual of C908 from T-Head does not document it specifically. It just said it supports B extension V1.0. [2] I have tested it by using this [3] which attempts to execute "add.uw", "andn", "clmulr", "bclr" and they doesn't traps on K230. But on JH7110, "clmulr" and "bclr" will trap. - Support for "zicbom" is tested by hand Have tested with some out-of-tree drivers from [4] that need DMA and they do not come to the dts currently. - Support for "zicboz" is tested by hand Have tested with my own bare mental M-Mode program [5] which tries to use zicboz to clear a 64B aligned block and got output[6] shows it supports zicboz. - Cache parameters are inferred from T-Head docs [2] and Canaan docs [1] L1i: 32KB, VIPT 4-Way set-associative, 64B Cacheline L1d: 32KB, VIPT 4-Way set-associative, 64B Cacheline L2: 256KB, PIPT 16-way set-associative, 64B Cacheline The numbers of cache sets are calculated from these parameters. - MMU only supports Sv39 The T-Head docs [2] say the C908 core can be configured to support Sv48 and Sv39 or only Sv39. On K230, I tried to write "riscv,sv48" on mmu-type in dts and boot the mainline kernel. However, it failed during the kernel probe and fell back to Sv39. I also tested it on M-Mode software, writing Sv48 to satp.mode will not trap but will leave the CSR unchanged. While writing Sv39, it will take effect. It shows that this CPU does not support Sv48. - Svpbmt and T-Head MAEE both supported T-Head C908 does support both Svpbmt and T-Head MAEE for page-based memory attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt is used here for mainline kernel support for K230. If the kernel wants to use Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS before entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0 on T-Head MAEE is NonCachable Memory. Once the kernel switches from bare metal to Sv39, It will lose dirty cache line modifications that haven't been written back to the memory. [1] https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html#chapter-1-introduction [2] https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699268369347/XuanTie-C908-UserManual.pdf [3] https://github.com/cyyself/rvb_test [4] https://github.com/cyyself/linux/tree/k230-mainline [5] https://github.com/cyyself/simple-sw-workbench/commit/32657d807d64217323a80cb04ce114671e51ed60 [6] https://gist.github.com/cyyself/aa98b07b8c77bb1d53b5a4c5e67a37cf Signed-off-by: Yangyu Chen Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/canaan/Makefile | 2 + arch/riscv/boot/dts/canaan/k230-canmv.dts | 24 ++++ arch/riscv/boot/dts/canaan/k230-evb.dts | 24 ++++ arch/riscv/boot/dts/canaan/k230.dtsi | 143 ++++++++++++++++++++++ 4 files changed, 193 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi diff --git a/arch/riscv/boot/dts/canaan/Makefile b/arch/riscv/boot/dts/canaan/Makefile index 987d1f0c41f0..7d54ea5c6f3d 100644 --- a/arch/riscv/boot/dts/canaan/Makefile +++ b/arch/riscv/boot/dts/canaan/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb +dtb-$(CONFIG_ARCH_CANAAN) += k230-canmv.dtb +dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts b/arch/riscv/boot/dts/canaan/k230-canmv.dts new file mode 100644 index 000000000000..9565915cead6 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 Yangyu Chen + */ + +#include "k230.dtsi" + +/ { + model = "Canaan CanMV-K230"; + compatible = "canaan,canmv-k230", "canaan,kendryte-k230"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ddr: memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts b/arch/riscv/boot/dts/canaan/k230-evb.dts new file mode 100644 index 000000000000..f898b8e62368 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k230-evb.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 Yangyu Chen + */ + +#include "k230.dtsi" + +/ { + model = "Kendryte K230 EVB"; + compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-k230"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ddr: memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi new file mode 100644 index 000000000000..104e08ef5869 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k230.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 Yangyu Chen + */ + +#include + +/dts-v1/; +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "canaan,kendryte-k230"; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <27000000>; + + cpu@0 { + compatible = "thead,c908", "riscv"; + device_type = "cpu"; + reg = <0>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zfh_zba_zbb_zbc_zbs_zvfh_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicsr", "zifencei", + "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zvfh", + "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <128>; + d-cache-size = <32768>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <262144>; + cache-sets = <256>; + cache-unified; + }; + }; + + apb_clk: apb-clk-clock { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "apb_clk"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + ranges; + + plic: interrupt-controller@f00000000 { + compatible = "canaan,k230-plic" ,"thead,c900-plic"; + reg = <0xf 0x00000000 0x0 0x04000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <208>; + }; + + clint: timer@f04000000 { + compatible = "canaan,k230-clint", "thead,c900-clint"; + reg = <0xf 0x04000000 0x0 0x00010000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; + }; + + uart0: serial@91400000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x91400000 0x0 0x1000>; + clocks = <&apb_clk>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: serial@91401000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x91401000 0x0 0x1000>; + clocks = <&apb_clk>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@91402000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x91402000 0x0 0x1000>; + clocks = <&apb_clk>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@91403000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x91403000 0x0 0x1000>; + clocks = <&apb_clk>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@91404000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x91404000 0x0 0x1000>; + clocks = <&apb_clk>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + }; +}; From f7e74a96da5ce89fa4b6d77f0407fe011fe8cd2f Mon Sep 17 00:00:00 2001 From: Jiayu Du Date: Sat, 27 Dec 2025 17:23:54 +0800 Subject: [PATCH 06/10] riscv: dts: canaan: Correct the formatting issues about k230 dts Correct the errors in the spacing format, and move the aliases from the SoC's dtsi to the board's dts, since it's more standard. Signed-off-by: Jiayu Du Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/canaan/k230-canmv.dts | 4 ++++ arch/riscv/boot/dts/canaan/k230-evb.dts | 4 ++++ arch/riscv/boot/dts/canaan/k230.dtsi | 6 +----- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts b/arch/riscv/boot/dts/canaan/k230-canmv.dts index 9565915cead6..593ca38e6824 100644 --- a/arch/riscv/boot/dts/canaan/k230-canmv.dts +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts @@ -9,6 +9,10 @@ / { model = "Canaan CanMV-K230"; compatible = "canaan,canmv-k230", "canaan,kendryte-k230"; + aliases { + serial0 = &uart0; + }; + chosen { stdout-path = "serial0:115200n8"; }; diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts b/arch/riscv/boot/dts/canaan/k230-evb.dts index f898b8e62368..bfa53f2e2403 100644 --- a/arch/riscv/boot/dts/canaan/k230-evb.dts +++ b/arch/riscv/boot/dts/canaan/k230-evb.dts @@ -9,6 +9,10 @@ / { model = "Kendryte K230 EVB"; compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-k230"; + aliases { + serial0 = &uart0; + }; + chosen { stdout-path = "serial0:115200n8"; }; diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi index 104e08ef5869..1aeb77160216 100644 --- a/arch/riscv/boot/dts/canaan/k230.dtsi +++ b/arch/riscv/boot/dts/canaan/k230.dtsi @@ -11,10 +11,6 @@ / { #size-cells = <2>; compatible = "canaan,kendryte-k230"; - aliases { - serial0 = &uart0; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -75,7 +71,7 @@ soc { ranges; plic: interrupt-controller@f00000000 { - compatible = "canaan,k230-plic" ,"thead,c900-plic"; + compatible = "canaan,k230-plic", "thead,c900-plic"; reg = <0xf 0x00000000 0x0 0x04000000>; interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; interrupt-controller; From 8205ceec006616adb4d8a86f1e53d8252fd3eddc Mon Sep 17 00:00:00 2001 From: Ze Huang <18771902331@163.com> Date: Thu, 26 Sep 2024 23:57:45 +0800 Subject: [PATCH 07/10] riscv: dts: canaan: Add k230's pinctrl node Add pinctrl device, containing default config for uart, pwm, iis, iic and mmc. Signed-off-by: Ze Huang <18771902331@163.com> Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/canaan/k230-canmv.dts | 304 ++++++++++++++++++++++ arch/riscv/boot/dts/canaan/k230-pinctrl.h | 18 ++ arch/riscv/boot/dts/canaan/k230.dtsi | 6 + 3 files changed, 328 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.h diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts b/arch/riscv/boot/dts/canaan/k230-canmv.dts index 593ca38e6824..32ba53d17c00 100644 --- a/arch/riscv/boot/dts/canaan/k230-canmv.dts +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts @@ -26,3 +26,307 @@ ddr: memory@0 { &uart0 { status = "okay"; }; + +&pinctrl { + jtag_pins: jtag-pins { + jtag-tck-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + input-enable; + bias-pull-down; + input-schmitt-enable; + }; + + jtag-tdi-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + input-enable; + bias-disable; + }; + + jtag-tdo-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + output-enable; + bias-disable; + }; + + jtag-tms-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + input-enable; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + uart2-pins-cfg { + pinmux = , /* uart2 txd */ + ; /* uart2 rxd */ + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + input-enable; + output-enable; + bias-disable; + }; + }; + + pwm2_pins: pwm2-pins { + pwm2-pin-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + pwm3_pins: pwm3-pins { + pwm3-pin-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + pwm4_pins: pwm4-pins { + pwm4-pin-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + iis_pins: iis-pins { + iis-clk-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + output-enable; + bias-disable; + }; + + iis-ws-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + output-enable; + bias-disable; + }; + + iis-din0-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + input-enable; + bias-disable; + }; + + iis-dout0-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + output-enable; + bias-disable; + }; + }; + + uart4_pins: uart4-pins { + uart4-txd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + uart4-rxd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + uart0_pins: uart0-pins { + uart0-txd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + uart0-rxd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + iic1_pins: iic1-pins { + iic1-pins-cfg { + pinmux = , /* iic1 scl */ + ; /* iic1 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + iic3_pins: iic3-pins { + iic3-pins-cfg { + pinmux = , /* iic3 scl */ + ; /* iic3 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + iic4_pins: iic4-pins { + iic4-pins-cfg { + pinmux = , /* iic4 scl */ + ; /* iic4 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + iic0_pins: iic0-pins { + iic0-pins-cfg { + pinmux = , /* iic0 scl */ + ; /* iic0 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + uart3_pins: uart3-pins { + uart3-txd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + uart3-rxd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + key_pins: key-pins { + key-pins-cfg { + pinmux = , /* key0 */ + ; /* key1 */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + mmc1_pins: mmc1-pins { + mmc1-cmd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + + mmc1-clk-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + mmc1-data-cfg { + pinmux = , /* mmc1 data0 */ + , /* mmc1 data1 */ + , /* mmc1 data2 */ + ; /* mmc1 data3 */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; +}; diff --git a/arch/riscv/boot/dts/canaan/k230-pinctrl.h b/arch/riscv/boot/dts/canaan/k230-pinctrl.h new file mode 100644 index 000000000000..63dd999ca55b --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k230-pinctrl.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2024 Canaan Bright Sight Co. Ltd + * Copyright (C) 2024 Ze Huang <18771902331@163.com> + */ + +#ifndef _K230_PINCTRL_H +#define _K230_PINCTRL_H + +#define K230_MSC_3V3 0 +#define K230_MSC_1V8 1 + +#define BANK_VOLTAGE_DEFAULT K230_MSC_1V8 +#define BANK_VOLTAGE_IO50_IO61 K230_MSC_3V3 + +#define K230_PINMUX(pin, mode) (((pin) << 8) | (mode)) + +#endif /* _K230_PINCTRL_H */ diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi index 1aeb77160216..5a1bf8a15abe 100644 --- a/arch/riscv/boot/dts/canaan/k230.dtsi +++ b/arch/riscv/boot/dts/canaan/k230.dtsi @@ -4,6 +4,7 @@ */ #include +#include "k230-pinctrl.h" /dts-v1/; / { @@ -86,6 +87,11 @@ clint: timer@f04000000 { interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; }; + pinctrl: pinctrl@91105000 { + compatible = "canaan,k230-pinctrl"; + reg = <0x0 0x91105000 0x0 0x100>; + }; + uart0: serial@91400000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x91400000 0x0 0x1000>; From 7071ae1d8a7623e4a83ada61f7e68761f6bef0e0 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Sun, 18 Jan 2026 22:25:07 +0800 Subject: [PATCH 08/10] riscv: dts: canaan: k230: Add "b" ISA extension "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update k230.dtsi to conform to this rule. Also synchronize "riscv,isa" with "riscv,isa-extensions". Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/canaan/k230.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi index 5a1bf8a15abe..041c9947a8fa 100644 --- a/arch/riscv/boot/dts/canaan/k230.dtsi +++ b/arch/riscv/boot/dts/canaan/k230.dtsi @@ -21,9 +21,9 @@ cpu@0 { compatible = "thead,c908", "riscv"; device_type = "cpu"; reg = <0>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zfh_zba_zbb_zbc_zbs_zvfh_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_zihpm_zfh_zba_zbb_zbc_zbs_zvfh_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicsr", "zifencei", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zvfh", "svpbmt"; From 714e4cb7784ad798c1e19134d0125d5751a70131 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Sat, 17 Jan 2026 18:06:23 +0800 Subject: [PATCH 09/10] riscv: dts: canaan: add reset controller for K230 Add the reset controller node for the K230 SoC. Also add the reset properties for all UART nodes. Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/canaan/k230.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi index 041c9947a8fa..a73b1926ab93 100644 --- a/arch/riscv/boot/dts/canaan/k230.dtsi +++ b/arch/riscv/boot/dts/canaan/k230.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include "k230-pinctrl.h" /dts-v1/; @@ -87,6 +88,12 @@ clint: timer@f04000000 { interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; }; + rst: reset-controller@91101000 { + compatible = "canaan,k230-rst"; + reg = <0x0 0x91101000 0x0 0x1000>; + #reset-cells = <1>; + }; + pinctrl: pinctrl@91105000 { compatible = "canaan,k230-pinctrl"; reg = <0x0 0x91105000 0x0 0x100>; @@ -99,6 +106,7 @@ uart0: serial@91400000 { interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; + resets = <&rst RST_UART0>; status = "disabled"; }; @@ -109,6 +117,7 @@ uart1: serial@91401000 { interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; + resets = <&rst RST_UART1>; status = "disabled"; }; @@ -119,6 +128,7 @@ uart2: serial@91402000 { interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; + resets = <&rst RST_UART2>; status = "disabled"; }; @@ -129,6 +139,7 @@ uart3: serial@91403000 { interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; + resets = <&rst RST_UART3>; status = "disabled"; }; @@ -139,6 +150,7 @@ uart4: serial@91404000 { interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; + resets = <&rst RST_UART4>; status = "disabled"; }; }; From 8f0a393b7d91ca66756123ac5f09b89c1696ff11 Mon Sep 17 00:00:00 2001 From: Xukai Wang Date: Sat, 25 Apr 2026 17:29:33 +0800 Subject: [PATCH 10/10] riscv: dts: canaan: Add clock definition for K230 This patch describes the clock controller integrated in K230 SoC and replace dummy clocks with the real ones for UARTs. For k230-canmv and k230-evb, they provide an additional external pulse input through a pin to serve as clock source. Co-developed-by: Troy Mitchell Signed-off-by: Troy Mitchell Signed-off-by: Xukai Wang Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/canaan/k230-canmv.dts | 11 ++++++++++ arch/riscv/boot/dts/canaan/k230-evb.dts | 11 ++++++++++ arch/riscv/boot/dts/canaan/k230.dtsi | 26 ++++++++++++++++------- 3 files changed, 40 insertions(+), 8 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts b/arch/riscv/boot/dts/canaan/k230-canmv.dts index 32ba53d17c00..2ba555f6de13 100644 --- a/arch/riscv/boot/dts/canaan/k230-canmv.dts +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts @@ -21,6 +21,12 @@ ddr: memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x20000000>; }; + + timerx_pulse_in: clock-50000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; }; &uart0 { @@ -330,3 +336,8 @@ mmc1-data-cfg { }; }; }; + +&sysclk { + clocks = <&osc24m>, <&timerx_pulse_in>; + clock-names = "osc24m", "timer-pulse-in"; +}; diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts b/arch/riscv/boot/dts/canaan/k230-evb.dts index bfa53f2e2403..4246e4bba6cc 100644 --- a/arch/riscv/boot/dts/canaan/k230-evb.dts +++ b/arch/riscv/boot/dts/canaan/k230-evb.dts @@ -21,8 +21,19 @@ ddr: memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x20000000>; }; + + timerx_pulse_in: clock-50000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; }; &uart0 { status = "okay"; }; + +&sysclk { + clocks = <&osc24m>, <&timerx_pulse_in>; + clock-names = "osc24m", "timer-pulse-in"; +}; diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi index a73b1926ab93..6dcb628a960b 100644 --- a/arch/riscv/boot/dts/canaan/k230.dtsi +++ b/arch/riscv/boot/dts/canaan/k230.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2024 Yangyu Chen */ +#include #include #include #include "k230-pinctrl.h" @@ -57,11 +58,11 @@ l2_cache: l2-cache { }; }; - apb_clk: apb-clk-clock { + osc24m: clock-24000000 { compatible = "fixed-clock"; - clock-frequency = <50000000>; - clock-output-names = "apb_clk"; #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc24m"; }; soc { @@ -99,10 +100,19 @@ pinctrl: pinctrl@91105000 { reg = <0x0 0x91105000 0x0 0x100>; }; + sysclk: clock-controller@91102000 { + compatible = "canaan,k230-clk"; + reg = <0x0 0x91102000 0x0 0x40>, + <0x0 0x91100000 0x0 0x108>; + clocks = <&osc24m>; + clock-names = "osc24m"; + #clock-cells = <1>; + }; + uart0: serial@91400000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x91400000 0x0 0x1000>; - clocks = <&apb_clk>; + clocks = <&sysclk K230_LS_UART0_RATE>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -113,7 +123,7 @@ uart0: serial@91400000 { uart1: serial@91401000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x91401000 0x0 0x1000>; - clocks = <&apb_clk>; + clocks = <&sysclk K230_LS_UART1_RATE>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -124,7 +134,7 @@ uart1: serial@91401000 { uart2: serial@91402000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x91402000 0x0 0x1000>; - clocks = <&apb_clk>; + clocks = <&sysclk K230_LS_UART2_RATE>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -135,7 +145,7 @@ uart2: serial@91402000 { uart3: serial@91403000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x91403000 0x0 0x1000>; - clocks = <&apb_clk>; + clocks = <&sysclk K230_LS_UART3_RATE>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -146,7 +156,7 @@ uart3: serial@91403000 { uart4: serial@91404000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x91404000 0x0 0x1000>; - clocks = <&apb_clk>; + clocks = <&sysclk K230_LS_UART4_RATE>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>;