mirror of
https://github.com/torvalds/linux.git
synced 2026-06-04 04:23:35 +02:00
Samsung DTS ARM64 changes for v5.20
1. Add CPU cache, UFS to Tesla FSD.
2. Add reboot-mode (boot into specific bootloader mode) to ExynosAutov9.
3. Add watchdogs to ExynosAutov9.
4. Add eMMC to Exynos7885 JackpotLTE (Samsung Galaxy A8).
5. DTS cleanup: white-spaces, node names, LED color/function.
6. Switch to DTS-local header for pinctrl register values instead of
bindings header. The bindings header is being deprecated because it
does not reflect the purpose of bindings.
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Merge tag 'samsung-dt64-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM64 changes for v5.20
1. Add CPU cache, UFS to Tesla FSD.
2. Add reboot-mode (boot into specific bootloader mode) to ExynosAutov9.
3. Add watchdogs to ExynosAutov9.
4. Add eMMC to Exynos7885 JackpotLTE (Samsung Galaxy A8).
5. DTS cleanup: white-spaces, node names, LED color/function.
6. Switch to DTS-local header for pinctrl register values instead of
bindings header. The bindings header is being deprecated because it
does not reflect the purpose of bindings.
* tag 'samsung-dt64-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Add internal eMMC support to jackpotlte
dt-bindings: clock: Add indices for Exynos7885 TREX clocks
dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS
arm64: dts: exynos: enable secondary ufs devices ExynosAutov9 SADK
arm64: dts: exynos: add secondary ufs devices in ExynosAutov9
arm64: dts: fsd: use local header for pinctrl register values
arm64: dts: exynos: use local header for pinctrl register values
arm64: dts: exynos: align MMC node name with dtschema
arm64: dts: exynos: adjust DT style of ufs nodes in ExynosAutov9
arm64: dts: exynos: adjust whitespace around '='
arm64: dts: fsd: add ufs device node
arm64: dts: exynos: add watchdog in ExynosAutov9
arm64: dts: exynos: add syscon reboot/reboot_mode support in ExynosAutov9
dt-bindings: soc: add samsung,boot-mode definitions
arm64: dts: fsd: Add cpu cache information
Link: https://lore.kernel.org/r/20220624080746.31947-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
813b080890
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@ -33,6 +33,7 @@ properties:
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|||
enum:
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- samsung,exynos7885-cmu-top
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- samsung,exynos7885-cmu-core
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- samsung,exynos7885-cmu-fsys
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- samsung,exynos7885-cmu-peri
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clocks:
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@ -88,6 +89,32 @@ allOf:
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- const: dout_core_cci
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- const: dout_core_g3d
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7885-cmu-fsys
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_FSYS bus clock (from CMU_TOP)
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- description: MMC_CARD clock (from CMU_TOP)
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- description: MMC_EMBD clock (from CMU_TOP)
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- description: MMC_SDIO clock (from CMU_TOP)
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- description: USB30DRD clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_fsys_bus
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- const: dout_fsys_mmc_card
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- const: dout_fsys_mmc_embd
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- const: dout_fsys_mmc_sdio
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- const: dout_fsys_usb30drd
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- if:
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properties:
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compatible:
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|
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79
arch/arm64/boot/dts/exynos/exynos-pinctrl.h
Normal file
79
arch/arm64/boot/dts/exynos/exynos-pinctrl.h
Normal file
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@ -0,0 +1,79 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Samsung Exynos DTS pinctrl constants
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*
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* Copyright (c) 2016 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2022 Linaro Ltd
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* Author: Krzysztof Kozlowski <krzk@kernel.org>
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*/
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#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
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#define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
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#define EXYNOS_PIN_PULL_NONE 0
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#define EXYNOS_PIN_PULL_DOWN 1
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#define EXYNOS_PIN_PULL_UP 3
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/* Pin function in power down mode */
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#define EXYNOS_PIN_PDN_OUT0 0
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#define EXYNOS_PIN_PDN_OUT1 1
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#define EXYNOS_PIN_PDN_INPUT 2
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#define EXYNOS_PIN_PDN_PREV 3
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/*
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* Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885, Exynos850
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* (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1)
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*/
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#define EXYNOS5420_PIN_DRV_LV1 0
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#define EXYNOS5420_PIN_DRV_LV2 1
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#define EXYNOS5420_PIN_DRV_LV3 2
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#define EXYNOS5420_PIN_DRV_LV4 3
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/* Drive strengths for Exynos5433 */
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#define EXYNOS5433_PIN_DRV_FAST_SR1 0
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#define EXYNOS5433_PIN_DRV_FAST_SR2 1
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#define EXYNOS5433_PIN_DRV_FAST_SR3 2
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#define EXYNOS5433_PIN_DRV_FAST_SR4 3
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#define EXYNOS5433_PIN_DRV_FAST_SR5 4
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#define EXYNOS5433_PIN_DRV_FAST_SR6 5
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#define EXYNOS5433_PIN_DRV_SLOW_SR1 8
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#define EXYNOS5433_PIN_DRV_SLOW_SR2 9
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#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa
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#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb
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#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc
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#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf
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/* Drive strengths for Exynos7 (except FSYS1) */
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#define EXYNOS7_PIN_DRV_LV1 0
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#define EXYNOS7_PIN_DRV_LV2 2
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#define EXYNOS7_PIN_DRV_LV3 1
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#define EXYNOS7_PIN_DRV_LV4 3
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/* Drive strengths for Exynos7 FSYS1 block */
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#define EXYNOS7_FSYS1_PIN_DRV_LV1 0
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#define EXYNOS7_FSYS1_PIN_DRV_LV2 4
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#define EXYNOS7_FSYS1_PIN_DRV_LV3 2
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#define EXYNOS7_FSYS1_PIN_DRV_LV4 6
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#define EXYNOS7_FSYS1_PIN_DRV_LV5 1
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#define EXYNOS7_FSYS1_PIN_DRV_LV6 5
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/* Drive strengths for Exynos850 GPIO_HSI block */
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#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */
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#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */
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#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */
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#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */
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#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */
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#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */
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#define EXYNOS_PIN_FUNC_INPUT 0
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#define EXYNOS_PIN_FUNC_OUTPUT 1
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#define EXYNOS_PIN_FUNC_2 2
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#define EXYNOS_PIN_FUNC_3 3
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#define EXYNOS_PIN_FUNC_4 4
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#define EXYNOS_PIN_FUNC_5 5
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#define EXYNOS_PIN_FUNC_6 6
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#define EXYNOS_PIN_FUNC_EINT 0xf
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#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT
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#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */
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@ -9,7 +9,7 @@
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* tree nodes are listed in this file.
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*/
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#include <dt-bindings/pinctrl/samsung.h>
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#include "exynos-pinctrl.h"
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#define PIN(_pin, _func, _pull, _drv) \
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pin- ## _pin { \
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@ -1820,7 +1820,7 @@ usbhost_dwc3: usb@15a00000 {
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};
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};
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mshc_0: mshc@15540000 {
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mshc_0: mmc@15540000 {
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compatible = "samsung,exynos7-dw-mshc-smu";
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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@ -1833,7 +1833,7 @@ mshc_0: mshc@15540000 {
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status = "disabled";
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};
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mshc_1: mshc@15550000 {
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mshc_1: mmc@15550000 {
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compatible = "samsung,exynos7-dw-mshc-smu";
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interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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@ -1846,7 +1846,7 @@ mshc_1: mshc@15550000 {
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status = "disabled";
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};
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mshc_2: mshc@15560000 {
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mshc_2: mmc@15560000 {
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compatible = "samsung,exynos7-dw-mshc-smu";
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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@ -357,7 +357,7 @@ &pinctrl_alive {
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pmic_irq: pmic-irq-pins {
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samsung,pins = "gpa0-2";
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samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
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samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
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};
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};
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@ -397,14 +397,14 @@ usb30_vbus_en: usb30-vbus-en-pins {
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samsung,pins = "gph1-1";
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samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
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samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
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samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
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};
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usb3drd_boost_en: usb3drd-boost-en-pins {
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samsung,pins = "gpf4-1";
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samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
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samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
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samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
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};
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};
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@ -9,7 +9,7 @@
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* device tree nodes in this file.
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*/
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#include <dt-bindings/pinctrl/samsung.h>
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#include "exynos-pinctrl.h"
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&pinctrl_alive {
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gpa0: gpa0-gpio-bank {
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@ -188,161 +188,161 @@ hs_i2c10_bus: hs-i2c10-bus-pins {
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samsung,pins = "gpb0-1", "gpb0-0";
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samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
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samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
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samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
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};
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hs_i2c11_bus: hs-i2c11-bus-pins {
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samsung,pins = "gpb0-3", "gpb0-2";
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samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
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samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
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samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
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};
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hs_i2c2_bus: hs-i2c2-bus-pins {
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samsung,pins = "gpd0-3", "gpd0-2";
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samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
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samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
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samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
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};
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uart0_data: uart0-data-pins {
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samsung,pins = "gpd0-0", "gpd0-1";
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samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
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samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
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||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
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||||
uart0_fctl: uart0-fctl-pins {
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samsung,pins = "gpd0-2", "gpd0-3";
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samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
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samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
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samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
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||||
};
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uart2_data: uart2-data-pins {
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samsung,pins = "gpd1-4", "gpd1-5";
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||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
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samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c3_bus: hs-i2c3-bus-pins {
|
||||
samsung,pins = "gpd1-3", "gpd1-2";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
uart1_data: uart1-data-pins {
|
||||
samsung,pins = "gpd1-0", "gpd1-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
uart1_fctl: uart1-fctl-pins {
|
||||
samsung,pins = "gpd1-2", "gpd1-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c0_bus: hs-i2c0-bus-pins {
|
||||
samsung,pins = "gpd2-1", "gpd2-0";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c1_bus: hs-i2c1-bus-pins {
|
||||
samsung,pins = "gpd2-3", "gpd2-2";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c9_bus: hs-i2c9-bus-pins {
|
||||
samsung,pins = "gpd2-7", "gpd2-6";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
pwm0_out: pwm0-out-pins {
|
||||
samsung,pins = "gpd2-4";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
pwm1_out: pwm1-out-pins {
|
||||
samsung,pins = "gpd2-5";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
pwm2_out: pwm2-out-pins {
|
||||
samsung,pins = "gpd2-6";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
pwm3_out: pwm3-out-pins {
|
||||
samsung,pins = "gpd2-7";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c8_bus: hs-i2c8-bus-pins {
|
||||
samsung,pins = "gpd5-3", "gpd5-2";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
uart3_data: uart3-data-pins {
|
||||
samsung,pins = "gpd5-0", "gpd5-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
spi2_bus: spi2-bus-pins {
|
||||
samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
spi1_bus: spi1-bus-pins {
|
||||
samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
spi0_bus: spi0-bus-pins {
|
||||
samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c4_bus: hs-i2c4-bus-pins {
|
||||
samsung,pins = "gpg3-1", "gpg3-0";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c5_bus: hs-i2c5-bus-pins {
|
||||
samsung,pins = "gpg3-3", "gpg3-2";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -359,7 +359,7 @@ hs_i2c6_bus: hs-i2c6-bus-pins {
|
|||
samsung,pins = "gpj0-1", "gpj0-0";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -376,7 +376,7 @@ hs_i2c7_bus: hs-i2c7-bus-pins {
|
|||
samsung,pins = "gpj1-1", "gpj1-0";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -393,7 +393,7 @@ spi3_bus: spi3-bus-pins {
|
|||
samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -410,7 +410,7 @@ spi4_bus: spi4-bus-pins {
|
|||
samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -427,35 +427,35 @@ sd2_clk: sd2-clk-pins {
|
|||
samsung,pins = "gpr4-0";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
|
||||
};
|
||||
|
||||
sd2_cmd: sd2-cmd-pins {
|
||||
samsung,pins = "gpr4-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
|
||||
};
|
||||
|
||||
sd2_cd: sd2-cd-pins {
|
||||
samsung,pins = "gpr4-2";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
|
||||
};
|
||||
|
||||
sd2_bus1: sd2-bus-width1-pins {
|
||||
samsung,pins = "gpr4-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
|
||||
};
|
||||
|
||||
sd2_bus4: sd2-bus-width4-pins {
|
||||
samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -683,20 +683,20 @@ spi5_bus: spi5-bus-pins {
|
|||
samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
ufs_refclk_out: ufs-refclk-out-pins {
|
||||
samsung,pins = "gpg2-4";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV2>;
|
||||
};
|
||||
|
||||
ufs_rst_n: ufs-rst-n-pins {
|
||||
samsung,pins = "gph1-5";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -60,6 +60,26 @@ power-key {
|
|||
};
|
||||
};
|
||||
|
||||
&mmc_0 {
|
||||
status = "okay";
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
cap-mmc-highspeed;
|
||||
non-removable;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
card-detect-delay = <200>;
|
||||
clock-frequency = <800000000>;
|
||||
bus-width = <8>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <0 4>;
|
||||
samsung,dw-mshc-ddr-timing = <2 4>;
|
||||
samsung,dw-mshc-hs400-timing = <0 2>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd0_clk_fast_slew_rate_3x &sd0_cmd &sd0_rdqs
|
||||
&sd0_bus1 &sd0_bus4 &sd0_bus8>;
|
||||
};
|
||||
|
||||
&oscclk {
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@
|
|||
* device tree nodes in this file.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/samsung.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "exynos-pinctrl.h"
|
||||
|
||||
&pinctrl_alive {
|
||||
etc0: etc0-gpio-bank {
|
||||
|
|
|
|||
|
|
@ -240,6 +240,25 @@ cmu_top: clock-controller@12060000 {
|
|||
clock-names = "oscclk";
|
||||
};
|
||||
|
||||
cmu_fsys: clock-controller@13400000 {
|
||||
compatible = "samsung,exynos7885-cmu-fsys";
|
||||
reg = <0x13400000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&oscclk>,
|
||||
<&cmu_top CLK_DOUT_FSYS_BUS>,
|
||||
<&cmu_top CLK_DOUT_FSYS_MMC_CARD>,
|
||||
<&cmu_top CLK_DOUT_FSYS_MMC_EMBD>,
|
||||
<&cmu_top CLK_DOUT_FSYS_MMC_SDIO>,
|
||||
<&cmu_top CLK_DOUT_FSYS_USB30DRD>;
|
||||
clock-names = "oscclk",
|
||||
"dout_fsys_bus",
|
||||
"dout_fsys_mmc_card",
|
||||
"dout_fsys_mmc_embd",
|
||||
"dout_fsys_mmc_sdio",
|
||||
"dout_fsys_usb30drd";
|
||||
};
|
||||
|
||||
pinctrl_alive: pinctrl@11cb0000 {
|
||||
compatible = "samsung,exynos7885-pinctrl";
|
||||
reg = <0x11cb0000 0x1000>;
|
||||
|
|
@ -274,6 +293,19 @@ pmu_system_controller: system-controller@11c80000 {
|
|||
reg = <0x11c80000 0x10000>;
|
||||
};
|
||||
|
||||
mmc_0: mmc@13500000 {
|
||||
compatible = "samsung,exynos7-dw-mshc-smu";
|
||||
reg = <0x13500000 0x2000>;
|
||||
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>,
|
||||
<&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>;
|
||||
clock-names = "biu", "ciu";
|
||||
fifo-depth = <0x40>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial_0: serial@13800000 {
|
||||
compatible = "samsung,exynos5433-uart";
|
||||
reg = <0x13800000 0x100>;
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/samsung.h>
|
||||
#include "exynos-pinctrl.h"
|
||||
|
||||
&pinctrl_alive {
|
||||
gpa0: gpa0-gpio-bank {
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
* device tree nodes in this file.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/samsung.h>
|
||||
#include "exynos-pinctrl.h"
|
||||
|
||||
&pinctrl_alive {
|
||||
gpa0: gpa0-gpio-bank {
|
||||
|
|
|
|||
|
|
@ -39,6 +39,14 @@ ufs_0_fixed_vcc_reg: regulator-0 {
|
|||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
ufs_1_fixed_vcc_reg: regulator-1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "ufs-vcc";
|
||||
gpio = <&gpg2 2 GPIO_ACTIVE_HIGH>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&serial_0 {
|
||||
|
|
@ -49,12 +57,22 @@ &ufs_0_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_1_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_0 {
|
||||
status = "okay";
|
||||
vcc-supply = <&ufs_0_fixed_vcc_reg>;
|
||||
vcc-fixed-regulator;
|
||||
};
|
||||
|
||||
&ufs_1 {
|
||||
status = "okay";
|
||||
vcc-supply = <&ufs_1_fixed_vcc_reg>;
|
||||
vcc-fixed-regulator;
|
||||
};
|
||||
|
||||
&usi_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
|
||||
#include <dt-bindings/clock/samsung,exynosautov9.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/samsung,boot-mode.h>
|
||||
#include <dt-bindings/soc/samsung,exynos-usi.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -312,6 +313,22 @@ pinctrl_peric1: pinctrl@10830000 {
|
|||
pmu_system_controller: system-controller@10460000 {
|
||||
compatible = "samsung,exynos7-pmu", "syscon";
|
||||
reg = <0x10460000 0x10000>;
|
||||
|
||||
reboot: syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
|
||||
value = <0x2>;
|
||||
mask = <0x2>;
|
||||
};
|
||||
|
||||
reboot-mode {
|
||||
compatible = "syscon-reboot-mode";
|
||||
offset = <0x810>; /* SYSIP_DAT0 */
|
||||
mode-bootloader = <EXYNOSAUTOV9_BOOT_BOOTLOADER>;
|
||||
mode-fastboot = <EXYNOSAUTOV9_BOOT_FASTBOOT>;
|
||||
mode-recovery = <EXYNOSAUTOV9_BOOT_RECOVERY>;
|
||||
};
|
||||
};
|
||||
|
||||
syscon_fsys2: syscon@17c20000 {
|
||||
|
|
@ -352,7 +369,7 @@ serial_0: serial@10300000 {
|
|||
};
|
||||
};
|
||||
|
||||
ufs_0_phy: ufs0-phy@17e04000 {
|
||||
ufs_0_phy: phy@17e04000 {
|
||||
compatible = "samsung,exynosautov9-ufs-phy";
|
||||
reg = <0x17e04000 0xc00>;
|
||||
reg-names = "phy-pma";
|
||||
|
|
@ -363,13 +380,13 @@ ufs_0_phy: ufs0-phy@17e04000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ufs_0: ufs0@17e00000 {
|
||||
compatible ="samsung,exynosautov9-ufs";
|
||||
ufs_0: ufs@17e00000 {
|
||||
compatible = "samsung,exynosautov9-ufs";
|
||||
|
||||
reg = <0x17e00000 0x100>, /* 0: HCI standard */
|
||||
<0x17e01100 0x410>, /* 1: Vendor-specific */
|
||||
<0x17e80000 0x8000>, /* 2: UNIPRO */
|
||||
<0x17dc0000 0x2200>; /* 3: UFS protector */
|
||||
reg = <0x17e00000 0x100>,
|
||||
<0x17e01100 0x410>,
|
||||
<0x17e80000 0x8000>,
|
||||
<0x17dc0000 0x2200>;
|
||||
reg-names = "hci", "vs_hci", "unipro", "ufsp";
|
||||
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>,
|
||||
|
|
@ -383,6 +400,58 @@ ufs_0: ufs0@17e00000 {
|
|||
samsung,sysreg = <&syscon_fsys2 0x710>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ufs_1_phy: phy@17f04000 {
|
||||
compatible = "samsung,exynosautov9-ufs-phy";
|
||||
reg = <0x17f04000 0xc00>;
|
||||
reg-names = "phy-pma";
|
||||
samsung,pmu-syscon = <&pmu_system_controller 0x72c>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&xtcxo>;
|
||||
clock-names = "ref_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ufs_1: ufs@17f00000 {
|
||||
compatible = "samsung,exynosautov9-ufs";
|
||||
|
||||
reg = <0x17f00000 0x100>,
|
||||
<0x17f01100 0x410>,
|
||||
<0x17f80000 0x8000>,
|
||||
<0x17de0000 0x2200>;
|
||||
reg-names = "hci", "vs_hci", "unipro", "ufsp";
|
||||
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK>,
|
||||
<&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO>;
|
||||
clock-names = "core_clk", "sclk_unipro_main";
|
||||
freq-table-hz = <0 0>, <0 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ufs_rst_n_1 &ufs_refclk_out_1>;
|
||||
phys = <&ufs_1_phy>;
|
||||
phy-names = "ufs-phy";
|
||||
samsung,sysreg = <&syscon_fsys2 0x714>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog_cl0: watchdog@10050000 {
|
||||
compatible = "samsung,exynosautov9-wdt";
|
||||
reg = <0x10050000 0x100>;
|
||||
interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER0>, <&xtcxo>;
|
||||
clock-names = "watchdog", "watchdog_src";
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
samsung,cluster-index = <0>;
|
||||
};
|
||||
|
||||
watchdog_cl1: watchdog@10060000 {
|
||||
compatible = "samsung,exynosautov9-wdt";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER1>, <&xtcxo>;
|
||||
clock-names = "watchdog", "watchdog_src";
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
samsung,cluster-index = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -37,3 +37,7 @@ &fin_pll {
|
|||
&serial_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
* https://www.tesla.com
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/samsung.h>
|
||||
#include "fsd-pinctrl.h"
|
||||
|
||||
&pinctrl_fsys0 {
|
||||
gpf0: gpf0-gpio-bank {
|
||||
|
|
@ -50,6 +50,20 @@ gpf5: gpf5-gpio-bank {
|
|||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
ufs_rst_n: ufs-rst-n-pins {
|
||||
samsung,pins = "gpf5-0";
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV2>;
|
||||
};
|
||||
|
||||
ufs_refclk_out: ufs-refclk-out-pins {
|
||||
samsung,pins = "gpf5-1";
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_peric {
|
||||
|
|
@ -223,107 +237,107 @@ gpg7: gpg7-gpio-bank {
|
|||
|
||||
pwm0_out: pwm0-out-pins {
|
||||
samsung,pins = "gpb6-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV2>;
|
||||
};
|
||||
|
||||
pwm1_out: pwm1-out-pins {
|
||||
samsung,pins = "gpb6-5";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV2>;
|
||||
};
|
||||
|
||||
hs_i2c0_bus: hs-i2c0-bus-pins {
|
||||
samsung,pins = "gpb0-0", "gpb0-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c1_bus: hs-i2c1-bus-pins {
|
||||
samsung,pins = "gpb0-2", "gpb0-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c2_bus: hs-i2c2-bus-pins {
|
||||
samsung,pins = "gpb0-4", "gpb0-5";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c3_bus: hs-i2c3-bus-pins {
|
||||
samsung,pins = "gpb0-6", "gpb0-7";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c4_bus: hs-i2c4-bus-pins {
|
||||
samsung,pins = "gpb1-0", "gpb1-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c5_bus: hs-i2c5-bus-pins {
|
||||
samsung,pins = "gpb1-2", "gpb1-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c6_bus: hs-i2c6-bus-pins {
|
||||
samsung,pins = "gpb1-4", "gpb1-5";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c7_bus: hs-i2c7-bus-pins {
|
||||
samsung,pins = "gpb1-6", "gpb1-7";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
uart0_data: uart0-data-pins {
|
||||
samsung,pins = "gpb7-0", "gpb7-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
uart1_data: uart1-data-pins {
|
||||
samsung,pins = "gpb7-4", "gpb7-5";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
spi0_bus: spi0-bus-pins {
|
||||
samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
spi1_bus: spi1-bus-pins {
|
||||
samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
spi2_bus: spi2-bus-pins {
|
||||
samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
samsung,pin-function = <FSD_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <FSD_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <FSD_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
33
arch/arm64/boot/dts/tesla/fsd-pinctrl.h
Normal file
33
arch/arm64/boot/dts/tesla/fsd-pinctrl.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Tesla FSD DTS pinctrl constants
|
||||
*
|
||||
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
* Copyright (c) 2022 Linaro Ltd
|
||||
* Author: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
*/
|
||||
|
||||
#ifndef __DTS_ARM64_TESLA_FSD_PINCTRL_H__
|
||||
#define __DTS_ARM64_TESLA_FSD_PINCTRL_H__
|
||||
|
||||
#define FSD_PIN_PULL_NONE 0
|
||||
#define FSD_PIN_PULL_DOWN 1
|
||||
#define FSD_PIN_PULL_UP 3
|
||||
|
||||
#define FSD_PIN_DRV_LV1 0
|
||||
#define FSD_PIN_DRV_LV2 2
|
||||
#define FSD_PIN_DRV_LV3 1
|
||||
#define FSD_PIN_DRV_LV4 3
|
||||
|
||||
#define FSD_PIN_FUNC_INPUT 0
|
||||
#define FSD_PIN_FUNC_OUTPUT 1
|
||||
#define FSD_PIN_FUNC_2 2
|
||||
#define FSD_PIN_FUNC_3 3
|
||||
#define FSD_PIN_FUNC_4 4
|
||||
#define FSD_PIN_FUNC_5 5
|
||||
#define FSD_PIN_FUNC_6 6
|
||||
#define FSD_PIN_FUNC_EINT 0xf
|
||||
#define FSD_PIN_FUNC_F FSD_PIN_FUNC_EINT
|
||||
|
||||
#endif /* __DTS_ARM64_TESLA_FSD_PINCTRL_H__ */
|
||||
|
|
@ -93,6 +93,13 @@ cpucl0_0: cpu@0 {
|
|||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&cpucl_l2>;
|
||||
};
|
||||
|
||||
cpucl0_1: cpu@1 {
|
||||
|
|
@ -102,6 +109,13 @@ cpucl0_1: cpu@1 {
|
|||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&cpucl_l2>;
|
||||
};
|
||||
|
||||
cpucl0_2: cpu@2 {
|
||||
|
|
@ -111,6 +125,13 @@ cpucl0_2: cpu@2 {
|
|||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&cpucl_l2>;
|
||||
};
|
||||
|
||||
cpucl0_3: cpu@3 {
|
||||
|
|
@ -119,6 +140,13 @@ cpucl0_3: cpu@3 {
|
|||
reg = <0x0 0x003>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&cpucl_l2>;
|
||||
};
|
||||
|
||||
/* Cluster 1 */
|
||||
|
|
@ -129,6 +157,13 @@ cpucl1_0: cpu@100 {
|
|||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&cpucl_l2>;
|
||||
};
|
||||
|
||||
cpucl1_1: cpu@101 {
|
||||
|
|
@ -138,6 +173,13 @@ cpucl1_1: cpu@101 {
|
|||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&cpucl_l2>;
|
||||
};
|
||||
|
||||
cpucl1_2: cpu@102 {
|
||||
|
|
@ -147,6 +189,13 @@ cpucl1_2: cpu@102 {
|
|||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&cpucl_l2>;
|
||||
};
|
||||
|
||||
cpucl1_3: cpu@103 {
|
||||
|
|
@ -156,6 +205,13 @@ cpucl1_3: cpu@103 {
|
|||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&cpucl_l2>;
|
||||
};
|
||||
|
||||
/* Cluster 2 */
|
||||
|
|
@ -166,6 +222,13 @@ cpucl2_0: cpu@200 {
|
|||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&cpucl_l2>;
|
||||
};
|
||||
|
||||
cpucl2_1: cpu@201 {
|
||||
|
|
@ -175,6 +238,13 @@ cpucl2_1: cpu@201 {
|
|||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&cpucl_l2>;
|
||||
};
|
||||
|
||||
cpucl2_2: cpu@202 {
|
||||
|
|
@ -184,6 +254,13 @@ cpucl2_2: cpu@202 {
|
|||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&cpucl_l2>;
|
||||
};
|
||||
|
||||
cpucl2_3: cpu@203 {
|
||||
|
|
@ -193,6 +270,20 @@ cpucl2_3: cpu@203 {
|
|||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&cpucl_l2>;
|
||||
};
|
||||
|
||||
cpucl_l2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x400000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <4096>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
|
|
@ -740,6 +831,35 @@ timer@10040000 {
|
|||
clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
};
|
||||
|
||||
ufs: ufs@15120000 {
|
||||
compatible = "tesla,fsd-ufs";
|
||||
reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */
|
||||
<0x0 0x15121100 0x0 0x200>, /* 1: Vendor specified */
|
||||
<0x0 0x15110000 0x0 0x8000>, /* 2: UNIPRO */
|
||||
<0x0 0x15130000 0x0 0x100>; /* 3: UFS protector */
|
||||
reg-names = "hci", "vs_hci", "unipro", "ufsp";
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>,
|
||||
<&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>;
|
||||
clock-names = "core_clk", "sclk_unipro_main";
|
||||
freq-table-hz = <0 0>, <0 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
|
||||
phys = <&ufs_phy>;
|
||||
phy-names = "ufs-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ufs_phy: ufs-phy@15124000 {
|
||||
compatible = "tesla,fsd-ufs-phy";
|
||||
reg = <0x0 0x15124000 0x0 0x800>;
|
||||
reg-names = "phy-pma";
|
||||
samsung,pmu-syscon = <&pmu_system_controller>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>;
|
||||
clock-names = "ref_clk";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -54,17 +54,39 @@
|
|||
#define CLK_GOUT_PERI_USI0 43
|
||||
#define CLK_GOUT_PERI_USI1 44
|
||||
#define CLK_GOUT_PERI_USI2 45
|
||||
#define TOP_NR_CLK 46
|
||||
#define CLK_MOUT_FSYS_BUS 46
|
||||
#define CLK_MOUT_FSYS_MMC_CARD 47
|
||||
#define CLK_MOUT_FSYS_MMC_EMBD 48
|
||||
#define CLK_MOUT_FSYS_MMC_SDIO 49
|
||||
#define CLK_MOUT_FSYS_USB30DRD 50
|
||||
#define CLK_DOUT_FSYS_BUS 51
|
||||
#define CLK_DOUT_FSYS_MMC_CARD 52
|
||||
#define CLK_DOUT_FSYS_MMC_EMBD 53
|
||||
#define CLK_DOUT_FSYS_MMC_SDIO 54
|
||||
#define CLK_DOUT_FSYS_USB30DRD 55
|
||||
#define CLK_GOUT_FSYS_BUS 56
|
||||
#define CLK_GOUT_FSYS_MMC_CARD 57
|
||||
#define CLK_GOUT_FSYS_MMC_EMBD 58
|
||||
#define CLK_GOUT_FSYS_MMC_SDIO 59
|
||||
#define CLK_GOUT_FSYS_USB30DRD 60
|
||||
#define TOP_NR_CLK 61
|
||||
|
||||
/* CMU_CORE */
|
||||
#define CLK_MOUT_CORE_BUS_USER 1
|
||||
#define CLK_MOUT_CORE_CCI_USER 2
|
||||
#define CLK_MOUT_CORE_G3D_USER 3
|
||||
#define CLK_MOUT_CORE_GIC 4
|
||||
#define CLK_DOUT_CORE_BUSP 5
|
||||
#define CLK_GOUT_CCI_ACLK 6
|
||||
#define CLK_GOUT_GIC400_CLK 7
|
||||
#define CORE_NR_CLK 8
|
||||
#define CLK_MOUT_CORE_BUS_USER 1
|
||||
#define CLK_MOUT_CORE_CCI_USER 2
|
||||
#define CLK_MOUT_CORE_G3D_USER 3
|
||||
#define CLK_MOUT_CORE_GIC 4
|
||||
#define CLK_DOUT_CORE_BUSP 5
|
||||
#define CLK_GOUT_CCI_ACLK 6
|
||||
#define CLK_GOUT_GIC400_CLK 7
|
||||
#define CLK_GOUT_TREX_D_CORE_ACLK 8
|
||||
#define CLK_GOUT_TREX_D_CORE_GCLK 9
|
||||
#define CLK_GOUT_TREX_D_CORE_PCLK 10
|
||||
#define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE 11
|
||||
#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE 12
|
||||
#define CLK_GOUT_TREX_P_CORE_PCLK 13
|
||||
#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE 14
|
||||
#define CORE_NR_CLK 15
|
||||
|
||||
/* CMU_PERI */
|
||||
#define CLK_MOUT_PERI_BUS_USER 1
|
||||
|
|
@ -112,4 +134,18 @@
|
|||
#define CLK_GOUT_WDT1_PCLK 43
|
||||
#define PERI_NR_CLK 44
|
||||
|
||||
/* CMU_FSYS */
|
||||
#define CLK_MOUT_FSYS_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS_MMC_CARD_USER 2
|
||||
#define CLK_MOUT_FSYS_MMC_EMBD_USER 3
|
||||
#define CLK_MOUT_FSYS_MMC_SDIO_USER 4
|
||||
#define CLK_MOUT_FSYS_USB30DRD_USER 4
|
||||
#define CLK_GOUT_MMC_CARD_ACLK 5
|
||||
#define CLK_GOUT_MMC_CARD_SDCLKIN 6
|
||||
#define CLK_GOUT_MMC_EMBD_ACLK 7
|
||||
#define CLK_GOUT_MMC_EMBD_SDCLKIN 8
|
||||
#define CLK_GOUT_MMC_SDIO_ACLK 9
|
||||
#define CLK_GOUT_MMC_SDIO_SDCLKIN 10
|
||||
#define FSYS_NR_CLK 11
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
|
||||
|
|
|
|||
18
include/dt-bindings/soc/samsung,boot-mode.h
Normal file
18
include/dt-bindings/soc/samsung,boot-mode.h
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2022 Samsung Electronics Co., Ltd.
|
||||
* Author: Chanho Park <chanho61.park@samsung.com>
|
||||
*
|
||||
* Device Tree bindings for Samsung Boot Mode.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_SAMSUNG_BOOT_MODE_H
|
||||
#define __DT_BINDINGS_SAMSUNG_BOOT_MODE_H
|
||||
|
||||
/* Boot mode definitions for Exynos Auto v9 SoC */
|
||||
|
||||
#define EXYNOSAUTOV9_BOOT_FASTBOOT 0xfa
|
||||
#define EXYNOSAUTOV9_BOOT_BOOTLOADER 0xfc
|
||||
#define EXYNOSAUTOV9_BOOT_RECOVERY 0xff
|
||||
|
||||
#endif /* __DT_BINDINGS_SAMSUNG_BOOT_MODE_H */
|
||||
Loading…
Reference in New Issue
Block a user