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Merge branch 'for-v5.20/exynos7885-emmc-clk' into next/dt64
This commit is contained in:
Krzysztof Kozlowski
commit
1a4f20cab6
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@ -33,6 +33,7 @@ properties:
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enum:
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- samsung,exynos7885-cmu-top
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- samsung,exynos7885-cmu-core
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- samsung,exynos7885-cmu-fsys
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- samsung,exynos7885-cmu-peri
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clocks:
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@ -88,6 +89,32 @@ allOf:
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- const: dout_core_cci
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- const: dout_core_g3d
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7885-cmu-fsys
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_FSYS bus clock (from CMU_TOP)
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- description: MMC_CARD clock (from CMU_TOP)
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- description: MMC_EMBD clock (from CMU_TOP)
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- description: MMC_SDIO clock (from CMU_TOP)
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- description: USB30DRD clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_fsys_bus
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- const: dout_fsys_mmc_card
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- const: dout_fsys_mmc_embd
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- const: dout_fsys_mmc_sdio
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- const: dout_fsys_usb30drd
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- if:
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properties:
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compatible:
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@ -60,6 +60,26 @@ power-key {
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};
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};
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&mmc_0 {
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status = "okay";
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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cap-mmc-highspeed;
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non-removable;
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mmc-hs400-enhanced-strobe;
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card-detect-delay = <200>;
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clock-frequency = <800000000>;
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bus-width = <8>;
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samsung,dw-mshc-ciu-div = <3>;
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samsung,dw-mshc-sdr-timing = <0 4>;
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samsung,dw-mshc-ddr-timing = <2 4>;
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samsung,dw-mshc-hs400-timing = <0 2>;
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pinctrl-names = "default";
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pinctrl-0 = <&sd0_clk_fast_slew_rate_3x &sd0_cmd &sd0_rdqs
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&sd0_bus1 &sd0_bus4 &sd0_bus8>;
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};
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&oscclk {
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clock-frequency = <26000000>;
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};
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@ -240,6 +240,25 @@ cmu_top: clock-controller@12060000 {
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clock-names = "oscclk";
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};
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cmu_fsys: clock-controller@13400000 {
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compatible = "samsung,exynos7885-cmu-fsys";
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reg = <0x13400000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>,
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<&cmu_top CLK_DOUT_FSYS_BUS>,
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<&cmu_top CLK_DOUT_FSYS_MMC_CARD>,
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<&cmu_top CLK_DOUT_FSYS_MMC_EMBD>,
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<&cmu_top CLK_DOUT_FSYS_MMC_SDIO>,
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<&cmu_top CLK_DOUT_FSYS_USB30DRD>;
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clock-names = "oscclk",
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"dout_fsys_bus",
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"dout_fsys_mmc_card",
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"dout_fsys_mmc_embd",
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"dout_fsys_mmc_sdio",
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"dout_fsys_usb30drd";
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};
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pinctrl_alive: pinctrl@11cb0000 {
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compatible = "samsung,exynos7885-pinctrl";
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reg = <0x11cb0000 0x1000>;
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@ -274,6 +293,19 @@ pmu_system_controller: system-controller@11c80000 {
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reg = <0x11c80000 0x10000>;
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};
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mmc_0: mmc@13500000 {
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compatible = "samsung,exynos7-dw-mshc-smu";
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reg = <0x13500000 0x2000>;
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>,
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<&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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serial_0: serial@13800000 {
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compatible = "samsung,exynos5433-uart";
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reg = <0x13800000 0x100>;
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@ -54,17 +54,39 @@
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#define CLK_GOUT_PERI_USI0 43
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#define CLK_GOUT_PERI_USI1 44
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#define CLK_GOUT_PERI_USI2 45
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#define TOP_NR_CLK 46
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#define CLK_MOUT_FSYS_BUS 46
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#define CLK_MOUT_FSYS_MMC_CARD 47
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#define CLK_MOUT_FSYS_MMC_EMBD 48
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#define CLK_MOUT_FSYS_MMC_SDIO 49
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#define CLK_MOUT_FSYS_USB30DRD 50
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#define CLK_DOUT_FSYS_BUS 51
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#define CLK_DOUT_FSYS_MMC_CARD 52
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#define CLK_DOUT_FSYS_MMC_EMBD 53
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#define CLK_DOUT_FSYS_MMC_SDIO 54
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#define CLK_DOUT_FSYS_USB30DRD 55
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#define CLK_GOUT_FSYS_BUS 56
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#define CLK_GOUT_FSYS_MMC_CARD 57
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#define CLK_GOUT_FSYS_MMC_EMBD 58
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#define CLK_GOUT_FSYS_MMC_SDIO 59
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#define CLK_GOUT_FSYS_USB30DRD 60
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#define TOP_NR_CLK 61
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/* CMU_CORE */
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#define CLK_MOUT_CORE_BUS_USER 1
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#define CLK_MOUT_CORE_CCI_USER 2
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#define CLK_MOUT_CORE_G3D_USER 3
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#define CLK_MOUT_CORE_GIC 4
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#define CLK_DOUT_CORE_BUSP 5
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#define CLK_GOUT_CCI_ACLK 6
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#define CLK_GOUT_GIC400_CLK 7
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#define CORE_NR_CLK 8
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#define CLK_MOUT_CORE_BUS_USER 1
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#define CLK_MOUT_CORE_CCI_USER 2
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#define CLK_MOUT_CORE_G3D_USER 3
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#define CLK_MOUT_CORE_GIC 4
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#define CLK_DOUT_CORE_BUSP 5
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#define CLK_GOUT_CCI_ACLK 6
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#define CLK_GOUT_GIC400_CLK 7
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#define CLK_GOUT_TREX_D_CORE_ACLK 8
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#define CLK_GOUT_TREX_D_CORE_GCLK 9
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#define CLK_GOUT_TREX_D_CORE_PCLK 10
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#define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE 11
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#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE 12
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#define CLK_GOUT_TREX_P_CORE_PCLK 13
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#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE 14
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#define CORE_NR_CLK 15
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/* CMU_PERI */
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#define CLK_MOUT_PERI_BUS_USER 1
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@ -112,4 +134,18 @@
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#define CLK_GOUT_WDT1_PCLK 43
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#define PERI_NR_CLK 44
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/* CMU_FSYS */
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#define CLK_MOUT_FSYS_BUS_USER 1
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#define CLK_MOUT_FSYS_MMC_CARD_USER 2
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#define CLK_MOUT_FSYS_MMC_EMBD_USER 3
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#define CLK_MOUT_FSYS_MMC_SDIO_USER 4
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#define CLK_MOUT_FSYS_USB30DRD_USER 4
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#define CLK_GOUT_MMC_CARD_ACLK 5
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#define CLK_GOUT_MMC_CARD_SDCLKIN 6
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#define CLK_GOUT_MMC_EMBD_ACLK 7
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#define CLK_GOUT_MMC_EMBD_SDCLKIN 8
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#define CLK_GOUT_MMC_SDIO_ACLK 9
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#define CLK_GOUT_MMC_SDIO_SDCLKIN 10
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#define FSYS_NR_CLK 11
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
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