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T-HEAD Devicetrees for v6.19
Add PWM controlled fan and it's associated thermal management for the Lichee Pi 4A board. Enable additional ISA extenstions supported by the T-Head C910 cores: Zfh, Ziccrse, XTheadvector. Add reset controllers of more TH1520 subsystems: AP, AO, DSP, MISC, VI. Signed-off-by: Drew Fustini <fustini@kernel.org> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQSy8G7QpEpV9aCf6Lbb7CzD2SixDAUCaRDChQAKCRDb7CzD2Six DNU3AQDMrJ6jcRJQbog1T2OnIxPyvOct1Hx+01cD62MaSFprHAEAsJ4L8s3HPMWf pj+Cq44DoFH6UV/ImJlxpYFL87J9TQY= =ykgv -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkghukACgkQmmx57+YA GNmV9A/9GUE328GSrWiJ63RsZmgnBhb0o2SRyQxQSmTWbaLnNeHebO0myNCUynK9 kqacDnOFyUyFu8J7bMqT5RtZTGZalvFtt7Uxld+ESjTxujBqCZz7QNEVvWzNUpzB pxIfJdWfm7GcQYZsM+6V+tpByVkrnh3smErm3vCt4TFCk9Eqkn0n+Vfe8Rvm3Tm9 ELZY/zC4LW4GMDX429wJs1d9N9c6zxYwhd/Q1kyO5iPV/eiLlTVVFlHQZZaJRlB0 TbAHVt5RxtN4AC2xLUAer3J1K4iZNnXvVbBb5kBnGny5FTxHSafB11V2BFwDKrDB eleUw8K6xXL5Jijau5rULF4e35Qo8SXRI6FaiezcZbFzqC/ChSzsSY6phGEd2REt Z/lXrpa4YhiFPNyJzRLCDeFp9vRHgMOwBng7eZWx2AOMhGGNOUp1ktgj4n2lsRf1 9AxII/D+Dfdvrl1aicTRxpKEknywJw1x4RPcM9jTQfbEh22inp4f2fdwjNtK85vp uvStggBXvACHSz8pM7g1iifLsrOoXIuN7/BRrnw7yBUTz6rtCLAwsIpqr2H7qPTA ke+4EcxLNZWhii8pMG/q/bsOdDoaylVHfDkA/hai0tUpseGDm7Sf1LutFIi6i7CO aYSIIXFIFSx8JFbgqncmDwXoZwFGc/y4npDcd5NTUR8eNygX9ME= =wIpW -----END PGP SIGNATURE----- Merge tag 'thead-dt-for-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt T-HEAD Devicetrees for v6.19 Add PWM controlled fan and it's associated thermal management for the Lichee Pi 4A board. Enable additional ISA extenstions supported by the T-Head C910 cores: Zfh, Ziccrse, XTheadvector. Add reset controllers of more TH1520 subsystems: AP, AO, DSP, MISC, VI. Signed-off-by: Drew Fustini <fustini@kernel.org> * tag 'thead-dt-for-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux: riscv: dts: thead: Add reset controllers of more subsystems for TH1520 riscv: dts: thead: Add PWM fan and thermal control riscv: dts: thead: Add PWM controller node riscv: dts: thead: add zfh for th1520 riscv: dts: thead: add ziccrse for th1520 riscv: dts: thead: add xtheadvector to the th1520 devicetree Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
7e90eede6b
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@ -28,9 +28,76 @@ aliases {
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chosen {
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stdout-path = "serial0:115200n8";
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};
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thermal-zones {
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cpu-thermal {
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polling-delay = <1000>;
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polling-delay-passive = <1000>;
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thermal-sensors = <&pvt 0>;
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trips {
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fan_config0: fan-trip0 {
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temperature = <39000>;
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hysteresis = <5000>;
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type = "active";
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};
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fan_config1: fan-trip1 {
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temperature = <50000>;
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hysteresis = <5000>;
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type = "active";
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};
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fan_config2: fan-trip2 {
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temperature = <60000>;
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hysteresis = <5000>;
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type = "active";
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};
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};
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cooling-maps {
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map-active-0 {
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cooling-device = <&fan 1 1>;
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trip = <&fan_config0>;
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};
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map-active-1 {
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cooling-device = <&fan 2 2>;
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trip = <&fan_config1>;
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};
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map-active-2 {
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cooling-device = <&fan 3 3>;
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trip = <&fan_config2>;
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};
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};
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};
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};
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fan: pwm-fan {
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pinctrl-names = "default";
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pinctrl-0 = <&fan_pins>;
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compatible = "pwm-fan";
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#cooling-cells = <2>;
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pwms = <&pwm 1 10000000 0>;
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cooling-levels = <0 66 196 255>;
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};
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};
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&padctrl0_apsys {
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fan_pins: fan-0 {
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pwm1-pins {
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pins = "GPIO3_3"; /* PWM1 */
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function = "pwm";
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bias-disable;
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drive-strength = <25>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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};
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uart0_pins: uart0-0 {
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tx-pins {
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pins = "UART0_TXD";
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@ -24,8 +24,11 @@ c910_0: cpu@0 {
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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"ziccrse", "zicntr", "zicsr",
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"zifencei", "zihpm", "zfh",
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"xtheadvector";
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thead,vlenb = <16>;
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reg = <0>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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@ -48,8 +51,11 @@ c910_1: cpu@1 {
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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"ziccrse", "zicntr", "zicsr",
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"zifencei", "zihpm", "zfh",
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"xtheadvector";
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thead,vlenb = <16>;
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reg = <1>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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@ -72,8 +78,11 @@ c910_2: cpu@2 {
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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"ziccrse", "zicntr", "zicsr",
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"zifencei", "zihpm", "zfh",
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"xtheadvector";
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thead,vlenb = <16>;
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reg = <2>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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@ -96,8 +105,11 @@ c910_3: cpu@3 {
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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"ziccrse", "zicntr", "zicsr",
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"zifencei", "zihpm", "zfh",
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"xtheadvector";
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thead,vlenb = <16>;
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reg = <3>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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@ -277,6 +289,12 @@ clint: timer@ffdc000000 {
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<&cpu3_intc 3>, <&cpu3_intc 7>;
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};
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rst_vi: reset-controller@ffe4040100 {
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compatible = "thead,th1520-reset-vi";
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reg = <0xff 0xe4040100 0x0 0x8>;
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#reset-cells = <1>;
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};
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spi0: spi@ffe700c000 {
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compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
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reg = <0xff 0xe700c000 0x0 0x1000>;
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@ -502,6 +520,25 @@ uart2: serial@ffec010000 {
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status = "disabled";
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};
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pwm: pwm@ffec01c000 {
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compatible = "thead,th1520-pwm";
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reg = <0xff 0xec01c000 0x0 0x4000>;
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clocks = <&clk CLK_PWM>;
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#pwm-cells = <3>;
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};
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rst_misc: reset-controller@ffec02c000 {
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compatible = "thead,th1520-reset-misc";
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reg = <0xff 0xec02c000 0x0 0x18>;
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#reset-cells = <1>;
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};
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rst_vp: reset-controller@ffecc30000 {
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compatible = "thead,th1520-reset-vp";
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reg = <0xff 0xecc30000 0x0 0x14>;
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#reset-cells = <1>;
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};
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clk: clock-controller@ffef010000 {
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compatible = "thead,th1520-clk-ap";
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reg = <0xff 0xef010000 0x0 0x1000>;
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@ -509,6 +546,18 @@ clk: clock-controller@ffef010000 {
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#clock-cells = <1>;
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};
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rst_ap: reset-controller@ffef014000 {
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compatible = "thead,th1520-reset-ap";
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reg = <0xff 0xef014000 0x0 0x1000>;
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#reset-cells = <1>;
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};
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rst_dsp: reset-controller@ffef040028 {
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compatible = "thead,th1520-reset-dsp";
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reg = <0xff 0xef040028 0x0 0x4>;
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#reset-cells = <1>;
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};
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gpu: gpu@ffef400000 {
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compatible = "thead,th1520-gpu", "img,img-bxm-4-64",
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"img,img-rogue";
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@ -681,6 +730,13 @@ aogpio: gpio-controller@0 {
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};
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};
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rst_ao: reset-controller@fffff44000 {
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compatible = "thead,th1520-reset-ao";
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reg = <0xff 0xfff44000 0x0 0x2000>;
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#reset-cells = <1>;
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status = "reserved";
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};
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padctrl_aosys: pinctrl@fffff4a000 {
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compatible = "thead,th1520-pinctrl";
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reg = <0xff 0xfff4a000 0x0 0x2000>;
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