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Renesas DTS updates for v6.19

Browse Source 
- Add thermal support for the RZ/G3S and RZ/G3E SoCs,
   - Add DT overlay support for the Raspberry Pi Display 2 and Argon40
     fan hats on the Retronix Sparrow Hawk board,
   - Add eMMC support for the Eagle Function expansion board,
   - Add initial support for the R-Car X5H (R8A78000) SoC and the
     Ironhide development board,
   - Move interrupt-parent properties to root nodes,
   - Add system watchdog timer support for R-Car Gen3 and Gen4 SoCs,
     which is reserved for secure firmware on R-Car Gen3 boards,
   - Add ADC support for the RZ/T2H and RZ/N2H SoCs and their evaluation
     boards,
   - Add watchdog timer support on the R-Car V3M Starter Kit board,
   - Add Cortex-A55 PMU support on the RZ/V2H, RZ/V2N, RZ/T2H, and RZ/N2H
     SoCs,
   - Add Imagination Technologies PowerVR Series 6XT GX6250 GPU support
     on the R-Car M3-W and M3-W+ SoCs,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.19

  - Add thermal support for the RZ/G3S and RZ/G3E SoCs,
  - Add DT overlay support for the Raspberry Pi Display 2 and Argon40
    fan hats on the Retronix Sparrow Hawk board,
  - Add eMMC support for the Eagle Function expansion board,
  - Add initial support for the R-Car X5H (R8A78000) SoC and the
    Ironhide development board,
  - Move interrupt-parent properties to root nodes,
  - Add system watchdog timer support for R-Car Gen3 and Gen4 SoCs,
    which is reserved for secure firmware on R-Car Gen3 boards,
  - Add ADC support for the RZ/T2H and RZ/N2H SoCs and their evaluation
    boards,
  - Add watchdog timer support on the R-Car V3M Starter Kit board,
  - Add Cortex-A55 PMU support on the RZ/V2H, RZ/V2N, RZ/T2H, and RZ/N2H
    SoCs,
  - Add Imagination Technologies PowerVR Series 6XT GX6250 GPU support
    on the R-Car M3-W and M3-W+ SoCs,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (80 commits)
  arm64: dts: renesas: sparrow-hawk: Fix full-size DP connector node name and labels
  arm64: dts: renesas: r8a77961: Add GX6250 GPU node
  arm64: dts: renesas: r8a77960: Add GX6250 GPU node
  ARM: dts: renesas: kzm9g: Name interrupts for accelerometer
  arm64: dts: renesas: r9a09g087: Add Cortex-A55 PMU node
  arm64: dts: renesas: r9a09g077: Add Cortex-A55 PMU node
  arm64: dts: renesas: r9a09g056: Add Cortex-A55 PMU node
  arm64: dts: renesas: r9a09g057: Add Cortex-A55 PMU node
  ARM: dts: renesas: r9a06g032-rzn1d400-db: Drop invalid #cells properties
  arm64: dts: renesas: v3msk: Enable watchdog timer
  arm64: dts: renesas: r8a779h0: Add SWDT node
  arm64: dts: renesas: r8a779g0: Add SWDT node
  arm64: dts: renesas: r8a779f0: Add SWDT node
  arm64: dts: renesas: r8a779a0: Add SWDT node
  arm64: dts: renesas: rzt2h/rzn2h-evk: Enable ADCs
  arm64: dts: renesas: r9a09g087: Add ADCs support
  arm64: dts: renesas: r9a09g077: Add ADCs support
  ARM: dts: renesas: koelsch: Update ADV7180 binding
  ARM: dts: renesas: r9a06g032: Move interrupt-parent to root node
  ARM: dts: renesas: r8a7794: Move interrupt-parent to root node
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-11-21 16:30:47 +01:00
commit 156c42c7fc
65 changed files with 1982 additions and 312 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/renesas/r7s72100.dtsi
View File

@ -14,6 +14,7 @@ / {
compatible = "renesas,r7s72100";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
i2c0 = &i2c0;
@ -84,7 +85,7 @@ p1_clk: p1 {
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
rtc_x1_clk: rtc_x1 {
@ -103,7 +104,6 @@ rtc_x3_clk: rtc_x3 {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;

1
arch/arm/boot/dts/renesas/r7s9210.dtsi
View File

@ -52,7 +52,6 @@ cpu@0 {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;

26
arch/arm/boot/dts/renesas/r8a7742.dtsi
View File

@ -14,6 +14,7 @@ / {
compatible = "renesas,r8a7742";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
@ -208,19 +209,19 @@ pcie_bus_clk: pcie_bus {
pmu-0 {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
pmu-1 {
compatible = "arm,cortex-a7-pmu";
interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
@ -234,7 +235,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@ -1932,10 +1932,10 @@ cooling-maps {
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

14
arch/arm/boot/dts/renesas/r8a7743.dtsi
View File

@ -14,6 +14,7 @@ / {
compatible = "renesas,r8a7743";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
@ -115,8 +116,8 @@ pcie_bus_clk: pcie_bus {
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
@ -130,7 +131,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@ -1841,10 +1841,10 @@ cooling-maps {
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

14
arch/arm/boot/dts/renesas/r8a7744.dtsi
View File

@ -14,6 +14,7 @@ / {
compatible = "renesas,r8a7744";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
@ -115,8 +116,8 @@ pcie_bus_clk: pcie_bus {
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
@ -130,7 +131,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@ -1827,10 +1827,10 @@ cooling-maps {
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

14
arch/arm/boot/dts/renesas/r8a7745.dtsi
View File

@ -14,6 +14,7 @@ / {
compatible = "renesas,r8a7745";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
aliases {
i2c0 = &i2c0;
@ -105,8 +106,8 @@ extal_clk: extal {
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
@ -120,7 +121,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@ -1631,10 +1631,10 @@ cmt1: timer@e6130000 {
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

14
arch/arm/boot/dts/renesas/r8a77470.dtsi
View File

@ -13,6 +13,7 @@ / {
compatible = "renesas,r8a77470";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
aliases {
i2c0 = &i2c0;
@ -66,8 +67,8 @@ extal_clk: extal {
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
@ -81,7 +82,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@ -1057,10 +1057,10 @@ cmt1: timer@e6130000 {
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

26
arch/arm/boot/dts/renesas/r8a7790.dtsi
View File

@ -16,6 +16,7 @@ / {
compatible = "renesas,r8a7790";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
aliases {
i2c0 = &i2c0;
@ -239,19 +240,19 @@ pcie_bus_clk: pcie_bus {
pmu-0 {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
pmu-1 {
compatible = "arm,cortex-a7-pmu";
interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
@ -265,7 +266,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -2012,10 +2012,10 @@ cooling-maps {
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

34
arch/arm/boot/dts/renesas/r8a7791-koelsch.dts
View File

@ -301,6 +301,16 @@ cec_clock: cec-clock {
clock-frequency = <12000000>;
};
composite-in {
compatible = "composite-video-connector";
port {
composite_con_in: endpoint {
remote-endpoint = <&adv7180_in>;
};
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
@ -383,13 +393,25 @@ ak4643: codec@12 {
};
composite-in@20 {
compatible = "adi,adv7180";
compatible = "adi,adv7180cp";
reg = <0x20>;
port {
adv7180: endpoint {
bus-width = <8>;
remote-endpoint = <&vin1ep>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7180_in: endpoint {
remote-endpoint = <&composite_con_in>;
};
};
port@3 {
reg = <3>;
adv7180_out: endpoint {
remote-endpoint = <&vin1ep>;
};
};
};
};
@ -900,7 +922,7 @@ &vin1 {
port {
vin1ep: endpoint {
remote-endpoint = <&adv7180>;
remote-endpoint = <&adv7180_out>;
bus-width = <8>;
};
};

14
arch/arm/boot/dts/renesas/r8a7791.dtsi
View File

@ -16,6 +16,7 @@ / {
compatible = "renesas,r8a7791";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
aliases {
i2c0 = &i2c0;
@ -137,8 +138,8 @@ pcie_bus_clk: pcie_bus {
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
@ -152,7 +153,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -1939,10 +1939,10 @@ cooling-maps {
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

14
arch/arm/boot/dts/renesas/r8a7792.dtsi
View File

@ -14,6 +14,7 @@ / {
compatible = "renesas,r8a7792";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
aliases {
i2c0 = &i2c0;
@ -94,8 +95,8 @@ lbsc: bus {
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
@ -109,7 +110,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -992,10 +992,10 @@ cmt1: timer@e6130000 {
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
};

1
arch/arm/boot/dts/renesas/r8a7793-gose.dts
View File

@ -373,7 +373,6 @@ adv7180_in: endpoint {
port@3 {
reg = <3>;
adv7180_out: endpoint {
bus-width = <8>;
remote-endpoint = <&vin1ep>;
};
};

14
arch/arm/boot/dts/renesas/r8a7793.dtsi
View File

@ -14,6 +14,7 @@ / {
compatible = "renesas,r8a7793";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
aliases {
i2c0 = &i2c0;
@ -122,8 +123,8 @@ extal_clk: extal {
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
@ -137,7 +138,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -1518,10 +1518,10 @@ cooling-maps {
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

14
arch/arm/boot/dts/renesas/r8a7794.dtsi
View File

@ -15,6 +15,7 @@ / {
compatible = "renesas,r8a7794";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
aliases {
i2c0 = &i2c0;
@ -104,8 +105,8 @@ extal_clk: extal {
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
@ -119,7 +120,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -1485,10 +1485,10 @@ cmt1: timer@e6130000 {
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

2
arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
View File

@ -308,8 +308,6 @@ &rtc0 {
&switch {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>;

3
arch/arm/boot/dts/renesas/r9a06g032.dtsi
View File

@ -13,6 +13,7 @@ / {
compatible = "renesas,r9a06g032";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
@ -63,7 +64,6 @@ soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
ranges;
rtc0: rtc@40006000 {
@ -522,7 +522,6 @@ can1: can@52105000 {
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
arm,cpu-registers-not-fw-configured;
always-on;
interrupts =

1
arch/arm/boot/dts/renesas/sh73a0-kzm9g.dts
View File

@ -209,6 +209,7 @@ accelerometer@1d {
reg = <0x1d>;
interrupts-extended = <&irqpin3 2 IRQ_TYPE_LEVEL_HIGH>,
<&irqpin3 3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "INT1", "INT2";
};
rtc@32 {

11
arch/arm64/boot/dts/renesas/Makefile
View File

@ -108,9 +108,18 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx219.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx462.dtbo
r8a779g3-sparrow-hawk-camera-j2-imx462-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j2-imx462.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx462.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-argon40.dtbo
r8a779g3-sparrow-hawk-fan-argon40-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-fan-argon40.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-argon40.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtbo
r8a779g3-sparrow-hawk-fan-pwm-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-fan-pwm.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-5in.dtbo
r8a779g3-sparrow-hawk-rpi-display-2-5in-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-rpi-display-2-5in.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-5in.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-7in.dtbo
r8a779g3-sparrow-hawk-rpi-display-2-7in-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-rpi-display-2-7in.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-7in.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single.dtb
r8a779g3-white-hawk-single-ard-audio-da7212-dtbs := r8a779g3-white-hawk-single.dtb white-hawk-ard-audio-da7212.dtbo
@ -136,6 +145,8 @@ dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
r8a779m5-salvator-xs-panel-aa104xd12-dtbs := r8a779m5-salvator-xs.dtb salvator-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs-panel-aa104xd12.dtb
dtb-$(CONFIG_ARCH_R8A78000) += r8a78000-ironhide.dtb
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-du-adv7513.dtbo

1
arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi
View File

@ -66,7 +66,6 @@ ov5645: ov5645@3c {
compatible = "ovti,ov5645";
reg = <0x3c>;
clocks = <&osc25250_clk>;
clock-frequency = <24000000>;
vdddo-supply = <&ov5645_vdddo_1v8>;
vdda-supply = <&ov5645_vdda_2v8>;
vddd-supply = <&ov5645_vddd_1v5>;

5
arch/arm64/boot/dts/renesas/draak.dtsi
View File

@ -722,6 +722,11 @@ &ssi4 {
shared-pin;
};
/* Firmware should reserve it but sadly doesn't */
&swdt {
status = "reserved";
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";

5
arch/arm64/boot/dts/renesas/ebisu.dtsi
View File

@ -858,6 +858,11 @@ &ssi1 {
shared-pin;
};
/* Firmware should reserve it but sadly doesn't */
&swdt {
status = "reserved";
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";

22
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View File

@ -14,6 +14,7 @@ / {
compatible = "renesas,r8a774a1";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
@ -235,17 +236,17 @@ pcie_bus_clk: pcie_bus {
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
};
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupts= <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>, <&a57_1>;
};
@ -263,7 +264,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -2863,10 +2863,10 @@ sensor3_crit: sensor3-crit {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

14
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View File

@ -14,6 +14,7 @@ / {
compatible = "renesas,r8a774b1";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
@ -128,8 +129,8 @@ pcie_bus_clk: pcie_bus {
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>, <&a57_1>;
};
@ -147,7 +148,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -2734,10 +2734,10 @@ sensor3_crit: sensor3-crit {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

14
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View File

@ -13,6 +13,7 @@ / {
compatible = "renesas,r8a774c0";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
@ -119,8 +120,8 @@ pcie_bus_clk: pcie_bus {
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupts= <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>, <&a53_1>;
};
@ -138,7 +139,6 @@ scif_clk: scif {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -2000,10 +2000,10 @@ target: trip-point1 {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

26
arch/arm64/boot/dts/renesas/r8a774e1.dtsi
View File

@ -14,6 +14,7 @@ / {
compatible = "renesas,r8a774e1";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
@ -297,19 +298,19 @@ pcie_bus_clk: pcie_bus {
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
};
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>;
};
@ -327,7 +328,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -2997,10 +2997,10 @@ map1 {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

36
arch/arm64/boot/dts/renesas/r8a77951.dtsi
View File

@ -18,6 +18,7 @@ / {
compatible = "renesas,r8a7795";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
@ -312,10 +313,10 @@ pcie_bus_clk: pcie_bus {
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>,
<&a53_1>,
<&a53_2>,
@ -324,10 +325,10 @@ pmu_a53 {
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>,
<&a57_1>,
<&a57_2>,
@ -348,7 +349,6 @@ scif_clk: scif {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -365,6 +365,16 @@ rwdt: watchdog@e6020000 {
status = "disabled";
};
swdt: watchdog@e6030000 {
compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
reg = <0 0xe6030000 0 0x0c>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A7795_CLK_OSC>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 401>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7795",
"renesas,rcar-gen3-gpio";
@ -3476,10 +3486,10 @@ map1 {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

49
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View File

@ -13,6 +13,7 @@ / {
compatible = "renesas,r8a7796";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
@ -284,17 +285,17 @@ pcie_bus_clk: pcie_bus {
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
};
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>, <&a57_1>;
};
@ -312,7 +313,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -330,6 +330,16 @@ rwdt: watchdog@e6020000 {
status = "disabled";
};
swdt: watchdog@e6030000 {
compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt";
reg = <0 0xe6030000 0 0x0c>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A7796_CLK_OSC>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 401>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7796",
"renesas,rcar-gen3-gpio";
@ -2565,6 +2575,23 @@ gic: interrupt-controller@f1010000 {
resets = <&cpg 408>;
};
gpu: gpu@fd000000 {
compatible = "renesas,r8a7796-gpu",
"img,img-gx6250",
"img,img-rogue";
reg = <0 0xfd000000 0 0x40000>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A7796_CLK_ZG>,
<&cpg CPG_CORE R8A7796_CLK_S2D1>,
<&cpg CPG_MOD 112>;
clock-names = "core", "mem", "sys";
power-domains = <&sysc R8A7796_PD_3DG_A>,
<&sysc R8A7796_PD_3DG_B>;
power-domain-names = "a", "b";
resets = <&cpg 112>;
status = "disabled";
};
pciec0: pcie@fe000000 {
compatible = "renesas,pcie-r8a7796",
"renesas,pcie-rcar-gen3";
@ -3074,10 +3101,10 @@ sensor3_crit: sensor3-crit {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

49
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View File

@ -13,6 +13,7 @@ / {
compatible = "renesas,r8a77961";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
@ -284,17 +285,17 @@ pcie_bus_clk: pcie_bus {
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
};
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>, <&a57_1>;
};
@ -312,7 +313,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -330,6 +330,16 @@ rwdt: watchdog@e6020000 {
status = "disabled";
};
swdt: watchdog@e6030000 {
compatible = "renesas,r8a77961-wdt", "renesas,rcar-gen3-wdt";
reg = <0 0xe6030000 0 0x0c>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A77961_CLK_OSC>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 401>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77961",
"renesas,rcar-gen3-gpio";
@ -2445,6 +2455,23 @@ gic: interrupt-controller@f1010000 {
resets = <&cpg 408>;
};
gpu: gpu@fd000000 {
compatible = "renesas,r8a77961-gpu",
"img,img-gx6250",
"img,img-rogue";
reg = <0 0xfd000000 0 0x40000>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A77961_CLK_ZG>,
<&cpg CPG_CORE R8A77961_CLK_S2D1>,
<&cpg CPG_MOD 112>;
clock-names = "core", "mem", "sys";
power-domains = <&sysc R8A77961_PD_3DG_A>,
<&sysc R8A77961_PD_3DG_B>;
power-domain-names = "a", "b";
resets = <&cpg 112>;
status = "disabled";
};
pciec0: pcie@fe000000 {
compatible = "renesas,pcie-r8a77961",
"renesas,pcie-rcar-gen3";
@ -2895,10 +2922,10 @@ sensor3_crit: sensor3-crit {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

24
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View File

@ -18,6 +18,7 @@ / {
compatible = "renesas,r8a77965";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
@ -163,8 +164,8 @@ pcie_bus_clk: pcie_bus {
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>,
<&a57_1>;
};
@ -183,7 +184,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -201,6 +201,16 @@ rwdt: watchdog@e6020000 {
status = "disabled";
};
swdt: watchdog@e6030000 {
compatible = "renesas,r8a77965-wdt", "renesas,rcar-gen3-wdt";
reg = <0 0xe6030000 0 0x0c>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A77965_CLK_OSC>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 401>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77965",
"renesas,rcar-gen3-gpio";
@ -2903,10 +2913,10 @@ map0 {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};

17
arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso
View File

@ -170,7 +170,24 @@ csi40_in: endpoint {
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-names = "default";
vmmc-supply = <&d3p3>;
vqmmc-supply = <&d1p8>;
bus-width = <8>;
non-removable;
status = "okay";
};
&pfc {
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
vin0_pins_parallel: vin0 {
groups = "vin0_data12", "vin0_sync", "vin0_clk", "vin0_clkenb";
function = "vin0";

5
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
View File

@ -417,3 +417,8 @@ &scif0 {
&scif_clk {
clock-frequency = <14745600>;
};
/* Firmware should reserve it but sadly doesn't */
&swdt {
status = "reserved";
};

11
arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
View File

@ -146,7 +146,6 @@ &i2c0 {
hdmi@39 {
compatible = "adi,adv7511w";
#sound-dai-cells = <0>;
reg = <0x39>;
interrupts-extended = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&vcc_d1_8v>;
@ -293,6 +292,11 @@ user@1bc0000 {
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
@ -300,3 +304,8 @@ &scif0 {
status = "okay";
};
/* Firmware should reserve it but sadly doesn't */
&swdt {
status = "reserved";
};

24
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View File

@ -15,6 +15,7 @@ / {
compatible = "renesas,r8a77970";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
@ -73,8 +74,8 @@ extalr_clk: extalr {
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>, <&a53_1>;
};
@ -92,7 +93,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -110,6 +110,16 @@ rwdt: watchdog@e6020000 {
status = "disabled";
};
swdt: watchdog@e6030000 {
compatible = "renesas,r8a77970-wdt", "renesas,rcar-gen3-wdt";
reg = <0 0xe6030000 0 0x0c>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A77970_CLK_OSC>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 401>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77970",
"renesas,rcar-gen3-gpio";
@ -1227,10 +1237,10 @@ cpu-crit {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
};

1
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
View File

@ -138,7 +138,6 @@ &i2c0 {
hdmi@39 {
compatible = "adi,adv7511w";
#sound-dai-cells = <0>;
reg = <0x39>;
interrupts-extended = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&vcc1v8_d4>;

22
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View File

@ -15,6 +15,7 @@ / {
compatible = "renesas,r8a77980";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
@ -100,10 +101,10 @@ pcie_bus_clk: pcie_bus {
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
};
@ -121,7 +122,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -1631,14 +1631,10 @@ sensor2-critical {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
};

24
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@ -13,6 +13,7 @@ / {
compatible = "renesas,r8a77990";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
@ -134,8 +135,8 @@ pcie_bus_clk: pcie_bus {
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>, <&a53_1>;
};
@ -153,7 +154,6 @@ scif_clk: scif {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -171,6 +171,16 @@ rwdt: watchdog@e6020000 {
status = "disabled";
};
swdt: watchdog@e6030000 {
compatible = "renesas,r8a77990-wdt", "renesas,rcar-gen3-wdt";
reg = <0 0xe6030000 0 0x0c>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A77990_CLK_OSC>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 401>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77990",
"renesas,rcar-gen3-gpio";
@ -2164,10 +2174,10 @@ target: trip-point1 {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
};

22
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View File

@ -14,6 +14,7 @@ / {
compatible = "renesas,r8a77995";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
@ -70,7 +71,7 @@ extal_clk: extal {
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
@ -86,7 +87,6 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -104,6 +104,16 @@ rwdt: watchdog@e6020000 {
status = "disabled";
};
swdt: watchdog@e6030000 {
compatible = "renesas,r8a77995-wdt", "renesas,rcar-gen3-wdt";
reg = <0 0xe6030000 0 0x0c>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A77995_CLK_OSC>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 401>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77995",
"renesas,rcar-gen3-gpio";
@ -1479,10 +1489,10 @@ cpu-crit {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
};

24
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View File

@ -13,6 +13,7 @@ / {
compatible = "renesas,r8a779a0";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
@ -60,7 +61,7 @@ extalr_clk: extalr {
pmu_a76 {
compatible = "arm,cortex-a76-pmu";
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
/* External SCIF clock - to be overridden by boards that provide it */
@ -72,7 +73,6 @@ scif_clk: scif {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -90,6 +90,16 @@ rwdt: watchdog@e6020000 {
status = "disabled";
};
swdt: watchdog@e6030000 {
compatible = "renesas,r8a779a0-wdt", "renesas,rcar-gen4-wdt";
reg = <0 0xe6030000 0 0x0c>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A779A0_CLK_OSC>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 1128>;
status = "disabled";
};
pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-r8a779a0";
reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
@ -3086,11 +3096,11 @@ sensor5_crit: sensor5-crit {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};

24
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
View File

@ -13,6 +13,7 @@ / {
compatible = "renesas,r8a779f0";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cluster01_opp: opp-table-0 {
compatible = "operating-points-v2";
@ -280,7 +281,7 @@ pcie1_clkref: pcie1-clkref {
pmu_a55 {
compatible = "arm,cortex-a55-pmu";
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
@ -297,7 +298,6 @@ scif_clk: scif {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -315,6 +315,16 @@ rwdt: watchdog@e6020000 {
status = "disabled";
};
swdt: watchdog@e6030000 {
compatible = "renesas,r8a779f0-wdt", "renesas,rcar-gen4-wdt";
reg = <0 0xe6030000 0 0x0c>;
interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A779F0_CLK_OSC>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 1128>;
status = "disabled";
};
pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-r8a779f0";
reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
@ -1340,11 +1350,11 @@ sensor3_crit: sensor3-crit {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};

24
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
View File

@ -13,6 +13,7 @@ / {
compatible = "renesas,r8a779g0";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/* External Audio clock - to be overridden by boards that provide it */
audio_clkin: audio_clkin {
@ -193,7 +194,7 @@ pcie1_clkref: pcie1-clkref {
pmu_a76 {
compatible = "arm,cortex-a76-pmu";
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
@ -216,7 +217,6 @@ scif_clk2: scif2 {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -234,6 +234,16 @@ rwdt: watchdog@e6020000 {
status = "disabled";
};
swdt: watchdog@e6030000 {
compatible = "renesas,r8a779g0-wdt", "renesas,rcar-gen4-wdt";
reg = <0 0xe6030000 0 0x0c>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A779G0_CLK_OSC>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 1128>;
status = "disabled";
};
pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-r8a779g0";
reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
@ -2601,11 +2611,11 @@ sensor4_crit: sensor4-crit {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};

51
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-argon40.dtso Normal file
View File

@ -0,0 +1,51 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Overlay for the Argon40 HAT blower fan on connector CN7
* on R-Car V4H ES3.0 Sparrow Hawk board
*
* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
*
* Example usage:
*
* # Localize hwmon sysfs directory that matches the PWM fan,
* # enable the PWM fan, and configure the fan speed manually.
* r8a779g3-sparrow-hawk$ ls -1 /sys/devices/platform/pwm-fan-ext/hwmon/hwmon?/pwm?_enable
* /sys/devices/platform/pwm-fan-ext/hwmon/hwmon0/pwm1_enable
*
* # Select mode 2 , enable fan PWM and regulator and keep them enabled.
* # For details, see Linux Documentation/hwmon/pwm-fan.rst
* r8a779g3-sparrow-hawk$ echo 2 > /sys/devices/platform/pwm-fan-ext/hwmon/hwmon0/pwm1_enable
*
* # Configure PWM fan speed in range 0..255 , 0 is stopped , 255 is full speed .
* # Fan speed 101 is about 2/5 of the PWM fan speed:
* r8a779g3-sparrow-hawk$ echo 101 > /sys/devices/platform/pwm-fan-ext/hwmon/hwmon0/pwm1
*/
/dts-v1/;
/plugin/;
&{/} {
pwm-fan-ext {
compatible = "pwm-fan";
#cooling-cells = <2>;
/* PWM period: 33us ~= 30 kHz */
pwms = <&pwmhat 0 33334 0>;
/* Available cooling levels */
cooling-levels = <0 50 100 150 200 255>;
fan-shutdown-percent = <100>;
};
};
/* Page 31 / IO_CN */
&i2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
status = "okay";
pwmhat: pwm@1a {
compatible = "argon40,fan-hat";
reg = <0x1a>;
#pwm-cells = <3>;
};
};

13
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-rpi-display-2-5in.dtso Normal file
View File

@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Overlay for the RPi Display 2 5" MIPI DSI panel connected
* to J4:DSI on R-Car V4H ES3.0 Sparrow Hawk board
*
* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
*/
#include "r8a779g3-sparrow-hawk-rpi-display-2.dtsi"
&panel {
compatible = "raspberrypi,dsi-5inch", "ilitek,ili9881c";
};

13
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-rpi-display-2-7in.dtso Normal file
View File

@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Overlay for the RPi Display 2 7" MIPI DSI panel connected
* to J4:DSI on R-Car V4H ES3.0 Sparrow Hawk board
*
* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
*/
#include "r8a779g3-sparrow-hawk-rpi-display-2.dtsi"
&panel {
compatible = "raspberrypi,dsi-7inch", "ilitek,ili9881c";
};

90
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-rpi-display-2.dtsi Normal file
View File

@ -0,0 +1,90 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Overlay for the RPi Display 2 MIPI DSI panel connected
* to J4:DSI on R-Car V4H ES3.0 Sparrow Hawk board
*
* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
display_bl: backlight {
compatible = "pwm-backlight";
pwms = <&mcu 0 255 0>;
};
reg_display: regulator-display {
compatible = "regulator-fixed";
regulator-name = "rpi-display";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_dsi_touch: regulator-dsi-touch {
compatible = "regulator-fixed";
gpio = <&mcu 1 GPIO_ACTIVE_HIGH>;
regulator-name = "rpi-touch";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <50000>;
enable-active-high;
};
};
&i2c0_mux3 {
#address-cells = <1>;
#size-cells = <0>;
mcu: gpio@45 {
compatible = "raspberrypi,touchscreen-panel-regulator-v2";
reg = <0x45>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <3>;
};
touchscreen@5d {
compatible = "goodix,gt911";
reg = <0x5d>;
AVDD28-supply = <&reg_dsi_touch>;
touchscreen-size-x = <720>;
touchscreen-size-y = <1280>;
};
};
&dsi0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel_in>;
data-lanes = <1 2>;
};
};
};
panel: panel@0 {
reg = <0>;
backlight = <&display_bl>;
power-supply = <&reg_display>;
reset-gpios = <&mcu 0 GPIO_ACTIVE_LOW>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};

6
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
View File

@ -119,13 +119,13 @@ memory@600000000 {
};
/* Page 27 / DSI to Display */
mini-dp-con {
dp-con {
compatible = "dp-connector";
label = "CN6";
type = "full-size";
port {
mini_dp_con_in: endpoint {
dp_con_in: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
@ -407,7 +407,7 @@ sn65dsi86_in: endpoint {
port@1 {
reg = <1>;
sn65dsi86_out: endpoint {
remote-endpoint = <&mini_dp_con_in>;
remote-endpoint = <&dp_con_in>;
};
};
};

24
arch/arm64/boot/dts/renesas/r8a779h0.dtsi
View File

@ -13,6 +13,7 @@ / {
compatible = "renesas,r8a779h0";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/* External Audio clock - to be overridden by boards that provide it */
audio_clkin: audio_clkin {
@ -158,7 +159,7 @@ pcie0_clkref: pcie0-clkref {
pmu-a76 {
compatible = "arm,cortex-a76-pmu";
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
@ -181,7 +182,6 @@ scif_clk2: scif-clk2 {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
@ -199,6 +199,16 @@ rwdt: watchdog@e6020000 {
status = "disabled";
};
swdt: watchdog@e6030000 {
compatible = "renesas,r8a779h0-wdt", "renesas,rcar-gen4-wdt";
reg = <0 0xe6030000 0 0x0c>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A779H0_CLK_OSC>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 1128>;
status = "disabled";
};
pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-r8a779h0";
reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
@ -2212,11 +2222,11 @@ sensor2_crit: sensor2-crit {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};

85
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts Normal file
View File

@ -0,0 +1,85 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the Ironhide board
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a78000.dtsi"
/ {
model = "Renesas Ironhide board based on r8a78000";
compatible = "renesas,ironhide", "renesas,r8a78000";
aliases {
serial0 = &hscif0;
};
chosen {
stdout-path = "serial0:1843200n8";
};
memory@60600000 {
device_type = "memory";
/* first 518MiB is reserved for other purposes. */
reg = <0x0 0x60600000 0x0 0x5fa00000>;
};
memory@1080000000 {
device_type = "memory";
reg = <0x10 0x80000000 0x0 0x80000000>;
};
memory@1200000000 {
device_type = "memory";
reg = <0x12 0x00000000 0x1 0x00000000>;
};
memory@1400000000 {
device_type = "memory";
reg = <0x14 0x00000000 0x1 0x00000000>;
};
memory@1600000000 {
device_type = "memory";
reg = <0x16 0x00000000 0x1 0x00000000>;
};
memory@1800000000 {
device_type = "memory";
reg = <0x18 0x00000000 0x1 0x00000000>;
};
memory@1a00000000 {
device_type = "memory";
reg = <0x1a 0x00000000 0x1 0x00000000>;
};
memory@1c00000000 {
device_type = "memory";
reg = <0x1c 0x00000000 0x1 0x00000000>;
};
memory@1e00000000 {
device_type = "memory";
reg = <0x1e 0x00000000 0x1 0x00000000>;
};
};
&extal_clk {
clock-frequency = <16666600>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&hscif0 {
uart-has-rtscts;
status = "okay";
};
&scif_clk {
clock-frequency = <26000000>;
};

787
arch/arm64/boot/dts/renesas/r8a78000.dtsi Normal file
View File

@ -0,0 +1,787 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car X5H (R8A78000) SoC
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "renesas,r8a78000";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&a720_0>;
};
core1 {
cpu = <&a720_1>;
};
core2 {
cpu = <&a720_2>;
};
core3 {
cpu = <&a720_3>;
};
};
cluster1 {
core0 {
cpu = <&a720_4>;
};
core1 {
cpu = <&a720_5>;
};
core2 {
cpu = <&a720_6>;
};
core3 {
cpu = <&a720_7>;
};
};
cluster2 {
core0 {
cpu = <&a720_8>;
};
core1 {
cpu = <&a720_9>;
};
core2 {
cpu = <&a720_10>;
};
core3 {
cpu = <&a720_11>;
};
};
cluster3 {
core0 {
cpu = <&a720_12>;
};
core1 {
cpu = <&a720_13>;
};
core2 {
cpu = <&a720_14>;
};
core3 {
cpu = <&a720_15>;
};
};
cluster4 {
core0 {
cpu = <&a720_16>;
};
core1 {
cpu = <&a720_17>;
};
core2 {
cpu = <&a720_18>;
};
core3 {
cpu = <&a720_19>;
};
};
cluster5 {
core0 {
cpu = <&a720_20>;
};
core1 {
cpu = <&a720_21>;
};
core2 {
cpu = <&a720_22>;
};
core3 {
cpu = <&a720_23>;
};
};
cluster6 {
core0 {
cpu = <&a720_24>;
};
core1 {
cpu = <&a720_25>;
};
core2 {
cpu = <&a720_26>;
};
core3 {
cpu = <&a720_27>;
};
};
cluster7 {
core0 {
cpu = <&a720_28>;
};
core1 {
cpu = <&a720_29>;
};
core2 {
cpu = <&a720_30>;
};
core3 {
cpu = <&a720_31>;
};
};
};
a720_0: cpu@0 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x0>;
device_type = "cpu";
next-level-cache = <&L2_CA720_0>;
};
a720_1: cpu@100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x100>;
device_type = "cpu";
next-level-cache = <&L2_CA720_1>;
};
a720_2: cpu@200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x200>;
device_type = "cpu";
next-level-cache = <&L2_CA720_2>;
};
a720_3: cpu@300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x300>;
device_type = "cpu";
next-level-cache = <&L2_CA720_3>;
};
a720_4: cpu@10000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10000>;
device_type = "cpu";
next-level-cache = <&L2_CA720_4>;
};
a720_5: cpu@10100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10100>;
device_type = "cpu";
next-level-cache = <&L2_CA720_5>;
};
a720_6: cpu@10200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10200>;
device_type = "cpu";
next-level-cache = <&L2_CA720_6>;
};
a720_7: cpu@10300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10300>;
device_type = "cpu";
next-level-cache = <&L2_CA720_7>;
};
a720_8: cpu@20000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20000>;
device_type = "cpu";
next-level-cache = <&L2_CA720_8>;
};
a720_9: cpu@20100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20100>;
device_type = "cpu";
next-level-cache = <&L2_CA720_9>;
};
a720_10: cpu@20200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20200>;
device_type = "cpu";
next-level-cache = <&L2_CA720_10>;
};
a720_11: cpu@20300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20300>;
device_type = "cpu";
next-level-cache = <&L2_CA720_11>;
};
a720_12: cpu@30000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30000>;
device_type = "cpu";
next-level-cache = <&L2_CA720_12>;
};
a720_13: cpu@30100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30100>;
device_type = "cpu";
next-level-cache = <&L2_CA720_13>;
};
a720_14: cpu@30200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30200>;
device_type = "cpu";
next-level-cache = <&L2_CA720_14>;
};
a720_15: cpu@30300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30300>;
device_type = "cpu";
next-level-cache = <&L2_CA720_15>;
};
a720_16: cpu@40000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40000>;
device_type = "cpu";
next-level-cache = <&L2_CA720_16>;
};
a720_17: cpu@40100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40100>;
device_type = "cpu";
next-level-cache = <&L2_CA720_17>;
};
a720_18: cpu@40200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40200>;
device_type = "cpu";
next-level-cache = <&L2_CA720_18>;
};
a720_19: cpu@40300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40300>;
device_type = "cpu";
next-level-cache = <&L2_CA720_19>;
};
a720_20: cpu@50000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50000>;
device_type = "cpu";
next-level-cache = <&L2_CA720_20>;
};
a720_21: cpu@50100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50100>;
device_type = "cpu";
next-level-cache = <&L2_CA720_21>;
};
a720_22: cpu@50200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50200>;
device_type = "cpu";
next-level-cache = <&L2_CA720_22>;
};
a720_23: cpu@50300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50300>;
device_type = "cpu";
next-level-cache = <&L2_CA720_23>;
};
a720_24: cpu@60000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60000>;
device_type = "cpu";
next-level-cache = <&L2_CA720_24>;
};
a720_25: cpu@60100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60100>;
device_type = "cpu";
next-level-cache = <&L2_CA720_25>;
};
a720_26: cpu@60200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60200>;
device_type = "cpu";
next-level-cache = <&L2_CA720_26>;
};
a720_27: cpu@60300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60300>;
device_type = "cpu";
next-level-cache = <&L2_CA720_27>;
};
a720_28: cpu@70000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70000>;
device_type = "cpu";
next-level-cache = <&L2_CA720_28>;
};
a720_29: cpu@70100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70100>;
device_type = "cpu";
next-level-cache = <&L2_CA720_29>;
};
a720_30: cpu@70200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70200>;
device_type = "cpu";
next-level-cache = <&L2_CA720_30>;
};
a720_31: cpu@70300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70300>;
device_type = "cpu";
next-level-cache = <&L2_CA720_31>;
};
L2_CA720_0: cache-controller-200 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_0>;
};
L2_CA720_1: cache-controller-201 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_0>;
};
L2_CA720_2: cache-controller-202 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_0>;
};
L2_CA720_3: cache-controller-203 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_0>;
};
L2_CA720_4: cache-controller-204 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_1>;
};
L2_CA720_5: cache-controller-205 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_1>;
};
L2_CA720_6: cache-controller-206 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_1>;
};
L2_CA720_7: cache-controller-207 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_1>;
};
L2_CA720_8: cache-controller-208 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_2>;
};
L2_CA720_9: cache-controller-209 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_2>;
};
L2_CA720_10: cache-controller-210 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_2>;
};
L2_CA720_11: cache-controller-211 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_2>;
};
L2_CA720_12: cache-controller-212 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_3>;
};
L2_CA720_13: cache-controller-213 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_3>;
};
L2_CA720_14: cache-controller-214 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_3>;
};
L2_CA720_15: cache-controller-215 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_3>;
};
L2_CA720_16: cache-controller-216 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_4>;
};
L2_CA720_17: cache-controller-217 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_4>;
};
L2_CA720_18: cache-controller-218 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_4>;
};
L2_CA720_19: cache-controller-219 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_4>;
};
L2_CA720_20: cache-controller-220 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_5>;
};
L2_CA720_21: cache-controller-221 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_5>;
};
L2_CA720_22: cache-controller-222 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_5>;
};
L2_CA720_23: cache-controller-223 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_5>;
};
L2_CA720_24: cache-controller-224 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_6>;
};
L2_CA720_25: cache-controller-225 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_6>;
};
L2_CA720_26: cache-controller-226 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_6>;
};
L2_CA720_27: cache-controller-227 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_6>;
};
L2_CA720_28: cache-controller-228 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_7>;
};
L2_CA720_29: cache-controller-229 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_7>;
};
L2_CA720_30: cache-controller-230 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_7>;
};
L2_CA720_31: cache-controller-231 {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_CA720_7>;
};
L3_CA720_0: cache-controller-30 {
compatible = "cache";
cache-unified;
cache-level = <3>;
};
L3_CA720_1: cache-controller-31 {
compatible = "cache";
cache-unified;
cache-level = <3>;
};
L3_CA720_2: cache-controller-32 {
compatible = "cache";
cache-unified;
cache-level = <3>;
};
L3_CA720_3: cache-controller-33 {
compatible = "cache";
cache-unified;
cache-level = <3>;
};
L3_CA720_4: cache-controller-34 {
compatible = "cache";
cache-unified;
cache-level = <3>;
};
L3_CA720_5: cache-controller-35 {
compatible = "cache";
cache-unified;
cache-level = <3>;
};
L3_CA720_6: cache-controller-36 {
compatible = "cache";
cache-unified;
cache-level = <3>;
};
L3_CA720_7: cache-controller-37 {
compatible = "cache";
cache-unified;
cache-level = <3>;
};
};
/*
* In the early phase, there is no clock control support,
* so assume that the clocks are enabled by default.
* Therefore, dummy clocks are used.
*/
dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <66666000>;
};
dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <266660000>;
};
extal_clk: extal-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* clock-frequency must be set on board */
};
extalr_clk: extalr-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* clock-frequency must be set on board */
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>; /* optional */
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
prr: chipid@189e0044 {
compatible = "renesas,prr";
reg = <0 0x189e0044 0 4>;
};
/* Application Processors manage View-1 of a GIC-720AE */
gic: interrupt-controller@39000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x39000000 0 0x10000>,
<0 0x39080000 0 0x800000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
scif0: serial@c0700000 {
compatible = "renesas,scif-r8a78000",
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc0700000 0 0x40>;
interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
scif1: serial@c0704000 {
compatible = "renesas,scif-r8a78000",
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc0704000 0 0x40>;
interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
scif3: serial@c0708000 {
compatible = "renesas,scif-r8a78000",
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc0708000 0 0x40>;
interrupts = <GIC_SPI 4076 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
scif4: serial@c070c000 {
compatible = "renesas,scif-r8a78000",
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc070c000 0 0x40>;
interrupts = <GIC_SPI 4077 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
hscif0: serial@c0710000 {
compatible = "renesas,hscif-r8a78000",
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc0710000 0 0x60>;
interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
hscif1: serial@c0714000 {
compatible = "renesas,hscif-r8a78000",
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc0714000 0 0x60>;
interrupts = <GIC_SPI 4079 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
hscif2: serial@c0718000 {
compatible = "renesas,hscif-r8a78000",
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc0718000 0 0x60>;
interrupts = <GIC_SPI 4080 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
hscif3: serial@c071c000 {
compatible = "renesas,hscif-r8a78000",
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc071c000 0 0x60>;
interrupts = <GIC_SPI 4081 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
};
};

16
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
View File

@ -12,6 +12,8 @@
#include "r9a07g043.dtsi"
/ {
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -37,7 +39,7 @@ L3_CA55: cache-controller-0 {
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
@ -47,19 +49,17 @@ psci {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};
};
&soc {
interrupt-parent = <&gic>;
cru: video@10830000 {
compatible = "renesas,r9a07g043-cru", "renesas,rzg2l-cru";
reg = <0 0x10830000 0 0x400>;

14
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View File

@ -12,6 +12,7 @@ / {
compatible = "renesas,r9a07g044";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
audio_clk1: audio1-clk {
compatible = "fixed-clock";
@ -159,7 +160,7 @@ opp-50000000 {
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
@ -169,7 +170,6 @@ psci {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -1450,11 +1450,11 @@ target: trip-point {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};

14
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View File

@ -12,6 +12,7 @@ / {
compatible = "renesas,r9a07g054";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
audio_clk1: audio1-clk {
compatible = "fixed-clock";
@ -159,7 +160,7 @@ opp-50000000 {
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
@ -169,7 +170,6 @@ psci {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -1458,11 +1458,11 @@ target: trip-point {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};

61
arch/arm64/boot/dts/renesas/r9a08g045.dtsi
View File

@ -13,6 +13,7 @@ / {
compatible = "renesas,r9a08g045";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
audio_clk1: audio1-clk {
compatible = "fixed-clock";
@ -92,7 +93,6 @@ psci {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -233,7 +233,6 @@ adc: adc@10058000 {
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
status = "disabled";
channel@0 {
reg = <0>;
@ -272,6 +271,17 @@ channel@8 {
};
};
tsu: thermal@10059000 {
compatible = "renesas,r9a08g045-tsu";
reg = <0 0x10059000 0 0x1000>;
clocks = <&cpg CPG_MOD R9A08G045_TSU_PCLK>;
resets = <&cpg R9A08G045_TSU_PRESETN>;
power-domains = <&cpg>;
#thermal-sensor-cells = <0>;
io-channels = <&adc 8>;
io-channel-names = "tsu";
};
i3c: i3c@1005b000 {
compatible = "renesas,r9a08g045-i3c";
reg = <0 0x1005b000 0 0x1000>;
@ -744,15 +754,52 @@ wdt0: watchdog@12800800 {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsu>;
sustainable-power = <423>;
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device = <&cpu0 0 2>;
contribution = <1024>;
};
};
trips {
cpu_crit: cpu-critical {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
cpu_alert1: trip-point1 {
temperature = <90000>;
hysteresis = <1000>;
type = "passive";
};
cpu_alert0: trip-point0 {
temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};
vbattb_xtal: vbattb-xtal {
compatible = "fixed-clock";
#clock-cells = <0>;

10
arch/arm64/boot/dts/renesas/r9a09g011.dtsi
View File

@ -12,6 +12,7 @@ / {
compatible = "renesas,r9a09g011";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
extal_clk: extal {
@ -50,7 +51,6 @@ L2_CA53: cache-controller-0 {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -368,10 +368,10 @@ pinctrl: pinctrl@b6250000 {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
};

60
arch/arm64/boot/dts/renesas/r9a09g047.dtsi
View File

@ -12,6 +12,7 @@ / {
compatible = "renesas,r9a09g047";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
audio_extal_clk: audio-clk {
compatible = "fixed-clock";
@ -64,6 +65,7 @@ cpu0: cpu@0 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>;
#cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
@ -74,6 +76,7 @@ cpu1: cpu@100 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>;
#cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
@ -84,6 +87,7 @@ cpu2: cpu@200 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>;
#cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
@ -94,6 +98,7 @@ cpu3: cpu@300 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>;
#cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
@ -155,7 +160,6 @@ rtxin_clk: rtxin-clk {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -617,6 +621,19 @@ wdt3: watchdog@13000400 {
status = "disabled";
};
tsu: thermal@14002000 {
compatible = "renesas,r9a09g047-tsu";
reg = <0 0x14002000 0 0x1000>;
interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "adi", "adcmpi";
clocks = <&cpg CPG_MOD 0x10a>;
resets = <&cpg 0xf8>;
power-domains = <&cpg>;
#thermal-sensor-cells = <0>;
renesas,tsu-trim = <&sys 0x330>;
};
i2c0: i2c@14400400 {
compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
reg = <0 0x14400400 0 0x400>;
@ -1173,13 +1190,44 @@ stmmac_axi_setup: stmmac-axi-config {
snps,blen = <16 8 4 0 0 0 0>;
};
thermal-zones {
cpu-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&tsu>;
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0 0 3>, <&cpu1 0 3>,
<&cpu2 0 3>, <&cpu3 0 3>;
contribution = <1024>;
};
};
trips {
target: trip-point {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
sensor_crit: sensor-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
};
};

17
arch/arm64/boot/dts/renesas/r9a09g056.dtsi
View File

@ -30,6 +30,7 @@ / {
compatible = "renesas,r9a09g056";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
audio_extal_clk: audio-clk {
compatible = "fixed-clock";
@ -152,6 +153,11 @@ opp-19687500 {
};
};
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@ -173,7 +179,6 @@ rtxin_clk: rtxin-clk {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -961,11 +966,11 @@ stmmac_axi_setup: stmmac-axi-config {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
};
};

17
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
View File

@ -12,6 +12,7 @@ / {
compatible = "renesas,r9a09g057";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
audio_extal_clk: audio-clk {
compatible = "fixed-clock";
@ -134,6 +135,11 @@ opp-19687500 {
};
};
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@ -155,7 +161,6 @@ rtxin_clk: rtxin-clk {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -1309,11 +1314,11 @@ stmmac_axi_setup: stmmac-axi-config {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
};
};

83
arch/arm64/boot/dts/renesas/r9a09g077.dtsi
View File

@ -12,6 +12,7 @@ / {
compatible = "renesas,r9a09g077";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
@ -64,6 +65,11 @@ extal_clk: extal {
clock-frequency = <0>;
};
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@ -71,7 +77,6 @@ psci {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -299,6 +304,72 @@ gic: interrupt-controller@83000000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
adc0: adc@90014000 {
compatible = "renesas,r9a09g077-adc";
reg = <0 0x90014000 0 0x400>;
interrupts = <GIC_SPI 698 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 699 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 700 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 851 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 852 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "adi", "gbadi", "gcadi",
"cmpai", "cmpbi", "wcmpm", "wcmpum";
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
<&cpg CPG_MOD 206>;
clock-names = "adclk", "pclk";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
status = "disabled";
};
adc1: adc@90014400 {
compatible = "renesas,r9a09g077-adc";
reg = <0 0x90014400 0 0x400>;
interrupts = <GIC_SPI 703 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 704 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 705 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 853 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 854 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "adi", "gbadi", "gcadi",
"cmpai", "cmpbi", "wcmpm", "wcmpum";
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
<&cpg CPG_MOD 207>;
clock-names = "adclk", "pclk";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
status = "disabled";
};
adc2: adc@80008000 {
compatible = "renesas,r9a09g077-adc";
reg = <0 0x80008000 0 0x400>;
interrupts = <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 709 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 710 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 856 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "adi", "gbadi", "gcadi",
"cmpai", "cmpbi", "wcmpm", "wcmpum";
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
<&cpg CPG_MOD 225>;
clock-names = "adclk", "pclk";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
status = "disabled";
};
ohci: usb@92040000 {
compatible = "generic-ohci";
reg = <0 0x92040000 0 0x100>;
@ -389,11 +460,11 @@ sdhi1_vqmmc: vqmmc-regulator {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
};
};

28
arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
View File

@ -182,3 +182,31 @@ usb_pins: usb-pins {
<RZT2H_PORT_PINMUX(0, 1, 0x13)>; /* OVRCUR */
};
};
&adc2 {
status = "okay";
channel@0 {
reg = <0x0>;
};
channel@1 {
reg = <0x1>;
};
channel@2 {
reg = <0x2>;
};
channel@3 {
reg = <0x3>;
};
channel@4 {
reg = <0x4>;
};
channel@5 {
reg = <0x5>;
};
};

83
arch/arm64/boot/dts/renesas/r9a09g087.dtsi
View File

@ -12,6 +12,7 @@ / {
compatible = "renesas,r9a09g087";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
@ -64,6 +65,11 @@ extal_clk: extal {
clock-frequency = <0>;
};
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@ -71,7 +77,6 @@ psci {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -299,6 +304,72 @@ gic: interrupt-controller@83000000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
adc0: adc@90014000 {
compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc";
reg = <0 0x90014000 0 0x400>;
interrupts = <GIC_SPI 698 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 699 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 700 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 851 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 852 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "adi", "gbadi", "gcadi",
"cmpai", "cmpbi", "wcmpm", "wcmpum";
clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>,
<&cpg CPG_MOD 206>;
clock-names = "adclk", "pclk";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
status = "disabled";
};
adc1: adc@90014400 {
compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc";
reg = <0 0x90014400 0 0x400>;
interrupts = <GIC_SPI 703 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 704 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 705 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 853 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 854 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "adi", "gbadi", "gcadi",
"cmpai", "cmpbi", "wcmpm", "wcmpum";
clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>,
<&cpg CPG_MOD 207>;
clock-names = "adclk", "pclk";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
status = "disabled";
};
adc2: adc@80008000 {
compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc";
reg = <0 0x80008000 0 0x400>;
interrupts = <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 709 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 710 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 856 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "adi", "gbadi", "gcadi",
"cmpai", "cmpbi", "wcmpm", "wcmpum";
clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>,
<&cpg CPG_MOD 225>;
clock-names = "adclk", "pclk";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
status = "disabled";
};
ohci: usb@92040000 {
compatible = "generic-ohci";
reg = <0 0x92040000 0 0x100>;
@ -389,11 +460,11 @@ sdhi1_vqmmc: vqmmc-regulator {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
};
};

64
arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
View File

@ -227,3 +227,67 @@ usb_pins: usb-pins {
<RZT2H_PORT_PINMUX(2, 3, 0x13)>; /* OVRCUR */
};
};
&adc2 {
status = "okay";
channel@0 {
reg = <0x0>;
};
channel@1 {
reg = <0x1>;
};
channel@2 {
reg = <0x2>;
};
channel@3 {
reg = <0x3>;
};
channel@4 {
reg = <0x4>;
};
channel@5 {
reg = <0x5>;
};
channel@6 {
reg = <0x6>;
};
channel@7 {
reg = <0x7>;
};
channel@8 {
reg = <0x8>;
};
channel@9 {
reg = <0x9>;
};
channel@a {
reg = <0xa>;
};
channel@b {
reg = <0xb>;
};
channel@c {
reg = <0xc>;
};
channel@d {
reg = <0xd>;
};
channel@e {
reg = <0xe>;
};
};

1
arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi
View File

@ -64,7 +64,6 @@ ov5645: camera@3c {
compatible = "ovti,ov5645";
reg = <0x3c>;
clocks = <&ov5645_fixed_clk>;
clock-frequency = <24000000>;
vdddo-supply = <&ov5645_vdddo_1v8>;
vdda-supply = <&ov5645_vdda_2v8>;
vddd-supply = <&ov5645_vddd_1v5>;

4
arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
View File

@ -84,10 +84,6 @@ x3_clk: x3-clock {
};
};
&adc {
status = "okay";
};
#if SW_CONFIG3 == SW_ON
&eth0 {
pinctrl-0 = <&eth0_pins>;

79
arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
View File

@ -244,3 +244,82 @@ &wdt2 {
status = "okay";
timeout-sec = <60>;
};
/*
* ADC0 AN000 can be connected to a potentiometer on the board or
* exposed on ADC header.
*
* T2H:
* SW17[1] = ON, SW17[2] = OFF - Potentiometer
* SW17[1] = OFF, SW17[2] = ON - CN41 header
* N2H:
* DSW6[1] = OFF, DSW6[2] = ON - Potentiometer
* DSW6[1] = ON, DSW6[2] = OFF - CN3 header
*/
&adc0 {
status = "okay";
channel@0 {
reg = <0x0>;
};
channel@1 {
reg = <0x1>;
};
channel@2 {
reg = <0x2>;
};
channel@3 {
reg = <0x3>;
};
};
/*
* ADC1 AN100 can be exposed on ADC header or on mikroBUS connector.
*
* T2H:
* SW18[1] = ON, SW18[2] = OFF - CN42 header
* SW18[1] = OFF, SW18[2] = ON - mikroBUS
* N2H:
* DSW6[3] = ON, DSW6[4] = OFF - CN4 header
* DSW6[3] = OFF, DSW6[4] = ON - mikroBUS
*
* ADC1 AN101 can be exposed on ADC header or on Grove2 connector.
*
* T2H:
* SW18[3] = ON, SW18[4] = OFF - CN42 header
* SW18[3] = OFF, SW18[4] = ON - Grove2
* N2H:
* DSW6[5] = ON, DSW6[6] = OFF - CN4 header
* DSW6[5] = OFF, DSW6[6] = ON - Grove2
*
* ADC1 AN102 can be exposed on ADC header or on Grove2 connector.
*
* T2H:
* SW18[5] = ON, SW18[6] = OFF - CN42 header
* SW18[5] = OFF, SW18[6] = ON - Grove2
* N2H:
* DSW6[7] = ON, DSW6[8] = OFF - CN4 header
* DSW6[7] = OFF, DSW6[8] = ON - Grove2
*/
&adc1 {
status = "okay";
channel@0 {
reg = <0x0>;
};
channel@1 {
reg = <0x1>;
};
channel@2 {
reg = <0x2>;
};
channel@3 {
reg = <0x3>;
};
};

5
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View File

@ -1004,6 +1004,11 @@ &ssi1 {
shared-pin;
};
/* Firmware should reserve it but sadly doesn't */
&swdt {
status = "reserved";
};
&usb_extal_clk {
clock-frequency = <50000000>;
};

5
arch/arm64/boot/dts/renesas/ulcb.dtsi
View File

@ -495,6 +495,11 @@ &ssi1 {
shared-pin;
};
/* Firmware should reserve it but sadly doesn't */
&swdt {
status = "reserved";
};
&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";