mirror of
https://github.com/torvalds/linux.git
synced 2026-06-02 11:33:28 +02:00
Qualcomm pinctrl Devicetree bindings changes for v6.2
Big set of refactoring and improving Qualcomm pin controller bindings:
1. Convert several bindings from TXT to DT schema format: MDM9615,
MSM8974, MSM8994, MSM8996, MSM8998, SC7180, SDM630, SDM845, SM8150.
2. Refactor existing DT schema bindings to be consistent and similar to
each other, remove unneeded pieces (provided by common bindings) and
unify the style.
2. Fix matching of the existing DT schema bindings, so they properly
validate the DTS. When looking for pin configuration (children
nodes), be specific and expect "state" or "pins" suffixes (depending
on the nesting. This allows the schema later to properly parse also
GPIO hogs, although it is not yet implemented. The changes require
aligning the DTS to new layout, but it does not break any
compatibility.
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Merge tag 'qcom-pinctrl-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel
Qualcomm pinctrl Devicetree bindings changes for v6.2
Big set of refactoring and improving Qualcomm pin controller bindings:
1. Convert several bindings from TXT to DT schema format: MDM9615,
MSM8974, MSM8994, MSM8996, MSM8998, SC7180, SDM630, SDM845, SM8150.
2. Refactor existing DT schema bindings to be consistent and similar to
each other, remove unneeded pieces (provided by common bindings) and
unify the style.
2. Fix matching of the existing DT schema bindings, so they properly
validate the DTS. When looking for pin configuration (children
nodes), be specific and expect "state" or "pins" suffixes (depending
on the nesting. This allows the schema later to properly parse also
GPIO hogs, although it is not yet implemented. The changes require
aligning the DTS to new layout, but it does not break any
compatibility.
This commit is contained in:
Linus Walleij
commit
7cac5ffc08
|
|
@ -7,11 +7,10 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
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title: Qualcomm Technologies, Inc. IPQ6018 TLMM block
|
||||
|
||||
maintainers:
|
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- Sricharan R <sricharan@codeaurora.org>
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- Bjorn Andersson <andersson@kernel.org>
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|
||||
description: |
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This binding describes the Top Level Mode Multiplexer block found in the
|
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IPQ6018 platform.
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm IPQ6018 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
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|
@ -20,36 +19,28 @@ properties:
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reg:
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maxItems: 1
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||||
|
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interrupts:
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description: Specifies the TLMM summary IRQ
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maxItems: 1
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|
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interrupts: true
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interrupt-controller: true
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|
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'#interrupt-cells':
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description:
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Specifies the PIN numbers and Flags, as defined in defined in
|
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include/dt-bindings/interrupt-controller/irq.h
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const: 2
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"#interrupt-cells": true
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gpio-controller: true
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"#gpio-cells": true
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gpio-ranges: true
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'#gpio-cells':
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description: Specifying the pin number and flags, as defined in
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include/dt-bindings/gpio/gpio.h
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const: 2
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gpio-ranges:
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maxItems: 1
|
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|
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#PIN CONFIGURATION NODES
|
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patternProperties:
|
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'-pinmux$':
|
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type: object
|
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"-state$":
|
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oneOf:
|
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- $ref: "#/$defs/qcom-ipq6018-tlmm-state"
|
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- patternProperties:
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"-pins$":
|
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$ref: "#/$defs/qcom-ipq6018-tlmm-state"
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additionalProperties: false
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|
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$defs:
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qcom-ipq6018-tlmm-state:
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description:
|
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Pinctrl node's client devices use subnodes for desired pin configuration.
|
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Client device subnodes use below standard properties.
|
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$ref: "/schemas/pinctrl/pincfg-node.yaml"
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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||||
|
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properties:
|
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pins:
|
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|
|
@ -63,7 +54,7 @@ patternProperties:
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sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
|
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qdsd_data3 ]
|
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minItems: 1
|
||||
maxItems: 4
|
||||
maxItems: 16
|
||||
|
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function:
|
||||
description:
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||||
|
|
@ -72,12 +63,12 @@ patternProperties:
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enum: [ adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char,
|
||||
atest_char0, atest_char1, atest_char2, atest_char3, atest_combodac,
|
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atest_gpsadc0, atest_gpsadc1, atest_tsens, atest_wlan0,
|
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atest_wlan1, backlight_en, bimc_dte0, bimc_dte1, blsp1_i2c,
|
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blsp2_i2c, blsp3_i2c, blsp4_i2c, blsp5_i2c, blsp6_i2c, blsp1_spi,
|
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atest_wlan1, backlight_en, bimc_dte0, bimc_dte1, blsp0_i2c, blsp1_i2c,
|
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blsp2_i2c, blsp3_i2c, blsp4_i2c, blsp5_i2c, blsp0_spi, blsp1_spi,
|
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blsp1_spi_cs1, blsp1_spi_cs2, blsp1_spi_cs3, blsp2_spi,
|
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blsp2_spi_cs1, blsp2_spi_cs2, blsp2_spi_cs3, blsp3_spi,
|
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blsp3_spi_cs1, blsp3_spi_cs2, blsp3_spi_cs3, blsp4_spi, blsp5_spi,
|
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blsp6_spi, blsp1_uart, blsp2_uart, blsp1_uim, blsp2_uim, cam1_rst,
|
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blsp0_uart, blsp1_uart, blsp2_uart, blsp1_uim, blsp2_uim, cam1_rst,
|
||||
cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c, cci_timer0,
|
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cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out, display_5v,
|
||||
dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, euro_us, ext_lpass,
|
||||
|
|
@ -92,64 +83,48 @@ patternProperties:
|
|||
qdss_ctitrig_in_b0, qdss_ctitrig_in_b1, qdss_ctitrig_out_a0,
|
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qdss_ctitrig_out_a1, qdss_ctitrig_out_b0, qdss_ctitrig_out_b1,
|
||||
qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
|
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qdss_tracedata_a, qdss_tracedata_b, reset_n, sd_card, sd_write,
|
||||
sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1, uim1, uim2, uim3,
|
||||
uim_batt, wcss_bt, wcss_fm, wcss_wlan, webcam1_rst ]
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
default: 2
|
||||
description:
|
||||
Selects the drive strength for the specified pins, in mA.
|
||||
qdss_tracedata_a, qdss_tracedata_b, qpic_pad, reset_n, sd_card,
|
||||
sd_write, sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1, uim1, uim2,
|
||||
uim3, uim_batt, wcss_bt, wcss_fm, wcss_wlan, webcam1_rst ]
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-disable: true
|
||||
|
||||
drive-strength: true
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,ipq6018-pinctrl";
|
||||
reg = <0x01000000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 80>;
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,ipq6018-pinctrl";
|
||||
reg = <0x01000000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 80>;
|
||||
|
||||
serial3-pinmux {
|
||||
pins = "gpio44", "gpio45";
|
||||
function = "blsp2_uart";
|
||||
drive-strength = <8>;
|
||||
bias-pull-down;
|
||||
};
|
||||
serial3-state {
|
||||
pins = "gpio44", "gpio45";
|
||||
function = "blsp2_uart";
|
||||
drive-strength = <8>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9607-pinctrl.yaml#
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9607-tlmm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. MDM9607 TLMM block
|
||||
|
|
@ -9,12 +9,10 @@ title: Qualcomm Technologies, Inc. MDM9607 TLMM block
|
|||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
MDM9607 platform.
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm MDM9607 SoC.
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
|
|
@ -26,10 +24,10 @@ properties:
|
|||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
'#interrupt-cells': true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
gpio-reserved-ranges: true
|
||||
'#gpio-cells': true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
|
|
@ -40,20 +38,20 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'-state$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-mdm9607-tlmm-state"
|
||||
- patternProperties:
|
||||
".*":
|
||||
$ref: "#/$defs/qcom-mdm9607-tlmm-state"
|
||||
|
||||
'$defs':
|
||||
$defs:
|
||||
qcom-mdm9607-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -115,20 +113,19 @@ patternProperties:
|
|||
|
||||
required:
|
||||
- pins
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,mdm9607-tlmm";
|
||||
reg = <0x01000000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&msmgpio 0 0 80>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,mdm9607-tlmm";
|
||||
reg = <0x01000000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&msmgpio 0 0 80>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
|
@ -1,161 +0,0 @@
|
|||
Qualcomm MDM9615 TLMM block
|
||||
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
MDM9615 platform.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,mdm9615-pinctrl"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the base address and size of the TLMM register space.
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: should specify the TLMM summary IRQ.
|
||||
|
||||
- interrupt-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as an interrupt controller
|
||||
|
||||
- #interrupt-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
- gpio-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as a gpio controller
|
||||
|
||||
- #gpio-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/gpio/gpio.h>
|
||||
|
||||
- gpio-ranges:
|
||||
Usage: required
|
||||
Definition: see ../gpio/gpio.txt
|
||||
|
||||
- gpio-reserved-ranges:
|
||||
Usage: optional
|
||||
Definition: see ../gpio/gpio.txt
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
|
||||
PIN CONFIGURATION NODES:
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function.
|
||||
|
||||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
|
||||
- pins:
|
||||
Usage: required
|
||||
Value type: <string-array>
|
||||
Definition: List of gpio pins affected by the properties specified in
|
||||
this subnode. Valid pins are:
|
||||
gpio0-gpio87
|
||||
|
||||
- function:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Specify the alternative function to be configured for the
|
||||
specified pins.
|
||||
Valid values are:
|
||||
gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart,
|
||||
sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio,
|
||||
cdc_mclk
|
||||
|
||||
- bias-disable:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as no pull.
|
||||
|
||||
- bias-pull-down:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull down.
|
||||
|
||||
- bias-pull-up:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull up.
|
||||
|
||||
- output-high:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
high.
|
||||
|
||||
- output-low:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
low.
|
||||
|
||||
- drive-strength:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Selects the drive strength for the specified pins, in mA.
|
||||
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
|
||||
|
||||
Example:
|
||||
|
||||
msmgpio: pinctrl@800000 {
|
||||
compatible = "qcom,mdm9615-pinctrl";
|
||||
reg = <0x800000 0x4000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&msmgpio 0 0 88>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 16 0x4>;
|
||||
|
||||
gsbi8_uart: gsbi8-uart {
|
||||
mux {
|
||||
pins = "gpio34", "gpio35";
|
||||
function = "gsbi8";
|
||||
};
|
||||
|
||||
tx {
|
||||
pins = "gpio34";
|
||||
drive-strength = <4>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rx {
|
||||
pins = "gpio35";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9615-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. MDM9615 TLMM block
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description: Top Level Mode Multiplexer pin controller in Qualcomm MDM9615 SoC.
|
||||
|
||||
$ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdm9615-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
'#interrupt-cells': true
|
||||
gpio-controller: true
|
||||
'#gpio-cells': true
|
||||
gpio-ranges: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-mdm9615-pinctrl-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-mdm9615-pinctrl-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
pattern: "^gpio([0-9]|[1-7][0-9]|8[0-7])$"
|
||||
minItems: 1
|
||||
maxItems: 16
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
|
||||
enum: [ gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart,
|
||||
sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio, cdc_mclk, ]
|
||||
|
||||
bias-disable: true
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
drive-strength: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
input-enable: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,mdm9615-pinctrl";
|
||||
reg = <0x01000000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&msmgpio 0 0 88>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
gsbi3-state {
|
||||
pins = "gpio8", "gpio9", "gpio10", "gpio11";
|
||||
function = "gsbi3";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
gsbi5-i2c-state {
|
||||
sda-pins {
|
||||
pins = "gpio16";
|
||||
function = "gsbi5_i2c";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio17";
|
||||
function = "gsbi5_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -9,9 +9,8 @@ title: Qualcomm Technologies, Inc. MSM8226 TLMM block
|
|||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
MSM8226 platform.
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm MSM8226 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -21,38 +20,32 @@ properties:
|
|||
description: Specifies the base address and size of the TLMM register space
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: Specifies the TLMM summary IRQ
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
description: Specifies the PIN numbers and Flags, as defined in
|
||||
include/dt-bindings/interrupt-controller/irq.h
|
||||
const: 2
|
||||
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
maxItems: 1
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-msm8226-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-msm8226-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-msm8226-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: "/schemas/pinctrl/pincfg-node.yaml"
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -71,65 +64,51 @@ patternProperties:
|
|||
Specify the alternative function to be configured for the specified
|
||||
pins. Functions are only valid for gpio pins.
|
||||
enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
|
||||
blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c5, blsp_spi1,
|
||||
blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_spi1,
|
||||
blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
|
||||
blsp_uart3, blsp_uart5, cam_mclk0, cam_mclk1, wlan ]
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
default: 2
|
||||
description:
|
||||
Selects the drive strength for the specified pins, in mA.
|
||||
blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1, sdc3,
|
||||
wlan ]
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-disable: true
|
||||
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
msmgpio: pinctrl@fd510000 {
|
||||
compatible = "qcom,msm8226-pinctrl";
|
||||
reg = <0xfd510000 0x4000>;
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
msmgpio: pinctrl@fd510000 {
|
||||
compatible = "qcom,msm8226-pinctrl";
|
||||
reg = <0xfd510000 0x4000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&msmgpio 0 0 117>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&msmgpio 0 0 117>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
serial-pins {
|
||||
pins = "gpio8", "gpio9";
|
||||
function = "blsp_uart3";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
serial-state {
|
||||
pins = "gpio8", "gpio9";
|
||||
function = "blsp_uart3";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,8 +10,7 @@ maintainers:
|
|||
- Stephan Gerhold <stephan@gerhold.net>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer (TLMM) block found
|
||||
in the MSM8909 platform.
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm MSM8909 SoC.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
|
@ -25,10 +24,10 @@ properties:
|
|||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
'#interrupt-cells': true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
gpio-reserved-ranges: true
|
||||
'#gpio-cells': true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
|
|
@ -39,12 +38,13 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'-state$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-msm8909-tlmm-state"
|
||||
- patternProperties:
|
||||
".*":
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-msm8909-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-msm8909-tlmm-state:
|
||||
|
|
@ -52,7 +52,7 @@ $defs:
|
|||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -112,41 +112,40 @@ $defs:
|
|||
|
||||
required:
|
||||
- pins
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pinctrl@1000000 {
|
||||
compatible = "qcom,msm8909-tlmm";
|
||||
reg = <0x1000000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 117>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
pinctrl@1000000 {
|
||||
compatible = "qcom,msm8909-tlmm";
|
||||
reg = <0x1000000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 117>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
gpio-wo-subnode-state {
|
||||
pins = "gpio1";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
uart-w-subnodes-state {
|
||||
rx {
|
||||
pins = "gpio4";
|
||||
function = "blsp_uart1";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
tx {
|
||||
pins = "gpio5";
|
||||
function = "blsp_uart1";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
gpio-wo-subnode-state {
|
||||
pins = "gpio1";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
uart-w-subnodes-state {
|
||||
rx-pins {
|
||||
pins = "gpio4";
|
||||
function = "blsp_uart1";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
tx-pins {
|
||||
pins = "gpio5";
|
||||
function = "blsp_uart1";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
|
|||
|
|
@ -9,9 +9,8 @@ title: Qualcomm Technologies, Inc. MSM8953 TLMM block
|
|||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
MSM8953 platform.
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm MSM8953 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -20,38 +19,30 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: Specifies the TLMM summary IRQ
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
description:
|
||||
Specifies the PIN numbers and Flags, as defined in defined in
|
||||
include/dt-bindings/interrupt-controller/irq.h
|
||||
const: 2
|
||||
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
||||
gpio-reserved-ranges: true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
|
||||
'#gpio-cells':
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-msm8953-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-msm8953-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-msm8953-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: "/schemas/pinctrl/pincfg-node.yaml"
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -113,60 +104,44 @@ patternProperties:
|
|||
uim_batt, us_emitter, us_euro, wcss_bt, wcss_fm, wcss_wlan,
|
||||
wcss_wlan0, wcss_wlan1, wcss_wlan2, wsa_en, wsa_io, wsa_irq ]
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
default: 2
|
||||
description:
|
||||
Selects the drive strength for the specified pins, in mA.
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-disable: true
|
||||
|
||||
drive-strength: true
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,msm8953-pinctrl";
|
||||
reg = <0x01000000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 142>;
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,msm8953-pinctrl";
|
||||
reg = <0x01000000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 142>;
|
||||
|
||||
serial_default: serial-pins {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "blsp_uart2";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
serial_default: serial-state {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "blsp_uart2";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,121 +0,0 @@
|
|||
Qualcomm MSM8974 TLMM block
|
||||
|
||||
Required properties:
|
||||
- compatible: "qcom,msm8974-pinctrl"
|
||||
- reg: Should be the base address and length of the TLMM block.
|
||||
- interrupts: Should be the parent IRQ of the TLMM block.
|
||||
- interrupt-controller: Marks the device node as an interrupt controller.
|
||||
- #interrupt-cells: Should be two.
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
- #gpio-cells : Should be two.
|
||||
The first cell is the gpio pin number and the
|
||||
second cell is used for optional parameters.
|
||||
- gpio-ranges: see ../gpio/gpio.txt
|
||||
|
||||
Optional properties:
|
||||
|
||||
- gpio-reserved-ranges: see ../gpio/gpio.txt
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function.
|
||||
|
||||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength.
|
||||
|
||||
Non-empty subnodes must specify the 'pins' property.
|
||||
Note that not all properties are valid for all pins.
|
||||
|
||||
|
||||
Valid values for pins are:
|
||||
gpio0-gpio145
|
||||
Supports mux, bias and drive-strength
|
||||
|
||||
sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data
|
||||
Supports bias and drive-strength
|
||||
|
||||
hsic_data, hsic_strobe
|
||||
Supports only mux
|
||||
|
||||
Valid values for function are:
|
||||
cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm,
|
||||
blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1,
|
||||
blsp_uim2, blsp_uart2, blsp_i2c2, blsp_spi2,
|
||||
blsp_uim3, blsp_uart3, blsp_i2c3, blsp_spi3,
|
||||
blsp_uim4, blsp_uart4, blsp_i2c4, blsp_spi4,
|
||||
blsp_uim5, blsp_uart5, blsp_i2c5, blsp_spi5,
|
||||
blsp_uim6, blsp_uart6, blsp_i2c6, blsp_spi6,
|
||||
blsp_uim7, blsp_uart7, blsp_i2c7, blsp_spi7,
|
||||
blsp_uim8, blsp_uart8, blsp_i2c8, blsp_spi8,
|
||||
blsp_uim9, blsp_uart9, blsp_i2c9, blsp_spi9,
|
||||
blsp_uim10, blsp_uart10, blsp_i2c10, blsp_spi10,
|
||||
blsp_uim11, blsp_uart11, blsp_i2c11, blsp_spi11,
|
||||
blsp_uim12, blsp_uart12, blsp_i2c12, blsp_spi12,
|
||||
blsp_spi1_cs1, blsp_spi2_cs2, blsp_spi_cs3, blsp_spi2_cs1, blsp_spi2_cs2
|
||||
blsp_spi2_cs3, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3,
|
||||
sdc3, sdc4, gcc_gp_clk1, gcc_gp_clk2, gcc_gp_clk3, cci_timer0, cci_timer1,
|
||||
cci_timer2, cci_timer3, cci_async_in0, cci_async_in1, cci_async_in2,
|
||||
cam_mckl0, cam_mclk1, cam_mclk2, cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc,
|
||||
hdmi_hpd, edp_hpd, gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk,
|
||||
gp_mn, tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s, spkr_mi2s,
|
||||
ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, hsic_ctl, gpio
|
||||
|
||||
(Note that this is not yet the complete list of functions)
|
||||
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
msmgpio: pinctrl@fd510000 {
|
||||
compatible = "qcom,msm8974-pinctrl";
|
||||
reg = <0xfd510000 0x4000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&msmgpio 0 0 146>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 208 0>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_default>;
|
||||
|
||||
uart2_default: uart2_default {
|
||||
mux {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "blsp_uart2";
|
||||
};
|
||||
|
||||
tx {
|
||||
pins = "gpio4";
|
||||
drive-strength = <4>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rx {
|
||||
pins = "gpio5";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,179 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8974-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm MSM8974 TLMM pin controller
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm MSM8974 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,msm8974-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 73
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 146
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-msm8974-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-msm8974-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-msm8974-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-5])$"
|
||||
- enum: [ hsic_data, hsic_strobe, sdc1_clk, sdc1_cmd, sdc1_data,
|
||||
sdc2_clk, sdc2_cmd, sdc2_data ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
|
||||
enum: [ gpio, cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm,
|
||||
blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1, blsp_uim2,
|
||||
blsp_uart2, blsp_i2c2, blsp_spi2, blsp_uim3, blsp_uart3,
|
||||
blsp_i2c3, blsp_spi3, blsp_uim4, blsp_uart4, blsp_i2c4,
|
||||
blsp_spi4, blsp_uim5, blsp_uart5, blsp_i2c5, blsp_spi5,
|
||||
blsp_uim6, blsp_uart6, blsp_i2c6, blsp_spi6, blsp_uim7,
|
||||
blsp_uart7, blsp_i2c7, blsp_spi7, blsp_uim8, blsp_uart8,
|
||||
blsp_i2c8, blsp_spi8, blsp_uim9, blsp_uart9, blsp_i2c9,
|
||||
blsp_spi9, blsp_uim10, blsp_uart10, blsp_i2c10, blsp_spi10,
|
||||
blsp_uim11, blsp_uart11, blsp_i2c11, blsp_spi11, blsp_uim12,
|
||||
blsp_uart12, blsp_i2c12, blsp_spi12, blsp_spi1_cs1,
|
||||
blsp_spi2_cs2, blsp_spi_cs3, blsp_spi2_cs1, blsp_spi2_cs2
|
||||
blsp_spi2_cs3, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3,
|
||||
sdc3, sdc4, gcc_gp_clk1, gcc_gp_clk2, gcc_gp_clk3, cci_timer0,
|
||||
cci_timer1, cci_timer2, cci_timer3, cci_async_in0,
|
||||
cci_async_in1, cci_async_in2, cam_mckl0, cam_mclk1, cam_mclk2,
|
||||
cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc, hdmi_hpd, edp_hpd,
|
||||
gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk, gp_mn,
|
||||
tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s,
|
||||
spkr_mi2s, ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, hsic_ctl ]
|
||||
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
bias-disable: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
pins:
|
||||
contains:
|
||||
enum:
|
||||
- hsic_data
|
||||
- hsic_strobe
|
||||
required:
|
||||
- pins
|
||||
then:
|
||||
properties:
|
||||
bias-pull-down: false
|
||||
bias-pull-up: false
|
||||
bias-disable: false
|
||||
drive-strength: false
|
||||
input-enable: false
|
||||
output-high: false
|
||||
output-low: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
tlmm: pinctrl@fd510000 {
|
||||
compatible = "qcom,msm8974-pinctrl";
|
||||
reg = <0xfd510000 0x4000>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&tlmm 0 0 146>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
sdc1-off-state {
|
||||
clk-pins {
|
||||
pins = "sdc1_clk";
|
||||
bias-disable;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
cmd-pins {
|
||||
pins = "sdc1_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "sdc1_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
blsp2-uart1-sleep-state {
|
||||
pins = "gpio41", "gpio42", "gpio43", "gpio44";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
hsic-state {
|
||||
pins = "hsic_data", "hsic_strobe";
|
||||
};
|
||||
};
|
||||
|
|
@ -1,186 +0,0 @@
|
|||
Qualcomm MSM8994 TLMM block
|
||||
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
MSM8994 platform.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Should contain one of:
|
||||
"qcom,msm8992-pinctrl",
|
||||
"qcom,msm8994-pinctrl".
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the base address and size of the TLMM register space.
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: should specify the TLMM summary IRQ.
|
||||
|
||||
- interrupt-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as an interrupt controller
|
||||
|
||||
- #interrupt-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
- gpio-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as a gpio controller
|
||||
|
||||
- #gpio-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/gpio/gpio.h>
|
||||
|
||||
- gpio-ranges:
|
||||
Usage: required
|
||||
Definition: see ../gpio/gpio.txt
|
||||
|
||||
- gpio-reserved-ranges:
|
||||
Usage: optional
|
||||
Definition: see ../gpio/gpio.txt
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
|
||||
PIN CONFIGURATION NODES:
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function.
|
||||
|
||||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
|
||||
- pins:
|
||||
Usage: required
|
||||
Value type: <string-array>
|
||||
Definition: List of gpio pins affected by the properties specified in
|
||||
this subnode.
|
||||
|
||||
Valid pins are:
|
||||
gpio0-gpio145
|
||||
Supports mux, bias and drive-strength
|
||||
|
||||
sdc1_clk, sdc1_cmd, sdc1_data sdc1_rclk, sdc2_clk,
|
||||
sdc2_cmd, sdc2_data
|
||||
Supports bias and drive-strength
|
||||
|
||||
- function:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Specify the alternative function to be configured for the
|
||||
specified pins. Functions are only valid for gpio pins.
|
||||
Valid values are:
|
||||
|
||||
audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
|
||||
blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_i2c9, blsp_i2c10, blsp_i2c11,
|
||||
blsp_i2c12, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3,
|
||||
blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3,
|
||||
blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9,
|
||||
blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3, blsp_spi11,
|
||||
blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3, blsp_uart4, blsp_uart5,
|
||||
blsp_uart6, blsp_uart7, blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11,
|
||||
blsp_uart12, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
|
||||
blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, blsp_uim11,
|
||||
blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b, blsp11_uart_rx_b,
|
||||
blsp11_uart_tx_b, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3,
|
||||
cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c0, cci_i2c1,
|
||||
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
|
||||
gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a,
|
||||
gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk,
|
||||
gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd, hdmi_rcv,
|
||||
mdp_vsync, mss_lte, nav_pps, nav_tsync, qdss_cti_trig_in_a,
|
||||
qdss_cti_trig_in_b, qdss_cti_trig_in_c, qdss_cti_trig_in_d,
|
||||
qdss_cti_trig_out_a, qdss_cti_trig_out_b, qdss_cti_trig_out_c,
|
||||
qdss_cti_trig_out_d, qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
|
||||
qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0,
|
||||
pci_e1, pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1,
|
||||
tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4, gpio
|
||||
|
||||
- bias-disable:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as no pull.
|
||||
|
||||
- bias-pull-down:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull down.
|
||||
|
||||
- bias-pull-up:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull up.
|
||||
|
||||
- output-high:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
high.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- output-low:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
low.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- drive-strength:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Selects the drive strength for the specified pins, in mA.
|
||||
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
|
||||
|
||||
Example:
|
||||
|
||||
msmgpio: pinctrl@fd510000 {
|
||||
compatible = "qcom,msm8994-pinctrl";
|
||||
reg = <0xfd510000 0x4000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&msmgpio 0 0 146>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
blsp1_uart2_default: blsp1_uart2_default {
|
||||
pinmux {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "blsp_uart2";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio4", "gpio5";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8994-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm MSM8994 TLMM pin controller
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm MSM8994 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,msm8992-pinctrl
|
||||
- qcom,msm8994-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 75
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 150
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-msm8994-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-msm8994-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-msm8994-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
|
||||
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
|
||||
sdc2_cmd, sdc2_data, sdc3_clk, sdc3_cmd, sdc3_data ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
|
||||
enum: [ gpio, audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3,
|
||||
blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
|
||||
blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1,
|
||||
blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2,
|
||||
blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3,
|
||||
blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8,
|
||||
blsp_spi9, blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2,
|
||||
blsp_spi10_cs3, blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2,
|
||||
blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7,
|
||||
blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
|
||||
blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
|
||||
blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
|
||||
blsp_uim11, blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b,
|
||||
blsp11_uart_rx_b, blsp11_uart_tx_b, cam_mclk0, cam_mclk1,
|
||||
cam_mclk2, cam_mclk3, cci_async_in0, cci_async_in1,
|
||||
cci_async_in2, cci_i2c0, cci_i2c1, cci_timer0, cci_timer1,
|
||||
cci_timer2, cci_timer3, cci_timer4, gcc_gp1_clk_a,
|
||||
gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a,
|
||||
gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk,
|
||||
gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd,
|
||||
hdmi_rcv, mdp_vsync, mss_lte, nav_pps, nav_tsync,
|
||||
qdss_cti_trig_in_a, qdss_cti_trig_in_b, qdss_cti_trig_in_c,
|
||||
qdss_cti_trig_in_d, qdss_cti_trig_out_a, qdss_cti_trig_out_b,
|
||||
qdss_cti_trig_out_c, qdss_cti_trig_out_d, qdss_traceclk_a,
|
||||
qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
|
||||
qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0, pci_e1,
|
||||
pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1,
|
||||
tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4 ]
|
||||
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
bias-disable: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
tlmm: pinctrl@fd510000 {
|
||||
compatible = "qcom,msm8994-pinctrl";
|
||||
reg = <0xfd510000 0x4000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&tlmm 0 0 146>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
blsp1-uart2-default-state {
|
||||
function = "blsp_uart2";
|
||||
pins = "gpio4", "gpio5";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp1-spi1-default-state {
|
||||
default-pins {
|
||||
pins = "gpio0", "gpio1", "gpio3";
|
||||
function = "blsp_spi1";
|
||||
drive-strength = <10>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cs-pins {
|
||||
pins = "gpio8";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,208 +0,0 @@
|
|||
Qualcomm MSM8996 TLMM block
|
||||
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
MSM8996 platform.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,msm8996-pinctrl"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the base address and size of the TLMM register space.
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: should specify the TLMM summary IRQ.
|
||||
|
||||
- interrupt-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as an interrupt controller
|
||||
|
||||
- #interrupt-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
- gpio-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as a gpio controller
|
||||
|
||||
- #gpio-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/gpio/gpio.h>
|
||||
|
||||
- gpio-ranges:
|
||||
Usage: required
|
||||
Definition: see ../gpio/gpio.txt
|
||||
|
||||
- gpio-reserved-ranges:
|
||||
Usage: optional
|
||||
Definition: see ../gpio/gpio.txt
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
|
||||
PIN CONFIGURATION NODES:
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function.
|
||||
|
||||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
|
||||
- pins:
|
||||
Usage: required
|
||||
Value type: <string-array>
|
||||
Definition: List of gpio pins affected by the properties specified in
|
||||
this subnode.
|
||||
|
||||
Valid pins are:
|
||||
gpio0-gpio149
|
||||
Supports mux, bias and drive-strength
|
||||
|
||||
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
|
||||
sdc2_data sdc1_rclk
|
||||
Supports bias and drive-strength
|
||||
|
||||
- function:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Specify the alternative function to be configured for the
|
||||
specified pins. Functions are only valid for gpio pins.
|
||||
Valid values are:
|
||||
|
||||
blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
|
||||
bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
|
||||
qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
|
||||
dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
|
||||
blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
|
||||
mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
|
||||
atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
|
||||
cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
|
||||
pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
|
||||
qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
|
||||
qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
|
||||
atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
|
||||
atest_usb20, atest_char0, dac_calib10, qdss_stm10,
|
||||
qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
|
||||
blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
|
||||
qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
|
||||
qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
|
||||
dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
|
||||
qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
|
||||
dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
|
||||
dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
|
||||
dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
|
||||
dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
|
||||
sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
|
||||
qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
|
||||
uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
|
||||
blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
|
||||
qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
|
||||
blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
|
||||
cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
|
||||
blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
|
||||
qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
|
||||
isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
|
||||
qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
|
||||
sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
|
||||
gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
|
||||
qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
|
||||
tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
|
||||
qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
|
||||
sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
|
||||
sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
|
||||
ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
|
||||
blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
|
||||
pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
|
||||
qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
|
||||
qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
|
||||
gpio
|
||||
|
||||
- bias-disable:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as no pull.
|
||||
|
||||
- bias-pull-down:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull down.
|
||||
|
||||
- bias-pull-up:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull up.
|
||||
|
||||
- output-high:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
high.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- output-low:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
low.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- drive-strength:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Selects the drive strength for the specified pins, in mA.
|
||||
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
|
||||
|
||||
Example:
|
||||
|
||||
tlmm: pinctrl@1010000 {
|
||||
compatible = "qcom,msm8996-pinctrl";
|
||||
reg = <0x01010000 0x300000>;
|
||||
interrupts = <0 208 0>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&tlmm 0 0 150>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
uart_console_active: uart_console_active {
|
||||
mux {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "blsp_uart8";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio4", "gpio5";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,182 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8996-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm MSM8996 TLMM pin controller
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm MSM8996 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,msm8996-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 75
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 150
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-msm8996-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-msm8996-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-msm8996-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
|
||||
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
|
||||
sdc2_cmd, sdc2_data ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
|
||||
enum: [ gpio, blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
|
||||
bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
|
||||
qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
|
||||
dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
|
||||
blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
|
||||
mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
|
||||
atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio,
|
||||
atest_char, cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8,
|
||||
qdss_tracedata_b, pll_reset, qdss_stm6, qdss_stm5, qdss_stm4,
|
||||
atest_usb2, cci_i2c, qdss_stm3, dac_calib3, atest_usb23,
|
||||
atest_char3, dac_calib4, qdss_stm2, atest_usb22, atest_char2,
|
||||
qdss_stm1, dac_calib5, atest_usb21, atest_char1, dbg_out,
|
||||
qdss_stm0, dac_calib6, atest_usb20, atest_char0, dac_calib10,
|
||||
qdss_stm10, qdss_cti_trig_in_a, cci_timer4, blsp_spi6,
|
||||
blsp_uart6, blsp_uim6, blsp2_spi, qdss_stm9,
|
||||
qdss_cti_trig_out_a, dac_calib11, qdss_stm8, cci_timer0,
|
||||
qdss_stm13, dac_calib7, cci_timer1, qdss_stm12, dac_calib8,
|
||||
cci_timer2, blsp1_spi, qdss_stm11, dac_calib9, cci_timer3,
|
||||
cci_async, dac_calib12, blsp_i2c6, qdss_tracectl_a,
|
||||
dac_calib13, qdss_traceclk_a, dac_calib14, dac_calib15,
|
||||
hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, dac_calib17,
|
||||
hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, dac_calib19,
|
||||
hdmi_hot, dac_calib20, dac_calib21, pci_e0, dac_calib22,
|
||||
dac_calib23, dac_calib24, tsif1_sync, dac_calib25, sd_write,
|
||||
tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, qdss_cti,
|
||||
blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, uim3,
|
||||
blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
|
||||
blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
|
||||
qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11,
|
||||
blsp_uart11, blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a,
|
||||
blsp_i2c11, cri_trng0, cri_trng1, cri_trng, qdss_stm18,
|
||||
pri_mi2s, qdss_stm17, blsp_spi4, blsp_uart4, blsp_uim4,
|
||||
qdss_stm16, qdss_stm15, blsp_i2c4, qdss_stm14, dac_calib26,
|
||||
spkr_i2s, audio_ref, lpass_slimbus, isense_dbg, tsense_pwm1,
|
||||
tsense_pwm2, btfm_slimbus, ter_mi2s, qdss_stm22, qdss_stm21,
|
||||
qdss_stm20, qdss_stm19, gcc_gp1_clk_b, sec_mi2s, blsp_spi5,
|
||||
blsp_uart5, blsp_uim5, gcc_gp2_clk_b, gcc_gp3_clk_b, blsp_i2c5,
|
||||
blsp_spi12, blsp_uart12, blsp_uim12, qdss_stm25, qdss_stm31,
|
||||
blsp_i2c12, qdss_stm30, qdss_stm29, tsif1_clk, qdss_stm28,
|
||||
tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, qdss_traceclk_b,
|
||||
tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, sdc4_clk,
|
||||
qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
|
||||
sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
|
||||
ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b,
|
||||
blsp11_uart_rx_b, blsp11_i2c_sda_b, prng_rosc,
|
||||
blsp11_i2c_scl_b, uim2, uim1, uim_batt, pci_e2, pa_indicator,
|
||||
adsp_ext, ddr_bist, qdss_tracedata_11, qdss_tracedata_12,
|
||||
modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, qspi_cs, ssbi2,
|
||||
ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3 ]
|
||||
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
bias-disable: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
tlmm: pinctrl@1010000 {
|
||||
compatible = "qcom,msm8996-pinctrl";
|
||||
reg = <0x01010000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&tlmm 0 0 150>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
blsp1-spi1-default-state {
|
||||
spi-pins {
|
||||
pins = "gpio0", "gpio1", "gpio3";
|
||||
function = "blsp_spi1";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cs-pins {
|
||||
pins = "gpio2";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
blsp1-spi1-sleep-state {
|
||||
pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,202 +0,0 @@
|
|||
Qualcomm MSM8998 TLMM block
|
||||
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
MSM8998 platform.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,msm8998-pinctrl"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the base address and size of the TLMM register space.
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: should specify the TLMM summary IRQ.
|
||||
|
||||
- interrupt-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as an interrupt controller
|
||||
|
||||
- #interrupt-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
- gpio-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as a gpio controller
|
||||
|
||||
- #gpio-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/gpio/gpio.h>
|
||||
|
||||
- gpio-ranges:
|
||||
Usage: required
|
||||
Definition: see ../gpio/gpio.txt
|
||||
|
||||
- gpio-reserved-ranges:
|
||||
Usage: optional
|
||||
Definition: see ../gpio/gpio.txt
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
|
||||
PIN CONFIGURATION NODES:
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function.
|
||||
|
||||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
|
||||
- pins:
|
||||
Usage: required
|
||||
Value type: <string-array>
|
||||
Definition: List of gpio pins affected by the properties specified in
|
||||
this subnode.
|
||||
|
||||
Valid pins are:
|
||||
gpio0-gpio149
|
||||
Supports mux, bias and drive-strength
|
||||
|
||||
sdc2_clk, sdc2_cmd, sdc2_data
|
||||
Supports bias and drive-strength
|
||||
|
||||
ufs_reset
|
||||
Supports bias and drive-strength
|
||||
|
||||
- function:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Specify the alternative function to be configured for the
|
||||
specified pins. Functions are only valid for gpio pins.
|
||||
Valid values are:
|
||||
|
||||
gpio, adsp_ext, agera_pll, atest_char, atest_gpsadc0,
|
||||
atest_gpsadc1, atest_tsens, atest_tsens2, atest_usb1,
|
||||
atest_usb10, atest_usb11, atest_usb12, atest_usb13,
|
||||
audio_ref, bimc_dte0, bimc_dte1, blsp10_spi, blsp10_spi_a,
|
||||
blsp10_spi_b, blsp11_i2c, blsp1_spi, blsp1_spi_a,
|
||||
blsp1_spi_b, blsp2_spi, blsp9_spi, blsp_i2c1, blsp_i2c2,
|
||||
blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7,
|
||||
blsp_i2c8, blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
|
||||
blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
|
||||
blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
|
||||
blsp_spi11, blsp_spi12, blsp_uart1_a, blsp_uart1_b,
|
||||
blsp_uart2_a, blsp_uart2_b, blsp_uart3_a, blsp_uart3_b,
|
||||
blsp_uart7_a, blsp_uart7_b, blsp_uart8, blsp_uart8_a,
|
||||
blsp_uart8_b, blsp_uart9_a, blsp_uart9_b, blsp_uim1_a,
|
||||
blsp_uim1_b, blsp_uim2_a, blsp_uim2_b, blsp_uim3_a,
|
||||
blsp_uim3_b, blsp_uim7_a, blsp_uim7_b, blsp_uim8_a,
|
||||
blsp_uim8_b, blsp_uim9_a, blsp_uim9_b, bt_reset,
|
||||
btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
|
||||
cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
|
||||
cri_trng0, cri_trng1, dbg_out, ddr_bist, edp_hot, edp_lcd,
|
||||
gcc_gp1_a, gcc_gp1_b, gcc_gp2_a, gcc_gp2_b, gcc_gp3_a,
|
||||
gcc_gp3_b, hdmi_cec, hdmi_ddc, hdmi_hot, hdmi_rcv,
|
||||
isense_dbg, jitter_bist, ldo_en, ldo_update, lpass_slimbus,
|
||||
m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
|
||||
mdp_vsync3, mdp_vsync_a, mdp_vsync_b, modem_tsync, mss_lte,
|
||||
nav_dr, nav_pps, pa_indicator, pci_e0, phase_flag,
|
||||
pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc,
|
||||
pwr_crypto, pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b,
|
||||
qdss_cti1_a, qdss_cti1_b, qdss, qlink_enable,
|
||||
qlink_request, qua_mi2s, sd_card, sd_write, sdc40, sdc41,
|
||||
sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu,
|
||||
spkr_i2s, ssbi1, ssc_irq, ter_mi2s, tgu_ch0, tgu_ch1,
|
||||
tsense_pwm1, tsense_pwm2, tsif0, tsif1,
|
||||
uim1_clk, uim1_data, uim1_present,
|
||||
uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
|
||||
uim_batt, usb_phy, vfr_1, vsense_clkout, vsense_data0,
|
||||
vsense_data1, vsense_mode, wlan1_adc0, wlan1_adc1,
|
||||
wlan2_adc0, wlan2_adc1,
|
||||
|
||||
- bias-disable:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as no pull.
|
||||
|
||||
- bias-pull-down:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull down.
|
||||
|
||||
- bias-pull-up:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull up.
|
||||
|
||||
- output-high:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
high.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- output-low:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
low.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- drive-strength:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Selects the drive strength for the specified pins, in mA.
|
||||
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
|
||||
|
||||
Example:
|
||||
|
||||
tlmm: pinctrl@03400000 {
|
||||
compatible = "qcom,msm8998-pinctrl";
|
||||
reg = <0x03400000 0xc00000>;
|
||||
interrupts = <0 208 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 175>;
|
||||
gpio-reserved-ranges = <0 4>, <81 4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
uart_console_active: uart_console_active {
|
||||
mux {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "blsp_uart8_a";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio4", "gpio5";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,171 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8998-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm MSM8998 TLMM pin controller
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm MSM8998 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,msm8998-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 75
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 150
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-msm8998-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-msm8998-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-msm8998-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
|
||||
- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
|
||||
enum: [ gpio, adsp_ext, agera_pll, atest_char, atest_gpsadc0,
|
||||
atest_gpsadc1, atest_tsens, atest_tsens2, atest_usb1,
|
||||
atest_usb10, atest_usb11, atest_usb12, atest_usb13, audio_ref,
|
||||
bimc_dte0, bimc_dte1, blsp10_spi, blsp10_spi_a, blsp10_spi_b,
|
||||
blsp11_i2c, blsp1_spi, blsp1_spi_a, blsp1_spi_b, blsp2_spi,
|
||||
blsp9_spi, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4,
|
||||
blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_i2c9,
|
||||
blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1, blsp_spi2,
|
||||
blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7,
|
||||
blsp_spi8, blsp_spi9, blsp_spi10, blsp_spi11, blsp_spi12,
|
||||
blsp_uart1_a, blsp_uart1_b, blsp_uart2_a, blsp_uart2_b,
|
||||
blsp_uart3_a, blsp_uart3_b, blsp_uart7_a, blsp_uart7_b,
|
||||
blsp_uart8, blsp_uart8_a, blsp_uart8_b, blsp_uart9_a,
|
||||
blsp_uart9_b, blsp_uim1_a, blsp_uim1_b, blsp_uim2_a,
|
||||
blsp_uim2_b, blsp_uim3_a, blsp_uim3_b, blsp_uim7_a,
|
||||
blsp_uim7_b, blsp_uim8_a, blsp_uim8_b, blsp_uim9_a,
|
||||
blsp_uim9_b, bt_reset, btfm_slimbus, cam_mclk, cci_async,
|
||||
cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
|
||||
cci_timer4, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
|
||||
edp_hot, edp_lcd, gcc_gp1_a, gcc_gp1_b, gcc_gp2_a, gcc_gp2_b,
|
||||
gcc_gp3_a, gcc_gp3_b, hdmi_cec, hdmi_ddc, hdmi_hot, hdmi_rcv,
|
||||
isense_dbg, jitter_bist, ldo_en, ldo_update, lpass_slimbus,
|
||||
m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
|
||||
mdp_vsync3, mdp_vsync_a, mdp_vsync_b, modem_tsync, mss_lte,
|
||||
nav_dr, nav_pps, pa_indicator, pci_e0, phase_flag,
|
||||
pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc,
|
||||
pwr_crypto, pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b,
|
||||
qdss_cti1_a, qdss_cti1_b, qdss, qlink_enable, qlink_request,
|
||||
qua_mi2s, sd_card, sd_write, sdc40, sdc41, sdc42, sdc43,
|
||||
sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ssbi1, ssc_irq,
|
||||
ter_mi2s, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, tsif0,
|
||||
tsif1, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
|
||||
uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1,
|
||||
vsense_clkout, vsense_data0, vsense_data1, vsense_mode,
|
||||
wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
|
||||
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
bias-disable: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
tlmm: pinctrl@3400000 {
|
||||
compatible = "qcom,msm8998-pinctrl";
|
||||
reg = <0x03400000 0xc00000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-ranges = <&tlmm 0 0 150>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-reserved-ranges = <0 4>, <81 4>;
|
||||
|
||||
sdc2-off-state {
|
||||
clk-pins {
|
||||
pins = "sdc2_clk";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cmd-pins {
|
||||
pins = "sdc2_cmd";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "sdc2_data";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdc2-cd-state {
|
||||
pins = "gpio95";
|
||||
function = "gpio";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,qcm2290-pinctrl.yaml#
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,qcm2290-tlmm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. QCM2290 TLMM block
|
||||
|
|
@ -10,8 +10,7 @@ maintainers:
|
|||
- Shawn Guo <shawn.guo@linaro.org>
|
||||
|
||||
description:
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
QCM2290 platform.
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm QCM2290 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -20,46 +19,30 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: Specifies the TLMM summary IRQ
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
description:
|
||||
Specifies the PIN numbers and Flags, as defined in defined in
|
||||
include/dt-bindings/interrupt-controller/irq.h
|
||||
const: 2
|
||||
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-state$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-qcm2290-tlmm-state"
|
||||
- patternProperties:
|
||||
".*":
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-qcm2290-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
'$defs':
|
||||
$defs:
|
||||
qcom-qcm2290-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -96,20 +79,11 @@ patternProperties:
|
|||
uim2_data, uim2_present, uim2_reset, usb_phy, vfr_1,
|
||||
vsense_trigger, wlan1_adc0, wlan1_adc1 ]
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
default: 2
|
||||
description:
|
||||
Selects the drive strength for the specified pins, in mA.
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-disable: true
|
||||
|
||||
drive-strength: true
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
|
|
@ -118,17 +92,11 @@ patternProperties:
|
|||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
@ -146,19 +114,19 @@ examples:
|
|||
gpio-ranges = <&tlmm 0 0 127>;
|
||||
|
||||
sdc2_on_state: sdc2-on-state {
|
||||
clk {
|
||||
clk-pins {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
|
||||
cmd {
|
||||
cmd-pins {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
data {
|
||||
data-pins {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
|
|
@ -1,187 +0,0 @@
|
|||
Qualcomm Technologies, Inc. SC7180 TLMM block
|
||||
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
SC7180 platform.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,sc7180-pinctrl"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the base address and size of the north, south and west
|
||||
TLMM tiles
|
||||
|
||||
- reg-names:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: names for the cells of reg, must contain "north", "south"
|
||||
and "west".
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: should specify the TLMM summary IRQ.
|
||||
|
||||
- interrupt-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as an interrupt controller
|
||||
|
||||
- #interrupt-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
- gpio-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as a gpio controller
|
||||
|
||||
- #gpio-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/gpio/gpio.h>
|
||||
|
||||
- gpio-ranges:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: see ../gpio/gpio.txt
|
||||
|
||||
- gpio-reserved-ranges:
|
||||
Usage: optional
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: see ../gpio/gpio.txt
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
|
||||
PIN CONFIGURATION NODES:
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function.
|
||||
|
||||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
|
||||
- pins:
|
||||
Usage: required
|
||||
Value type: <string-array>
|
||||
Definition: List of gpio pins affected by the properties specified in
|
||||
this subnode.
|
||||
|
||||
Valid pins are:
|
||||
gpio0-gpio118
|
||||
Supports mux, bias and drive-strength
|
||||
|
||||
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
|
||||
sdc2_data sdc1_rclk
|
||||
Supports bias and drive-strength
|
||||
|
||||
ufs_reset
|
||||
Supports bias and drive-strength
|
||||
|
||||
- function:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Specify the alternative function to be configured for the
|
||||
specified pins. Functions are only valid for gpio pins.
|
||||
Valid values are:
|
||||
|
||||
adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,
|
||||
atest_char1, atest_char2, atest_char3, atest_tsens,
|
||||
atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
|
||||
atest_usb12, atest_usb13, atest_usb2, atest_usb20,
|
||||
atest_usb21, atest_usb22, atest_usb23, audio_ref,
|
||||
btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
|
||||
cci_timer1, cci_timer2, cci_timer3, cci_timer4,
|
||||
cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
|
||||
ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1, gcc_gp2,
|
||||
gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,
|
||||
jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,
|
||||
mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0,
|
||||
mi2s_1, mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag,
|
||||
PLL_BIST, pll_bypassnl, pll_reset, prng_rosc, qdss,
|
||||
qdss_cti, qlink_enable, qlink_request, qspi_clk, qspi_cs,
|
||||
qspi_data, qup00, qup01, qup02_i2c, qup02_uart, qup03,
|
||||
qup04_i2c, qup04_uart, qup05, qup10, qup11_i2c, qup11_uart,
|
||||
qup12, qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb,
|
||||
sdc2_tb, sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2,
|
||||
tgu_ch3, tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt,
|
||||
usb_phy, vfr_1, _V_GPIO, _V_PPS_IN, _V_PPS_OUT,
|
||||
vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0,
|
||||
wlan2_adc1,
|
||||
|
||||
- bias-disable:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as no pull.
|
||||
|
||||
- bias-pull-down:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull down.
|
||||
|
||||
- bias-pull-up:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull up.
|
||||
|
||||
- output-high:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
high.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- output-low:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
low.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- drive-strength:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Selects the drive strength for the specified pins, in mA.
|
||||
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
|
||||
|
||||
Example:
|
||||
|
||||
tlmm: pinctrl@3500000 {
|
||||
compatible = "qcom,sc7180-pinctrl";
|
||||
reg = <0x3500000 0x300000>,
|
||||
<0x3900000 0x300000>,
|
||||
<0x3D00000 0x300000>;
|
||||
reg-names = "west", "north", "south";
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 119>;
|
||||
gpio-reserved-ranges = <0 4>, <106 4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sc7180-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SC7180 TLMM pin controller
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SC7180 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7180-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 3
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: west
|
||||
- const: north
|
||||
- const: south
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 60
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 119
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sc7180-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sc7180-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-sc7180-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
|
||||
- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
|
||||
sdc2_cmd, sdc2_data, ufs_reset ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
|
||||
enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,
|
||||
atest_char1, atest_char2, atest_char3, atest_tsens,
|
||||
atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
|
||||
atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
|
||||
atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
|
||||
cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
|
||||
cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0,
|
||||
ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1,
|
||||
gcc_gp2, gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,
|
||||
jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,
|
||||
mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1,
|
||||
mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag, PLL_BIST,
|
||||
pll_bypassnl, pll_reset, prng_rosc, qdss, qdss_cti,
|
||||
qlink_enable, qlink_request, qspi_clk, qspi_cs, qspi_data,
|
||||
qup00, qup01, qup02_i2c, qup02_uart, qup03, qup04_i2c,
|
||||
qup04_uart, qup05, qup10, qup11_i2c, qup11_uart, qup12,
|
||||
qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb, sdc2_tb,
|
||||
sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
|
||||
tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt, usb_phy, vfr_1,
|
||||
_V_GPIO, _V_PPS_IN, _V_PPS_OUT, vsense_trigger, wlan1_adc0,
|
||||
wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
|
||||
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
bias-disable: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
tlmm: pinctrl@3500000 {
|
||||
compatible = "qcom,sc7180-pinctrl";
|
||||
reg = <0x03500000 0x300000>,
|
||||
<0x03900000 0x300000>,
|
||||
<0x03d00000 0x300000>;
|
||||
reg-names = "west", "north", "south";
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 120>;
|
||||
wakeup-parent = <&pdc>;
|
||||
|
||||
dp_hot_plug_det: dp-hot-plug-det-state {
|
||||
pins = "gpio117";
|
||||
function = "dp_hot";
|
||||
};
|
||||
|
||||
qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
|
||||
spi-pins {
|
||||
pins = "gpio53", "gpio54", "gpio55";
|
||||
function = "qup15";
|
||||
};
|
||||
|
||||
cs-pins {
|
||||
pins = "gpio56";
|
||||
function = "gpio";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -4,15 +4,14 @@
|
|||
$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
|
||||
Low Power Island (LPI) TLMM block
|
||||
title: Qualcomm SC7280 SoC LPASS LPI TLMM
|
||||
|
||||
maintainers:
|
||||
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
LPASS LPI IP on most Qualcomm SoCs
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
|
||||
(LPASS) Low Power Island (LPI) of Qualcomm SC7280 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -24,12 +23,11 @@ properties:
|
|||
type: boolean
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
"#gpio-cells":
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
const: 2
|
||||
|
|
@ -37,9 +35,17 @@ properties:
|
|||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sc7280-lpass-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sc7280-lpass-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-sc7280-lpass-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
|
|
@ -83,13 +89,10 @@ patternProperties:
|
|||
3: Reserved (No adjustments)
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-bus-hold: true
|
||||
bias-disable: true
|
||||
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
|
|
@ -102,7 +105,7 @@ required:
|
|||
- compatible
|
||||
- reg
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- "#gpio-cells"
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -116,4 +119,21 @@ examples:
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&lpass_tlmm 0 0 15>;
|
||||
|
||||
dmic01-state {
|
||||
dmic01-clk-pins {
|
||||
pins = "gpio6";
|
||||
function = "dmic1_clk";
|
||||
};
|
||||
|
||||
dmic01-clk-sleep-pins {
|
||||
pins = "gpio6";
|
||||
function = "dmic1_clk";
|
||||
};
|
||||
};
|
||||
|
||||
tx-swr-data-sleep-state {
|
||||
pins = "gpio1", "gpio2", "gpio14";
|
||||
function = "swr_tx_data";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,9 +9,8 @@ title: Qualcomm Technologies, Inc. SC7280 TLMM block
|
|||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
SC7280 platform.
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SC7280 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -43,17 +42,26 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 174
|
||||
maxItems: 175
|
||||
|
||||
wakeup-parent: true
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sc7280-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sc7280-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-sc7280-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -62,7 +70,7 @@ patternProperties:
|
|||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$"
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
|
||||
- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
|
||||
sdc2_cmd, sdc2_data, ufs_reset ]
|
||||
minItems: 1
|
||||
|
|
@ -102,35 +110,18 @@ patternProperties:
|
|||
uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac,
|
||||
usb_phy, vfr_0, vfr_1, vsense_trigger ]
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
default: 2
|
||||
description:
|
||||
Selects the drive strength for the specified pins, in mA.
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-bus-hold: true
|
||||
bias-disable: true
|
||||
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/pincfg-node.yaml
|
||||
- if:
|
||||
properties:
|
||||
pins:
|
||||
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$"
|
||||
then:
|
||||
required:
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
|
|
@ -162,7 +153,7 @@ examples:
|
|||
gpio-ranges = <&tlmm 0 0 175>;
|
||||
wakeup-parent = <&pdc>;
|
||||
|
||||
qup_uart5_default: qup-uart5-pins {
|
||||
qup_uart5_default: qup-uart5-state {
|
||||
pins = "gpio46", "gpio47";
|
||||
function = "qup13";
|
||||
drive-strength = <2>;
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-pinctrl.yaml#
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-tlmm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. SC8180X TLMM block
|
||||
|
|
@ -9,12 +9,10 @@ title: Qualcomm Technologies, Inc. SC8180X TLMM block
|
|||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
SC8180X platform.
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SC8180X SoC.
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
|
|
@ -26,9 +24,9 @@ properties:
|
|||
|
||||
reg-names:
|
||||
items:
|
||||
- const: "west"
|
||||
- const: "east"
|
||||
- const: "south"
|
||||
- const: west
|
||||
- const: east
|
||||
- const: south
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
|
|
@ -47,7 +45,7 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'-state$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sc8180x-tlmm-state"
|
||||
- patternProperties:
|
||||
|
|
@ -55,12 +53,13 @@ patternProperties:
|
|||
$ref: "#/$defs/qcom-sc8180x-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
'$defs':
|
||||
$defs:
|
||||
qcom-sc8180x-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -112,16 +111,6 @@ patternProperties:
|
|||
required:
|
||||
- pins
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
- if:
|
||||
properties:
|
||||
pins:
|
||||
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"
|
||||
then:
|
||||
required:
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
@ -4,15 +4,14 @@
|
|||
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
|
||||
Low Power Island (LPI) TLMM block
|
||||
title: Qualcomm SC8280XP SoC LPASS LPI TLMM
|
||||
|
||||
maintainers:
|
||||
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
LPASS LPI IP on most Qualcomm SoCs
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
|
||||
(LPASS) Low Power Island (LPI) of Qualcomm SC8280XP SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -35,7 +34,7 @@ properties:
|
|||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
"#gpio-cells":
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
const: 2
|
||||
|
|
@ -43,9 +42,17 @@ properties:
|
|||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sc8280xp-lpass-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sc8280xp-lpass-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-sc8280xp-lpass-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
|
|
@ -58,7 +65,7 @@ patternProperties:
|
|||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
pattern: "^gpio([0-1]|1[0-8]])$"
|
||||
pattern: "^gpio([0-1]|1[0-8])$"
|
||||
|
||||
function:
|
||||
enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
|
||||
|
|
@ -112,7 +119,7 @@ required:
|
|||
- clocks
|
||||
- clock-names
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- "#gpio-cells"
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -130,4 +137,21 @@ examples:
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&lpi_tlmm 0 0 18>;
|
||||
|
||||
dmic01-state {
|
||||
dmic01-clk-pins {
|
||||
pins = "gpio16";
|
||||
function = "dmic1_clk";
|
||||
};
|
||||
|
||||
dmic01-clk-sleep-pins {
|
||||
pins = "gpio16";
|
||||
function = "dmic1_clk";
|
||||
};
|
||||
};
|
||||
|
||||
tx-swr-data-sleep-state {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "swr_tx_data";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-pinctrl.yaml#
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-tlmm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. SC8280XP TLMM block
|
||||
|
|
@ -10,8 +10,7 @@ maintainers:
|
|||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
SC8280XP platform.
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SC8280XP SoC.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
|
@ -25,10 +24,10 @@ properties:
|
|||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
'#interrupt-cells': true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
gpio-reserved-ranges: true
|
||||
'#gpio-cells': true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
|
|
@ -39,7 +38,7 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'-state$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
|
||||
- patternProperties:
|
||||
|
|
@ -47,12 +46,13 @@ patternProperties:
|
|||
$ref: "#/$defs/qcom-sc8280xp-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
'$defs':
|
||||
$defs:
|
||||
qcom-sc8280xp-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -113,16 +113,6 @@ patternProperties:
|
|||
required:
|
||||
- pins
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
- if:
|
||||
properties:
|
||||
pins:
|
||||
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
|
||||
then:
|
||||
required:
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
@ -139,8 +129,8 @@ examples:
|
|||
gpio-ranges = <&tlmm 0 0 230>;
|
||||
|
||||
gpio-wo-subnode-state {
|
||||
pins = "gpio1";
|
||||
function = "gpio";
|
||||
pins = "gpio1";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
uart-w-subnodes-state {
|
||||
|
|
@ -0,0 +1,188 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sdm630-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SDM630 and SDM660 TLMM pin controller
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SDM630 and SDM660 SoC.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sdm630-pinctrl
|
||||
- qcom,sdm660-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 3
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: south
|
||||
- const: center
|
||||
- const: north
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 57
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 114
|
||||
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sdm630-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sdm630-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-sdm630-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-3])$"
|
||||
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
|
||||
sdc2_cmd, sdc2_data ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
|
||||
atest_char2, atest_char3, atest_gpsadc0, atest_gpsadc1,
|
||||
atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
|
||||
atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20,
|
||||
atest_usb21, atest_usb22, atest_usb23, audio_ref, bimc_dte0,
|
||||
bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4,
|
||||
blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8_a, blsp_i2c8_b,
|
||||
blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2,
|
||||
blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8_a,
|
||||
blsp_spi8_b, blsp_spi8_cs1, blsp_spi8_cs2, blsp_uart1,
|
||||
blsp_uart2, blsp_uart5, blsp_uart6_a, blsp_uart6_b, blsp_uim1,
|
||||
blsp_uim2, blsp_uim5, blsp_uim6, cam_mclk, cci_async, cci_i2c,
|
||||
cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, gcc_gp1,
|
||||
gcc_gp2, gcc_gp3, gpio, gps_tx_a, gps_tx_b, gps_tx_c,
|
||||
isense_dbg, jitter_bist, ldo_en, ldo_update, m_voc, mdp_vsync,
|
||||
mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, mss_lte,
|
||||
nav_pps_a, nav_pps_b, nav_pps_c, pa_indicator, phase_flag0,
|
||||
phase_flag1, phase_flag10, phase_flag11, phase_flag12,
|
||||
phase_flag13, phase_flag14, phase_flag15, phase_flag16,
|
||||
phase_flag17, phase_flag18, phase_flag19, phase_flag2,
|
||||
phase_flag20, phase_flag21, phase_flag22, phase_flag23,
|
||||
phase_flag24, phase_flag25, phase_flag26, phase_flag27,
|
||||
phase_flag28, phase_flag29, phase_flag3, phase_flag30,
|
||||
phase_flag31, phase_flag4, phase_flag5, phase_flag6,
|
||||
phase_flag7, phase_flag8, phase_flag9, pll_bypassnl, pll_reset,
|
||||
pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto, pwr_modem,
|
||||
pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a, qdss_cti1_b,
|
||||
qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11,
|
||||
qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, qdss_gpio2,
|
||||
qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7,
|
||||
qdss_gpio8, qdss_gpio9, qlink_enable, qlink_request, qspi_clk,
|
||||
qspi_cs, qspi_data0, qspi_data1, qspi_data2, qspi_data3,
|
||||
qspi_resetn, sec_mi2s, sndwire_clk, sndwire_data, sp_cmu,
|
||||
ssc_irq, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, uim1_clk,
|
||||
uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
|
||||
uim2_present, uim2_reset, uim_batt, vfr_1, vsense_clkout,
|
||||
vsense_data0, vsense_data1, vsense_mode, wlan1_adc0,
|
||||
wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
|
||||
|
||||
bias-disable: true
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
tlmm: pinctrl@3100000 {
|
||||
compatible = "qcom,sdm630-pinctrl";
|
||||
reg = <0x03100000 0x400000>,
|
||||
<0x03500000 0x400000>,
|
||||
<0x03900000 0x400000>;
|
||||
reg-names = "south", "center", "north";
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&tlmm 0 0 114>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
blsp1-uart1-default-state {
|
||||
pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp2_uart1_default: blsp2-uart1-active-state {
|
||||
tx-rts-pins {
|
||||
pins = "gpio16", "gpio19";
|
||||
function = "blsp_uart5";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rx-pins {
|
||||
pins = "gpio17";
|
||||
function = "blsp_uart5";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
cts-pins {
|
||||
pins = "gpio18";
|
||||
function = "blsp_uart5";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,191 +0,0 @@
|
|||
Qualcomm Technologies, Inc. SDM660 TLMM block
|
||||
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
SDM660 platform.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,sdm660-pinctrl" or
|
||||
"qcom,sdm630-pinctrl".
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the base address and size of the north, center and south
|
||||
TLMM tiles.
|
||||
|
||||
- reg-names:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: names for the cells of reg, must contain "north", "center"
|
||||
and "south".
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: should specify the TLMM summary IRQ.
|
||||
|
||||
- interrupt-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as an interrupt controller
|
||||
|
||||
- #interrupt-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
- gpio-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as a gpio controller
|
||||
|
||||
- gpio-ranges:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Specifies the mapping between gpio controller and
|
||||
pin-controller pins.
|
||||
|
||||
- #gpio-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/gpio/gpio.h>
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
|
||||
PIN CONFIGURATION NODES:
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function.
|
||||
|
||||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
|
||||
- pins:
|
||||
Usage: required
|
||||
Value type: <string-array>
|
||||
Definition: List of gpio pins affected by the properties specified in
|
||||
this subnode. Valid pins are:
|
||||
gpio0-gpio113,
|
||||
Supports mux, bias and drive-strength
|
||||
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, sdc2_data sdc1_rclk,
|
||||
Supports bias and drive-strength
|
||||
|
||||
- function:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Specify the alternative function to be configured for the
|
||||
specified pins. Functions are only valid for gpio pins.
|
||||
Valid values are:
|
||||
adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
|
||||
atest_char2, atest_char3, atest_gpsadc0, atest_gpsadc1,
|
||||
atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
|
||||
atest_usb11, atest_usb12, atest_usb13, atest_usb2,
|
||||
atest_usb20, atest_usb21, atest_usb22, atest_usb23,
|
||||
audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1, blsp_i2c2,
|
||||
blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7,
|
||||
blsp_i2c8_a, blsp_i2c8_b, blsp_spi1, blsp_spi2, blsp_spi3,
|
||||
blsp_spi3_cs1, blsp_spi3_cs2, blsp_spi4, blsp_spi5,
|
||||
blsp_spi6, blsp_spi7, blsp_spi8_a, blsp_spi8_b,
|
||||
blsp_spi8_cs1, blsp_spi8_cs2, blsp_uart1, blsp_uart2,
|
||||
blsp_uart5, blsp_uart6_a, blsp_uart6_b, blsp_uim1,
|
||||
blsp_uim2, blsp_uim5, blsp_uim6, cam_mclk, cci_async,
|
||||
cci_i2c, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
|
||||
gcc_gp1, gcc_gp2, gcc_gp3, gpio, gps_tx_a, gps_tx_b, gps_tx_c,
|
||||
isense_dbg, jitter_bist, ldo_en, ldo_update, m_voc, mdp_vsync,
|
||||
mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, mss_lte,
|
||||
nav_pps_a, nav_pps_b, nav_pps_c, pa_indicator, phase_flag0,
|
||||
phase_flag1, phase_flag10, phase_flag11, phase_flag12,
|
||||
phase_flag13, phase_flag14, phase_flag15, phase_flag16,
|
||||
phase_flag17, phase_flag18, phase_flag19, phase_flag2,
|
||||
phase_flag20, phase_flag21, phase_flag22, phase_flag23,
|
||||
phase_flag24, phase_flag25, phase_flag26, phase_flag27,
|
||||
phase_flag28, phase_flag29, phase_flag3, phase_flag30,
|
||||
phase_flag31, phase_flag4, phase_flag5, phase_flag6,
|
||||
phase_flag7, phase_flag8, phase_flag9, pll_bypassnl,
|
||||
pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto,
|
||||
pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a,
|
||||
qdss_cti1_b, qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10,
|
||||
qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15,
|
||||
qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,
|
||||
qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink_enable, qlink_request,
|
||||
qspi_clk, qspi_cs, qspi_data0, qspi_data1, qspi_data2,
|
||||
qspi_data3, qspi_resetn, sec_mi2s, sndwire_clk, sndwire_data,
|
||||
sp_cmu, ssc_irq, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2,
|
||||
uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
|
||||
uim2_data, uim2_present, uim2_reset, uim_batt, vfr_1,
|
||||
vsense_clkout, vsense_data0, vsense_data1, vsense_mode,
|
||||
wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1
|
||||
|
||||
- bias-disable:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as no pull.
|
||||
|
||||
- bias-pull-down:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull down.
|
||||
|
||||
- bias-pull-up:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull up.
|
||||
|
||||
- output-high:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
high.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- output-low:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
low.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- drive-strength:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Selects the drive strength for the specified pins, in mA.
|
||||
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
|
||||
|
||||
Example:
|
||||
|
||||
tlmm: pinctrl@3100000 {
|
||||
compatible = "qcom,sdm660-pinctrl";
|
||||
reg = <0x3100000 0x200000>,
|
||||
<0x3500000 0x200000>,
|
||||
<0x3900000 0x200000>;
|
||||
reg-names = "south", "center", "north";
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&tlmm 0 0 114>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
|
@ -1,176 +0,0 @@
|
|||
Qualcomm SDM845 TLMM block
|
||||
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
SDM845 platform.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,sdm845-pinctrl"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the base address and size of the TLMM register space.
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: should specify the TLMM summary IRQ.
|
||||
|
||||
- interrupt-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as an interrupt controller
|
||||
|
||||
- #interrupt-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
- gpio-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as a gpio controller
|
||||
|
||||
- #gpio-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/gpio/gpio.h>
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
|
||||
PIN CONFIGURATION NODES:
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function.
|
||||
|
||||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
|
||||
- pins:
|
||||
Usage: required
|
||||
Value type: <string-array>
|
||||
Definition: List of gpio pins affected by the properties specified in
|
||||
this subnode.
|
||||
|
||||
Valid pins are:
|
||||
gpio0-gpio149
|
||||
Supports mux, bias and drive-strength
|
||||
|
||||
sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset
|
||||
Supports bias and drive-strength
|
||||
|
||||
- function:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Specify the alternative function to be configured for the
|
||||
specified pins. Functions are only valid for gpio pins.
|
||||
Valid values are:
|
||||
|
||||
gpio, adsp_ext, agera_pll, atest_char, atest_tsens,
|
||||
atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
|
||||
atest_usb12, atest_usb13, atest_usb2, atest_usb20,
|
||||
atest_usb21, atest_usb22, atest_usb23, audio_ref,
|
||||
btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
|
||||
cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
|
||||
cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
|
||||
ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
|
||||
gcc_gp2, gcc_gp3, jitter_bist, ldo_en, ldo_update,
|
||||
lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1,
|
||||
mdp_vsync2, mdp_vsync3, mss_lte, nav_pps, pa_indicator,
|
||||
pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl,
|
||||
pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti,
|
||||
qdss, qlink_enable, qlink_request, qua_mi2s, qup0, qup1,
|
||||
qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, qup4,
|
||||
qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
|
||||
qspi_clk, qspi_cs, qspi_data, sd_write, sdc4_clk, sdc4_cmd,
|
||||
sdc4_data, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu_ch0,
|
||||
tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2,
|
||||
tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync,
|
||||
tsif2_clk, tsif2_data, tsif2_en, tsif2_error, tsif2_sync,
|
||||
uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
|
||||
uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy,
|
||||
vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0,
|
||||
wlan2_adc1,
|
||||
|
||||
- bias-disable:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as no pull.
|
||||
|
||||
- bias-pull-down:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull down.
|
||||
|
||||
- bias-pull-up:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull up.
|
||||
|
||||
- output-high:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
high.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- output-low:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
low.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- drive-strength:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Selects the drive strength for the specified pins, in mA.
|
||||
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
|
||||
|
||||
Example:
|
||||
|
||||
tlmm: pinctrl@3400000 {
|
||||
compatible = "qcom,sdm845-pinctrl";
|
||||
reg = <0x03400000 0xc00000>;
|
||||
interrupts = <GIC_SPI 208 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
qup9_active: qup9-active {
|
||||
mux {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "qup9";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio4", "gpio5";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sdm845-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SDM845 TLMM pin controller
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SDM845 SoC.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 75
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 150
|
||||
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sdm845-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sdm845-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-sdm845-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
|
||||
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2,
|
||||
atest_usb1, atest_usb10, atest_usb11, atest_usb12, atest_usb13,
|
||||
atest_usb2, atest_usb20, atest_usb21, atest_usb22, atest_usb23,
|
||||
audio_ref, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
|
||||
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
|
||||
cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
|
||||
ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
|
||||
gcc_gp2, gcc_gp3, gpio, jitter_bist, ldo_en, ldo_update,
|
||||
lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
|
||||
mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator, pci_e0,
|
||||
pci_e1, phase_flag, pll_bist, pll_bypassnl, pll_reset,
|
||||
pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable,
|
||||
qlink_request, qspi_clk, qspi_cs, qspi_data, qua_mi2s, qup0,
|
||||
qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3,
|
||||
qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
|
||||
sdc4_clk, sdc4_cmd, sdc4_data, sd_write, sec_mi2s, sp_cmu,
|
||||
spkr_i2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
|
||||
tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
|
||||
tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
|
||||
tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
|
||||
uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
|
||||
uim_batt, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
|
||||
wlan1_adc1, wlan2_adc0, wlan2_adc1]
|
||||
|
||||
bias-disable: true
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pinctrl@3400000 {
|
||||
compatible = "qcom,sdm845-pinctrl";
|
||||
reg = <0x03400000 0xc00000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 151>;
|
||||
wakeup-parent = <&pdc_intc>;
|
||||
|
||||
cci0-default-state {
|
||||
pins = "gpio17", "gpio18";
|
||||
function = "cci_i2c";
|
||||
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
cam0-default-state {
|
||||
rst-pins {
|
||||
pins = "gpio9";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mclk0-pins {
|
||||
pins = "gpio13";
|
||||
function = "cam_mclk";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -9,9 +9,8 @@ title: Qualcomm Technologies, Inc. SDX55 TLMM block
|
|||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
SDX55 platform.
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SDX55 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -21,38 +20,32 @@ properties:
|
|||
description: Specifies the base address and size of the TLMM register space
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: Specifies the TLMM summary IRQ
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
description: Specifies the PIN numbers and Flags, as defined in
|
||||
include/dt-bindings/interrupt-controller/irq.h
|
||||
const: 2
|
||||
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
maxItems: 1
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sdx55-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sdx55-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-sdx55-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: "/schemas/pinctrl/pincfg-node.yaml"
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -96,62 +89,46 @@ patternProperties:
|
|||
uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
|
||||
uim2_reset, usb2phy_ac, vsense_trigger ]
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
default: 2
|
||||
description:
|
||||
Selects the drive strength for the specified pins, in mA.
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-disable: true
|
||||
|
||||
drive-strength: true
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
tlmm: pinctrl@1f00000 {
|
||||
compatible = "qcom,sdx55-pinctrl";
|
||||
reg = <0x0f100000 0x300000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 108>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
tlmm: pinctrl@1f00000 {
|
||||
compatible = "qcom,sdx55-pinctrl";
|
||||
reg = <0x0f100000 0x300000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 108>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
serial-pins {
|
||||
pins = "gpio8", "gpio9";
|
||||
function = "blsp_uart3";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
serial-state {
|
||||
pins = "gpio8", "gpio9";
|
||||
function = "blsp_uart3";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-pinctrl.yaml#
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-tlmm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. SDX65 TLMM block
|
||||
|
|
@ -10,8 +10,7 @@ maintainers:
|
|||
- Vamsi krishna Lanka <quic_vamslank@quicinc.com>
|
||||
|
||||
description:
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
SDX65 platform.
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SDX65 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -20,44 +19,32 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
description: Specifies the PIN numbers and Flags, as defined in
|
||||
include/dt-bindings/interrupt-controller/irq.h
|
||||
const: 2
|
||||
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
maxItems: 1
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-state$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sdx65-tlmm-state"
|
||||
- patternProperties:
|
||||
".*":
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sdx65-tlmm-state"
|
||||
'$defs':
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-sdx65-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -122,37 +109,24 @@ patternProperties:
|
|||
qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
|
||||
gpio ]
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
default: 2
|
||||
description:
|
||||
Selects the drive strength for the specified pins, in mA.
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-disable: true
|
||||
|
||||
drive-strength: true
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
@ -175,13 +149,13 @@ examples:
|
|||
};
|
||||
|
||||
uart-w-subnodes-state {
|
||||
rx {
|
||||
rx-pins {
|
||||
pins = "gpio4";
|
||||
function = "blsp_uart1";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
tx {
|
||||
tx-pins {
|
||||
pins = "gpio5";
|
||||
function = "blsp_uart1";
|
||||
bias-disable;
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-pinctrl.yaml#
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-tlmm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block
|
||||
|
|
@ -10,15 +10,14 @@ maintainers:
|
|||
- Iskren Chernev <iskren.chernev@gmail.com>
|
||||
|
||||
description:
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
SM4250/6115 platforms.
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SM4250 and SM6115
|
||||
SoCs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm6115-tlmm
|
||||
|
||||
reg:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
reg-names:
|
||||
|
|
@ -27,35 +26,17 @@ properties:
|
|||
- const: south
|
||||
- const: east
|
||||
|
||||
interrupts:
|
||||
description: Specifies the TLMM summary IRQ
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
description:
|
||||
Specifies the PIN numbers and Flags, as defined in defined in
|
||||
include/dt-bindings/interrupt-controller/irq.h
|
||||
const: 2
|
||||
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
gpio-reserved-ranges: true
|
||||
|
||||
wakeup-parent: true
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-state$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sm6115-tlmm-state"
|
||||
- patternProperties:
|
||||
|
|
@ -63,12 +44,13 @@ patternProperties:
|
|||
$ref: "#/$defs/qcom-sm6115-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
'$defs':
|
||||
$defs:
|
||||
qcom-sm6115-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -101,50 +83,25 @@ patternProperties:
|
|||
uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger,
|
||||
wlan1_adc0, elan1_adc1 ]
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
default: 2
|
||||
description:
|
||||
Selects the drive strength for the specified pins, in mA.
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-disable: true
|
||||
|
||||
drive-strength: true
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
- if:
|
||||
properties:
|
||||
pins:
|
||||
pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
|
||||
then:
|
||||
required:
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
@ -1,19 +1,17 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-pinctrl.yaml#
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-tlmm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm Technologies, Inc. SM6125 TLMM block
|
||||
|
||||
maintainers:
|
||||
- Martin Botka <martin.botka@somainline.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer (TLMM) block found
|
||||
in the SM6125 platform.
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SM6125 SoC.
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
|
|
@ -21,21 +19,20 @@ properties:
|
|||
const: qcom,sm6125-tlmm
|
||||
|
||||
reg:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: "west"
|
||||
- const: "south"
|
||||
- const: "east"
|
||||
- const: west
|
||||
- const: south
|
||||
- const: east
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
'#interrupt-cells': true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
gpio-reserved-ranges: true
|
||||
'#gpio-cells': true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
|
|
@ -47,7 +44,7 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'-state$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sm6125-tlmm-state"
|
||||
- patternProperties:
|
||||
|
|
@ -61,6 +58,7 @@ $defs:
|
|||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -112,16 +110,6 @@ $defs:
|
|||
required:
|
||||
- pins
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
- if:
|
||||
properties:
|
||||
pins:
|
||||
pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$"
|
||||
then:
|
||||
required:
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-pinctrl.yaml#
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-tlmm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. SM6350 TLMM block
|
||||
|
|
@ -9,12 +9,10 @@ title: Qualcomm Technologies, Inc. SM6350 TLMM block
|
|||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer (TLMM) block found
|
||||
in the SM6350 platform.
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SM6350 SoC.
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
|
|
@ -26,10 +24,10 @@ properties:
|
|||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
'#interrupt-cells': true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
gpio-reserved-ranges: true
|
||||
'#gpio-cells': true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
|
|
@ -40,7 +38,7 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'-state$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sm6350-tlmm-state"
|
||||
- patternProperties:
|
||||
|
|
@ -54,6 +52,7 @@ $defs:
|
|||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -111,16 +110,6 @@ $defs:
|
|||
required:
|
||||
- pins
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
- if:
|
||||
properties:
|
||||
pins:
|
||||
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-7])$"
|
||||
then:
|
||||
required:
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
@ -9,12 +9,10 @@ title: Qualcomm Technologies, Inc. SM6375 TLMM block
|
|||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer (TLMM) block found
|
||||
in the SM6375 platform.
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SM6375 SoC.
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
|
|
@ -26,10 +24,10 @@ properties:
|
|||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
'#interrupt-cells': true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
gpio-reserved-ranges: true
|
||||
'#gpio-cells': true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
|
|
@ -40,7 +38,7 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'-state$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sm6375-tlmm-state"
|
||||
- patternProperties:
|
||||
|
|
@ -54,6 +52,7 @@ $defs:
|
|||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -120,16 +119,6 @@ $defs:
|
|||
required:
|
||||
- pins
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
- if:
|
||||
properties:
|
||||
pins:
|
||||
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-6])$"
|
||||
then:
|
||||
required:
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -1,190 +0,0 @@
|
|||
Qualcomm SM8150 TLMM block
|
||||
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
QCS404 platform.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,sm8150-pinctrl"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the base address and size of the north, south, west
|
||||
and east TLMM tiles.
|
||||
|
||||
- reg-names:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Defintiion: names for the cells of reg, must contain "north", "south"
|
||||
"west" and "east".
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: should specify the TLMM summary IRQ.
|
||||
|
||||
- interrupt-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as an interrupt controller
|
||||
|
||||
- #interrupt-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
- gpio-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as a gpio controller
|
||||
|
||||
- #gpio-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/gpio/gpio.h>
|
||||
|
||||
- gpio-ranges:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: see ../gpio/gpio.txt
|
||||
|
||||
- gpio-reserved-ranges:
|
||||
Usage: optional
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: see ../gpio/gpio.txt
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
|
||||
PIN CONFIGURATION NODES:
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function.
|
||||
|
||||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
|
||||
- pins:
|
||||
Usage: required
|
||||
Value type: <string-array>
|
||||
Definition: List of gpio pins affected by the properties specified in
|
||||
this subnode.
|
||||
|
||||
Valid pins are:
|
||||
gpio0-gpio149
|
||||
Supports mux, bias and drive-strength
|
||||
|
||||
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
|
||||
sdc2_data sdc1_rclk
|
||||
Supports bias and drive-strength
|
||||
|
||||
ufs_reset
|
||||
Supports bias and drive-strength
|
||||
|
||||
- function:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Specify the alternative function to be configured for the
|
||||
specified pins. Functions are only valid for gpio pins.
|
||||
Valid values are:
|
||||
|
||||
adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
|
||||
atest_char0, atest_char1, atest_char2, atest_char3,
|
||||
audio_ref, atest_usb1, atest_usb2, atest_usb10,
|
||||
atest_usb11, atest_usb12, atest_usb13, atest_usb20,
|
||||
atest_usb21, atest_usb22, atest_usb2, atest_usb23,
|
||||
btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
|
||||
cci_timer1, cci_timer2, cci_timer3, cci_timer4,
|
||||
cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
|
||||
ddr_pxi0, ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd,
|
||||
emac_phy, emac_pps, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
|
||||
hs1_mi2s, hs2_mi2s, hs3_mi2s, jitter_bist,
|
||||
lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
|
||||
mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps,
|
||||
pa_indicator, pci_e0, phase_flag, pll_bypassnl,
|
||||
pll_bist, pci_e1, pll_reset, pri_mi2s, pri_mi2s_ws,
|
||||
prng_rosc, qdss, qdss_cti, qlink_request, qlink_enable,
|
||||
qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qua_mi2s,
|
||||
qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
|
||||
qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16,
|
||||
qup17, qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii,
|
||||
sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu, ter_mi2s,
|
||||
tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
|
||||
tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
|
||||
usb2phy_ac, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
|
||||
wlan1_adc1, wlan2_adc0, wlan2_adc1, wmss_reset
|
||||
|
||||
- bias-disable:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configued as no pull.
|
||||
|
||||
- bias-pull-down:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configued as pull down.
|
||||
|
||||
- bias-pull-up:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configued as pull up.
|
||||
|
||||
- output-high:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
high.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- output-low:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
low.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- drive-strength:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Selects the drive strength for the specified pins, in mA.
|
||||
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
|
||||
|
||||
Example:
|
||||
|
||||
tlmm: pinctrl@3000000 {
|
||||
compatible = "qcom,sm8150-pinctrl";
|
||||
reg = <0x03100000 0x300000>,
|
||||
<0x03500000 0x300000>,
|
||||
<0x03900000 0x300000>,
|
||||
<0x03D00000 0x300000>;
|
||||
reg-names = "west", "east", "north", "south";
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 175>;
|
||||
gpio-reserved-ranges = <0 4>, <126 4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8150-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8150 TLMM pin controller
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SM8150 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8150-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: west
|
||||
- const: east
|
||||
- const: north
|
||||
- const: south
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 88
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 175
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sm8150-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sm8150-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-sm8150-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
|
||||
- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
|
||||
enum: [ adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
|
||||
atest_char0, atest_char1, atest_char2, atest_char3, audio_ref,
|
||||
atest_usb1, atest_usb2, atest_usb10, atest_usb11, atest_usb12,
|
||||
atest_usb13, atest_usb20, atest_usb21, atest_usb22, atest_usb2,
|
||||
atest_usb23, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
|
||||
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
|
||||
cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
|
||||
ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd, emac_phy, emac_pps,
|
||||
gcc_gp1, gcc_gp2, gcc_gp3, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s,
|
||||
jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
|
||||
mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator,
|
||||
pci_e0, phase_flag, pll_bypassnl, pll_bist, pci_e1, pll_reset,
|
||||
pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti,
|
||||
qlink_request, qlink_enable, qspi0, qspi1, qspi2, qspi3,
|
||||
qspi_clk, qspi_cs, qua_mi2s, qup0, qup1, qup2, qup3, qup4,
|
||||
qup5, qup6, qup7, qup8, qup9, qup10, qup11, qup12, qup13,
|
||||
qup14, qup15, qup16, qup17, qup18, qup19, qup_l4, qup_l5,
|
||||
qup_l6, rgmii, sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu,
|
||||
ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
|
||||
tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, usb2phy_ac,
|
||||
usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
|
||||
wlan2_adc0, wlan2_adc1, wmss_reset ]
|
||||
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
bias-disable: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
tlmm: pinctrl@3100000 {
|
||||
compatible = "qcom,sm8150-pinctrl";
|
||||
reg = <0x03100000 0x300000>,
|
||||
<0x03500000 0x300000>,
|
||||
<0x03900000 0x300000>,
|
||||
<0x03d00000 0x300000>;
|
||||
reg-names = "west", "east", "north", "south";
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-ranges = <&tlmm 0 0 176>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
wakeup-parent = <&pdc>;
|
||||
|
||||
qup-spi0-default-state {
|
||||
pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
||||
function = "qup0";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcie1-default-state {
|
||||
perst-pins {
|
||||
pins = "gpio102";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
clkreq-pins {
|
||||
pins = "gpio103";
|
||||
function = "pci_e1";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
wake-pins {
|
||||
pins = "gpio104";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -4,22 +4,20 @@
|
|||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
|
||||
Low Power Island (LPI) TLMM block
|
||||
title: Qualcomm SM8250 SoC LPASS LPI TLMM
|
||||
|
||||
maintainers:
|
||||
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
LPASS LPI IP on most Qualcomm SoCs
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
|
||||
(LPASS) Low Power Island (LPI) of Qualcomm SM8250 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8250-lpass-lpi-pinctrl
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
clocks:
|
||||
|
|
@ -34,7 +32,7 @@ properties:
|
|||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
"#gpio-cells":
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
const: 2
|
||||
|
|
@ -42,9 +40,17 @@ properties:
|
|||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sm8250-lpass-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sm8250-lpass-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-sm8250-lpass-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
|
|
@ -88,13 +94,11 @@ patternProperties:
|
|||
3: Reserved (No adjustments)
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-bus-hold: true
|
||||
bias-disable: true
|
||||
|
||||
input-enable: true
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
|
|
@ -104,7 +108,7 @@ patternProperties:
|
|||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: pinctrl.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
@ -112,7 +116,7 @@ required:
|
|||
- clocks
|
||||
- clock-names
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- "#gpio-cells"
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -130,4 +134,28 @@ examples:
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&lpi_tlmm 0 0 14>;
|
||||
|
||||
wsa-swr-active-state {
|
||||
clk-pins {
|
||||
pins = "gpio10";
|
||||
function = "wsa_swr_clk";
|
||||
drive-strength = <2>;
|
||||
slew-rate = <1>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "gpio11";
|
||||
function = "wsa_swr_data";
|
||||
drive-strength = <2>;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
tx-swr-sleep-clk-state {
|
||||
pins = "gpio0";
|
||||
function = "swr_tx_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,133 +9,109 @@ title: Qualcomm Technologies, Inc. SM8250 TLMM block
|
|||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
SM8250 platform.
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in the Qualcomm SM8250 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8250-pinctrl
|
||||
|
||||
reg:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: "west"
|
||||
- const: "south"
|
||||
- const: "north"
|
||||
|
||||
interrupts:
|
||||
description: Specifies the TLMM summary IRQ
|
||||
maxItems: 1
|
||||
- const: west
|
||||
- const: south
|
||||
- const: north
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
description:
|
||||
Specifies the PIN numbers and Flags, as defined in defined in
|
||||
include/dt-bindings/interrupt-controller/irq.h
|
||||
const: 2
|
||||
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 90
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 180
|
||||
|
||||
patternProperties:
|
||||
'^.*$':
|
||||
if:
|
||||
type: object
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
|
||||
- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sm8250-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sm8250-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
$defs:
|
||||
qcom-sm8250-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c,
|
||||
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
|
||||
cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
|
||||
ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
|
||||
ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
|
||||
mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
|
||||
mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
|
||||
mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1,
|
||||
pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
|
||||
pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3,
|
||||
qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14,
|
||||
qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6,
|
||||
qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41,
|
||||
sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1,
|
||||
tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data,
|
||||
tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en,
|
||||
tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ]
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
|
||||
- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
default: 2
|
||||
description:
|
||||
Selects the drive strength for the specified pins, in mA.
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
|
||||
bias-pull-down: true
|
||||
enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c,
|
||||
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
|
||||
cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
|
||||
ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
|
||||
ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
|
||||
mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
|
||||
mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
|
||||
mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1,
|
||||
pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
|
||||
pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3,
|
||||
qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14,
|
||||
qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6,
|
||||
qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41,
|
||||
sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1,
|
||||
tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data,
|
||||
tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en,
|
||||
tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ]
|
||||
|
||||
bias-pull-up: true
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
bias-disable: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
bias-disable: true
|
||||
required:
|
||||
- pins
|
||||
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
- if:
|
||||
properties:
|
||||
pins:
|
||||
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
|
||||
then:
|
||||
required:
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
@ -143,16 +119,16 @@ examples:
|
|||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
pinctrl@1f00000 {
|
||||
compatible = "qcom,sm8250-pinctrl";
|
||||
reg = <0x0f100000 0x300000>,
|
||||
<0x0f500000 0x300000>,
|
||||
<0x0f900000 0x300000>;
|
||||
reg-names = "west", "south", "north";
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 180>;
|
||||
wakeup-parent = <&pdc>;
|
||||
compatible = "qcom,sm8250-pinctrl";
|
||||
reg = <0x0f100000 0x300000>,
|
||||
<0x0f500000 0x300000>,
|
||||
<0x0f900000 0x300000>;
|
||||
reg-names = "west", "south", "north";
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 180>;
|
||||
wakeup-parent = <&pdc>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-pinctrl.yaml#
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-tlmm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. SM8350 TLMM block
|
||||
|
|
@ -9,12 +9,10 @@ title: Qualcomm Technologies, Inc. SM8350 TLMM block
|
|||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer (TLMM) block found
|
||||
in the SM8350 platform.
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SM8350 SoC.
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
|
|
@ -26,10 +24,10 @@ properties:
|
|||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
'#interrupt-cells': true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
gpio-reserved-ranges: true
|
||||
'#gpio-cells': true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
|
|
@ -40,7 +38,7 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'-state$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sm8350-tlmm-state"
|
||||
- patternProperties:
|
||||
|
|
@ -54,6 +52,7 @@ $defs:
|
|||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -108,16 +107,6 @@ $defs:
|
|||
required:
|
||||
- pins
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
- if:
|
||||
properties:
|
||||
pins:
|
||||
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$"
|
||||
then:
|
||||
required:
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
@ -4,15 +4,14 @@
|
|||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
|
||||
Low Power Island (LPI) TLMM block
|
||||
title: Qualcomm SM8450 SoC LPASS LPI TLMM
|
||||
|
||||
maintainers:
|
||||
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
LPASS LPI IP on most Qualcomm SoCs
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
|
||||
(LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -35,7 +34,7 @@ properties:
|
|||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
"#gpio-cells":
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
const: 2
|
||||
|
|
@ -43,9 +42,17 @@ properties:
|
|||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sm8450-lpass-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sm8450-lpass-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-sm8450-lpass-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
|
|
@ -58,7 +65,7 @@ patternProperties:
|
|||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
pattern: "^gpio([0-9]|[1-2][0-9]])$"
|
||||
pattern: "^gpio([0-9]|[1-2][0-9])$"
|
||||
|
||||
function:
|
||||
enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
|
||||
|
|
@ -114,7 +121,7 @@ required:
|
|||
- clocks
|
||||
- clock-names
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- "#gpio-cells"
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -132,4 +139,28 @@ examples:
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&lpi_tlmm 0 0 23>;
|
||||
|
||||
wsa-swr-active-state {
|
||||
clk-pins {
|
||||
pins = "gpio10";
|
||||
function = "wsa_swr_clk";
|
||||
drive-strength = <2>;
|
||||
slew-rate = <1>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "gpio11";
|
||||
function = "wsa_swr_data";
|
||||
drive-strength = <2>;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
tx-swr-sleep-clk-state {
|
||||
pins = "gpio0";
|
||||
function = "swr_tx_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-pinctrl.yaml#
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-tlmm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. SM8450 TLMM block
|
||||
|
|
@ -9,9 +9,8 @@ title: Qualcomm Technologies, Inc. SM8450 TLMM block
|
|||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer (TLMM) block found
|
||||
in the SM8450 platform.
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SM8450 SoC.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
|
@ -25,7 +24,7 @@ properties:
|
|||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
'#interrupt-cells': true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
|
|
@ -35,7 +34,7 @@ properties:
|
|||
gpio-line-names:
|
||||
maxItems: 209
|
||||
|
||||
'#gpio-cells': true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
|
|
@ -46,7 +45,7 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'-state$':
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sm8450-tlmm-state"
|
||||
- patternProperties:
|
||||
|
|
@ -60,6 +59,7 @@ $defs:
|
|||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
|
|
@ -112,16 +112,6 @@ $defs:
|
|||
required:
|
||||
- pins
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
- if:
|
||||
properties:
|
||||
pins:
|
||||
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
|
||||
then:
|
||||
required:
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
@ -65,10 +65,6 @@ additionalProperties: true
|
|||
|
||||
$defs:
|
||||
qcom-tlmm-state:
|
||||
allOf:
|
||||
- $ref: pincfg-node.yaml#
|
||||
- $ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
|
|
@ -82,5 +78,21 @@ $defs:
|
|||
output-high: true
|
||||
output-low: true
|
||||
|
||||
allOf:
|
||||
- $ref: pincfg-node.yaml#
|
||||
- $ref: pinmux-node.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
pattern: "^gpio"
|
||||
then:
|
||||
required:
|
||||
- function
|
||||
else:
|
||||
properties:
|
||||
function: false
|
||||
|
||||
additionalProperties: true
|
||||
...
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user