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mvebu dt64 for 4.14 (part 1)
For Armada 37xx:
- GIC improvement
- Add PMUv3
- Enable USB2 on EspressoBin
For Armada 7K/8K:
- add GPIO interrupts for CP110
- add pinctrl nodes to describe the CPM I2C0 and CPS SPI1
- re-order RTC nodes in Marvell CP110 description
- on MacchiatoBin
- fix USB3 regulator definition
- add support for i2c mux
- add support for PCIe
- add an stdout-path
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Merge tag 'mvebu-dt64-4.14-1' of git://git.infradead.org/linux-mvebu into next/dt64
Pull "mvebu dt64 for 4.14 (part 1)" from Gregory CLEMENT:
For Armada 37xx:
- GIC improvement
- Add PMUv3
- Enable USB2 on EspressoBin
For Armada 7K/8K:
- add GPIO interrupts for CP110
- add pinctrl nodes to describe the CPM I2C0 and CPS SPI1
- re-order RTC nodes in Marvell CP110 description
- on MacchiatoBin
- fix USB3 regulator definition
- add support for i2c mux
- add support for PCIe
- add an stdout-path
* tag 'mvebu-dt64-4.14-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: re-order RTC nodes in Marvell CP110 description
arm64: dts: marvell: mcbin: add an stdout-path
arm64: dts: marvell: mcbin: add support for PCIe
arm64: dts: marvell: mcbin: add support for i2c mux
arm64: dts: marvell: fix USB3 regulator definition on MacchiatoBin
arm64: dts: marvell: mcbin: add pinctrl nodes
arm64: dts: marvell: cp110: add GPIO interrupts
ARM64: dts: marvell: armada-37xx: Enable USB2 on espressobin
ARM64: dts: marvell: armada-37xx: Wire PMUv3
ARM64: dts: marvell: armada-37xx: Enable memory-mapped GIC CPU interface
ARM64: dts: marvell: armada-37xx: Fix GIC maintenance interrupt
This commit is contained in:
Arnd Bergmann
commit
77dcb02f0d
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@ -81,6 +81,11 @@ &usb3 {
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status = "okay";
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};
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/* J8 */
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&usb2 {
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status = "okay";
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};
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&mdio {
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switch0: switch0@1 {
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compatible = "marvell,mv88e6085";
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@ -81,6 +81,11 @@ timer {
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<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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@ -322,7 +327,11 @@ gic: interrupt-controller@1d00000 {
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x1d00000 0x10000>, /* GICD */
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<0x1d40000 0x40000>; /* GICR */
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<0x1d40000 0x40000>, /* GICR */
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<0x1d80000 0x2000>, /* GICC */
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<0x1d90000 0x2000>, /* GICH */
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<0x1da0000 0x20000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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@ -46,11 +46,17 @@
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#include "armada-8040.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Marvell 8040 MACHIATOBin";
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compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
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"marvell,armada-ap806-quad", "marvell,armada-ap806";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@00000000 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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@ -77,11 +83,13 @@ v_vddo_h: regulator-1-8v {
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v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&cpm_gpio2 15 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_xhci_vbus_pins>;
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regulator-name = "v_5v0_usb3_hst_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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/* actually GPIO controlled, but 8k has no GPIO support yet */
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regulator-always-on;
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status = "okay";
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};
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@ -112,10 +120,44 @@ &ap_sdhci0 {
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&cpm_i2c0 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_i2c0_pins>;
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status = "okay";
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};
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&cpm_i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_i2c1_pins>;
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status = "okay";
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i2c-switch@70 {
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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sfpp0_i2c: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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sfpp1_i2c: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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sfp_1g_i2c: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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};
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};
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&cpm_mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_ge_mdio_pins>;
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status = "okay";
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ge_phy: ethernet-phy@0 {
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@ -123,6 +165,43 @@ ge_phy: ethernet-phy@0 {
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};
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};
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&cpm_pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_pcie_pins>;
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num-lanes = <4>;
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num-viewport = <8>;
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reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&cpm_pinctrl {
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cpm_ge_mdio_pins: ge-mdio-pins {
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marvell,pins = "mpp32", "mpp34";
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marvell,function = "ge";
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};
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cpm_i2c1_pins: i2c1-pins {
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marvell,pins = "mpp35", "mpp36";
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marvell,function = "i2c1";
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};
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cpm_i2c0_pins: i2c0-pins {
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marvell,pins = "mpp37", "mpp38";
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marvell,function = "i2c0";
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};
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cpm_xhci_vbus_pins: xhci0-vbus-pins {
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marvell,pins = "mpp47";
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marvell,function = "gpio";
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};
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cpm_pcie_pins: pcie-pins {
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marvell,pins = "mpp52";
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marvell,function = "gpio";
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};
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cpm_sdhci_pins: sdhci-pins {
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marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
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"mpp60", "mpp61";
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marvell,function = "sdio";
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};
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};
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&cpm_sata0 {
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/* CPM Lane 0 - U29 */
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status = "okay";
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@ -132,6 +211,8 @@ &cpm_sdhci0 {
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/* U6 */
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broken-cd;
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_sdhci_pins>;
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status = "okay";
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vqmmc-supply = <&v_3_3>;
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};
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@ -157,6 +238,13 @@ &cps_eth1 {
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phy-mode = "sgmii";
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};
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&cps_pinctrl {
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cps_spi1_pins: spi1-pins {
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marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
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marvell,function = "spi1";
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};
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};
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&cps_sata0 {
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/* CPS Lane 1 - U32 */
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/* CPS Lane 3 - U31 */
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@ -164,6 +252,8 @@ &cps_sata0 {
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};
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&cps_spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cps_spi1_pins>;
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status = "okay";
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spi-flash@0 {
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@ -115,6 +115,13 @@ cpm_icu: interrupt-controller@1e0000 {
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msi-parent = <&gicp>;
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};
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cpm_rtc: rtc@284000 {
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compatible = "marvell,armada-8k-rtc";
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reg = <0x284000 0x20>, <0x284080 0x24>;
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reg-names = "rtc", "rtc-soc";
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interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
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};
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cpm_syscon0: system-controller@440000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x440000 0x1000>;
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@ -131,8 +138,12 @@ cpm_gpio1: gpio@100 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&cpm_pinctrl 0 0 32>;
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interrupt-controller;
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interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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cpm_gpio2: gpio@140 {
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@ -142,17 +153,15 @@ cpm_gpio2: gpio@140 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&cpm_pinctrl 0 32 31>;
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interrupt-controller;
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interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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cpm_rtc: rtc@284000 {
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compatible = "marvell,armada-8k-rtc";
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reg = <0x284000 0x20>, <0x284080 0x24>;
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reg-names = "rtc", "rtc-soc";
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interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
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};
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cpm_sata0: sata@540000 {
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compatible = "marvell,armada-8k-ahci",
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"generic-ahci";
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@ -60,13 +60,6 @@ config-space@f4000000 {
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compatible = "simple-bus";
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ranges = <0x0 0x0 0xf4000000 0x2000000>;
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cps_rtc: rtc@284000 {
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compatible = "marvell,armada-8k-rtc";
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reg = <0x284000 0x20>, <0x284080 0x24>;
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reg-names = "rtc", "rtc-soc";
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interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
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};
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cps_ethernet: ethernet@0 {
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compatible = "marvell,armada-7k-pp22";
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reg = <0x0 0x100000>, <0x129000 0xb000>;
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@ -122,6 +115,13 @@ cps_icu: interrupt-controller@1e0000 {
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msi-parent = <&gicp>;
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};
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cps_rtc: rtc@284000 {
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compatible = "marvell,armada-8k-rtc";
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reg = <0x284000 0x20>, <0x284080 0x24>;
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reg-names = "rtc", "rtc-soc";
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interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
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};
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cps_syscon0: system-controller@440000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x440000 0x1000>;
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@ -138,8 +138,12 @@ cps_gpio1: gpio@100 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&cps_pinctrl 0 0 32>;
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interrupt-controller;
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interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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cps_gpio2: gpio@140 {
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@ -149,6 +153,11 @@ cps_gpio2: gpio@140 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&cps_pinctrl 0 32 31>;
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interrupt-controller;
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interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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