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memory: tegra: Implement EMEM regs and ICC ops for Tegra114
Prepare Internal Memory Controller for introduction of External Memory Controller. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Link: https://patch.msgid.link/20260427070312.81679-3-clamor95@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Svyatoslav Ryhel
Krzysztof Kozlowski
parent
b42834da6f
commit
750fed9230
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@ -3,6 +3,7 @@
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* Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/mm.h>
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@ -1101,6 +1102,195 @@ static const struct tegra_mc_reset tegra114_mc_resets[] = {
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TEGRA114_MC_RESET(VI, 0x200, 0x204, 17),
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};
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static void tegra114_mc_tune_client_latency(struct tegra_mc *mc,
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const struct tegra_mc_client *client,
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unsigned int bandwidth_mbytes_sec)
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{
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u32 arb_tolerance_compensation_nsec, arb_tolerance_compensation_div;
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unsigned int fifo_size = client->fifo_size;
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u32 arb_nsec, la_ticks, value;
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/* see 20.3.1.1 Client Configuration in Tegra4 TRM v01p */
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if (bandwidth_mbytes_sec)
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arb_nsec = fifo_size * NSEC_PER_USEC / bandwidth_mbytes_sec;
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else
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arb_nsec = U32_MAX;
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/*
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* Latency allowness should be set with consideration for the module's
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* latency tolerance and internal buffering capabilities.
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*
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* Display memory clients use isochronous transfers and have very low
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* tolerance to a belated transfers. Hence we need to compensate the
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* memory arbitration imperfection for them in order to prevent FIFO
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* underflow condition when memory bus is busy.
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*
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* VI clients also need a stronger compensation.
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*/
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switch (client->swgroup) {
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case TEGRA_SWGROUP_MPCORE:
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case TEGRA_SWGROUP_PTC:
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/*
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* We always want lower latency for these clients, hence
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* don't touch them.
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*/
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return;
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case TEGRA_SWGROUP_DC:
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case TEGRA_SWGROUP_DCB:
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arb_tolerance_compensation_nsec = 1050;
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arb_tolerance_compensation_div = 2;
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break;
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case TEGRA_SWGROUP_VI:
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arb_tolerance_compensation_nsec = 1050;
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arb_tolerance_compensation_div = 1;
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break;
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default:
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arb_tolerance_compensation_nsec = 150;
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arb_tolerance_compensation_div = 1;
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break;
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}
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if (arb_nsec > arb_tolerance_compensation_nsec)
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arb_nsec -= arb_tolerance_compensation_nsec;
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else
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arb_nsec = 0;
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arb_nsec /= arb_tolerance_compensation_div;
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/*
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* Latency allowance is a number of ticks a request from a particular
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* client may wait in the EMEM arbiter before it becomes a high-priority
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* request.
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*/
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la_ticks = arb_nsec / mc->tick;
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la_ticks = min(la_ticks, client->regs.la.mask);
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value = mc_readl(mc, client->regs.la.reg);
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value &= ~(client->regs.la.mask << client->regs.la.shift);
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value |= la_ticks << client->regs.la.shift;
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mc_writel(mc, value, client->regs.la.reg);
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}
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static int tegra114_mc_icc_set(struct icc_node *src, struct icc_node *dst)
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{
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struct tegra_mc *mc = icc_provider_to_tegra_mc(src->provider);
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const struct tegra_mc_client *client = &mc->soc->clients[src->id];
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u64 peak_bandwidth = icc_units_to_bps(src->peak_bw);
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/*
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* Skip pre-initialization that is done by icc_node_add(), which sets
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* bandwidth to maximum for all clients before drivers are loaded.
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*
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* This doesn't make sense for us because we don't have drivers for all
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* clients and it's okay to keep configuration left from bootloader
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* during boot, at least for today.
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*/
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if (src == dst)
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return 0;
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/* convert bytes/sec to megabytes/sec */
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do_div(peak_bandwidth, 1000000);
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tegra114_mc_tune_client_latency(mc, client, peak_bandwidth);
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return 0;
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}
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static int tegra114_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,
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u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
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{
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/*
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* ISO clients need to reserve extra bandwidth up-front because
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* there could be high bandwidth pressure during initial filling
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* of the client's FIFO buffers. Secondly, we need to take into
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* account impurities of the memory subsystem.
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*/
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if (tag & TEGRA_MC_ICC_TAG_ISO)
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peak_bw = tegra_mc_scale_percents(peak_bw, 400);
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*agg_avg += avg_bw;
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*agg_peak = max(*agg_peak, peak_bw);
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return 0;
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}
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static struct icc_node_data *
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tegra114_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
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{
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struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
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const struct tegra_mc_client *client;
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unsigned int i, idx = spec->args[0];
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struct icc_node_data *ndata;
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struct icc_node *node;
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list_for_each_entry(node, &mc->provider.nodes, node_list) {
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if (node->id != idx)
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continue;
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ndata = kzalloc_obj(*ndata);
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if (!ndata)
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return ERR_PTR(-ENOMEM);
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client = &mc->soc->clients[idx];
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ndata->node = node;
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switch (client->swgroup) {
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case TEGRA_SWGROUP_DC:
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case TEGRA_SWGROUP_DCB:
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case TEGRA_SWGROUP_PTC:
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case TEGRA_SWGROUP_VI:
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/* these clients are isochronous by default */
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ndata->tag = TEGRA_MC_ICC_TAG_ISO;
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break;
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default:
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ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT;
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break;
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}
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return ndata;
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}
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for (i = 0; i < mc->soc->num_clients; i++) {
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if (mc->soc->clients[i].id == idx)
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return ERR_PTR(-EPROBE_DEFER);
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}
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dev_err(mc->dev, "invalid ICC client ID %u\n", idx);
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return ERR_PTR(-EINVAL);
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}
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static const struct tegra_mc_icc_ops tegra114_mc_icc_ops = {
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.xlate_extended = tegra114_mc_of_icc_xlate_extended,
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.aggregate = tegra114_mc_icc_aggreate,
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.set = tegra114_mc_icc_set,
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};
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static const unsigned long tegra114_mc_emem_regs[] = {
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MC_EMEM_ARB_CFG,
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MC_EMEM_ARB_OUTSTANDING_REQ,
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MC_EMEM_ARB_TIMING_RCD,
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MC_EMEM_ARB_TIMING_RP,
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MC_EMEM_ARB_TIMING_RC,
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MC_EMEM_ARB_TIMING_RAS,
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MC_EMEM_ARB_TIMING_FAW,
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MC_EMEM_ARB_TIMING_RRD,
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MC_EMEM_ARB_TIMING_RAP2PRE,
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MC_EMEM_ARB_TIMING_WAP2PRE,
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MC_EMEM_ARB_TIMING_R2R,
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MC_EMEM_ARB_TIMING_W2W,
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MC_EMEM_ARB_TIMING_R2W,
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MC_EMEM_ARB_TIMING_W2R,
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MC_EMEM_ARB_DA_TURNS,
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MC_EMEM_ARB_DA_COVERS,
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MC_EMEM_ARB_MISC0,
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MC_EMEM_ARB_RING1_THROTTLE,
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};
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static const struct tegra_mc_intmask tegra114_mc_intmasks[] = {
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{
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.reg = MC_INTMASK,
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@ -1116,11 +1306,14 @@ const struct tegra_mc_soc tegra114_mc_soc = {
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.atom_size = 32,
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.client_id_mask = 0x7f,
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.smmu = &tegra114_smmu_soc,
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.emem_regs = tegra114_mc_emem_regs,
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.num_emem_regs = ARRAY_SIZE(tegra114_mc_emem_regs),
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.intmasks = tegra114_mc_intmasks,
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.num_intmasks = ARRAY_SIZE(tegra114_mc_intmasks),
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.reset_ops = &tegra_mc_reset_ops_common,
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.resets = tegra114_mc_resets,
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.num_resets = ARRAY_SIZE(tegra114_mc_resets),
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.icc_ops = &tegra114_mc_icc_ops,
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.ops = &tegra30_mc_ops,
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.regs = &tegra20_mc_regs,
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.handle_irq = tegra30_mc_irq_handlers,
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