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Merge branch 'for-v7.2/tegra114-mc-bindings' into mem-ctrl-next

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This commit is contained in:
Krzysztof Kozlowski 2026-05-04 20:46:50 +02:00
commit b42834da6f
3 changed files with 101 additions and 171 deletions
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174
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
View File

@ -16,7 +16,9 @@ description: |
properties:
compatible:
const: nvidia,tegra124-emc
enum:
- nvidia,tegra114-emc
- nvidia,tegra124-emc
reg:
maxItems: 1
@ -29,6 +31,9 @@ properties:
items:
- const: emc
interrupts:
maxItems: 1
"#interconnect-cells":
const: 0
@ -164,153 +169,12 @@ patternProperties:
nvidia,emc-configuration:
description:
EMC timing characterization data. These are the registers (see
section "15.6.2 EMC Registers" in the TRM) whose values need to
section "20.11.2 EMC Registers" in the Tegra114 TRM or section
"15.6.2 EMC Registers" in the Tegra124 TRM) whose values need to
be specified, according to the board documentation.
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: EMC_RC
- description: EMC_RFC
- description: EMC_RFC_SLR
- description: EMC_RAS
- description: EMC_RP
- description: EMC_R2W
- description: EMC_W2R
- description: EMC_R2P
- description: EMC_W2P
- description: EMC_RD_RCD
- description: EMC_WR_RCD
- description: EMC_RRD
- description: EMC_REXT
- description: EMC_WEXT
- description: EMC_WDV
- description: EMC_WDV_MASK
- description: EMC_QUSE
- description: EMC_QUSE_WIDTH
- description: EMC_IBDLY
- description: EMC_EINPUT
- description: EMC_EINPUT_DURATION
- description: EMC_PUTERM_EXTRA
- description: EMC_PUTERM_WIDTH
- description: EMC_PUTERM_ADJ
- description: EMC_CDB_CNTL_1
- description: EMC_CDB_CNTL_2
- description: EMC_CDB_CNTL_3
- description: EMC_QRST
- description: EMC_QSAFE
- description: EMC_RDV
- description: EMC_RDV_MASK
- description: EMC_REFRESH
- description: EMC_BURST_REFRESH_NUM
- description: EMC_PRE_REFRESH_REQ_CNT
- description: EMC_PDEX2WR
- description: EMC_PDEX2RD
- description: EMC_PCHG2PDEN
- description: EMC_ACT2PDEN
- description: EMC_AR2PDEN
- description: EMC_RW2PDEN
- description: EMC_TXSR
- description: EMC_TXSRDLL
- description: EMC_TCKE
- description: EMC_TCKESR
- description: EMC_TPD
- description: EMC_TFAW
- description: EMC_TRPAB
- description: EMC_TCLKSTABLE
- description: EMC_TCLKSTOP
- description: EMC_TREFBW
- description: EMC_FBIO_CFG6
- description: EMC_ODT_WRITE
- description: EMC_ODT_READ
- description: EMC_FBIO_CFG5
- description: EMC_CFG_DIG_DLL
- description: EMC_CFG_DIG_DLL_PERIOD
- description: EMC_DLL_XFORM_DQS0
- description: EMC_DLL_XFORM_DQS1
- description: EMC_DLL_XFORM_DQS2
- description: EMC_DLL_XFORM_DQS3
- description: EMC_DLL_XFORM_DQS4
- description: EMC_DLL_XFORM_DQS5
- description: EMC_DLL_XFORM_DQS6
- description: EMC_DLL_XFORM_DQS7
- description: EMC_DLL_XFORM_DQS8
- description: EMC_DLL_XFORM_DQS9
- description: EMC_DLL_XFORM_DQS10
- description: EMC_DLL_XFORM_DQS11
- description: EMC_DLL_XFORM_DQS12
- description: EMC_DLL_XFORM_DQS13
- description: EMC_DLL_XFORM_DQS14
- description: EMC_DLL_XFORM_DQS15
- description: EMC_DLL_XFORM_QUSE0
- description: EMC_DLL_XFORM_QUSE1
- description: EMC_DLL_XFORM_QUSE2
- description: EMC_DLL_XFORM_QUSE3
- description: EMC_DLL_XFORM_QUSE4
- description: EMC_DLL_XFORM_QUSE5
- description: EMC_DLL_XFORM_QUSE6
- description: EMC_DLL_XFORM_QUSE7
- description: EMC_DLL_XFORM_ADDR0
- description: EMC_DLL_XFORM_ADDR1
- description: EMC_DLL_XFORM_ADDR2
- description: EMC_DLL_XFORM_ADDR3
- description: EMC_DLL_XFORM_ADDR4
- description: EMC_DLL_XFORM_ADDR5
- description: EMC_DLL_XFORM_QUSE8
- description: EMC_DLL_XFORM_QUSE9
- description: EMC_DLL_XFORM_QUSE10
- description: EMC_DLL_XFORM_QUSE11
- description: EMC_DLL_XFORM_QUSE12
- description: EMC_DLL_XFORM_QUSE13
- description: EMC_DLL_XFORM_QUSE14
- description: EMC_DLL_XFORM_QUSE15
- description: EMC_DLI_TRIM_TXDQS0
- description: EMC_DLI_TRIM_TXDQS1
- description: EMC_DLI_TRIM_TXDQS2
- description: EMC_DLI_TRIM_TXDQS3
- description: EMC_DLI_TRIM_TXDQS4
- description: EMC_DLI_TRIM_TXDQS5
- description: EMC_DLI_TRIM_TXDQS6
- description: EMC_DLI_TRIM_TXDQS7
- description: EMC_DLI_TRIM_TXDQS8
- description: EMC_DLI_TRIM_TXDQS9
- description: EMC_DLI_TRIM_TXDQS10
- description: EMC_DLI_TRIM_TXDQS11
- description: EMC_DLI_TRIM_TXDQS12
- description: EMC_DLI_TRIM_TXDQS13
- description: EMC_DLI_TRIM_TXDQS14
- description: EMC_DLI_TRIM_TXDQS15
- description: EMC_DLL_XFORM_DQ0
- description: EMC_DLL_XFORM_DQ1
- description: EMC_DLL_XFORM_DQ2
- description: EMC_DLL_XFORM_DQ3
- description: EMC_DLL_XFORM_DQ4
- description: EMC_DLL_XFORM_DQ5
- description: EMC_DLL_XFORM_DQ6
- description: EMC_DLL_XFORM_DQ7
- description: EMC_XM2CMDPADCTRL
- description: EMC_XM2CMDPADCTRL4
- description: EMC_XM2CMDPADCTRL5
- description: EMC_XM2DQPADCTRL2
- description: EMC_XM2DQPADCTRL3
- description: EMC_XM2CLKPADCTRL
- description: EMC_XM2CLKPADCTRL2
- description: EMC_XM2COMPPADCTRL
- description: EMC_XM2VTTGENPADCTRL
- description: EMC_XM2VTTGENPADCTRL2
- description: EMC_XM2VTTGENPADCTRL3
- description: EMC_XM2DQSPADCTRL3
- description: EMC_XM2DQSPADCTRL4
- description: EMC_XM2DQSPADCTRL5
- description: EMC_XM2DQSPADCTRL6
- description: EMC_DSR_VTTGEN_DRV
- description: EMC_TXDSRVTTGEN
- description: EMC_FBIO_SPARE
- description: EMC_ZCAL_WAIT_CNT
- description: EMC_MRS_WAIT_CNT2
- description: EMC_CTT
- description: EMC_CTT_DURATION
- description: EMC_CFG_PIPE
- description: EMC_DYN_SELF_REF_CONTROL
- description: EMC_QPOP
minItems: 97
maxItems: 143
required:
- clock-frequency
@ -318,9 +182,7 @@ patternProperties:
- nvidia,emc-auto-cal-config2
- nvidia,emc-auto-cal-config3
- nvidia,emc-auto-cal-interval
- nvidia,emc-bgbias-ctl0
- nvidia,emc-cfg
- nvidia,emc-cfg-2
- nvidia,emc-ctt-term-ctrl
- nvidia,emc-mode-1
- nvidia,emc-mode-2
@ -344,6 +206,22 @@ required:
- "#interconnect-cells"
- operating-points-v2
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra124-emc
then:
patternProperties:
"^emc-timings-[0-9]+$":
patternProperties:
"^timing-[0-9]+$":
required:
- nvidia,emc-bgbias-ctl0
- nvidia,emc-cfg-2
additionalProperties: false
examples:

31
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml
View File

@ -19,7 +19,9 @@ description: |
properties:
compatible:
const: nvidia,tegra124-mc
enum:
- nvidia,tegra114-mc
- nvidia,tegra124-mc
reg:
maxItems: 1
@ -64,29 +66,12 @@ patternProperties:
nvidia,emem-configuration:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
description:
Values to be written to the EMEM register block. See section
"15.6.1 MC Registers" in the TRM.
items:
- description: MC_EMEM_ARB_CFG
- description: MC_EMEM_ARB_OUTSTANDING_REQ
- description: MC_EMEM_ARB_TIMING_RCD
- description: MC_EMEM_ARB_TIMING_RP
- description: MC_EMEM_ARB_TIMING_RC
- description: MC_EMEM_ARB_TIMING_RAS
- description: MC_EMEM_ARB_TIMING_FAW
- description: MC_EMEM_ARB_TIMING_RRD
- description: MC_EMEM_ARB_TIMING_RAP2PRE
- description: MC_EMEM_ARB_TIMING_WAP2PRE
- description: MC_EMEM_ARB_TIMING_R2R
- description: MC_EMEM_ARB_TIMING_W2W
- description: MC_EMEM_ARB_TIMING_R2W
- description: MC_EMEM_ARB_TIMING_W2R
- description: MC_EMEM_ARB_DA_TURNS
- description: MC_EMEM_ARB_DA_COVERS
- description: MC_EMEM_ARB_MISC0
- description: MC_EMEM_ARB_MISC1
- description: MC_EMEM_ARB_RING1_THROTTLE
"20.11.1 MC Registers" in the Tegea114 TRM or
"15.6.1 MC Registers" in the Tegra124 TRM.
minItems: 18
maxItems: 19
required:
- clock-frequency

67
include/dt-bindings/memory/tegra114-mc.h
View File

@ -40,4 +40,71 @@
#define TEGRA114_MC_RESET_VDE 14
#define TEGRA114_MC_RESET_VI 15
#define TEGRA114_MC_PTCR 0
#define TEGRA114_MC_DISPLAY0A 1
#define TEGRA114_MC_DISPLAY0AB 2
#define TEGRA114_MC_DISPLAY0B 3
#define TEGRA114_MC_DISPLAY0BB 4
#define TEGRA114_MC_DISPLAY0C 5
#define TEGRA114_MC_DISPLAY0CB 6
#define TEGRA114_MC_DISPLAY1B 7
#define TEGRA114_MC_DISPLAY1BB 8
#define TEGRA114_MC_EPPUP 9
#define TEGRA114_MC_G2PR 10
#define TEGRA114_MC_G2SR 11
#define TEGRA114_MC_MPEUNIFBR 12
#define TEGRA114_MC_VIRUV 13
#define TEGRA114_MC_AFIR 14
#define TEGRA114_MC_AVPCARM7R 15
#define TEGRA114_MC_DISPLAYHC 16
#define TEGRA114_MC_DISPLAYHCB 17
#define TEGRA114_MC_FDCDRD 18
#define TEGRA114_MC_FDCDRD2 19
#define TEGRA114_MC_G2DR 20
#define TEGRA114_MC_HDAR 21
#define TEGRA114_MC_HOST1XDMAR 22
#define TEGRA114_MC_HOST1XR 23
#define TEGRA114_MC_IDXSRD 24
#define TEGRA114_MC_IDXSRD2 25
#define TEGRA114_MC_MPE_IPRED 26
#define TEGRA114_MC_MPEAMEMRD 27
#define TEGRA114_MC_MPECSRD 28
#define TEGRA114_MC_PPCSAHBDMAR 29
#define TEGRA114_MC_PPCSAHBSLVR 30
#define TEGRA114_MC_SATAR 31
#define TEGRA114_MC_TEXSRD 32
#define TEGRA114_MC_TEXSRD2 33
#define TEGRA114_MC_VDEBSEVR 34
#define TEGRA114_MC_VDEMBER 35
#define TEGRA114_MC_VDEMCER 36
#define TEGRA114_MC_VDETPER 37
#define TEGRA114_MC_MPCORELPR 38
#define TEGRA114_MC_MPCORER 39
#define TEGRA114_MC_EPPU 40
#define TEGRA114_MC_EPPV 41
#define TEGRA114_MC_EPPY 42
#define TEGRA114_MC_MPEUNIFBW 43
#define TEGRA114_MC_VIWSB 44
#define TEGRA114_MC_VIWU 45
#define TEGRA114_MC_VIWV 46
#define TEGRA114_MC_VIWY 47
#define TEGRA114_MC_G2DW 48
#define TEGRA114_MC_AFIW 49
#define TEGRA114_MC_AVPCARM7W 50
#define TEGRA114_MC_FDCDWR 51
#define TEGRA114_MC_FDCDWR2 52
#define TEGRA114_MC_HDAW 53
#define TEGRA114_MC_HOST1XW 54
#define TEGRA114_MC_ISPW 55
#define TEGRA114_MC_MPCORELPW 56
#define TEGRA114_MC_MPCOREW 57
#define TEGRA114_MC_MPECSWR 58
#define TEGRA114_MC_PPCSAHBDMAW 59
#define TEGRA114_MC_PPCSAHBSLVW 60
#define TEGRA114_MC_SATAW 61
#define TEGRA114_MC_VDEBSEVW 62
#define TEGRA114_MC_VDEDBGW 63
#define TEGRA114_MC_VDEMBEW 64
#define TEGRA114_MC_VDETPMW 65
#endif