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Berlin DT changes for v3.17
- L2CC latency properties for BG2Q - DW i2c nodes for BG2Q and corresponding dev board - SMP related nodes for BG2 and BG2Q -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJTsWf4AAoJEN2kpao7fSL49BkQAIFRcw5YH8Ss72do+sDxNQMU in1GZ5mHBrLzu0qjAbEe3jrKmXUQDWhRqkIVtM4A6HTb9RwM+85eNVfziyld0K8F O6tErJlVhvK6hG63Cl/M/QIZZEMoAsOeM/NRrOoij0yftFdgdHz1mUp+RFxtdiuS mL8iarnn2mL9IpiBZYz1I+0Y7HxgX5+dVdG9uHRzhzLJffxkl0kki21dtaKEUInv n2RlF93L9PtVgRGUer9UEXDRG7VNd594fT56q5kOU8vyYsLXltDcvzI56+jIXO+s JsjTTUsboXOHK9BCzjONcRYiLZQ8g4M5GkeNOb6oDpy3sQSS7ORf4WpKYhyRnvVI 0MMY/RzVO06WOXdTW0yd25pH6j/EmkpqGa+8RqGwXk1twJqyPL5cfPzwbqtQ4Re3 RNXtbwp6qxECJ4oRf8rc8xUlWKH49xf0hiVkX1aKQKp+8qsyOvhCug4sAnFehOZM DShXdxmGM9bSi9wYswLs+a1dPEJPlpE2ALUfZAYUuxwsziAPTztioKVS8Ht7TjBA aqINoFNOlpi0m84SbXGIP0E3inhpe6KdrD98tPFPlxWhi3uom4i8qsjbRcHDIjYp Hg9oa3U+Go2C4UPFnhqMxCbQFK1tgNOCGHrTRsLsO3uJ9g+IbFkqQPH088PO8eOm aLcy2Hxd9AnhIU2GZTB6 =PEAV -----END PGP SIGNATURE----- Merge tag 'berlin-dt-3.17-1' of git://git.infradead.org/users/hesselba/linux-berlin into next/dt Merge "Berlin DT changes for v3.17" from Sebastian Hesselbarth: - L2CC latency properties for BG2Q - DW i2c nodes for BG2Q and corresponding dev board - SMP related nodes for BG2 and BG2Q * tag 'berlin-dt-3.17-1' of git://git.infradead.org/users/hesselba/linux-berlin: ARM: dts: berlin: add SMP related nodes and properties for BG2Q ARM: dts: berlin: add SMP related nodes and properties for BG2 Documentation: bindings: add the marvell,berlin-smp CPU enable method Documentation: bindings: add the Berlin CPU control doc ARM: dts: berlin: enable i2c0 and i2c2 ARM: dts: berlin: add I2C nodes for BG2Q ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
74498a6de2
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@ -0,0 +1,41 @@
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========================================================
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Secondary CPU enable-method "marvell,berlin-smp" binding
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========================================================
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This document describes the "marvell,berlin-smp" method for enabling secondary
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CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
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be defined in the "cpus" node.
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Enable method name: "marvell,berlin-smp"
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Compatible machines: "marvell,berlin2" and "marvell,berlin2q"
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Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
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Related properties: (none)
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Note:
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This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
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"marvell,berlin-cpu-ctrl"[1].
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Example:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "marvell,berlin-smp";
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cpu@0 {
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compatible = "marvell,pj4b";
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device_type = "cpu";
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next-level-cache = <&l2>;
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reg = <0>;
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};
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cpu@1 {
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compatible = "marvell,pj4b";
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device_type = "cpu";
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next-level-cache = <&l2>;
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reg = <1>;
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};
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};
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--
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[1] arm/marvell,berlin.txt
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@ -24,6 +24,22 @@ SoC and board used. Currently known SoC compatibles are:
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...
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}
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* Marvell Berlin CPU control bindings
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CPU control register allows various operations on CPUs, like resetting them
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independently.
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Required properties:
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- compatible: should be "marvell,berlin-cpu-ctrl"
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- reg: address and length of the register set
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Example:
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cpu-ctrl@f7dd0000 {
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compatible = "marvell,berlin-cpu-ctrl";
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reg = <0xf7dd0000 0x10000>;
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};
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* Marvell Berlin2 chip control binding
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Marvell Berlin SoCs have a chip control register set providing several
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@ -22,6 +22,7 @@ / {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "marvell,berlin-smp";
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cpu@0 {
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compatible = "marvell,pj4b";
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@ -78,6 +79,11 @@ local-timer@ad0600 {
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clocks = <&chip CLKID_TWD>;
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};
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cpu-ctrl@dd0000 {
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compatible = "marvell,berlin-cpu-ctrl";
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reg = <0xdd0000 0x10000>;
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};
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apb@e80000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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@ -34,6 +34,14 @@ &sdhci2 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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&i2c2 {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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@ -18,6 +18,7 @@ / {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "marvell,berlin-smp";
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cpu@0 {
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compatible = "arm,cortex-a9";
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@ -90,6 +91,8 @@ l2: l2-cache-controller@ac0000 {
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compatible = "arm,pl310-cache";
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reg = <0xac0000 0x1000>;
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cache-level = <2>;
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arm,data-latency = <2 2 2>;
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arm,tag-latency = <2 2 2>;
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};
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scu: snoop-control-unit@ad0000 {
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@ -111,6 +114,11 @@ gic: interrupt-controller@ad1000 {
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#interrupt-cells = <3>;
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};
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cpu-ctrl@dd0000 {
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compatible = "marvell,berlin-cpu-ctrl";
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reg = <0xdd0000 0x10000>;
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};
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apb@e80000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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@ -191,6 +199,32 @@ portd: gpio-port@3 {
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};
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};
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i2c0: i2c@1400 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1400 0x100>;
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interrupt-parent = <&aic>;
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interrupts = <4>;
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clocks = <&chip CLKID_CFG>;
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pinctrl-0 = <&twsi0_pmux>;
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pinctrl-names = "default";
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status = "disabled";
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};
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i2c1: i2c@1800 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1800 0x100>;
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interrupt-parent = <&aic>;
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interrupts = <5>;
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clocks = <&chip CLKID_CFG>;
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pinctrl-0 = <&twsi1_pmux>;
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pinctrl-names = "default";
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status = "disabled";
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};
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timer0: timer@2c00 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c00 0x14>;
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@ -301,6 +335,16 @@ chip: chip-control@ea0000 {
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reg = <0xea0000 0x400>, <0xdd0170 0x10>;
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clocks = <&refclk>;
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clock-names = "refclk";
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twsi0_pmux: twsi0-pmux {
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groups = "G6";
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function = "twsi0";
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};
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twsi1_pmux: twsi1-pmux {
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groups = "G7";
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function = "twsi1";
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};
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};
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apb@fc0000 {
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@ -311,6 +355,32 @@ apb@fc0000 {
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ranges = <0 0xfc0000 0x10000>;
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interrupt-parent = <&sic>;
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i2c2: i2c@7000 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x7000 0x100>;
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interrupt-parent = <&sic>;
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interrupts = <6>;
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clocks = <&refclk>;
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pinctrl-0 = <&twsi2_pmux>;
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pinctrl-names = "default";
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status = "disabled";
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};
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i2c3: i2c@8000 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x8000 0x100>;
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interrupt-parent = <&sic>;
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interrupts = <7>;
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clocks = <&refclk>;
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pinctrl-0 = <&twsi3_pmux>;
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pinctrl-names = "default";
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status = "disabled";
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};
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uart0: uart@9000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x9000 0x100>;
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@ -348,6 +418,16 @@ uart1_pmux: uart1-pmux {
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groups = "GSM14";
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function = "uart1";
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};
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twsi2_pmux: twsi2-pmux {
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groups = "GSM13";
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function = "twsi2";
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};
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twsi3_pmux: twsi3-pmux {
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groups = "GSM14";
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function = "twsi3";
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};
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};
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sic: interrupt-controller@e000 {
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